Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4394

1

T16

4

T5

6

T20

2

auto[1]

2152

1

T3

4

T5

2

T6

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	232	1			T6	2		T55	2		T58	2
auto[134217728:268435455]	192	1			T89	2		T7	2		T94	2
auto[268435456:402653183]	240	1			T29	2		T58	2		T25	2
auto[402653184:536870911]	202	1			T5	2		T56	2		T59	2
auto[536870912:671088639]	190	1			T56	2		T30	2		T206	2
auto[671088640:805306367]	186	1			T6	2		T44	2		T30	2
auto[805306368:939524095]	162	1			T29	2		T55	2		T25	2
auto[939524096:1073741823]	176	1			T56	2		T85	2		T30	2
auto[1073741824:1207959551]	242	1			T20	2		T199	2		T101	2
auto[1207959552:1342177279]	200	1			T42	2		T60	2		T134	2
auto[1342177280:1476395007]	218	1			T199	2		T60	2		T101	2
auto[1476395008:1610612735]	228	1			T16	2		T6	2		T29	2
auto[1610612736:1744830463]	212	1			T6	2		T29	2		T127	2
auto[1744830464:1879048191]	182	1			T42	2		T45	2		T60	2
auto[1879048192:2013265919]	178	1			T56	2		T25	2		T59	2
auto[2013265920:2147483647]	188	1			T30	2		T43	4		T135	2
auto[2147483648:2281701375]	210	1			T55	2		T21	2		T60	2
auto[2281701376:2415919103]	210	1			T55	2		T25	2		T89	2
auto[2415919104:2550136831]	172	1			T5	2		T6	2		T29	2
auto[2550136832:2684354559]	242	1			T6	2		T58	2		T89	2
auto[2684354560:2818572287]	206	1			T6	2		T55	2		T44	2
auto[2818572288:2952790015]	212	1			T5	2		T127	2		T55	2
auto[2952790016:3087007743]	228	1			T3	2		T25	2		T101	2
auto[3087007744:3221225471]	172	1			T5	2		T6	2		T127	2
auto[3221225472:3355443199]	214	1			T60	2		T52	2		T62	2
auto[3355443200:3489660927]	178	1			T6	2		T30	2		T89	2
auto[3489660928:3623878655]	206	1			T58	2		T86	2		T59	2
auto[3623878656:3758096383]	244	1			T86	2		T60	4		T7	2
auto[3758096384:3892314111]	218	1			T58	4		T31	2		T60	2
auto[3892314112:4026531839]	216	1			T16	2		T6	2		T86	2
auto[4026531840:4160749567]	186	1			T133	2		T101	4		T151	2
auto[4160749568:4294967295]	204	1			T3	2		T31	4		T61	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	162	1			T6	2		T58	2		T42	2
auto[0:134217727]	auto[1]	70	1			T55	2		T101	2		T368	2
auto[134217728:268435455]	auto[0]	124	1			T94	2		T154	2		T27	2
auto[134217728:268435455]	auto[1]	68	1			T89	2		T7	2		T27	2
auto[268435456:402653183]	auto[0]	158	1			T25	2		T42	2		T133	2
auto[268435456:402653183]	auto[1]	82	1			T29	2		T58	2		T131	2
auto[402653184:536870911]	auto[0]	132	1			T56	2		T59	2		T101	2
auto[402653184:536870911]	auto[1]	70	1			T5	2		T152	2		T27	2
auto[536870912:671088639]	auto[0]	130	1			T56	2		T206	2		T79	2
auto[536870912:671088639]	auto[1]	60	1			T30	2		T105	2		T109	2
auto[671088640:805306367]	auto[0]	116	1			T44	2		T101	2		T54	4
auto[671088640:805306367]	auto[1]	70	1			T6	2		T30	2		T101	2
auto[805306368:939524095]	auto[0]	118	1			T29	2		T55	2		T25	2
auto[805306368:939524095]	auto[1]	44	1			T101	2		T207	2		T105	2
auto[939524096:1073741823]	auto[0]	120	1			T56	2		T101	4		T26	2
auto[939524096:1073741823]	auto[1]	56	1			T85	2		T30	2		T77	2
auto[1073741824:1207959551]	auto[0]	166	1			T20	2		T199	2		T101	2
auto[1073741824:1207959551]	auto[1]	76	1			T103	2		T217	2		T406	2
auto[1207959552:1342177279]	auto[0]	142	1			T42	2		T60	2		T101	4
auto[1207959552:1342177279]	auto[1]	58	1			T134	2		T51	2		T101	2
auto[1342177280:1476395007]	auto[0]	156	1			T101	2		T62	2		T208	2
auto[1342177280:1476395007]	auto[1]	62	1			T199	2		T60	2		T325	2
auto[1476395008:1610612735]	auto[0]	138	1			T16	2		T29	2		T61	2
auto[1476395008:1610612735]	auto[1]	90	1			T6	2		T30	2		T42	2
auto[1610612736:1744830463]	auto[0]	152	1			T6	2		T29	2		T58	2
auto[1610612736:1744830463]	auto[1]	60	1			T127	2		T153	2		T54	2
auto[1744830464:1879048191]	auto[0]	128	1			T60	2		T52	2		T69	2
auto[1744830464:1879048191]	auto[1]	54	1			T42	2		T45	2		T7	2
auto[1879048192:2013265919]	auto[0]	122	1			T56	2		T25	2		T199	2
auto[1879048192:2013265919]	auto[1]	56	1			T59	2		T93	2		T278	2
auto[2013265920:2147483647]	auto[0]	138	1			T30	2		T43	2		T135	2
auto[2013265920:2147483647]	auto[1]	50	1			T43	2		T69	2		T77	2
auto[2147483648:2281701375]	auto[0]	146	1			T55	2		T21	2		T60	2
auto[2147483648:2281701375]	auto[1]	64	1			T325	2		T136	2		T106	2
auto[2281701376:2415919103]	auto[0]	132	1			T25	2		T89	2		T43	2
auto[2281701376:2415919103]	auto[1]	78	1			T55	2		T60	2		T101	2
auto[2415919104:2550136831]	auto[0]	116	1			T5	2		T29	2		T43	2
auto[2415919104:2550136831]	auto[1]	56	1			T6	2		T31	2		T60	2
auto[2550136832:2684354559]	auto[0]	178	1			T58	2		T89	2		T42	2
auto[2550136832:2684354559]	auto[1]	64	1			T6	2		T93	2		T74	4
auto[2684354560:2818572287]	auto[0]	134	1			T6	2		T44	2		T89	2
auto[2684354560:2818572287]	auto[1]	72	1			T55	2		T86	2		T54	2
auto[2818572288:2952790015]	auto[0]	138	1			T5	2		T127	2		T207	4
auto[2818572288:2952790015]	auto[1]	74	1			T55	2		T89	2		T42	2
auto[2952790016:3087007743]	auto[0]	150	1			T25	2		T101	2		T153	2
auto[2952790016:3087007743]	auto[1]	78	1			T3	2		T7	2		T62	2
auto[3087007744:3221225471]	auto[0]	116	1			T5	2		T127	2		T44	2
auto[3087007744:3221225471]	auto[1]	56	1			T6	2		T151	2		T37	2
auto[3221225472:3355443199]	auto[0]	140	1			T60	2		T52	2		T62	2
auto[3221225472:3355443199]	auto[1]	74	1			T9	2		T107	2		T38	2
auto[3355443200:3489660927]	auto[0]	116	1			T6	2		T30	2		T89	2
auto[3355443200:3489660927]	auto[1]	62	1			T199	2		T131	2		T60	2
auto[3489660928:3623878655]	auto[0]	144	1			T58	2		T59	2		T43	2
auto[3489660928:3623878655]	auto[1]	62	1			T86	2		T60	2		T151	2
auto[3623878656:3758096383]	auto[0]	150	1			T60	4		T62	4		T94	2
auto[3623878656:3758096383]	auto[1]	94	1			T86	2		T7	2		T153	2
auto[3758096384:3892314111]	auto[0]	152	1			T58	2		T31	2		T60	2
auto[3758096384:3892314111]	auto[1]	66	1			T58	2		T54	2		T46	2
auto[3892314112:4026531839]	auto[0]	142	1			T16	2		T6	2		T131	2
auto[3892314112:4026531839]	auto[1]	74	1			T86	2		T101	2		T152	2
auto[4026531840:4160749567]	auto[0]	118	1			T133	2		T101	4		T26	2
auto[4026531840:4160749567]	auto[1]	68	1			T151	2		T65	2		T95	2
auto[4160749568:4294967295]	auto[0]	120	1			T31	4		T101	2		T52	2
auto[4160749568:4294967295]	auto[1]	84	1			T3	2		T61	2		T291	2