Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 98.11 98.60 100.00 99.02 98.41 91.14


Total test records in report: 1081
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T184 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.278496230 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:30 PM PDT 24 113176493 ps
T1004 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3252254639 Jul 21 06:23:16 PM PDT 24 Jul 21 06:23:33 PM PDT 24 15713941 ps
T1005 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3306345142 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:53 PM PDT 24 16046885 ps
T1006 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1236949970 Jul 21 06:23:12 PM PDT 24 Jul 21 06:24:00 PM PDT 24 1290040193 ps
T1007 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3947690942 Jul 21 06:23:46 PM PDT 24 Jul 21 06:23:57 PM PDT 24 110733394 ps
T1008 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1119594466 Jul 21 06:23:09 PM PDT 24 Jul 21 06:23:26 PM PDT 24 43880043 ps
T1009 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1427364779 Jul 21 06:23:27 PM PDT 24 Jul 21 06:23:45 PM PDT 24 862777049 ps
T1010 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1135868087 Jul 21 06:23:34 PM PDT 24 Jul 21 06:23:44 PM PDT 24 8025053 ps
T168 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2352446066 Jul 21 06:23:37 PM PDT 24 Jul 21 06:23:52 PM PDT 24 144055758 ps
T1011 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2844018118 Jul 21 06:23:34 PM PDT 24 Jul 21 06:23:45 PM PDT 24 217955859 ps
T1012 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3096488310 Jul 21 06:23:16 PM PDT 24 Jul 21 06:23:32 PM PDT 24 43116833 ps
T1013 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2026302169 Jul 21 06:23:51 PM PDT 24 Jul 21 06:23:57 PM PDT 24 32613321 ps
T1014 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2369828118 Jul 21 06:23:45 PM PDT 24 Jul 21 06:23:56 PM PDT 24 58009797 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.20056305 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:53 PM PDT 24 55443751 ps
T1016 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.399191463 Jul 21 06:23:19 PM PDT 24 Jul 21 06:23:41 PM PDT 24 170086200 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2492401801 Jul 21 06:23:14 PM PDT 24 Jul 21 06:23:37 PM PDT 24 242907234 ps
T1018 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2275166168 Jul 21 06:23:46 PM PDT 24 Jul 21 06:23:55 PM PDT 24 111073332 ps
T1019 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1844669537 Jul 21 06:23:33 PM PDT 24 Jul 21 06:23:45 PM PDT 24 143086386 ps
T1020 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1479306410 Jul 21 06:23:39 PM PDT 24 Jul 21 06:23:52 PM PDT 24 261922233 ps
T1021 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2547213428 Jul 21 06:23:49 PM PDT 24 Jul 21 06:23:56 PM PDT 24 27843177 ps
T1022 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2220359286 Jul 21 06:23:45 PM PDT 24 Jul 21 06:23:56 PM PDT 24 237931056 ps
T1023 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1523803762 Jul 21 06:23:25 PM PDT 24 Jul 21 06:23:41 PM PDT 24 35492395 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.883106648 Jul 21 06:23:19 PM PDT 24 Jul 21 06:23:36 PM PDT 24 534328855 ps
T1025 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2594353557 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:28 PM PDT 24 366450905 ps
T1026 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1390145296 Jul 21 06:23:53 PM PDT 24 Jul 21 06:23:58 PM PDT 24 10116655 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2916815854 Jul 21 06:23:17 PM PDT 24 Jul 21 06:23:34 PM PDT 24 53289046 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1208481904 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:28 PM PDT 24 50768745 ps
T1029 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2671914712 Jul 21 06:23:11 PM PDT 24 Jul 21 06:23:28 PM PDT 24 67193112 ps
T1030 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1841399825 Jul 21 06:23:45 PM PDT 24 Jul 21 06:23:54 PM PDT 24 141313922 ps
T1031 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2307112051 Jul 21 06:23:18 PM PDT 24 Jul 21 06:23:35 PM PDT 24 42265048 ps
T1032 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2271648700 Jul 21 06:23:38 PM PDT 24 Jul 21 06:23:50 PM PDT 24 85842984 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2464580451 Jul 21 06:23:37 PM PDT 24 Jul 21 06:23:46 PM PDT 24 11935626 ps
T1034 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2264031239 Jul 21 06:23:53 PM PDT 24 Jul 21 06:23:59 PM PDT 24 12898133 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3415889404 Jul 21 06:23:34 PM PDT 24 Jul 21 06:23:44 PM PDT 24 140426814 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.946459702 Jul 21 06:23:39 PM PDT 24 Jul 21 06:23:50 PM PDT 24 38986212 ps
T1037 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3625105804 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:53 PM PDT 24 44203397 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1115411311 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:29 PM PDT 24 147300712 ps
T1039 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.830099193 Jul 21 06:23:46 PM PDT 24 Jul 21 06:23:55 PM PDT 24 82413368 ps
T1040 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.844530988 Jul 21 06:23:50 PM PDT 24 Jul 21 06:23:57 PM PDT 24 14331341 ps
T1041 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2219164107 Jul 21 06:23:14 PM PDT 24 Jul 21 06:23:33 PM PDT 24 63631560 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2037020761 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:53 PM PDT 24 25989564 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1758370484 Jul 21 06:23:09 PM PDT 24 Jul 21 06:23:26 PM PDT 24 81489577 ps
T177 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.269856984 Jul 21 06:23:28 PM PDT 24 Jul 21 06:23:46 PM PDT 24 965535139 ps
T1044 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.924478534 Jul 21 06:23:56 PM PDT 24 Jul 21 06:24:01 PM PDT 24 25547629 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.785586205 Jul 21 06:23:25 PM PDT 24 Jul 21 06:23:45 PM PDT 24 371112873 ps
T1046 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3755834426 Jul 21 06:23:13 PM PDT 24 Jul 21 06:23:33 PM PDT 24 318756452 ps
T1047 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.651664064 Jul 21 06:23:21 PM PDT 24 Jul 21 06:23:39 PM PDT 24 1739938175 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3607057291 Jul 21 06:23:31 PM PDT 24 Jul 21 06:23:42 PM PDT 24 21935205 ps
T1049 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1871694406 Jul 21 06:23:58 PM PDT 24 Jul 21 06:24:02 PM PDT 24 10145706 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.58545499 Jul 21 06:23:13 PM PDT 24 Jul 21 06:23:31 PM PDT 24 47384150 ps
T1051 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1673731283 Jul 21 06:23:21 PM PDT 24 Jul 21 06:23:36 PM PDT 24 29653485 ps
T1052 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1518969468 Jul 21 06:23:21 PM PDT 24 Jul 21 06:23:38 PM PDT 24 222441686 ps
T1053 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1169145618 Jul 21 06:23:44 PM PDT 24 Jul 21 06:24:02 PM PDT 24 3303040544 ps
T1054 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4023936958 Jul 21 06:23:27 PM PDT 24 Jul 21 06:23:40 PM PDT 24 44056426 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3916501756 Jul 21 06:23:18 PM PDT 24 Jul 21 06:23:34 PM PDT 24 207106171 ps
T1056 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.948405692 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:27 PM PDT 24 27871160 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1789114234 Jul 21 06:23:12 PM PDT 24 Jul 21 06:23:29 PM PDT 24 33658710 ps
T1058 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1257210848 Jul 21 06:23:33 PM PDT 24 Jul 21 06:23:45 PM PDT 24 137448135 ps
T1059 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4126712319 Jul 21 06:23:39 PM PDT 24 Jul 21 06:23:53 PM PDT 24 311129791 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.576560428 Jul 21 06:23:19 PM PDT 24 Jul 21 06:23:35 PM PDT 24 49506750 ps
T1061 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.897138174 Jul 21 06:23:43 PM PDT 24 Jul 21 06:23:52 PM PDT 24 86350444 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.183900919 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:29 PM PDT 24 202002324 ps
T1063 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3397053044 Jul 21 06:23:49 PM PDT 24 Jul 21 06:23:55 PM PDT 24 11913622 ps
T1064 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3608124143 Jul 21 06:23:54 PM PDT 24 Jul 21 06:23:59 PM PDT 24 32649323 ps
T1065 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3927770129 Jul 21 06:23:37 PM PDT 24 Jul 21 06:23:53 PM PDT 24 162197787 ps
T1066 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3522573432 Jul 21 06:23:13 PM PDT 24 Jul 21 06:23:32 PM PDT 24 1056582877 ps
T1067 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3075398632 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:26 PM PDT 24 26551322 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1543098013 Jul 21 06:23:45 PM PDT 24 Jul 21 06:23:55 PM PDT 24 192268346 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3640975791 Jul 21 06:23:38 PM PDT 24 Jul 21 06:23:49 PM PDT 24 38395973 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2418654381 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:30 PM PDT 24 165867655 ps
T1071 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.82412713 Jul 21 06:23:19 PM PDT 24 Jul 21 06:23:37 PM PDT 24 113244471 ps
T1072 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4275247158 Jul 21 06:23:14 PM PDT 24 Jul 21 06:23:31 PM PDT 24 70351325 ps
T1073 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3065357979 Jul 21 06:23:14 PM PDT 24 Jul 21 06:23:31 PM PDT 24 19895496 ps
T1074 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3916500185 Jul 21 06:23:14 PM PDT 24 Jul 21 06:23:42 PM PDT 24 1265374864 ps
T1075 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.21215893 Jul 21 06:23:43 PM PDT 24 Jul 21 06:23:53 PM PDT 24 56456027 ps
T1076 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2684612138 Jul 21 06:23:26 PM PDT 24 Jul 21 06:23:42 PM PDT 24 137330189 ps
T1077 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.401636511 Jul 21 06:23:45 PM PDT 24 Jul 21 06:23:56 PM PDT 24 321293671 ps
T1078 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2904654530 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:58 PM PDT 24 172469409 ps
T1079 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2720610051 Jul 21 06:23:44 PM PDT 24 Jul 21 06:23:53 PM PDT 24 43418376 ps
T1080 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3637081351 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:27 PM PDT 24 12149855 ps
T1081 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4181889587 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:27 PM PDT 24 37358525 ps

Test location /workspace/coverage/default/41.keymgr_stress_all.3977963264
Short name T5
Test name
Test status
Simulation time 4184184477 ps
CPU time 31.97 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 208840 kb
Host smart-5fae496d-b9e0-40a9-b543-a594d933ae32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977963264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3977963264
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1880199564
Short name T54
Test name
Test status
Simulation time 5414948568 ps
CPU time 75.14 seconds
Started Jul 21 05:37:30 PM PDT 24
Finished Jul 21 05:38:45 PM PDT 24
Peak memory 216928 kb
Host smart-21dda667-2cce-4225-8d37-588b743d6a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880199564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1880199564
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2572048875
Short name T31
Test name
Test status
Simulation time 617264438 ps
CPU time 11.9 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 220484 kb
Host smart-0ba3fc50-c23e-44a8-b1ea-e65b406ce747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572048875 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2572048875
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4083172116
Short name T60
Test name
Test status
Simulation time 4069321549 ps
CPU time 15.21 seconds
Started Jul 21 05:38:50 PM PDT 24
Finished Jul 21 05:39:06 PM PDT 24
Peak memory 215572 kb
Host smart-c0dab07d-d6b5-4dcc-9a7c-4132e6017e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083172116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4083172116
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2350914400
Short name T13
Test name
Test status
Simulation time 682207489 ps
CPU time 19.53 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 239092 kb
Host smart-e82b4820-b017-428e-893c-bae6c574ac2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350914400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2350914400
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2548064903
Short name T55
Test name
Test status
Simulation time 1391419965 ps
CPU time 15.49 seconds
Started Jul 21 05:38:29 PM PDT 24
Finished Jul 21 05:38:45 PM PDT 24
Peak memory 221904 kb
Host smart-d096151c-42d4-49cd-8c40-0cc85f3b5983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548064903 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2548064903
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1011994609
Short name T101
Test name
Test status
Simulation time 6144469807 ps
CPU time 150.15 seconds
Started Jul 21 05:39:19 PM PDT 24
Finished Jul 21 05:41:50 PM PDT 24
Peak memory 222392 kb
Host smart-8199a68d-052d-4d97-8669-e248c10aebc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011994609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1011994609
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1775398786
Short name T21
Test name
Test status
Simulation time 65759769 ps
CPU time 1.96 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 222540 kb
Host smart-a9d58e6b-74c1-4310-87f2-333f68c0da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775398786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1775398786
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1982872287
Short name T73
Test name
Test status
Simulation time 1455089410 ps
CPU time 51.72 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 222220 kb
Host smart-f888a665-6f43-43c0-b249-8bf30b75deb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982872287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1982872287
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1517429755
Short name T16
Test name
Test status
Simulation time 43299884 ps
CPU time 2.14 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 222316 kb
Host smart-945b14f8-3d8b-41c3-a6ff-29260bc647f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517429755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1517429755
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2180081333
Short name T131
Test name
Test status
Simulation time 4231661805 ps
CPU time 14.24 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:38 PM PDT 24
Peak memory 214120 kb
Host smart-6bfc4f17-f789-4fcf-bd7e-6746ee35effa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180081333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2180081333
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.325471200
Short name T10
Test name
Test status
Simulation time 272434735 ps
CPU time 3.73 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 214368 kb
Host smart-fb2f5c78-d770-4bea-b41d-4d1a169466fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325471200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.325471200
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.525658896
Short name T153
Test name
Test status
Simulation time 3298795075 ps
CPU time 88.64 seconds
Started Jul 21 05:37:24 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 214972 kb
Host smart-4a85c189-dfb9-40a3-b698-b63431620b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525658896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.525658896
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1341060877
Short name T25
Test name
Test status
Simulation time 2449650075 ps
CPU time 21.09 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:47 PM PDT 24
Peak memory 222412 kb
Host smart-5c6930aa-1085-4f61-8266-e2f15c1cb37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341060877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1341060877
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2014559062
Short name T115
Test name
Test status
Simulation time 180404520 ps
CPU time 2.52 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 214748 kb
Host smart-59be67b6-1128-4df8-9e2d-b3d6f5e629f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014559062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2014559062
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.96543604
Short name T377
Test name
Test status
Simulation time 170507884 ps
CPU time 9.12 seconds
Started Jul 21 05:37:58 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 222180 kb
Host smart-7b2dbde2-49f8-4f5e-92e9-4c879ae43f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96543604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.96543604
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3958574324
Short name T172
Test name
Test status
Simulation time 162188335 ps
CPU time 5.55 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:35 PM PDT 24
Peak memory 214484 kb
Host smart-73fa20a3-b9dd-4c86-9a7b-60cd00af2859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958574324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3958574324
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.9174281
Short name T217
Test name
Test status
Simulation time 3311900079 ps
CPU time 64.23 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:37:39 PM PDT 24
Peak memory 215604 kb
Host smart-6274c913-0f11-46d1-983e-03291800a416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9174281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.9174281
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1408631977
Short name T6
Test name
Test status
Simulation time 723407813 ps
CPU time 10.03 seconds
Started Jul 21 05:38:16 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 222340 kb
Host smart-fa9c83a1-f9df-44d5-994a-54b604042b9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408631977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1408631977
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.571144507
Short name T296
Test name
Test status
Simulation time 60322041 ps
CPU time 4.1 seconds
Started Jul 21 05:37:58 PM PDT 24
Finished Jul 21 05:38:02 PM PDT 24
Peak memory 214124 kb
Host smart-e1dbe8c3-0a51-4dc1-851c-982d4c651c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571144507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.571144507
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1771158201
Short name T408
Test name
Test status
Simulation time 1208599971 ps
CPU time 10.04 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 214012 kb
Host smart-0d5d6783-7198-4679-8547-0102ac9c4b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771158201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1771158201
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2029767634
Short name T42
Test name
Test status
Simulation time 142670141 ps
CPU time 2.87 seconds
Started Jul 21 05:36:46 PM PDT 24
Finished Jul 21 05:36:50 PM PDT 24
Peak memory 222084 kb
Host smart-a4babf14-8fa7-4802-baa9-875f36050f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029767634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2029767634
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2291047331
Short name T103
Test name
Test status
Simulation time 1519083064 ps
CPU time 46.67 seconds
Started Jul 21 05:36:58 PM PDT 24
Finished Jul 21 05:37:45 PM PDT 24
Peak memory 221376 kb
Host smart-2e3b6b36-a908-4d01-874a-fc79b6552bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291047331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2291047331
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1018211617
Short name T285
Test name
Test status
Simulation time 2487500816 ps
CPU time 66.85 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:37:22 PM PDT 24
Peak memory 215356 kb
Host smart-edbdd77e-e9d3-471f-8ef1-a12b1df1ea48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018211617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1018211617
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1821643528
Short name T59
Test name
Test status
Simulation time 119283961 ps
CPU time 2.03 seconds
Started Jul 21 05:37:09 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 219852 kb
Host smart-b3190b36-d084-4449-8516-46bbb41b536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821643528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1821643528
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2645134077
Short name T23
Test name
Test status
Simulation time 51969147 ps
CPU time 3.42 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:30 PM PDT 24
Peak memory 209548 kb
Host smart-2f808290-7c34-49a3-ad06-7b9db01f3737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645134077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2645134077
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3605832510
Short name T118
Test name
Test status
Simulation time 840328131 ps
CPU time 5.54 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:35 PM PDT 24
Peak memory 214628 kb
Host smart-1a4d983e-743c-4040-9c04-ca74572e4da9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605832510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3605832510
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2214026619
Short name T46
Test name
Test status
Simulation time 100030455 ps
CPU time 2.01 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:05 PM PDT 24
Peak memory 209164 kb
Host smart-0c2d6dd3-c1a1-435c-a2b2-bb0bd80a0380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214026619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2214026619
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3982320437
Short name T74
Test name
Test status
Simulation time 4174110387 ps
CPU time 19.91 seconds
Started Jul 21 05:39:13 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 215096 kb
Host smart-f4d25052-3674-4dd3-8191-671fce33c34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982320437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3982320437
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.31560027
Short name T140
Test name
Test status
Simulation time 240882504 ps
CPU time 6.68 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 222512 kb
Host smart-2d5d411a-2fc3-42f7-8337-e2ac27f31152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31560027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.31560027
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1844825386
Short name T878
Test name
Test status
Simulation time 401824481 ps
CPU time 11.05 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 222152 kb
Host smart-28e25e6c-ef33-429a-a068-845f11a835bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844825386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1844825386
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2452905262
Short name T34
Test name
Test status
Simulation time 81696397 ps
CPU time 2.73 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 210064 kb
Host smart-1251ca3b-5671-425c-b39d-b830d2b85b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452905262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2452905262
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2036194309
Short name T415
Test name
Test status
Simulation time 117938240 ps
CPU time 4.36 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 214216 kb
Host smart-76d6ad90-98da-4d08-8dd3-1e6294b4160c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036194309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2036194309
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1306176945
Short name T66
Test name
Test status
Simulation time 5701589751 ps
CPU time 8.05 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 211292 kb
Host smart-fd8534a3-7364-4f03-b812-bd459c3c12d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306176945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1306176945
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2541571777
Short name T62
Test name
Test status
Simulation time 1932098734 ps
CPU time 23.14 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:57 PM PDT 24
Peak memory 222292 kb
Host smart-17dee033-8546-46b2-946e-af18e7a5b42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541571777 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2541571777
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2802141619
Short name T229
Test name
Test status
Simulation time 817977504 ps
CPU time 17 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 216284 kb
Host smart-15d32062-e2e3-42a9-84c9-79a418f6aff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802141619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2802141619
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1963552423
Short name T19
Test name
Test status
Simulation time 140256877 ps
CPU time 0.88 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:21 PM PDT 24
Peak memory 205820 kb
Host smart-ec8b89a9-58e4-4f70-ae9f-1ec2ab54ed7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963552423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1963552423
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3378332101
Short name T270
Test name
Test status
Simulation time 1639951547 ps
CPU time 21.44 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:54 PM PDT 24
Peak memory 216096 kb
Host smart-19f5e300-2254-41d7-980b-3051c3d31ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378332101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3378332101
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3869520305
Short name T151
Test name
Test status
Simulation time 772993583 ps
CPU time 11.54 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:17 PM PDT 24
Peak memory 214064 kb
Host smart-f7e5e019-bb0c-4582-91ef-6f2c7477d3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869520305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3869520305
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2600265401
Short name T232
Test name
Test status
Simulation time 6343209934 ps
CPU time 65.16 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:40:10 PM PDT 24
Peak memory 216620 kb
Host smart-3a9bbc8c-d9c6-4fb4-8e8a-f807b8396319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600265401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2600265401
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1063018869
Short name T114
Test name
Test status
Simulation time 927825648 ps
CPU time 3.42 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214744 kb
Host smart-a65dbb6e-77ae-4805-933c-9c463b5874a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063018869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1063018869
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2645306455
Short name T300
Test name
Test status
Simulation time 180577198 ps
CPU time 3.22 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 213944 kb
Host smart-515fdde6-1971-44e6-af0f-db2cb11d8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645306455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2645306455
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2931730883
Short name T238
Test name
Test status
Simulation time 513509091 ps
CPU time 13.74 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 214032 kb
Host smart-a546b3b4-1a55-4498-9087-afea4b9f27bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931730883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2931730883
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3222230903
Short name T783
Test name
Test status
Simulation time 320678416 ps
CPU time 2.96 seconds
Started Jul 21 05:37:43 PM PDT 24
Finished Jul 21 05:37:46 PM PDT 24
Peak memory 221144 kb
Host smart-b7027406-0e48-4592-a93b-538db665087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222230903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3222230903
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1442749897
Short name T220
Test name
Test status
Simulation time 2052999218 ps
CPU time 27.93 seconds
Started Jul 21 05:38:14 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 222116 kb
Host smart-55380657-57d9-4828-943b-9a245f442f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442749897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1442749897
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4060181035
Short name T174
Test name
Test status
Simulation time 574047527 ps
CPU time 12.79 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:39:07 PM PDT 24
Peak memory 220384 kb
Host smart-df8ba3b4-4400-4ccd-8b17-7c95ec8e1af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060181035 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4060181035
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2213741566
Short name T183
Test name
Test status
Simulation time 401680075 ps
CPU time 6.15 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 214436 kb
Host smart-18a083de-a9c3-42c1-ac42-b46223053b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213741566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2213741566
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1658587957
Short name T167
Test name
Test status
Simulation time 249591490 ps
CPU time 5.1 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:58 PM PDT 24
Peak memory 214368 kb
Host smart-ce35353a-2310-4235-9f07-1933ef7a121a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658587957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1658587957
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1610436914
Short name T185
Test name
Test status
Simulation time 1437306596 ps
CPU time 6.02 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 206292 kb
Host smart-5a2fa412-b355-4141-ba9a-5c5da0d3d781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610436914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1610436914
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1380544182
Short name T387
Test name
Test status
Simulation time 64567665 ps
CPU time 2.98 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 207656 kb
Host smart-4928fd7a-c2e8-4d6d-8342-fc302bd4bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380544182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1380544182
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.574934551
Short name T57
Test name
Test status
Simulation time 59852196 ps
CPU time 2.05 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 214088 kb
Host smart-504a3708-13d9-4744-b332-18d52de8e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574934551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.574934551
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1738707067
Short name T156
Test name
Test status
Simulation time 146262818 ps
CPU time 4.65 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 218092 kb
Host smart-0f5d998d-5249-4eb6-ae5f-457cb37d5047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738707067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1738707067
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2239514763
Short name T161
Test name
Test status
Simulation time 300490393 ps
CPU time 2.25 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 217268 kb
Host smart-4e8daaf9-5c8e-42a8-87ac-e834c69c3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239514763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2239514763
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1300450923
Short name T159
Test name
Test status
Simulation time 75340756 ps
CPU time 3.72 seconds
Started Jul 21 05:38:38 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 217448 kb
Host smart-188d77c5-53b1-4eea-a1e0-ff794ed870f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300450923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1300450923
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4254171168
Short name T589
Test name
Test status
Simulation time 135286543 ps
CPU time 2.11 seconds
Started Jul 21 05:37:10 PM PDT 24
Finished Jul 21 05:37:13 PM PDT 24
Peak memory 214000 kb
Host smart-ad9a62d7-fb63-475f-9998-f983b2e514ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254171168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4254171168
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3673065854
Short name T284
Test name
Test status
Simulation time 578611827 ps
CPU time 4.96 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:27 PM PDT 24
Peak memory 213932 kb
Host smart-36582cf2-90b4-449e-ad0c-598e4548b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673065854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3673065854
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2864173222
Short name T388
Test name
Test status
Simulation time 104121760 ps
CPU time 2.42 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 210036 kb
Host smart-36532f2c-ecae-410d-9e64-54003801d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864173222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2864173222
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3633054751
Short name T782
Test name
Test status
Simulation time 2935781660 ps
CPU time 30.38 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 216892 kb
Host smart-d7f11dc4-1c6a-47e1-b2b9-771c2c2fb157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633054751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3633054751
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1777467877
Short name T204
Test name
Test status
Simulation time 3111436757 ps
CPU time 41.96 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 215384 kb
Host smart-98edba1b-1241-4c03-b60f-fffd6b52fc25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777467877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1777467877
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2670886297
Short name T91
Test name
Test status
Simulation time 201856970 ps
CPU time 4.67 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:26 PM PDT 24
Peak memory 214076 kb
Host smart-9a8c938b-1556-498f-a56a-fb137cf881ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670886297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2670886297
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2732355725
Short name T179
Test name
Test status
Simulation time 250173633 ps
CPU time 4.95 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 206168 kb
Host smart-00979924-859c-4e94-9099-bbd0a5283fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732355725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2732355725
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2868834423
Short name T176
Test name
Test status
Simulation time 770494075 ps
CPU time 8.14 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 214452 kb
Host smart-c4e8e337-9f8b-4ab1-8e3b-27ecc4710b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868834423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2868834423
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1459710517
Short name T164
Test name
Test status
Simulation time 70171675 ps
CPU time 2.42 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:30 PM PDT 24
Peak memory 214864 kb
Host smart-77034ee8-8d65-43d6-8de9-bfc0c55910c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459710517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1459710517
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3836826626
Short name T157
Test name
Test status
Simulation time 373498715 ps
CPU time 4.4 seconds
Started Jul 21 05:39:03 PM PDT 24
Finished Jul 21 05:39:08 PM PDT 24
Peak memory 217620 kb
Host smart-8a017018-79f2-4ded-a942-4b600799f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836826626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3836826626
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3706279360
Short name T405
Test name
Test status
Simulation time 2994431962 ps
CPU time 14.13 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 215416 kb
Host smart-2e6b0eb5-bcb0-45b0-a0ef-8f3be90f230a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706279360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3706279360
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3786934540
Short name T287
Test name
Test status
Simulation time 1556212718 ps
CPU time 13.42 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 215600 kb
Host smart-ea94f4bd-f9bd-496a-bb65-58c1b5f81ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786934540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3786934540
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2584090452
Short name T302
Test name
Test status
Simulation time 365172700 ps
CPU time 3.62 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 213884 kb
Host smart-b9dcd024-76ad-4622-9d2a-97d29d1374e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584090452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2584090452
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3694669135
Short name T39
Test name
Test status
Simulation time 137877665 ps
CPU time 2.95 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:02 PM PDT 24
Peak memory 206720 kb
Host smart-ea6c69c9-c273-455c-948c-70b3766053e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694669135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3694669135
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.352305458
Short name T214
Test name
Test status
Simulation time 125303576 ps
CPU time 5.88 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 214136 kb
Host smart-90a02682-b67d-4c7c-9fb1-28273b3a3193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352305458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.352305458
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2171224268
Short name T152
Test name
Test status
Simulation time 348261536 ps
CPU time 3.98 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 215316 kb
Host smart-280981a1-c414-4f9f-bc57-f713a3247490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171224268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2171224268
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1053218758
Short name T158
Test name
Test status
Simulation time 66590990 ps
CPU time 2.8 seconds
Started Jul 21 05:36:35 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 215648 kb
Host smart-b4172ae5-bdd9-40b6-9cb4-0eff2e9fc04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053218758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1053218758
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2632308890
Short name T160
Test name
Test status
Simulation time 59142119 ps
CPU time 2.55 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 222432 kb
Host smart-6851df05-2817-4756-a0ac-494a4351d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632308890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2632308890
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4156262827
Short name T412
Test name
Test status
Simulation time 136024590 ps
CPU time 2.92 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 214812 kb
Host smart-8d0ef2dc-b219-4ca8-a2fe-2ec9c94f626a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156262827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4156262827
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2148709436
Short name T225
Test name
Test status
Simulation time 421468266 ps
CPU time 4.79 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:27 PM PDT 24
Peak memory 222136 kb
Host smart-cca9274d-fc45-4b31-a0c5-02d0c14182a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148709436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2148709436
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4005800841
Short name T345
Test name
Test status
Simulation time 87591758 ps
CPU time 2.23 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:28 PM PDT 24
Peak memory 205996 kb
Host smart-b585bbdf-0495-47b3-8946-2e9c4c5bb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005800841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4005800841
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1395049423
Short name T866
Test name
Test status
Simulation time 90943158 ps
CPU time 3.06 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 213988 kb
Host smart-7bc923d8-28ca-4ef9-a6e1-7324afe0620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395049423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1395049423
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1207464934
Short name T309
Test name
Test status
Simulation time 121946358 ps
CPU time 6.88 seconds
Started Jul 21 05:38:27 PM PDT 24
Finished Jul 21 05:38:35 PM PDT 24
Peak memory 222300 kb
Host smart-a001fbd6-177a-4dd6-88e5-8ce4ebac2498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207464934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1207464934
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2117721169
Short name T155
Test name
Test status
Simulation time 55852485 ps
CPU time 3.89 seconds
Started Jul 21 05:38:44 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 215280 kb
Host smart-e8e8cc9d-eef3-4551-b06b-8bfe2e8afbc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117721169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2117721169
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1117153148
Short name T601
Test name
Test status
Simulation time 1308843189 ps
CPU time 12.41 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:39:07 PM PDT 24
Peak memory 210516 kb
Host smart-1959ea3d-b8c2-4ff4-82e3-42e087538314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117153148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1117153148
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1360474654
Short name T170
Test name
Test status
Simulation time 231190206 ps
CPU time 4.76 seconds
Started Jul 21 06:23:31 PM PDT 24
Finished Jul 21 06:23:46 PM PDT 24
Peak memory 215816 kb
Host smart-80d37aec-41ea-4151-a980-d266102e2dce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360474654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1360474654
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2214069466
Short name T187
Test name
Test status
Simulation time 323813828 ps
CPU time 6.55 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:49 PM PDT 24
Peak memory 214364 kb
Host smart-9febf3b0-625a-4ea7-91d3-b1ef011ae43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214069466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2214069466
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1530085924
Short name T175
Test name
Test status
Simulation time 143952587 ps
CPU time 3.53 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 214436 kb
Host smart-d7716797-6e72-40a8-aa6f-41616269e776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530085924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1530085924
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4239455783
Short name T14
Test name
Test status
Simulation time 592434448 ps
CPU time 6.95 seconds
Started Jul 21 05:36:18 PM PDT 24
Finished Jul 21 05:36:25 PM PDT 24
Peak memory 237800 kb
Host smart-42eeb346-6650-4a3b-aeac-b76d776020d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239455783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4239455783
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3270130227
Short name T162
Test name
Test status
Simulation time 381878790 ps
CPU time 11.8 seconds
Started Jul 21 05:37:55 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 222412 kb
Host smart-2462f960-f8d2-4014-9baf-481b24106e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270130227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3270130227
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3198556023
Short name T268
Test name
Test status
Simulation time 2828486433 ps
CPU time 27.84 seconds
Started Jul 21 05:36:18 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 208356 kb
Host smart-800c00a0-a922-49b6-8619-c6f6fb58d1e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198556023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3198556023
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4113956675
Short name T251
Test name
Test status
Simulation time 156993910 ps
CPU time 4 seconds
Started Jul 21 05:36:21 PM PDT 24
Finished Jul 21 05:36:25 PM PDT 24
Peak memory 218304 kb
Host smart-f64cb57b-a8ef-465b-98a3-d9d859c02c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113956675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4113956675
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3207284860
Short name T231
Test name
Test status
Simulation time 288766301 ps
CPU time 3.81 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:57 PM PDT 24
Peak memory 210060 kb
Host smart-cfc12d23-29c8-48bf-8907-74a502efd466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207284860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3207284860
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3810790054
Short name T235
Test name
Test status
Simulation time 168883756 ps
CPU time 3.51 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:06 PM PDT 24
Peak memory 207624 kb
Host smart-3e5c17e3-a430-48f4-ba62-1052c77249da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810790054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3810790054
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3174619018
Short name T255
Test name
Test status
Simulation time 498994683 ps
CPU time 6.77 seconds
Started Jul 21 05:36:59 PM PDT 24
Finished Jul 21 05:37:06 PM PDT 24
Peak memory 207640 kb
Host smart-8c24c804-57ae-496b-b066-d68425fee0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174619018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3174619018
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2039828063
Short name T87
Test name
Test status
Simulation time 531707038 ps
CPU time 4.13 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:04 PM PDT 24
Peak memory 206572 kb
Host smart-7af9eff6-b6eb-4dcb-af9e-5f9ba739a114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039828063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2039828063
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3301864366
Short name T352
Test name
Test status
Simulation time 190461990 ps
CPU time 3.49 seconds
Started Jul 21 05:36:58 PM PDT 24
Finished Jul 21 05:37:02 PM PDT 24
Peak memory 214792 kb
Host smart-d9161d61-8622-432f-8c90-81fe729d27e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301864366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3301864366
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2813264851
Short name T353
Test name
Test status
Simulation time 187912248 ps
CPU time 5.59 seconds
Started Jul 21 05:37:08 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 215728 kb
Host smart-4a4306bc-e57f-48f8-8091-a1ba4b92d1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813264851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2813264851
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.573244059
Short name T336
Test name
Test status
Simulation time 1276046836 ps
CPU time 67.48 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:38:11 PM PDT 24
Peak memory 214372 kb
Host smart-2d3f80fb-f848-4e56-b2fe-7822ab14a830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573244059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.573244059
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3394381752
Short name T53
Test name
Test status
Simulation time 236359414 ps
CPU time 2.72 seconds
Started Jul 21 05:37:09 PM PDT 24
Finished Jul 21 05:37:12 PM PDT 24
Peak memory 218696 kb
Host smart-d2e1233e-7943-4386-ab53-a929b3e659dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394381752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3394381752
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1302363016
Short name T344
Test name
Test status
Simulation time 127321503 ps
CPU time 3.74 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 209468 kb
Host smart-c1d29409-6a00-4b2f-b6d0-2f43335ad58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302363016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1302363016
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1270666554
Short name T357
Test name
Test status
Simulation time 52549812 ps
CPU time 2.92 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:24 PM PDT 24
Peak memory 208992 kb
Host smart-b7cc2a5d-c953-4679-92bc-5690b9c91610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270666554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1270666554
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2687400136
Short name T263
Test name
Test status
Simulation time 55551298 ps
CPU time 2.45 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:30 PM PDT 24
Peak memory 222112 kb
Host smart-c563aa3c-7a9a-4405-9ef4-91c95ecb3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687400136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2687400136
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3092197924
Short name T201
Test name
Test status
Simulation time 4196914201 ps
CPU time 37.37 seconds
Started Jul 21 05:37:55 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 216308 kb
Host smart-19af65c6-1b1a-4bb8-9921-369c273407ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092197924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3092197924
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1306360868
Short name T261
Test name
Test status
Simulation time 142523467 ps
CPU time 4.18 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 214092 kb
Host smart-2b1fc921-1fa1-42f5-8e05-a2b27b9199de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306360868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1306360868
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1168697833
Short name T273
Test name
Test status
Simulation time 2887837170 ps
CPU time 40.63 seconds
Started Jul 21 05:36:29 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 214540 kb
Host smart-29ee609a-f05e-4f42-bc40-0f462c460cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168697833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1168697833
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2764806419
Short name T100
Test name
Test status
Simulation time 49427861 ps
CPU time 3.24 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 222228 kb
Host smart-10e6b33b-153c-4c28-ae07-7b0a49b44d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764806419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2764806419
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3773558391
Short name T213
Test name
Test status
Simulation time 73643008 ps
CPU time 3.36 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 208408 kb
Host smart-46499d70-4af0-45fd-9d6a-617af0831423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773558391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3773558391
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2817890786
Short name T84
Test name
Test status
Simulation time 3906934813 ps
CPU time 70.7 seconds
Started Jul 21 05:38:27 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 215856 kb
Host smart-a0079845-a20f-4660-aca3-4c889f46437c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817890786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2817890786
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2510888712
Short name T311
Test name
Test status
Simulation time 1197140813 ps
CPU time 31.45 seconds
Started Jul 21 05:38:27 PM PDT 24
Finished Jul 21 05:38:59 PM PDT 24
Peak memory 213968 kb
Host smart-55a21185-0d79-4989-a082-496891ab651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510888712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2510888712
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3938679564
Short name T312
Test name
Test status
Simulation time 6982559376 ps
CPU time 19.51 seconds
Started Jul 21 05:38:35 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 215248 kb
Host smart-7626602a-588e-4e09-a861-8a1acf8ed9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938679564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3938679564
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2484839435
Short name T230
Test name
Test status
Simulation time 1226394564 ps
CPU time 19.95 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 222160 kb
Host smart-2889476b-ad63-45fd-8de0-c34fc0b7b43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484839435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2484839435
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.384934268
Short name T163
Test name
Test status
Simulation time 231055028 ps
CPU time 4.4 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:26 PM PDT 24
Peak memory 217692 kb
Host smart-919d36bc-d139-44f9-b649-b0962ba4a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384934268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.384934268
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1305445959
Short name T148
Test name
Test status
Simulation time 272376389 ps
CPU time 4.16 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 206236 kb
Host smart-ed676532-b5f2-4adc-bbc8-f09f02d70f3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305445959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
305445959
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2904258071
Short name T942
Test name
Test status
Simulation time 1309936112 ps
CPU time 31.94 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:58 PM PDT 24
Peak memory 206232 kb
Host smart-b4c62fc2-0adc-4f77-87e5-1b8516415da7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904258071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
904258071
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.541445551
Short name T987
Test name
Test status
Simulation time 30366540 ps
CPU time 1.43 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:25 PM PDT 24
Peak memory 206236 kb
Host smart-7bb204ab-edd9-447e-a8ba-2ae25e9d1998
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541445551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.541445551
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1613831004
Short name T936
Test name
Test status
Simulation time 50874637 ps
CPU time 1.49 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 206300 kb
Host smart-36621e4f-4c89-4e72-b4be-782e43132802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613831004 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1613831004
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1119594466
Short name T1008
Test name
Test status
Simulation time 43880043 ps
CPU time 0.88 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 206084 kb
Host smart-2bccd607-2c9d-4af2-8ad8-6148edab659a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119594466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1119594466
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3637081351
Short name T1080
Test name
Test status
Simulation time 12149855 ps
CPU time 0.78 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 206092 kb
Host smart-4f9687dd-f826-49e6-982b-e5415c224d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637081351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3637081351
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1712888039
Short name T983
Test name
Test status
Simulation time 232352459 ps
CPU time 2.61 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 206292 kb
Host smart-325a21d5-fc19-4a30-b7ae-b4ae5a4a31e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712888039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1712888039
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2594353557
Short name T1025
Test name
Test status
Simulation time 366450905 ps
CPU time 3.52 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:28 PM PDT 24
Peak memory 214636 kb
Host smart-b246ecb6-1abe-4b93-add6-757375967e60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594353557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2594353557
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2418654381
Short name T1070
Test name
Test status
Simulation time 165867655 ps
CPU time 6.69 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:30 PM PDT 24
Peak memory 220828 kb
Host smart-d44002b6-31dc-478e-8b1f-b47a62538df4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418654381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2418654381
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.235432601
Short name T947
Test name
Test status
Simulation time 39599014 ps
CPU time 2.78 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:28 PM PDT 24
Peak memory 217436 kb
Host smart-d5d2170a-fc62-4afb-ae47-3bbac9c38023
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235432601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.235432601
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.961607732
Short name T182
Test name
Test status
Simulation time 77534838 ps
CPU time 2.67 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:28 PM PDT 24
Peak memory 214432 kb
Host smart-ec750223-38df-4ca7-ba73-96a136d70439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961607732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
961607732
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.878598828
Short name T969
Test name
Test status
Simulation time 139247357 ps
CPU time 7.53 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 206208 kb
Host smart-34f5c7e9-056a-4648-b76a-f7414b38c0fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878598828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.878598828
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.297807503
Short name T952
Test name
Test status
Simulation time 873270584 ps
CPU time 14.17 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 206216 kb
Host smart-d39ad361-b8ea-471c-9b64-4e94d08c313b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297807503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.297807503
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2671914712
Short name T1029
Test name
Test status
Simulation time 67193112 ps
CPU time 1.01 seconds
Started Jul 21 06:23:11 PM PDT 24
Finished Jul 21 06:23:28 PM PDT 24
Peak memory 206072 kb
Host smart-3c344462-a720-4e9a-bc2b-80e900f63d03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671914712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
671914712
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3075398632
Short name T1067
Test name
Test status
Simulation time 26551322 ps
CPU time 1.47 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 214576 kb
Host smart-928468b6-0a5b-4c88-aafe-875a781bb42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075398632 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3075398632
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.948405692
Short name T1056
Test name
Test status
Simulation time 27871160 ps
CPU time 1.06 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 206160 kb
Host smart-5bbc0cd6-4d09-494b-8f04-cacff04c8d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948405692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.948405692
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4181889587
Short name T1081
Test name
Test status
Simulation time 37358525 ps
CPU time 0.72 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 206092 kb
Host smart-4914e034-8d6b-4677-a207-fbdf8b7fd29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181889587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4181889587
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1758370484
Short name T1043
Test name
Test status
Simulation time 81489577 ps
CPU time 1.35 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 206236 kb
Host smart-a0ac883c-c747-4013-bb7c-7eada3f16515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758370484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1758370484
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1208481904
Short name T1028
Test name
Test status
Simulation time 50768745 ps
CPU time 2.13 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:28 PM PDT 24
Peak memory 214732 kb
Host smart-83060e2e-31e7-4139-8b77-c4c6ac526a42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208481904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1208481904
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.183900919
Short name T1062
Test name
Test status
Simulation time 202002324 ps
CPU time 4.68 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 214568 kb
Host smart-6fa8e507-30df-4d4d-b6d1-f1da05d92dec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183900919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.183900919
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1115411311
Short name T1038
Test name
Test status
Simulation time 147300712 ps
CPU time 2.5 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 222648 kb
Host smart-a36d94a8-afb5-4eb8-80db-e20d11e07e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115411311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1115411311
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.278496230
Short name T184
Test name
Test status
Simulation time 113176493 ps
CPU time 4.93 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:30 PM PDT 24
Peak memory 206224 kb
Host smart-09eaf6b1-0522-4ca6-97df-779ba46e8723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278496230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
278496230
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3048762615
Short name T953
Test name
Test status
Simulation time 123903778 ps
CPU time 1.29 seconds
Started Jul 21 06:23:25 PM PDT 24
Finished Jul 21 06:23:39 PM PDT 24
Peak memory 206332 kb
Host smart-ebc3aa71-a061-4f53-b380-e7cd5ce9ec9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048762615 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3048762615
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2130544781
Short name T954
Test name
Test status
Simulation time 89068269 ps
CPU time 1.16 seconds
Started Jul 21 06:23:25 PM PDT 24
Finished Jul 21 06:23:39 PM PDT 24
Peak memory 206164 kb
Host smart-3609b305-9f4c-4600-8dea-520149bac2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130544781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2130544781
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3607057291
Short name T1048
Test name
Test status
Simulation time 21935205 ps
CPU time 0.76 seconds
Started Jul 21 06:23:31 PM PDT 24
Finished Jul 21 06:23:42 PM PDT 24
Peak memory 206008 kb
Host smart-47a518d4-a543-496b-8d46-c80a68302603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607057291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3607057291
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.841697220
Short name T144
Test name
Test status
Simulation time 332348637 ps
CPU time 2.95 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 206232 kb
Host smart-99950746-100e-41bf-9020-18167654bf8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841697220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.841697220
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3071879563
Short name T120
Test name
Test status
Simulation time 96275142 ps
CPU time 3.47 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214592 kb
Host smart-0bef5c40-5ce0-44f8-b69c-962db118a31b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071879563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3071879563
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.785586205
Short name T1045
Test name
Test status
Simulation time 371112873 ps
CPU time 7.88 seconds
Started Jul 21 06:23:25 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214592 kb
Host smart-adf80a8e-fd23-4829-aab2-ab2276c1780e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785586205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.785586205
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2684612138
Short name T1076
Test name
Test status
Simulation time 137330189 ps
CPU time 3.45 seconds
Started Jul 21 06:23:26 PM PDT 24
Finished Jul 21 06:23:42 PM PDT 24
Peak memory 217780 kb
Host smart-79fb16ab-cd26-4e89-ba40-2f34eaece5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684612138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2684612138
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2733564207
Short name T938
Test name
Test status
Simulation time 207367542 ps
CPU time 2.08 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 206344 kb
Host smart-a82f6303-cf1b-4de9-8569-c5654897c6cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733564207 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2733564207
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1584170580
Short name T142
Test name
Test status
Simulation time 35994909 ps
CPU time 0.88 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:43 PM PDT 24
Peak memory 206104 kb
Host smart-9186b416-8f69-4c63-8178-562cf4c9ae8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584170580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1584170580
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3415889404
Short name T1035
Test name
Test status
Simulation time 140426814 ps
CPU time 0.94 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 206064 kb
Host smart-203e479f-64ae-4773-b0d0-7662d1b23c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415889404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3415889404
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2646629825
Short name T968
Test name
Test status
Simulation time 206712569 ps
CPU time 1.85 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:43 PM PDT 24
Peak memory 206220 kb
Host smart-ae40082d-169b-4d39-be88-c0e4452f302e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646629825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2646629825
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2844018118
Short name T1011
Test name
Test status
Simulation time 217955859 ps
CPU time 1.79 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214580 kb
Host smart-620ee6b9-7b54-4cb1-a9bb-9cc076e7d588
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844018118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2844018118
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3528331981
Short name T991
Test name
Test status
Simulation time 87714356 ps
CPU time 4.91 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 220928 kb
Host smart-981e3c22-6ee1-4174-871a-d72f358e5445
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528331981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3528331981
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.243145082
Short name T967
Test name
Test status
Simulation time 755773274 ps
CPU time 2.58 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:46 PM PDT 24
Peak memory 214416 kb
Host smart-7d8474f1-9205-4760-a93f-d33fb242280c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243145082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.243145082
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3693563476
Short name T958
Test name
Test status
Simulation time 45692961 ps
CPU time 1.47 seconds
Started Jul 21 06:23:35 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214564 kb
Host smart-584ef698-1348-475f-9705-0159b0c89fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693563476 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3693563476
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3762972369
Short name T994
Test name
Test status
Simulation time 50358475 ps
CPU time 1.25 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 206300 kb
Host smart-1fb69928-c3d5-4fc2-8645-cdaa5d010563
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762972369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3762972369
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1135868087
Short name T1010
Test name
Test status
Simulation time 8025053 ps
CPU time 0.87 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 206008 kb
Host smart-d0751d44-508b-40ef-906e-29bd74cb388c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135868087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1135868087
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1844669537
Short name T1019
Test name
Test status
Simulation time 143086386 ps
CPU time 2.55 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 206224 kb
Host smart-380b773e-3227-4453-8143-8f09ba0bca04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844669537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1844669537
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1257210848
Short name T1058
Test name
Test status
Simulation time 137448135 ps
CPU time 2.95 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214564 kb
Host smart-e66273a9-2a60-48de-8177-ab7b502d76a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257210848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1257210848
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3984347109
Short name T971
Test name
Test status
Simulation time 1426091024 ps
CPU time 8.41 seconds
Started Jul 21 06:23:32 PM PDT 24
Finished Jul 21 06:23:50 PM PDT 24
Peak memory 214664 kb
Host smart-defabf69-ce0a-4988-8417-b4b11b7fc6b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984347109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3984347109
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1650539261
Short name T972
Test name
Test status
Simulation time 278233630 ps
CPU time 1.98 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 214396 kb
Host smart-6a565469-77f2-4770-af07-f2752898f267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650539261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1650539261
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.759135186
Short name T960
Test name
Test status
Simulation time 55452582 ps
CPU time 1.65 seconds
Started Jul 21 06:23:43 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 214504 kb
Host smart-f04e4844-5562-4ce6-a650-41227ea922b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759135186 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.759135186
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.897138174
Short name T1061
Test name
Test status
Simulation time 86350444 ps
CPU time 1.12 seconds
Started Jul 21 06:23:43 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 206100 kb
Host smart-7d09d25f-3a54-4520-a2e8-383ff17fa152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897138174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.897138174
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2464580451
Short name T1033
Test name
Test status
Simulation time 11935626 ps
CPU time 0.73 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:46 PM PDT 24
Peak memory 206012 kb
Host smart-bb3552d8-d589-4381-a746-4483c759f0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464580451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2464580451
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.946459702
Short name T1036
Test name
Test status
Simulation time 38986212 ps
CPU time 2.54 seconds
Started Jul 21 06:23:39 PM PDT 24
Finished Jul 21 06:23:50 PM PDT 24
Peak memory 206404 kb
Host smart-0bc3c9ef-d490-4240-b6ce-ec80e3dafff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946459702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.946459702
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3927770129
Short name T1065
Test name
Test status
Simulation time 162197787 ps
CPU time 8.07 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 222852 kb
Host smart-44ddcbc5-55ca-4649-a359-296925cc6541
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927770129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3927770129
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.945551554
Short name T921
Test name
Test status
Simulation time 114705050 ps
CPU time 1.86 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 214460 kb
Host smart-4d8ac34e-17e1-46ed-9fd6-56e4e14ff863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945551554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.945551554
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.21215893
Short name T1075
Test name
Test status
Simulation time 56456027 ps
CPU time 2.02 seconds
Started Jul 21 06:23:43 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 214436 kb
Host smart-577f0422-7a9a-4be6-8da9-ec566aebc118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215893 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.21215893
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2055546077
Short name T986
Test name
Test status
Simulation time 20350640 ps
CPU time 1.17 seconds
Started Jul 21 06:23:41 PM PDT 24
Finished Jul 21 06:23:50 PM PDT 24
Peak memory 206260 kb
Host smart-9d286ac6-63ab-470d-996c-45c7c62bcd9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055546077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2055546077
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1391951088
Short name T931
Test name
Test status
Simulation time 37029142 ps
CPU time 0.69 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 205896 kb
Host smart-5ea03817-e364-4bc9-8538-9ae29110a12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391951088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1391951088
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2298219341
Short name T984
Test name
Test status
Simulation time 434728818 ps
CPU time 3.75 seconds
Started Jul 21 06:23:39 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 206240 kb
Host smart-7669999a-df8a-4ee4-8e2d-e4fab7c623ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298219341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2298219341
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3280638388
Short name T117
Test name
Test status
Simulation time 75597780 ps
CPU time 2.52 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:49 PM PDT 24
Peak memory 214668 kb
Host smart-8f3aef2b-a0b0-49da-a04f-48d806f375bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280638388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3280638388
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2271648700
Short name T1032
Test name
Test status
Simulation time 85842984 ps
CPU time 3.87 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:50 PM PDT 24
Peak memory 214696 kb
Host smart-9ee60541-ce59-4b9c-9f56-b31402a470b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271648700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2271648700
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2967609000
Short name T950
Test name
Test status
Simulation time 706265200 ps
CPU time 2.36 seconds
Started Jul 21 06:23:36 PM PDT 24
Finished Jul 21 06:23:47 PM PDT 24
Peak memory 215428 kb
Host smart-f4fb4b65-9f45-4dfe-8932-75102ac3c348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967609000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2967609000
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2352446066
Short name T168
Test name
Test status
Simulation time 144055758 ps
CPU time 6.29 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 214364 kb
Host smart-83bab408-86be-4ee3-b267-85bb2ff0a954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352446066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2352446066
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3640975791
Short name T1069
Test name
Test status
Simulation time 38395973 ps
CPU time 2.13 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:49 PM PDT 24
Peak memory 214552 kb
Host smart-e8b66d64-937d-4221-80d0-43d98712e1d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640975791 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3640975791
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1319817899
Short name T145
Test name
Test status
Simulation time 102747103 ps
CPU time 1.48 seconds
Started Jul 21 06:23:39 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 206140 kb
Host smart-a84f9227-aeb8-45a8-ab93-02746c7cfce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319817899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1319817899
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3308904118
Short name T918
Test name
Test status
Simulation time 8348092 ps
CPU time 0.83 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:48 PM PDT 24
Peak memory 206040 kb
Host smart-0f5fe1b8-6612-4df3-b532-f09c167db1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308904118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3308904118
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.20056305
Short name T1015
Test name
Test status
Simulation time 55443751 ps
CPU time 1.68 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206116 kb
Host smart-473d7030-8cdf-473d-a2ba-d0b866376a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20056305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sam
e_csr_outstanding.20056305
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4126712319
Short name T1059
Test name
Test status
Simulation time 311129791 ps
CPU time 4.56 seconds
Started Jul 21 06:23:39 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 214628 kb
Host smart-40d49dd9-e28e-43c5-90fd-cf3eaab7c626
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126712319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4126712319
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2887075552
Short name T963
Test name
Test status
Simulation time 188424290 ps
CPU time 4.69 seconds
Started Jul 21 06:23:42 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 214580 kb
Host smart-e0bba316-5bc3-4a3a-9a8c-7c3866f699f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887075552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2887075552
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2829353206
Short name T937
Test name
Test status
Simulation time 557278110 ps
CPU time 2.22 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:47 PM PDT 24
Peak memory 217204 kb
Host smart-a8cb4c07-e325-41f1-9f68-ab1338b450ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829353206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2829353206
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3736709485
Short name T955
Test name
Test status
Simulation time 56142431 ps
CPU time 2.98 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:49 PM PDT 24
Peak memory 214292 kb
Host smart-f6babf38-1de8-43e2-b102-8a44c16a30eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736709485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3736709485
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2810677159
Short name T943
Test name
Test status
Simulation time 224691213 ps
CPU time 1.68 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 214636 kb
Host smart-5d286ce2-1367-4e00-b4a0-90c206f0df9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810677159 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2810677159
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2720610051
Short name T1079
Test name
Test status
Simulation time 43418376 ps
CPU time 0.95 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206104 kb
Host smart-f8cdc7f6-15c5-45f0-a16e-a0841d87ea0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720610051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2720610051
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1655024257
Short name T924
Test name
Test status
Simulation time 25931682 ps
CPU time 0.75 seconds
Started Jul 21 06:23:38 PM PDT 24
Finished Jul 21 06:23:47 PM PDT 24
Peak memory 206032 kb
Host smart-b28b5a64-d1a2-489b-9c6a-c17a5d771c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655024257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1655024257
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2369828118
Short name T1014
Test name
Test status
Simulation time 58009797 ps
CPU time 2.45 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 206148 kb
Host smart-fc74d585-fde3-449e-8690-9bee1b8f2b2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369828118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2369828118
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1047340358
Short name T944
Test name
Test status
Simulation time 79369632 ps
CPU time 2.69 seconds
Started Jul 21 06:23:42 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 218876 kb
Host smart-d09dc3b4-eaf7-4143-a20e-eb2cbc2c493a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047340358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1047340358
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1479306410
Short name T1020
Test name
Test status
Simulation time 261922233 ps
CPU time 5.05 seconds
Started Jul 21 06:23:39 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 214608 kb
Host smart-c50f4612-d6a9-478a-83fb-43ef134e5b4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479306410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1479306410
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3691393188
Short name T964
Test name
Test status
Simulation time 63151036 ps
CPU time 2.83 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:49 PM PDT 24
Peak memory 206244 kb
Host smart-de0b42b0-bf26-45de-8acd-cd3245d1f227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691393188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3691393188
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.787461186
Short name T165
Test name
Test status
Simulation time 537338276 ps
CPU time 5.52 seconds
Started Jul 21 06:23:37 PM PDT 24
Finished Jul 21 06:23:51 PM PDT 24
Peak memory 214464 kb
Host smart-fac3f9be-b87b-4154-b8a2-071a52e245ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787461186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.787461186
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2037020761
Short name T1042
Test name
Test status
Simulation time 25989564 ps
CPU time 1.1 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206228 kb
Host smart-cc961e78-6aee-46de-b813-9f0bbc4d5cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037020761 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2037020761
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1775133450
Short name T1003
Test name
Test status
Simulation time 29741078 ps
CPU time 1.49 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206104 kb
Host smart-0bc05d1f-145c-4eb2-9f3f-52ff3ba745a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775133450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1775133450
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.51733564
Short name T935
Test name
Test status
Simulation time 12862315 ps
CPU time 0.7 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:54 PM PDT 24
Peak memory 205976 kb
Host smart-c2fbf1bb-49fe-4a65-8975-aa4dbf3813a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51733564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.51733564
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.830099193
Short name T1039
Test name
Test status
Simulation time 82413368 ps
CPU time 2 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206156 kb
Host smart-f9346caa-956c-4aa8-b0ee-a23b22064545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830099193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.830099193
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3648756264
Short name T113
Test name
Test status
Simulation time 149639622 ps
CPU time 1.95 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:54 PM PDT 24
Peak memory 214760 kb
Host smart-1a15a0e5-ab80-460f-9458-13168f68c81e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648756264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3648756264
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2904654530
Short name T1078
Test name
Test status
Simulation time 172469409 ps
CPU time 6.92 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:58 PM PDT 24
Peak memory 214636 kb
Host smart-a926665e-e76c-49a3-9da5-56c8b6b6286a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904654530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2904654530
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.401636511
Short name T1077
Test name
Test status
Simulation time 321293671 ps
CPU time 3.16 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 216564 kb
Host smart-23534a22-91a2-4b79-8f44-cd443dd95c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401636511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.401636511
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.988814127
Short name T390
Test name
Test status
Simulation time 31335202 ps
CPU time 2.01 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 214444 kb
Host smart-142535a2-a9c3-4224-9bbe-c68a098f6a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988814127 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.988814127
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2275166168
Short name T1018
Test name
Test status
Simulation time 111073332 ps
CPU time 1.52 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206168 kb
Host smart-28828595-227a-4934-bc2e-b6f11db2b3e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275166168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2275166168
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3189554468
Short name T917
Test name
Test status
Simulation time 13723149 ps
CPU time 0.84 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206028 kb
Host smart-c1f3b9b3-420a-4f29-bb64-81dd8090dfd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189554468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3189554468
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3947690942
Short name T1007
Test name
Test status
Simulation time 110733394 ps
CPU time 3.81 seconds
Started Jul 21 06:23:46 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206256 kb
Host smart-94119b8f-1dcd-4aed-9904-6410306727bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947690942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3947690942
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2220359286
Short name T1022
Test name
Test status
Simulation time 237931056 ps
CPU time 2.63 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 214564 kb
Host smart-44a6f061-1ad2-4942-8f20-2a0a000b6d50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220359286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2220359286
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1169145618
Short name T1053
Test name
Test status
Simulation time 3303040544 ps
CPU time 9.34 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:24:02 PM PDT 24
Peak memory 221220 kb
Host smart-98d9b023-ed56-4ea8-a4de-509651d75a9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169145618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1169145618
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3708357008
Short name T929
Test name
Test status
Simulation time 573834832 ps
CPU time 2.87 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206252 kb
Host smart-5c610129-cb23-4f82-8143-e738d8dac3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708357008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3708357008
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.992910623
Short name T196
Test name
Test status
Simulation time 323781191 ps
CPU time 1.2 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206160 kb
Host smart-22679334-e94e-4062-b657-a70eee77a8ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992910623 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.992910623
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1841399825
Short name T1030
Test name
Test status
Simulation time 141313922 ps
CPU time 1.01 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:54 PM PDT 24
Peak memory 206096 kb
Host smart-3a39ef31-5c0f-409f-b46b-7b6945d9dcbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841399825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1841399825
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3625105804
Short name T1037
Test name
Test status
Simulation time 44203397 ps
CPU time 0.75 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 205996 kb
Host smart-f6a12924-a2ce-4a44-95e3-507fda83231c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625105804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3625105804
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1543098013
Short name T1068
Test name
Test status
Simulation time 192268346 ps
CPU time 2.39 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206232 kb
Host smart-9e1c0600-8239-41cc-acaa-61c9ae63d314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543098013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1543098013
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.400205233
Short name T119
Test name
Test status
Simulation time 410010902 ps
CPU time 3.29 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 214544 kb
Host smart-d7b8296a-83ce-42cb-ba9c-2347a2b83f37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400205233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.400205233
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2690669657
Short name T121
Test name
Test status
Simulation time 2867633822 ps
CPU time 13.9 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 214740 kb
Host smart-066a20c5-fbbc-459c-8ded-e87c8af42e6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690669657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2690669657
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.73282237
Short name T925
Test name
Test status
Simulation time 170838553 ps
CPU time 2.91 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:54 PM PDT 24
Peak memory 222704 kb
Host smart-45e963d0-584d-41cf-94c4-9bbfdcd70572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73282237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.73282237
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1510695355
Short name T191
Test name
Test status
Simulation time 512293114 ps
CPU time 5.03 seconds
Started Jul 21 06:23:45 PM PDT 24
Finished Jul 21 06:23:58 PM PDT 24
Peak memory 214340 kb
Host smart-3dde081e-7f9d-400c-b50e-f260c6bce669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510695355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1510695355
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1295965863
Short name T169
Test name
Test status
Simulation time 1019415320 ps
CPU time 8.02 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 206264 kb
Host smart-d74f2a94-e945-4952-8808-d513fe050173
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295965863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
295965863
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2901473336
Short name T980
Test name
Test status
Simulation time 1721676447 ps
CPU time 8.43 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:40 PM PDT 24
Peak memory 206340 kb
Host smart-71a50bfd-29af-499c-8c4f-66f471ba365d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901473336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
901473336
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.991612052
Short name T988
Test name
Test status
Simulation time 79807339 ps
CPU time 1.18 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 206288 kb
Host smart-3c9266f7-2953-40ad-93e7-15a21e4f0705
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991612052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.991612052
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3960029036
Short name T976
Test name
Test status
Simulation time 191090157 ps
CPU time 1.49 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 214512 kb
Host smart-b6c27ee4-9b71-4fc1-899b-2351baf1cf16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960029036 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3960029036
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1682802501
Short name T149
Test name
Test status
Simulation time 127425969 ps
CPU time 1.47 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 206208 kb
Host smart-66f4442c-1fdb-4c09-87f7-c91508a712b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682802501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1682802501
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2307528952
Short name T941
Test name
Test status
Simulation time 38138999 ps
CPU time 0.79 seconds
Started Jul 21 06:23:15 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 206032 kb
Host smart-14bb2f57-c796-4ff9-8eb0-34f5fcae4ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307528952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2307528952
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1415845657
Short name T150
Test name
Test status
Simulation time 68389568 ps
CPU time 2.5 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 206140 kb
Host smart-ca8da8cb-7f37-42af-a869-8a0202c0fa13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415845657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1415845657
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3399527603
Short name T961
Test name
Test status
Simulation time 529434341 ps
CPU time 7.28 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 214712 kb
Host smart-fc6c1e0b-1054-495d-8407-1166b7eda7ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399527603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3399527603
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3879182012
Short name T951
Test name
Test status
Simulation time 70674210 ps
CPU time 2.06 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 214392 kb
Host smart-54184cf9-4241-4160-927d-8226bfe347d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879182012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3879182012
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3306345142
Short name T1005
Test name
Test status
Simulation time 16046885 ps
CPU time 0.72 seconds
Started Jul 21 06:23:44 PM PDT 24
Finished Jul 21 06:23:53 PM PDT 24
Peak memory 206024 kb
Host smart-f0d4aa27-558d-4300-8ead-dc787f3807f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306345142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3306345142
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1233891725
Short name T948
Test name
Test status
Simulation time 8589420 ps
CPU time 0.69 seconds
Started Jul 21 06:23:43 PM PDT 24
Finished Jul 21 06:23:52 PM PDT 24
Peak memory 205976 kb
Host smart-e2334b4e-927c-4e16-b857-f088253261af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233891725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1233891725
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3598850328
Short name T927
Test name
Test status
Simulation time 105905565 ps
CPU time 0.87 seconds
Started Jul 21 06:23:49 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 206040 kb
Host smart-04645412-cb5f-4e6e-9d4f-8b1beac80edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598850328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3598850328
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2720447313
Short name T1000
Test name
Test status
Simulation time 10563790 ps
CPU time 0.72 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 205972 kb
Host smart-ee4b6107-7669-4209-b2a5-b1d1ffc87fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720447313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2720447313
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3996711773
Short name T996
Test name
Test status
Simulation time 23163164 ps
CPU time 0.81 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206064 kb
Host smart-a784367a-810e-440b-b697-b0092a8dd49e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996711773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3996711773
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3608124143
Short name T1064
Test name
Test status
Simulation time 32649323 ps
CPU time 0.72 seconds
Started Jul 21 06:23:54 PM PDT 24
Finished Jul 21 06:23:59 PM PDT 24
Peak memory 205940 kb
Host smart-1ffe29d6-78bd-4568-a60b-19d2188f8bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608124143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3608124143
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.135212995
Short name T919
Test name
Test status
Simulation time 39301979 ps
CPU time 0.83 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 205976 kb
Host smart-7f7d8480-bb14-484f-be6c-0b299af53471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135212995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.135212995
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2263039069
Short name T974
Test name
Test status
Simulation time 30252829 ps
CPU time 0.68 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206052 kb
Host smart-e26d2e27-2d29-4cfb-b65e-f78d52c04007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263039069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2263039069
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1744361109
Short name T922
Test name
Test status
Simulation time 42399693 ps
CPU time 0.72 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206000 kb
Host smart-5e308eea-064e-4744-a572-718169a84755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744361109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1744361109
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4088246231
Short name T926
Test name
Test status
Simulation time 18131295 ps
CPU time 0.7 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206012 kb
Host smart-c6423cd5-af1e-4d48-9270-79105e0aea76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088246231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4088246231
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3916500185
Short name T1074
Test name
Test status
Simulation time 1265374864 ps
CPU time 12.15 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:42 PM PDT 24
Peak memory 206220 kb
Host smart-0a195fbd-9655-4d25-826a-d75ca311c8ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916500185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
916500185
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1236949970
Short name T1006
Test name
Test status
Simulation time 1290040193 ps
CPU time 32.2 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:24:00 PM PDT 24
Peak memory 206228 kb
Host smart-82798497-ffb5-4736-a35d-bb7b7cda9c23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236949970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
236949970
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4275247158
Short name T1072
Test name
Test status
Simulation time 70351325 ps
CPU time 0.86 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 206088 kb
Host smart-3d9a7454-746e-4282-93d0-c72f3d68e413
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275247158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
275247158
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.58545499
Short name T1050
Test name
Test status
Simulation time 47384150 ps
CPU time 1.84 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 214544 kb
Host smart-47a5a06e-fb24-4022-9f97-cd8c99015a85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58545499 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.58545499
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2075308162
Short name T985
Test name
Test status
Simulation time 28515671 ps
CPU time 1.1 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:30 PM PDT 24
Peak memory 206156 kb
Host smart-ac1da5d6-d104-481c-a67e-102bd01cf2e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075308162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2075308162
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1247806626
Short name T934
Test name
Test status
Simulation time 31468480 ps
CPU time 0.79 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:30 PM PDT 24
Peak memory 206016 kb
Host smart-3fc76aa3-6bbc-47bb-af4f-edd4ec635ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247806626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1247806626
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4035693601
Short name T146
Test name
Test status
Simulation time 159072004 ps
CPU time 2.63 seconds
Started Jul 21 06:23:16 PM PDT 24
Finished Jul 21 06:23:34 PM PDT 24
Peak memory 206256 kb
Host smart-502a329f-1cdc-433f-bfed-cc4036bad9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035693601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4035693601
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3755834426
Short name T1046
Test name
Test status
Simulation time 318756452 ps
CPU time 3.37 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 219776 kb
Host smart-29e0dd6e-7b8c-4229-abde-644edd04dfb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755834426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3755834426
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1510037381
Short name T1002
Test name
Test status
Simulation time 536996462 ps
CPU time 4.54 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 220544 kb
Host smart-9b464673-6d4e-4eb8-a992-1d18554ddf78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510037381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1510037381
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2916815854
Short name T1027
Test name
Test status
Simulation time 53289046 ps
CPU time 1.56 seconds
Started Jul 21 06:23:17 PM PDT 24
Finished Jul 21 06:23:34 PM PDT 24
Peak memory 215544 kb
Host smart-60ed0e83-b72e-4fd4-9250-c383ad529953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916815854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2916815854
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.844530988
Short name T1040
Test name
Test status
Simulation time 14331341 ps
CPU time 0.67 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206036 kb
Host smart-1fe50bb1-a6a5-4e06-bc37-ea1b4600a05c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844530988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.844530988
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.217699053
Short name T957
Test name
Test status
Simulation time 132828463 ps
CPU time 0.72 seconds
Started Jul 21 06:23:51 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206036 kb
Host smart-b1231caf-25d1-438e-a11f-808a26b79b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217699053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.217699053
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1033239822
Short name T962
Test name
Test status
Simulation time 10597686 ps
CPU time 0.77 seconds
Started Jul 21 06:23:54 PM PDT 24
Finished Jul 21 06:23:59 PM PDT 24
Peak memory 206016 kb
Host smart-f2844deb-2ca4-471e-9da8-1e87cc6e0de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033239822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1033239822
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.321979873
Short name T975
Test name
Test status
Simulation time 34529567 ps
CPU time 0.85 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 205940 kb
Host smart-5075bf53-10b3-4e0e-9f86-1d9f64ad8fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321979873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.321979873
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1508263248
Short name T993
Test name
Test status
Simulation time 8450665 ps
CPU time 0.69 seconds
Started Jul 21 06:23:49 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 206000 kb
Host smart-37e1fed6-f8f9-40d6-9a13-0f9e3fc5f954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508263248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1508263248
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.716156006
Short name T992
Test name
Test status
Simulation time 17755878 ps
CPU time 0.72 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 205956 kb
Host smart-4cdb728e-1791-4203-a67c-fe0555339b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716156006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.716156006
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1851769810
Short name T928
Test name
Test status
Simulation time 35679835 ps
CPU time 0.73 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206008 kb
Host smart-75a0f011-28a1-4e72-a59c-1fe487fd8068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851769810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1851769810
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3765760738
Short name T945
Test name
Test status
Simulation time 12400913 ps
CPU time 0.84 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 206008 kb
Host smart-79262106-90e8-4e28-a461-03851fb9450a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765760738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3765760738
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3064010076
Short name T973
Test name
Test status
Simulation time 9397574 ps
CPU time 0.72 seconds
Started Jul 21 06:23:49 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 205952 kb
Host smart-1c84a766-bdf2-48b9-b9ef-f3beb2e9e26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064010076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3064010076
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1571925593
Short name T933
Test name
Test status
Simulation time 7819260 ps
CPU time 0.71 seconds
Started Jul 21 06:23:54 PM PDT 24
Finished Jul 21 06:23:59 PM PDT 24
Peak memory 206016 kb
Host smart-0c6705d2-0988-4662-83f3-984b7def2d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571925593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1571925593
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2492401801
Short name T1017
Test name
Test status
Simulation time 242907234 ps
CPU time 7.21 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 206248 kb
Host smart-5d8a0810-2dcf-4b1f-84d4-a1686aa484ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492401801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
492401801
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.370069571
Short name T965
Test name
Test status
Simulation time 4418290719 ps
CPU time 15.29 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 206300 kb
Host smart-b769a4d5-bc2b-4bba-98ae-f6ccb063924d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370069571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.370069571
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1789114234
Short name T1057
Test name
Test status
Simulation time 33658710 ps
CPU time 1.2 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 206356 kb
Host smart-2d3807ff-facf-4274-accd-eae6d05ba498
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789114234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
789114234
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1808199485
Short name T949
Test name
Test status
Simulation time 30998179 ps
CPU time 1.76 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 218880 kb
Host smart-294c8b9e-3a40-4c8a-9989-cc8addacb809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808199485 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1808199485
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2602132724
Short name T995
Test name
Test status
Simulation time 28563491 ps
CPU time 1.24 seconds
Started Jul 21 06:23:15 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 206288 kb
Host smart-131b382f-bc18-48fd-9231-55ab4df07690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602132724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2602132724
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3065357979
Short name T1073
Test name
Test status
Simulation time 19895496 ps
CPU time 0.75 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 205996 kb
Host smart-ce15910d-893a-48eb-8d5f-a66d60e2f0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065357979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3065357979
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1518969468
Short name T1052
Test name
Test status
Simulation time 222441686 ps
CPU time 2.25 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 206268 kb
Host smart-5337c611-86f2-4256-9a72-ab8c4c4ee2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518969468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1518969468
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1966913964
Short name T112
Test name
Test status
Simulation time 142093570 ps
CPU time 2.96 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 214640 kb
Host smart-e4794720-e957-4193-8cdf-c4ce5782259f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966913964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1966913964
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1923547518
Short name T939
Test name
Test status
Simulation time 36288329 ps
CPU time 2.2 seconds
Started Jul 21 06:23:12 PM PDT 24
Finished Jul 21 06:23:30 PM PDT 24
Peak memory 214428 kb
Host smart-ae04ed65-7d0f-40b6-b3f2-37e6560dff4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923547518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1923547518
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2158428756
Short name T188
Test name
Test status
Simulation time 203508557 ps
CPU time 3.43 seconds
Started Jul 21 06:23:22 PM PDT 24
Finished Jul 21 06:23:40 PM PDT 24
Peak memory 214512 kb
Host smart-d59f7805-5bba-48dd-9b4c-e53fb27d9dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158428756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2158428756
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1390145296
Short name T1026
Test name
Test status
Simulation time 10116655 ps
CPU time 0.72 seconds
Started Jul 21 06:23:53 PM PDT 24
Finished Jul 21 06:23:58 PM PDT 24
Peak memory 205472 kb
Host smart-1aa2b29f-159f-4c55-888b-e5593ea58846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390145296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1390145296
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3397053044
Short name T1063
Test name
Test status
Simulation time 11913622 ps
CPU time 0.82 seconds
Started Jul 21 06:23:49 PM PDT 24
Finished Jul 21 06:23:55 PM PDT 24
Peak memory 205988 kb
Host smart-3d1754b1-03cb-42d1-856a-3dbcc7f3c6a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397053044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3397053044
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2547213428
Short name T1021
Test name
Test status
Simulation time 27843177 ps
CPU time 0.69 seconds
Started Jul 21 06:23:49 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 206004 kb
Host smart-4e6a73ed-8ab4-4543-bafb-d226fadf8668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547213428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2547213428
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2426701903
Short name T920
Test name
Test status
Simulation time 18969983 ps
CPU time 0.69 seconds
Started Jul 21 06:23:50 PM PDT 24
Finished Jul 21 06:23:56 PM PDT 24
Peak memory 206052 kb
Host smart-c0e1156e-0433-40f0-9424-bb691a2a7168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426701903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2426701903
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2264031239
Short name T1034
Test name
Test status
Simulation time 12898133 ps
CPU time 0.91 seconds
Started Jul 21 06:23:53 PM PDT 24
Finished Jul 21 06:23:59 PM PDT 24
Peak memory 205656 kb
Host smart-58bb5812-c131-4aab-8822-e483480f0587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264031239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2264031239
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2026302169
Short name T1013
Test name
Test status
Simulation time 32613321 ps
CPU time 0.77 seconds
Started Jul 21 06:23:51 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 205972 kb
Host smart-ff9578a6-f8d4-440e-96ca-b30df9451649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026302169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2026302169
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.924478534
Short name T1044
Test name
Test status
Simulation time 25547629 ps
CPU time 0.83 seconds
Started Jul 21 06:23:56 PM PDT 24
Finished Jul 21 06:24:01 PM PDT 24
Peak memory 205972 kb
Host smart-165caf34-397a-41f5-b61c-26bf1a830f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924478534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.924478534
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2117207850
Short name T940
Test name
Test status
Simulation time 10288017 ps
CPU time 0.73 seconds
Started Jul 21 06:23:59 PM PDT 24
Finished Jul 21 06:24:04 PM PDT 24
Peak memory 206048 kb
Host smart-4ef76a3b-471a-4a5b-8c6b-b744f0fe9358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117207850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2117207850
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1786702192
Short name T923
Test name
Test status
Simulation time 24607906 ps
CPU time 0.92 seconds
Started Jul 21 06:23:57 PM PDT 24
Finished Jul 21 06:24:02 PM PDT 24
Peak memory 206008 kb
Host smart-037b7254-4443-442d-acd4-48ce552d859f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786702192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1786702192
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1871694406
Short name T1049
Test name
Test status
Simulation time 10145706 ps
CPU time 0.82 seconds
Started Jul 21 06:23:58 PM PDT 24
Finished Jul 21 06:24:02 PM PDT 24
Peak memory 206028 kb
Host smart-99c54f5a-4bae-4de4-8b20-bb7a6dec55a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871694406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1871694406
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.576560428
Short name T1060
Test name
Test status
Simulation time 49506750 ps
CPU time 2.08 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:35 PM PDT 24
Peak memory 214604 kb
Host smart-f4698dfc-9da1-47a9-8a60-d27e1e304a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576560428 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.576560428
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3252254639
Short name T1004
Test name
Test status
Simulation time 15713941 ps
CPU time 1.16 seconds
Started Jul 21 06:23:16 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 206160 kb
Host smart-321ae23b-b7d2-4f39-8019-9f488b5b5314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252254639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3252254639
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3096488310
Short name T1012
Test name
Test status
Simulation time 43116833 ps
CPU time 0.79 seconds
Started Jul 21 06:23:16 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 206036 kb
Host smart-0b2bd32f-59bd-486e-bf66-39e128753f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096488310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3096488310
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2998813003
Short name T978
Test name
Test status
Simulation time 167223722 ps
CPU time 2.25 seconds
Started Jul 21 06:23:15 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 206172 kb
Host smart-87863744-046c-4e1e-97b3-2fd2ffed9e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998813003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2998813003
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3522573432
Short name T1066
Test name
Test status
Simulation time 1056582877 ps
CPU time 2.7 seconds
Started Jul 21 06:23:13 PM PDT 24
Finished Jul 21 06:23:32 PM PDT 24
Peak memory 214684 kb
Host smart-817d5bef-8422-4ddc-85d1-9a3e9b015f14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522573432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3522573432
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1587924630
Short name T982
Test name
Test status
Simulation time 237558658 ps
CPU time 5.63 seconds
Started Jul 21 06:23:15 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 220832 kb
Host smart-aa19521d-68d8-4532-bc3a-e62c32a8bb2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587924630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1587924630
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2219164107
Short name T1041
Test name
Test status
Simulation time 63631560 ps
CPU time 2.54 seconds
Started Jul 21 06:23:14 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 222528 kb
Host smart-8b193ef3-513e-4977-b804-7e2399c7a733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219164107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2219164107
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2307112051
Short name T1031
Test name
Test status
Simulation time 42265048 ps
CPU time 1.94 seconds
Started Jul 21 06:23:18 PM PDT 24
Finished Jul 21 06:23:35 PM PDT 24
Peak memory 214460 kb
Host smart-94d3455a-70e3-45cc-bf09-ae37d694998a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307112051 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2307112051
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.490756552
Short name T1001
Test name
Test status
Simulation time 122693090 ps
CPU time 1.62 seconds
Started Jul 21 06:23:20 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 206216 kb
Host smart-5daa7fcd-9fd8-4440-9b90-35e1313d64b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490756552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.490756552
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3601640245
Short name T930
Test name
Test status
Simulation time 32130600 ps
CPU time 0.73 seconds
Started Jul 21 06:23:18 PM PDT 24
Finished Jul 21 06:23:34 PM PDT 24
Peak memory 205988 kb
Host smart-d3900866-33a1-42dd-b101-9714c5a45085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601640245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3601640245
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2148305142
Short name T143
Test name
Test status
Simulation time 48887499 ps
CPU time 1.59 seconds
Started Jul 21 06:23:20 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 206176 kb
Host smart-6aaa1cad-f9cb-4c32-a19f-7de9978ebc4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148305142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2148305142
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.883106648
Short name T1024
Test name
Test status
Simulation time 534328855 ps
CPU time 2.6 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 214716 kb
Host smart-f7ab955d-b90d-4e59-9768-c52704fed4a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883106648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.883106648
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.667983789
Short name T979
Test name
Test status
Simulation time 2433209751 ps
CPU time 8.88 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 214784 kb
Host smart-6e0e56b9-5eb5-4345-9877-0aea126499d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667983789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.667983789
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1677041378
Short name T956
Test name
Test status
Simulation time 68423532 ps
CPU time 2.4 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 214336 kb
Host smart-b26cad99-231b-447c-9a4d-26ec9fa19d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677041378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1677041378
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.82412713
Short name T1071
Test name
Test status
Simulation time 113244471 ps
CPU time 3.67 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 206224 kb
Host smart-4b0276c5-27ce-49eb-a7a1-04f579d3c52c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82412713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.82412713
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.117333794
Short name T989
Test name
Test status
Simulation time 303090767 ps
CPU time 2.09 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:35 PM PDT 24
Peak memory 214544 kb
Host smart-5356b58c-1ea9-48c6-a701-3eeed8d5a0e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117333794 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.117333794
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1673731283
Short name T1051
Test name
Test status
Simulation time 29653485 ps
CPU time 1.6 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 206200 kb
Host smart-4ad80d66-e5e4-4495-b892-b44be8f0631c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673731283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1673731283
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3983540504
Short name T966
Test name
Test status
Simulation time 28038420 ps
CPU time 0.74 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:34 PM PDT 24
Peak memory 205936 kb
Host smart-c229b4f1-1b42-466c-a60b-e02aba99f167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983540504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3983540504
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.707714082
Short name T997
Test name
Test status
Simulation time 88971566 ps
CPU time 1.66 seconds
Started Jul 21 06:23:20 PM PDT 24
Finished Jul 21 06:23:36 PM PDT 24
Peak memory 206300 kb
Host smart-9464447a-0600-4617-a15c-d81297256c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707714082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.707714082
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.16097189
Short name T116
Test name
Test status
Simulation time 113235836 ps
CPU time 3.46 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 214660 kb
Host smart-835d9d0c-44f7-4cd2-a6f8-e9d56fe410ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16097189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_
reg_errors.16097189
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.399191463
Short name T1016
Test name
Test status
Simulation time 170086200 ps
CPU time 7.07 seconds
Started Jul 21 06:23:19 PM PDT 24
Finished Jul 21 06:23:41 PM PDT 24
Peak memory 220836 kb
Host smart-9bc8ad17-c065-44dc-bd37-467593d94b04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399191463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.399191463
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1200687823
Short name T999
Test name
Test status
Simulation time 244252266 ps
CPU time 2.68 seconds
Started Jul 21 06:23:22 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 214428 kb
Host smart-d342c34a-da47-4fdc-a864-7c1826d45ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200687823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1200687823
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4064078349
Short name T186
Test name
Test status
Simulation time 229781427 ps
CPU time 6.38 seconds
Started Jul 21 06:23:18 PM PDT 24
Finished Jul 21 06:23:40 PM PDT 24
Peak memory 214360 kb
Host smart-8d946e15-b8c0-4f34-a1df-39bdb8f2ec45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064078349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4064078349
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.78571824
Short name T981
Test name
Test status
Simulation time 36435182 ps
CPU time 2.42 seconds
Started Jul 21 06:23:31 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 220080 kb
Host smart-bd46d6d6-1399-4c29-923d-eb28f4927a2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78571824 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.78571824
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.473728743
Short name T932
Test name
Test status
Simulation time 15680524 ps
CPU time 0.92 seconds
Started Jul 21 06:23:31 PM PDT 24
Finished Jul 21 06:23:42 PM PDT 24
Peak memory 206076 kb
Host smart-5d158771-97c3-4bee-a84e-cdf7d4411744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473728743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.473728743
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1885648237
Short name T946
Test name
Test status
Simulation time 13658216 ps
CPU time 0.77 seconds
Started Jul 21 06:23:34 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 205976 kb
Host smart-d8d152e5-0d52-4b17-8dba-0bd92539e68d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885648237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1885648237
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1703508442
Short name T147
Test name
Test status
Simulation time 93661118 ps
CPU time 2.22 seconds
Started Jul 21 06:23:30 PM PDT 24
Finished Jul 21 06:23:43 PM PDT 24
Peak memory 206216 kb
Host smart-167d3f8c-8ca5-4bf8-9803-cc2ec0ba917d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703508442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1703508442
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3916501756
Short name T1055
Test name
Test status
Simulation time 207106171 ps
CPU time 1.25 seconds
Started Jul 21 06:23:18 PM PDT 24
Finished Jul 21 06:23:34 PM PDT 24
Peak memory 214636 kb
Host smart-b877c100-a0f3-4449-befe-31a7f61eeff7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916501756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3916501756
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.651664064
Short name T1047
Test name
Test status
Simulation time 1739938175 ps
CPU time 4.44 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:39 PM PDT 24
Peak memory 220720 kb
Host smart-7a953a3d-ca2d-43d1-8449-a0a68d2ea24e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651664064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.651664064
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.347525487
Short name T970
Test name
Test status
Simulation time 334029300 ps
CPU time 5.5 seconds
Started Jul 21 06:23:21 PM PDT 24
Finished Jul 21 06:23:41 PM PDT 24
Peak memory 214496 kb
Host smart-aa01bd75-e753-409f-b95c-641658d31853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347525487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.347525487
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3119678629
Short name T178
Test name
Test status
Simulation time 226198272 ps
CPU time 4.36 seconds
Started Jul 21 06:23:18 PM PDT 24
Finished Jul 21 06:23:37 PM PDT 24
Peak memory 214448 kb
Host smart-310590bf-9848-42ad-9d9c-087d83e42a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119678629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3119678629
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1523803762
Short name T1023
Test name
Test status
Simulation time 35492395 ps
CPU time 2.31 seconds
Started Jul 21 06:23:25 PM PDT 24
Finished Jul 21 06:23:41 PM PDT 24
Peak memory 214460 kb
Host smart-679e9f37-cfb4-49eb-b469-f95abfe795f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523803762 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1523803762
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4023936958
Short name T1054
Test name
Test status
Simulation time 44056426 ps
CPU time 1.28 seconds
Started Jul 21 06:23:27 PM PDT 24
Finished Jul 21 06:23:40 PM PDT 24
Peak memory 206248 kb
Host smart-9ce3ff54-600f-4088-93dc-0c13d6aad8c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023936958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4023936958
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.658394128
Short name T998
Test name
Test status
Simulation time 10751497 ps
CPU time 0.72 seconds
Started Jul 21 06:23:24 PM PDT 24
Finished Jul 21 06:23:38 PM PDT 24
Peak memory 205964 kb
Host smart-6713ac55-310d-424e-8461-e78660716bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658394128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.658394128
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2172871156
Short name T959
Test name
Test status
Simulation time 34730167 ps
CPU time 2.12 seconds
Started Jul 21 06:23:25 PM PDT 24
Finished Jul 21 06:23:40 PM PDT 24
Peak memory 206320 kb
Host smart-532406f4-2af7-42ea-8223-37714ba4889f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172871156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2172871156
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1566212398
Short name T990
Test name
Test status
Simulation time 173002413 ps
CPU time 1.57 seconds
Started Jul 21 06:23:33 PM PDT 24
Finished Jul 21 06:23:44 PM PDT 24
Peak memory 214680 kb
Host smart-9e9ad5ce-3ab5-4582-953f-5f9330e10ec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566212398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1566212398
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1427364779
Short name T1009
Test name
Test status
Simulation time 862777049 ps
CPU time 6.23 seconds
Started Jul 21 06:23:27 PM PDT 24
Finished Jul 21 06:23:45 PM PDT 24
Peak memory 220692 kb
Host smart-2ccded76-569d-48c4-ad17-13a43afe8b25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427364779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1427364779
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.894342666
Short name T977
Test name
Test status
Simulation time 121239988 ps
CPU time 2.92 seconds
Started Jul 21 06:23:27 PM PDT 24
Finished Jul 21 06:23:42 PM PDT 24
Peak memory 216652 kb
Host smart-a6b2bd95-8940-4814-a524-50d9b1c32e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894342666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.894342666
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.269856984
Short name T177
Test name
Test status
Simulation time 965535139 ps
CPU time 6.59 seconds
Started Jul 21 06:23:28 PM PDT 24
Finished Jul 21 06:23:46 PM PDT 24
Peak memory 206136 kb
Host smart-e4f5955a-5803-4f07-9213-018a3acfb3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269856984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
269856984
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3814441193
Short name T618
Test name
Test status
Simulation time 130238703 ps
CPU time 0.73 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:15 PM PDT 24
Peak memory 205816 kb
Host smart-33156f3b-55aa-4a5c-92e5-678f175c936d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814441193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3814441193
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2755771023
Short name T11
Test name
Test status
Simulation time 152126107 ps
CPU time 3.5 seconds
Started Jul 21 05:36:17 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 214308 kb
Host smart-7c893b42-f521-490b-a0b2-1b05e8467c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755771023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2755771023
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1359086291
Short name T858
Test name
Test status
Simulation time 1791766271 ps
CPU time 13.3 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:28 PM PDT 24
Peak memory 214040 kb
Host smart-16cf3597-e275-43cd-b019-f1841dd318f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359086291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1359086291
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2863584336
Short name T454
Test name
Test status
Simulation time 130552091 ps
CPU time 5.68 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 214160 kb
Host smart-dc5b3190-9c5c-4a33-b3ed-ccd9ec6286a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863584336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2863584336
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1679523269
Short name T43
Test name
Test status
Simulation time 172489924 ps
CPU time 3.18 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:16 PM PDT 24
Peak memory 213996 kb
Host smart-e6c175c0-d150-47b1-b52b-92b338854626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679523269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1679523269
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3308518400
Short name T75
Test name
Test status
Simulation time 374304239 ps
CPU time 6.21 seconds
Started Jul 21 05:36:16 PM PDT 24
Finished Jul 21 05:36:23 PM PDT 24
Peak memory 222288 kb
Host smart-f1bf6e94-0d20-405a-80ad-4cf0b83c7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308518400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3308518400
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3099034606
Short name T857
Test name
Test status
Simulation time 474476012 ps
CPU time 9.37 seconds
Started Jul 21 05:36:14 PM PDT 24
Finished Jul 21 05:36:24 PM PDT 24
Peak memory 207060 kb
Host smart-86b04ee8-b2ca-4e33-b5b3-dd13be4b0747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099034606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3099034606
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3745931016
Short name T488
Test name
Test status
Simulation time 185440031 ps
CPU time 6.22 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 207684 kb
Host smart-beddea27-8926-49cf-934f-039308a9da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745931016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3745931016
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1635019646
Short name T308
Test name
Test status
Simulation time 1576491956 ps
CPU time 9.52 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:25 PM PDT 24
Peak memory 208392 kb
Host smart-7185f16c-34ad-4960-886c-fe36a823c9ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635019646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1635019646
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3551467905
Short name T732
Test name
Test status
Simulation time 126391956 ps
CPU time 3.85 seconds
Started Jul 21 05:36:14 PM PDT 24
Finished Jul 21 05:36:18 PM PDT 24
Peak memory 207556 kb
Host smart-58f72c0a-defa-4ed8-8eee-147d7b482f68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551467905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3551467905
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1680554174
Short name T212
Test name
Test status
Simulation time 42551099 ps
CPU time 2.43 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:17 PM PDT 24
Peak memory 206528 kb
Host smart-fe047b32-433d-4b38-80e3-93c83b1ba8fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680554174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1680554174
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2074821793
Short name T674
Test name
Test status
Simulation time 25361339 ps
CPU time 1.84 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:17 PM PDT 24
Peak memory 207028 kb
Host smart-d47f83e4-98eb-40b7-b8e0-e865da7dbd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074821793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2074821793
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3185776863
Short name T693
Test name
Test status
Simulation time 427517509 ps
CPU time 4.62 seconds
Started Jul 21 05:36:14 PM PDT 24
Finished Jul 21 05:36:19 PM PDT 24
Peak memory 206576 kb
Host smart-d045c445-8976-4947-84ef-e88db34f142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185776863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3185776863
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.16000984
Short name T332
Test name
Test status
Simulation time 1931544111 ps
CPU time 17.4 seconds
Started Jul 21 05:36:16 PM PDT 24
Finished Jul 21 05:36:34 PM PDT 24
Peak memory 215628 kb
Host smart-ce94edc2-6997-48fb-9804-5493d5c5697e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16000984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.16000984
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3525085352
Short name T68
Test name
Test status
Simulation time 1862957868 ps
CPU time 20.54 seconds
Started Jul 21 05:36:17 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 222340 kb
Host smart-4512ac92-708e-48bf-bf0d-085a260d2877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525085352 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3525085352
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.172918240
Short name T757
Test name
Test status
Simulation time 353418843 ps
CPU time 4.55 seconds
Started Jul 21 05:36:16 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 209192 kb
Host smart-947c5721-38c6-4ebf-b231-5132bbc7a929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172918240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.172918240
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.347916511
Short name T468
Test name
Test status
Simulation time 216108385 ps
CPU time 3 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:18 PM PDT 24
Peak memory 210796 kb
Host smart-f8f0f7b0-97d5-440a-9170-ad63a82f79dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347916511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.347916511
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.368480254
Short name T548
Test name
Test status
Simulation time 19305595 ps
CPU time 1.01 seconds
Started Jul 21 05:36:19 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 205824 kb
Host smart-ee2df14a-95e8-4d1f-92eb-ad19ebcfb744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368480254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.368480254
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3927995226
Short name T28
Test name
Test status
Simulation time 461794275 ps
CPU time 2.1 seconds
Started Jul 21 05:36:19 PM PDT 24
Finished Jul 21 05:36:22 PM PDT 24
Peak memory 209488 kb
Host smart-ef229efe-1035-4fc8-bdd2-1a7047c379ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927995226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3927995226
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1083226800
Short name T753
Test name
Test status
Simulation time 219483009 ps
CPU time 2.99 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:36:24 PM PDT 24
Peak memory 209916 kb
Host smart-c9761e0c-f9a1-4c47-a194-44cc4cc7147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083226800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1083226800
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3567516162
Short name T26
Test name
Test status
Simulation time 116286814 ps
CPU time 3.83 seconds
Started Jul 21 05:36:19 PM PDT 24
Finished Jul 21 05:36:23 PM PDT 24
Peak memory 214064 kb
Host smart-ac4b6177-863d-4b6d-a97e-23b51767c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567516162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3567516162
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4272656897
Short name T838
Test name
Test status
Simulation time 101458020 ps
CPU time 2.7 seconds
Started Jul 21 05:36:23 PM PDT 24
Finished Jul 21 05:36:26 PM PDT 24
Peak memory 213884 kb
Host smart-7cda9d28-36fd-462b-8c0f-9ce1b2118090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272656897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4272656897
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2173673565
Short name T406
Test name
Test status
Simulation time 36029023 ps
CPU time 2.85 seconds
Started Jul 21 05:36:19 PM PDT 24
Finished Jul 21 05:36:23 PM PDT 24
Peak memory 214072 kb
Host smart-01722f54-41c3-46b5-addf-f4c1cc3b3ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173673565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2173673565
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1738801746
Short name T715
Test name
Test status
Simulation time 125951395 ps
CPU time 5.4 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:36:26 PM PDT 24
Peak memory 209528 kb
Host smart-c143f095-5492-45fb-b84b-3205d2a7af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738801746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1738801746
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.17936145
Short name T679
Test name
Test status
Simulation time 541717828 ps
CPU time 4.51 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:36:25 PM PDT 24
Peak memory 206744 kb
Host smart-11feb2dd-cf1a-4d94-a2de-e9d7c179a59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17936145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.17936145
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.424302007
Short name T626
Test name
Test status
Simulation time 955390627 ps
CPU time 22.25 seconds
Started Jul 21 05:36:22 PM PDT 24
Finished Jul 21 05:36:45 PM PDT 24
Peak memory 208260 kb
Host smart-875b969a-94b9-4170-8148-498ed7a1fe3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424302007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.424302007
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.999671198
Short name T432
Test name
Test status
Simulation time 237743299 ps
CPU time 2.49 seconds
Started Jul 21 05:36:18 PM PDT 24
Finished Jul 21 05:36:22 PM PDT 24
Peak memory 208536 kb
Host smart-fcf70524-fae2-4793-9799-cd0cd04ddf74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999671198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.999671198
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.440407458
Short name T872
Test name
Test status
Simulation time 59001572 ps
CPU time 3.06 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:36:23 PM PDT 24
Peak memory 209500 kb
Host smart-312d7839-f68a-4a6d-a6f5-c1dddf7cfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440407458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.440407458
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1373675111
Short name T420
Test name
Test status
Simulation time 67274853 ps
CPU time 2.36 seconds
Started Jul 21 05:36:16 PM PDT 24
Finished Jul 21 05:36:19 PM PDT 24
Peak memory 208132 kb
Host smart-73b89873-87a0-43df-9b97-009d84fd0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373675111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1373675111
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.534475502
Short name T81
Test name
Test status
Simulation time 1056466714 ps
CPU time 24.45 seconds
Started Jul 21 05:36:25 PM PDT 24
Finished Jul 21 05:36:50 PM PDT 24
Peak memory 222260 kb
Host smart-876e5ceb-910a-47bc-adb5-2d0100ed5f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534475502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.534475502
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1172735600
Short name T660
Test name
Test status
Simulation time 341161658 ps
CPU time 17.21 seconds
Started Jul 21 05:36:18 PM PDT 24
Finished Jul 21 05:36:36 PM PDT 24
Peak memory 222308 kb
Host smart-941bc69d-49df-4ce1-8f53-4e28aa9e0ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172735600 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1172735600
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2943908169
Short name T181
Test name
Test status
Simulation time 244235129 ps
CPU time 2.15 seconds
Started Jul 21 05:36:19 PM PDT 24
Finished Jul 21 05:36:22 PM PDT 24
Peak memory 209844 kb
Host smart-55860420-8cb8-4ede-9721-66bfce412786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943908169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2943908169
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1639680871
Short name T827
Test name
Test status
Simulation time 41157194 ps
CPU time 0.84 seconds
Started Jul 21 05:36:58 PM PDT 24
Finished Jul 21 05:36:59 PM PDT 24
Peak memory 205824 kb
Host smart-c56fbb18-772e-45ea-ad37-60f5b403d74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639680871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1639680871
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2126139618
Short name T244
Test name
Test status
Simulation time 40980627 ps
CPU time 1.89 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 207632 kb
Host smart-21d5588f-f7fe-4b68-81df-fc424c18fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126139618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2126139618
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2124291031
Short name T640
Test name
Test status
Simulation time 131962088 ps
CPU time 5.87 seconds
Started Jul 21 05:36:58 PM PDT 24
Finished Jul 21 05:37:04 PM PDT 24
Peak memory 214076 kb
Host smart-a67937be-9c73-4e40-acd6-871e48b6c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124291031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2124291031
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2494358504
Short name T788
Test name
Test status
Simulation time 199822571 ps
CPU time 2.32 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 214132 kb
Host smart-fa668b99-61c2-46ba-a7a7-03224fa3b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494358504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2494358504
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3097564676
Short name T442
Test name
Test status
Simulation time 187818859 ps
CPU time 5.95 seconds
Started Jul 21 05:36:54 PM PDT 24
Finished Jul 21 05:37:01 PM PDT 24
Peak memory 209740 kb
Host smart-da95f401-2372-4f38-9d4b-57317299e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097564676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3097564676
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3809356911
Short name T583
Test name
Test status
Simulation time 112570751 ps
CPU time 4.37 seconds
Started Jul 21 05:36:54 PM PDT 24
Finished Jul 21 05:36:59 PM PDT 24
Peak memory 208264 kb
Host smart-86af3af4-e515-43f9-8621-acae681fec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809356911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3809356911
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.920207417
Short name T556
Test name
Test status
Simulation time 71576621 ps
CPU time 3.42 seconds
Started Jul 21 05:36:55 PM PDT 24
Finished Jul 21 05:36:59 PM PDT 24
Peak memory 208728 kb
Host smart-ee7002cd-8a23-4e82-9d61-29e726295db8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920207417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.920207417
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3244269902
Short name T506
Test name
Test status
Simulation time 251591726 ps
CPU time 4.38 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:58 PM PDT 24
Peak memory 206612 kb
Host smart-7793923c-a1dc-42cb-a694-3c180d368797
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244269902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3244269902
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.76784197
Short name T659
Test name
Test status
Simulation time 399299882 ps
CPU time 5.9 seconds
Started Jul 21 05:36:52 PM PDT 24
Finished Jul 21 05:36:59 PM PDT 24
Peak memory 207664 kb
Host smart-9ee92130-b8b6-447a-aa5c-17b64efebdf9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76784197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.76784197
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.959938141
Short name T292
Test name
Test status
Simulation time 326727786 ps
CPU time 2.37 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 207304 kb
Host smart-dac78662-3842-48a0-96f4-105bfa116c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959938141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.959938141
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1864163838
Short name T772
Test name
Test status
Simulation time 100522809 ps
CPU time 3.19 seconds
Started Jul 21 05:36:54 PM PDT 24
Finished Jul 21 05:36:58 PM PDT 24
Peak memory 206704 kb
Host smart-7c597376-4013-4d03-9f27-90e9be2b3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864163838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1864163838
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3621710176
Short name T875
Test name
Test status
Simulation time 3870523904 ps
CPU time 29.31 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:30 PM PDT 24
Peak memory 217532 kb
Host smart-cbf9d8c0-abad-4439-9651-22646f1e4f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621710176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3621710176
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3200419759
Short name T286
Test name
Test status
Simulation time 378961247 ps
CPU time 4.14 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 214052 kb
Host smart-dc5e4584-4e7b-4c79-af01-0ab7940f444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200419759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3200419759
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3145305675
Short name T63
Test name
Test status
Simulation time 212084590 ps
CPU time 2.98 seconds
Started Jul 21 05:37:05 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 209832 kb
Host smart-d5b95fe9-f78c-4100-9d69-a35f6402c108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145305675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3145305675
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1385737947
Short name T856
Test name
Test status
Simulation time 40132598 ps
CPU time 0.76 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:02 PM PDT 24
Peak memory 205848 kb
Host smart-4404ec05-c823-4e57-8dad-ad39826fe035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385737947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1385737947
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2462778477
Short name T154
Test name
Test status
Simulation time 287867950 ps
CPU time 8.07 seconds
Started Jul 21 05:37:01 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 215192 kb
Host smart-2f56968c-5e16-4da8-b0df-e936848803d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462778477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2462778477
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.515505315
Short name T743
Test name
Test status
Simulation time 610824526 ps
CPU time 3.75 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 209856 kb
Host smart-f282f2f9-d5cd-4485-82f9-85e8a508cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515505315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.515505315
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3135176485
Short name T295
Test name
Test status
Simulation time 604985736 ps
CPU time 4.7 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 214068 kb
Host smart-99810e64-d543-4ec2-8545-3ff4a127aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135176485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3135176485
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2197234716
Short name T860
Test name
Test status
Simulation time 135437835 ps
CPU time 5.47 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:06 PM PDT 24
Peak memory 214080 kb
Host smart-de43a0af-0617-46c8-8b96-435277960c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197234716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2197234716
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2977946641
Short name T328
Test name
Test status
Simulation time 429723398 ps
CPU time 2.78 seconds
Started Jul 21 05:36:59 PM PDT 24
Finished Jul 21 05:37:02 PM PDT 24
Peak memory 222264 kb
Host smart-ffa5c9f1-47cd-48a4-8462-34bec68c3ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977946641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2977946641
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.720027219
Short name T829
Test name
Test status
Simulation time 118772642 ps
CPU time 1.77 seconds
Started Jul 21 05:36:59 PM PDT 24
Finished Jul 21 05:37:01 PM PDT 24
Peak memory 206676 kb
Host smart-0a679597-041a-4244-b826-fc0d48fd14bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720027219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.720027219
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.262628672
Short name T88
Test name
Test status
Simulation time 112655541 ps
CPU time 3.05 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 206660 kb
Host smart-94da1d2e-7539-480c-a39f-8ef0cd49d11c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262628672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.262628672
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2376268431
Short name T280
Test name
Test status
Simulation time 14427125455 ps
CPU time 27.7 seconds
Started Jul 21 05:37:03 PM PDT 24
Finished Jul 21 05:37:31 PM PDT 24
Peak memory 208352 kb
Host smart-7a4a0eae-500f-4013-804c-aa57201d18bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376268431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2376268431
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3078230629
Short name T892
Test name
Test status
Simulation time 503103722 ps
CPU time 5.82 seconds
Started Jul 21 05:37:01 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 218144 kb
Host smart-9aa36bd3-a744-4ec7-9359-618a6c722365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078230629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3078230629
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4182019962
Short name T580
Test name
Test status
Simulation time 32078389 ps
CPU time 2.07 seconds
Started Jul 21 05:37:01 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 206940 kb
Host smart-83d2b09b-3901-4a81-bbc6-a90ffa16a208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182019962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4182019962
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4257430197
Short name T622
Test name
Test status
Simulation time 176872654 ps
CPU time 3.99 seconds
Started Jul 21 05:36:59 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 209272 kb
Host smart-cf3d6746-518c-48ed-9326-313dee0224cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257430197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4257430197
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4127080722
Short name T444
Test name
Test status
Simulation time 17989595 ps
CPU time 0.95 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 205908 kb
Host smart-87ea0755-b571-46d6-a8ac-12fc5ec2313b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127080722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4127080722
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2646140526
Short name T448
Test name
Test status
Simulation time 227675851 ps
CPU time 4.02 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 222496 kb
Host smart-6a237ba1-3ecb-4dba-8798-a7c232676385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646140526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2646140526
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.160013251
Short name T411
Test name
Test status
Simulation time 22292786 ps
CPU time 1.41 seconds
Started Jul 21 05:37:00 PM PDT 24
Finished Jul 21 05:37:02 PM PDT 24
Peak memory 208600 kb
Host smart-5ee40dab-170a-4b17-aa92-60b8106093ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160013251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.160013251
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3882835986
Short name T92
Test name
Test status
Simulation time 28386591 ps
CPU time 2.34 seconds
Started Jul 21 05:37:03 PM PDT 24
Finished Jul 21 05:37:06 PM PDT 24
Peak memory 213960 kb
Host smart-de4889da-f120-4b2b-af9a-e21b260d5ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882835986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3882835986
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3309445226
Short name T365
Test name
Test status
Simulation time 240269285 ps
CPU time 4.33 seconds
Started Jul 21 05:37:07 PM PDT 24
Finished Jul 21 05:37:12 PM PDT 24
Peak memory 213944 kb
Host smart-ee871d61-efb2-40dd-8fbc-9dd9f24e786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309445226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3309445226
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2367932152
Short name T726
Test name
Test status
Simulation time 136180108 ps
CPU time 3.08 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 218124 kb
Host smart-f91a91a5-fe71-495a-bb08-977bf318110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367932152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2367932152
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2925235139
Short name T479
Test name
Test status
Simulation time 49822960 ps
CPU time 2.56 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 206680 kb
Host smart-eb9d51b9-6d43-4d42-9f7f-56bbf6ce0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925235139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2925235139
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.911491081
Short name T569
Test name
Test status
Simulation time 1356487455 ps
CPU time 17.7 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:20 PM PDT 24
Peak memory 208080 kb
Host smart-956f4ee7-1345-493f-a6a7-a52fe876816e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911491081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.911491081
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.888351048
Short name T904
Test name
Test status
Simulation time 332510445 ps
CPU time 8.91 seconds
Started Jul 21 05:37:03 PM PDT 24
Finished Jul 21 05:37:12 PM PDT 24
Peak memory 207852 kb
Host smart-bb4dd690-79db-432f-a32a-a254bd1d16e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888351048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.888351048
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1945741303
Short name T805
Test name
Test status
Simulation time 165502843 ps
CPU time 6.13 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 207956 kb
Host smart-b16bca39-4883-46c2-ac63-d9827f3d9701
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945741303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1945741303
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.142919861
Short name T655
Test name
Test status
Simulation time 34110327 ps
CPU time 2.02 seconds
Started Jul 21 05:37:08 PM PDT 24
Finished Jul 21 05:37:10 PM PDT 24
Peak memory 215228 kb
Host smart-c44f8902-96d5-45ad-9f0e-4f88101950be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142919861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.142919861
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2175440201
Short name T436
Test name
Test status
Simulation time 240751920 ps
CPU time 3.04 seconds
Started Jul 21 05:37:02 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 206720 kb
Host smart-bccbcf5f-b44e-4042-888e-b13a98f3ffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175440201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2175440201
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3603988301
Short name T194
Test name
Test status
Simulation time 861510594 ps
CPU time 11.6 seconds
Started Jul 21 05:37:06 PM PDT 24
Finished Jul 21 05:37:18 PM PDT 24
Peak memory 219056 kb
Host smart-85e640cc-b5a0-4c64-8431-4c3e9c8656f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603988301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3603988301
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2885214923
Short name T886
Test name
Test status
Simulation time 396816670 ps
CPU time 4.44 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 214072 kb
Host smart-2a01d065-eeb9-4135-b65b-013b8043158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885214923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2885214923
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1283688537
Short name T577
Test name
Test status
Simulation time 678490037 ps
CPU time 2.94 seconds
Started Jul 21 05:37:05 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 210036 kb
Host smart-5bc2b594-2259-4d83-a1d5-20732885e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283688537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1283688537
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1037885467
Short name T37
Test name
Test status
Simulation time 293209886 ps
CPU time 4.34 seconds
Started Jul 21 05:37:05 PM PDT 24
Finished Jul 21 05:37:10 PM PDT 24
Peak memory 209900 kb
Host smart-e160a71b-2cea-4ad9-b2de-e88a815ef2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037885467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1037885467
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2708124620
Short name T708
Test name
Test status
Simulation time 743036659 ps
CPU time 4.04 seconds
Started Jul 21 05:37:07 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 209840 kb
Host smart-cdb7f17f-d8f7-4643-bb56-cb466c45f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708124620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2708124620
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1713500393
Short name T769
Test name
Test status
Simulation time 389247644 ps
CPU time 4.72 seconds
Started Jul 21 05:37:06 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 214148 kb
Host smart-d92cc5ae-fa1a-458b-afac-57703a4ba0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713500393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1713500393
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.429286938
Short name T884
Test name
Test status
Simulation time 68777522 ps
CPU time 2.4 seconds
Started Jul 21 05:37:08 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 214012 kb
Host smart-829238f1-8aae-4d4a-a02b-f80ae691aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429286938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.429286938
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.2256126452
Short name T747
Test name
Test status
Simulation time 570799652 ps
CPU time 11.7 seconds
Started Jul 21 05:37:06 PM PDT 24
Finished Jul 21 05:37:18 PM PDT 24
Peak memory 214148 kb
Host smart-66ee4e7f-8773-4609-847b-bbdc5e9d9dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256126452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2256126452
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1305367385
Short name T558
Test name
Test status
Simulation time 69190818 ps
CPU time 2.98 seconds
Started Jul 21 05:37:06 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 206656 kb
Host smart-53318dcb-4428-4d5c-84f4-625312e38ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305367385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1305367385
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1270272330
Short name T422
Test name
Test status
Simulation time 142575096 ps
CPU time 3.78 seconds
Started Jul 21 05:37:03 PM PDT 24
Finished Jul 21 05:37:08 PM PDT 24
Peak memory 206640 kb
Host smart-66d324cd-70a6-40c0-b63a-9e376441b191
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270272330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1270272330
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1196347280
Short name T598
Test name
Test status
Simulation time 441901561 ps
CPU time 6.24 seconds
Started Jul 21 05:37:07 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 208604 kb
Host smart-88f0f7fd-8df9-416e-bcc6-b7cd719e9d11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196347280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1196347280
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2702386275
Short name T423
Test name
Test status
Simulation time 125711700 ps
CPU time 4.24 seconds
Started Jul 21 05:37:07 PM PDT 24
Finished Jul 21 05:37:12 PM PDT 24
Peak memory 208100 kb
Host smart-c4fb0fe1-ea59-4ecc-a80f-e6e7b3e92dd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702386275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2702386275
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2193616945
Short name T500
Test name
Test status
Simulation time 1600479697 ps
CPU time 3.19 seconds
Started Jul 21 05:37:05 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 209820 kb
Host smart-2ed69373-9041-4c11-84f0-f9b9f85a78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193616945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2193616945
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2508952444
Short name T581
Test name
Test status
Simulation time 396449922 ps
CPU time 4.26 seconds
Started Jul 21 05:37:04 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 206896 kb
Host smart-4118f078-3e63-4d8b-91d5-3839fbae4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508952444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2508952444
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3198612737
Short name T658
Test name
Test status
Simulation time 110468784 ps
CPU time 3.3 seconds
Started Jul 21 05:37:05 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 208176 kb
Host smart-127ed542-07c4-4f0a-934e-afa356150828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198612737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3198612737
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.267092950
Short name T192
Test name
Test status
Simulation time 316548428 ps
CPU time 9.29 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:22 PM PDT 24
Peak memory 218472 kb
Host smart-53cbe14a-2657-4806-8365-9064665369de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267092950 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.267092950
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1138260646
Short name T370
Test name
Test status
Simulation time 564879581 ps
CPU time 5.21 seconds
Started Jul 21 05:37:07 PM PDT 24
Finished Jul 21 05:37:12 PM PDT 24
Peak memory 209516 kb
Host smart-ba148c79-e791-454b-922f-7d8fea6d6a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138260646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1138260646
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2959027268
Short name T48
Test name
Test status
Simulation time 49120670 ps
CPU time 2.22 seconds
Started Jul 21 05:37:08 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 209400 kb
Host smart-ce119552-2789-4f3d-b918-be372bdc392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959027268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2959027268
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4231738439
Short name T528
Test name
Test status
Simulation time 70804864 ps
CPU time 0.82 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:13 PM PDT 24
Peak memory 205776 kb
Host smart-d222c8cb-80ff-460b-850d-4384d376e9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231738439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4231738439
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2194411462
Short name T241
Test name
Test status
Simulation time 51918201 ps
CPU time 3.47 seconds
Started Jul 21 05:37:13 PM PDT 24
Finished Jul 21 05:37:17 PM PDT 24
Peak memory 214052 kb
Host smart-80d095ba-1c8a-4fbf-98b1-c2b33fc24644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194411462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2194411462
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3369945333
Short name T814
Test name
Test status
Simulation time 99204909 ps
CPU time 3.27 seconds
Started Jul 21 05:37:10 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 214328 kb
Host smart-1f4e4746-d67c-4faf-bc4f-5192ae9acd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369945333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3369945333
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2331291516
Short name T751
Test name
Test status
Simulation time 235005255 ps
CPU time 3.32 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 207340 kb
Host smart-81be2b51-4a29-40e0-8aef-ac9990f1cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331291516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2331291516
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1635411967
Short name T303
Test name
Test status
Simulation time 399181588 ps
CPU time 3.28 seconds
Started Jul 21 05:37:13 PM PDT 24
Finished Jul 21 05:37:17 PM PDT 24
Peak memory 214464 kb
Host smart-9cf7d46e-1352-4ac6-94c0-b5a860a022ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635411967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1635411967
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1881607623
Short name T317
Test name
Test status
Simulation time 268340912 ps
CPU time 4.13 seconds
Started Jul 21 05:37:13 PM PDT 24
Finished Jul 21 05:37:18 PM PDT 24
Peak memory 214064 kb
Host smart-dafa0b6a-0de2-41fe-8b87-89a84b7ab433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881607623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1881607623
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3209100697
Short name T240
Test name
Test status
Simulation time 844664167 ps
CPU time 20.36 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 208148 kb
Host smart-254a4e88-8284-411f-90b8-7be80a90b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209100697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3209100697
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.757145326
Short name T529
Test name
Test status
Simulation time 133905794 ps
CPU time 5.05 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:18 PM PDT 24
Peak memory 206520 kb
Host smart-4cb26b92-b74b-4b8c-9966-5fdd1534eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757145326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.757145326
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3048784015
Short name T807
Test name
Test status
Simulation time 238848981 ps
CPU time 3.01 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 206584 kb
Host smart-a1d9ff3d-7b15-4db9-932f-cca53101eb73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048784015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3048784015
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.78746868
Short name T481
Test name
Test status
Simulation time 789725107 ps
CPU time 10.84 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:24 PM PDT 24
Peak memory 208840 kb
Host smart-7e0d71d0-35a7-482d-8347-b5dede0b3d2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78746868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.78746868
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4072767083
Short name T552
Test name
Test status
Simulation time 217249110 ps
CPU time 3.29 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:24 PM PDT 24
Peak memory 206484 kb
Host smart-340a8950-2d38-4e14-ac6e-d3dd3ce0472b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072767083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4072767083
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.280773723
Short name T801
Test name
Test status
Simulation time 152971478 ps
CPU time 3.35 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 209216 kb
Host smart-42329a88-84eb-403f-9a43-be66d8655e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280773723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.280773723
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2871361135
Short name T485
Test name
Test status
Simulation time 115860711 ps
CPU time 2.69 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 208068 kb
Host smart-5feeeb1c-4f8a-401e-a2a3-ea6099c32223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871361135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2871361135
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.850982180
Short name T912
Test name
Test status
Simulation time 735596102 ps
CPU time 24.01 seconds
Started Jul 21 05:37:10 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 216984 kb
Host smart-80199737-3a8f-43d9-8e71-214efc76ead7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850982180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.850982180
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.183225662
Short name T610
Test name
Test status
Simulation time 194917728 ps
CPU time 5.86 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:17 PM PDT 24
Peak memory 214076 kb
Host smart-a351c5c2-0e14-4b4f-890d-11de9dffec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183225662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.183225662
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1697942140
Short name T173
Test name
Test status
Simulation time 46177927 ps
CPU time 1.52 seconds
Started Jul 21 05:37:14 PM PDT 24
Finished Jul 21 05:37:16 PM PDT 24
Peak memory 209688 kb
Host smart-67b4b9fd-5785-4dd9-b8f1-7939dcd1f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697942140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1697942140
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.26773021
Short name T590
Test name
Test status
Simulation time 54354294 ps
CPU time 0.97 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:20 PM PDT 24
Peak memory 205856 kb
Host smart-c8b3ab37-8f2d-434a-a998-2b9695dd6572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26773021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.26773021
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.349523267
Short name T787
Test name
Test status
Simulation time 390000970 ps
CPU time 3.42 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:26 PM PDT 24
Peak memory 209848 kb
Host smart-697bace4-fc8e-4129-badf-b8bd752ecb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349523267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.349523267
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1199466721
Short name T97
Test name
Test status
Simulation time 67843226 ps
CPU time 3.85 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 209452 kb
Host smart-29bde8b6-7e83-4448-8d8f-26341726c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199466721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1199466721
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1447121162
Short name T363
Test name
Test status
Simulation time 228171069 ps
CPU time 4.53 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:24 PM PDT 24
Peak memory 206824 kb
Host smart-fa05bbea-7f5f-4670-b3a7-ceeda525454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447121162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1447121162
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.987910457
Short name T792
Test name
Test status
Simulation time 1899646521 ps
CPU time 4.22 seconds
Started Jul 21 05:37:14 PM PDT 24
Finished Jul 21 05:37:19 PM PDT 24
Peak memory 222080 kb
Host smart-ed688f31-8630-4c70-9435-38e352729e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987910457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.987910457
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2451930762
Short name T848
Test name
Test status
Simulation time 2314404340 ps
CPU time 63.27 seconds
Started Jul 21 05:37:12 PM PDT 24
Finished Jul 21 05:38:15 PM PDT 24
Peak memory 209932 kb
Host smart-9641e3c2-16d9-44af-b0a9-d3e3bd5a9d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451930762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2451930762
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2437075410
Short name T723
Test name
Test status
Simulation time 345046383 ps
CPU time 8.82 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 207764 kb
Host smart-20922065-3858-4213-8dcf-ae94ec39de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437075410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2437075410
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3410076452
Short name T617
Test name
Test status
Simulation time 1089466011 ps
CPU time 7.68 seconds
Started Jul 21 05:37:13 PM PDT 24
Finished Jul 21 05:37:21 PM PDT 24
Peak memory 208796 kb
Host smart-5f479b09-97b8-45f0-aad3-a0428afcafff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410076452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3410076452
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2617742075
Short name T901
Test name
Test status
Simulation time 171998781 ps
CPU time 2.77 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:23 PM PDT 24
Peak memory 208244 kb
Host smart-8eca4c85-5b34-4481-b20d-90ab1dbe382a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617742075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2617742075
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1301895818
Short name T459
Test name
Test status
Simulation time 364496306 ps
CPU time 9.55 seconds
Started Jul 21 05:37:14 PM PDT 24
Finished Jul 21 05:37:24 PM PDT 24
Peak memory 208412 kb
Host smart-21c6fca3-2f37-4c88-abe9-67c15f5a26bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301895818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1301895818
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2838444546
Short name T294
Test name
Test status
Simulation time 31303007 ps
CPU time 2.22 seconds
Started Jul 21 05:37:18 PM PDT 24
Finished Jul 21 05:37:21 PM PDT 24
Peak memory 207992 kb
Host smart-e4a5c925-bc1c-44f5-99da-5745217bef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838444546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2838444546
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1774795845
Short name T888
Test name
Test status
Simulation time 1146097654 ps
CPU time 5.74 seconds
Started Jul 21 05:37:11 PM PDT 24
Finished Jul 21 05:37:18 PM PDT 24
Peak memory 207672 kb
Host smart-90a5a113-6147-4c66-98fe-5f7004b8b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774795845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1774795845
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.300458447
Short name T203
Test name
Test status
Simulation time 7542780994 ps
CPU time 22.63 seconds
Started Jul 21 05:37:22 PM PDT 24
Finished Jul 21 05:37:45 PM PDT 24
Peak memory 215548 kb
Host smart-ba428985-cc23-4bc7-92a6-5ab5913d2302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300458447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.300458447
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3241109918
Short name T236
Test name
Test status
Simulation time 1275581709 ps
CPU time 23.42 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:42 PM PDT 24
Peak memory 222340 kb
Host smart-e2dc90c3-e744-437a-9d2b-c0a1d24a7e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241109918 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3241109918
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1336869163
Short name T645
Test name
Test status
Simulation time 302009079 ps
CPU time 4.26 seconds
Started Jul 21 05:37:10 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 207720 kb
Host smart-1fefa403-21f2-43b3-87d1-659279191c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336869163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1336869163
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2320732020
Short name T471
Test name
Test status
Simulation time 1987062100 ps
CPU time 11.52 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 210596 kb
Host smart-d0fe3974-edfc-4390-80bd-7d67ce671f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320732020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2320732020
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3679577934
Short name T813
Test name
Test status
Simulation time 16537478 ps
CPU time 0.91 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:23 PM PDT 24
Peak memory 205832 kb
Host smart-416adc49-be7d-4902-85e9-94582190d691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679577934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3679577934
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1901647299
Short name T624
Test name
Test status
Simulation time 346517064 ps
CPU time 2.83 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 207244 kb
Host smart-c632a39c-f6fb-4697-bb7a-135b2d7e7946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901647299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1901647299
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_random.92472764
Short name T359
Test name
Test status
Simulation time 360067968 ps
CPU time 4.11 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 209420 kb
Host smart-44761b61-ae72-478a-9064-b55290f7302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92472764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.92472764
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3908776111
Short name T687
Test name
Test status
Simulation time 136081875 ps
CPU time 3.87 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:23 PM PDT 24
Peak memory 207960 kb
Host smart-c7928e38-b39a-4e78-95f3-baaf6c9beba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908776111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3908776111
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1709388917
Short name T108
Test name
Test status
Simulation time 124234207 ps
CPU time 3.21 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:26 PM PDT 24
Peak memory 206784 kb
Host smart-9d535e9e-062b-4a2d-b875-caebe3db186b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709388917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1709388917
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3066482045
Short name T744
Test name
Test status
Simulation time 1443367086 ps
CPU time 6.84 seconds
Started Jul 21 05:37:17 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 207696 kb
Host smart-8dd5aaeb-549d-46ba-8c4d-a3b9c3dcf1ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066482045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3066482045
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1732777251
Short name T551
Test name
Test status
Simulation time 81195616 ps
CPU time 2.53 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:22 PM PDT 24
Peak memory 206736 kb
Host smart-9ec32581-b775-439e-a2a3-59f77b0e0645
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732777251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1732777251
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2189476900
Short name T842
Test name
Test status
Simulation time 63561586 ps
CPU time 2.99 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 209388 kb
Host smart-8eb5ae39-afc7-474b-9383-e38de9280f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189476900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2189476900
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.614213985
Short name T712
Test name
Test status
Simulation time 139709322 ps
CPU time 5.07 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:26 PM PDT 24
Peak memory 206628 kb
Host smart-ae73cd63-94d0-4bd4-9eae-c03b1c28370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614213985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.614213985
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3318432540
Short name T898
Test name
Test status
Simulation time 2310166633 ps
CPU time 32.3 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:54 PM PDT 24
Peak memory 215068 kb
Host smart-4ee21c39-0afd-4d3a-9269-2fd80302d70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318432540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3318432540
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4209435766
Short name T135
Test name
Test status
Simulation time 1312042734 ps
CPU time 41.35 seconds
Started Jul 21 05:37:18 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 222116 kb
Host smart-b8171b4d-ceea-4487-be48-047530d16572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209435766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4209435766
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3425741055
Short name T619
Test name
Test status
Simulation time 249993449 ps
CPU time 2.58 seconds
Started Jul 21 05:37:22 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 209596 kb
Host smart-520f4bfe-5468-4c81-ae3d-1d04a3d3da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425741055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3425741055
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3103656969
Short name T896
Test name
Test status
Simulation time 14987724 ps
CPU time 0.79 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:27 PM PDT 24
Peak memory 205860 kb
Host smart-857723ef-d747-4fd7-8210-32eaba258cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103656969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3103656969
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1713595503
Short name T319
Test name
Test status
Simulation time 66082403 ps
CPU time 4.79 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:27 PM PDT 24
Peak memory 214080 kb
Host smart-a6c7a9a0-8de5-4a18-b5ac-01ab6bc65427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713595503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1713595503
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.935814991
Short name T9
Test name
Test status
Simulation time 100402542 ps
CPU time 3.41 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 214372 kb
Host smart-5810a5b2-ebe1-4fa8-a492-2031e79788aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935814991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.935814991
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1942569526
Short name T527
Test name
Test status
Simulation time 126789728 ps
CPU time 3.33 seconds
Started Jul 21 05:37:19 PM PDT 24
Finished Jul 21 05:37:23 PM PDT 24
Peak memory 209908 kb
Host smart-46f0ae7e-1d98-48a7-a5aa-3d9a126dd27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942569526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1942569526
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3127941976
Short name T304
Test name
Test status
Simulation time 120912215 ps
CPU time 5.39 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 214048 kb
Host smart-7259d605-6397-446e-8f88-039d7f77f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127941976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3127941976
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.209110687
Short name T825
Test name
Test status
Simulation time 430475509 ps
CPU time 5.64 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:28 PM PDT 24
Peak memory 207528 kb
Host smart-fe4a4c65-f57d-4d59-9ae4-9dc47e094186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209110687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.209110687
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3665281845
Short name T464
Test name
Test status
Simulation time 61925199 ps
CPU time 2.29 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:23 PM PDT 24
Peak memory 206564 kb
Host smart-bb57b181-79c6-4ae5-8d37-c92b2d5d4e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665281845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3665281845
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1763551196
Short name T466
Test name
Test status
Simulation time 69650426 ps
CPU time 2.96 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:25 PM PDT 24
Peak memory 207884 kb
Host smart-5208e9d2-f834-4146-af36-21cf7405ab01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763551196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1763551196
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1041819754
Short name T197
Test name
Test status
Simulation time 574687262 ps
CPU time 5.11 seconds
Started Jul 21 05:37:21 PM PDT 24
Finished Jul 21 05:37:27 PM PDT 24
Peak memory 208432 kb
Host smart-a660c6b6-3eff-427d-a04c-f401ae49e34e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041819754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1041819754
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1190378935
Short name T642
Test name
Test status
Simulation time 1659654135 ps
CPU time 37.91 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 208252 kb
Host smart-b24b45f2-09b1-42ae-81f2-429b892475c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190378935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1190378935
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3786013310
Short name T490
Test name
Test status
Simulation time 74138013 ps
CPU time 3.04 seconds
Started Jul 21 05:37:25 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 207732 kb
Host smart-2a258cab-23ee-4441-b9e2-bc68a251c075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786013310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3786013310
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.575980570
Short name T567
Test name
Test status
Simulation time 4463919572 ps
CPU time 15.26 seconds
Started Jul 21 05:37:20 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 207724 kb
Host smart-654b3c6a-eafa-46ec-b4b1-a51dfdcc68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575980570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.575980570
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.595841597
Short name T233
Test name
Test status
Simulation time 1920432347 ps
CPU time 14.91 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:48 PM PDT 24
Peak memory 220160 kb
Host smart-765ce288-ddc1-4777-9893-ccc285332fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595841597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.595841597
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3909501126
Short name T275
Test name
Test status
Simulation time 387290309 ps
CPU time 6.94 seconds
Started Jul 21 05:37:24 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 218340 kb
Host smart-b212fba7-55e8-4479-970d-de2fdcc06fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909501126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3909501126
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2160434405
Short name T472
Test name
Test status
Simulation time 343236069 ps
CPU time 2.5 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 210268 kb
Host smart-1e1efdf8-3e98-4f05-8b3e-70c2dfb93eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160434405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2160434405
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3854139709
Short name T461
Test name
Test status
Simulation time 39130427 ps
CPU time 0.77 seconds
Started Jul 21 05:37:31 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 205300 kb
Host smart-1339ee79-99a4-4561-b748-9b376633d4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854139709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3854139709
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3643511
Short name T65
Test name
Test status
Simulation time 194093619 ps
CPU time 2.52 seconds
Started Jul 21 05:37:25 PM PDT 24
Finished Jul 21 05:37:28 PM PDT 24
Peak memory 208852 kb
Host smart-ef87b853-cb8c-49e2-827b-671414e1f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3643511
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.101168361
Short name T553
Test name
Test status
Simulation time 28168464 ps
CPU time 2.11 seconds
Started Jul 21 05:37:28 PM PDT 24
Finished Jul 21 05:37:31 PM PDT 24
Peak memory 214064 kb
Host smart-5fd05266-7146-4597-8a19-5e38816b1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101168361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.101168361
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2228591478
Short name T219
Test name
Test status
Simulation time 88784494 ps
CPU time 2.99 seconds
Started Jul 21 05:37:27 PM PDT 24
Finished Jul 21 05:37:30 PM PDT 24
Peak memory 220100 kb
Host smart-f4667e5f-f7f2-4ac3-aceb-937a63c2dbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228591478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2228591478
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2049849082
Short name T524
Test name
Test status
Simulation time 5315933384 ps
CPU time 45.3 seconds
Started Jul 21 05:37:31 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 213544 kb
Host smart-8622cde8-ce75-47a6-bca0-db7802961f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049849082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2049849082
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3758351421
Short name T758
Test name
Test status
Simulation time 1678634265 ps
CPU time 41 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 208032 kb
Host smart-da12616d-a0e6-4320-862b-faa13f3af08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758351421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3758351421
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2780208380
Short name T396
Test name
Test status
Simulation time 1045395427 ps
CPU time 24.76 seconds
Started Jul 21 05:37:25 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 208060 kb
Host smart-2d6508ee-4d70-47dc-b3ea-8a67672750dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780208380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2780208380
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4099424424
Short name T518
Test name
Test status
Simulation time 1194599529 ps
CPU time 3.11 seconds
Started Jul 21 05:37:28 PM PDT 24
Finished Jul 21 05:37:32 PM PDT 24
Peak memory 208064 kb
Host smart-4732f327-4ad3-4112-b94e-8579e7a08612
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099424424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4099424424
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2098151266
Short name T279
Test name
Test status
Simulation time 677703466 ps
CPU time 3.32 seconds
Started Jul 21 05:37:30 PM PDT 24
Finished Jul 21 05:37:34 PM PDT 24
Peak memory 206612 kb
Host smart-bc8e0837-fafa-47e0-8e0e-3da0bad56539
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098151266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2098151266
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2489369084
Short name T470
Test name
Test status
Simulation time 293634830 ps
CPU time 3.43 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 215448 kb
Host smart-b4a28a39-0e62-4862-ac1f-965e040b03aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489369084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2489369084
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3836156827
Short name T395
Test name
Test status
Simulation time 65719714 ps
CPU time 2.43 seconds
Started Jul 21 05:37:27 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 208172 kb
Host smart-441bd66c-591f-4cf4-97b3-d3cc1fa7561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836156827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3836156827
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.407380410
Short name T358
Test name
Test status
Simulation time 5283932584 ps
CPU time 21.79 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:52 PM PDT 24
Peak memory 222480 kb
Host smart-7651f037-a233-4786-b0fc-1a9d7601e05f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407380410 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.407380410
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2846780653
Short name T333
Test name
Test status
Simulation time 184105820 ps
CPU time 6.66 seconds
Started Jul 21 05:37:23 PM PDT 24
Finished Jul 21 05:37:30 PM PDT 24
Peak memory 214056 kb
Host smart-78434385-9042-4cb2-82dc-cf17acebe72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846780653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2846780653
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.520639925
Short name T789
Test name
Test status
Simulation time 61848747 ps
CPU time 2.79 seconds
Started Jul 21 05:37:28 PM PDT 24
Finished Jul 21 05:37:31 PM PDT 24
Peak memory 209660 kb
Host smart-e0516f34-5f52-4469-a1ad-2987203246ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520639925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.520639925
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1766367550
Short name T625
Test name
Test status
Simulation time 28011108 ps
CPU time 0.76 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 205840 kb
Host smart-cfbc7171-8e25-483d-b73f-3a87eab51817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766367550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1766367550
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.615818134
Short name T777
Test name
Test status
Simulation time 77269886 ps
CPU time 3.32 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 214032 kb
Host smart-b22f9d60-96e3-4592-8abf-2bb5861337d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615818134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.615818134
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1675533086
Short name T218
Test name
Test status
Simulation time 545920594 ps
CPU time 2.5 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 221412 kb
Host smart-1e0a467c-a861-4e73-9c4e-9d0597578b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675533086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1675533086
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.333314599
Short name T320
Test name
Test status
Simulation time 9208435744 ps
CPU time 14.56 seconds
Started Jul 21 05:37:28 PM PDT 24
Finished Jul 21 05:37:44 PM PDT 24
Peak memory 214176 kb
Host smart-e18d942f-68bd-4a46-9ef8-6bf63e703a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333314599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.333314599
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1834848633
Short name T797
Test name
Test status
Simulation time 73313231 ps
CPU time 3.53 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 213980 kb
Host smart-c22b525b-6825-434c-8052-5dcc947e7fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834848633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1834848633
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1335506063
Short name T8
Test name
Test status
Simulation time 234551347 ps
CPU time 2.87 seconds
Started Jul 21 05:37:28 PM PDT 24
Finished Jul 21 05:37:31 PM PDT 24
Peak memory 214204 kb
Host smart-23e39a63-1d34-4bad-90be-230110846874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335506063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1335506063
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.192052679
Short name T573
Test name
Test status
Simulation time 66393883 ps
CPU time 4.21 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:34 PM PDT 24
Peak memory 208104 kb
Host smart-0ae7512a-de6d-4e6e-a174-34c15a38ca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192052679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.192052679
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.549033943
Short name T656
Test name
Test status
Simulation time 198302964 ps
CPU time 6.15 seconds
Started Jul 21 05:37:27 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 207944 kb
Host smart-814a5451-e631-4715-a500-d1b0735d59fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549033943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.549033943
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1903419548
Short name T511
Test name
Test status
Simulation time 62053221 ps
CPU time 3.2 seconds
Started Jul 21 05:37:29 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 208332 kb
Host smart-0f253e15-939f-4bb4-9316-abec6d512534
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903419548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1903419548
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1548903806
Short name T631
Test name
Test status
Simulation time 455517236 ps
CPU time 3.9 seconds
Started Jul 21 05:37:25 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 206584 kb
Host smart-f8538d5f-0278-487c-adf0-788ab19fb563
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548903806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1548903806
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2214115919
Short name T663
Test name
Test status
Simulation time 140421481 ps
CPU time 2.57 seconds
Started Jul 21 05:37:26 PM PDT 24
Finished Jul 21 05:37:29 PM PDT 24
Peak memory 207436 kb
Host smart-0f93ba9a-9edb-4920-90cd-bd0d7e5e2923
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214115919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2214115919
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.994352512
Short name T579
Test name
Test status
Simulation time 27932585 ps
CPU time 1.93 seconds
Started Jul 21 05:37:36 PM PDT 24
Finished Jul 21 05:37:38 PM PDT 24
Peak memory 214096 kb
Host smart-163b1762-de18-4978-ba18-a0c38ac50ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994352512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.994352512
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2778101960
Short name T752
Test name
Test status
Simulation time 369950781 ps
CPU time 10.16 seconds
Started Jul 21 05:37:25 PM PDT 24
Finished Jul 21 05:37:36 PM PDT 24
Peak memory 208104 kb
Host smart-fe41fa17-7f2c-4b7c-b4a2-0a736b33351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778101960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2778101960
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2302887381
Short name T193
Test name
Test status
Simulation time 462500147 ps
CPU time 8.73 seconds
Started Jul 21 05:37:36 PM PDT 24
Finished Jul 21 05:37:45 PM PDT 24
Peak memory 222228 kb
Host smart-7e6cc438-5d9a-4452-bf19-ef0bb4485de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302887381 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2302887381
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2727768495
Short name T586
Test name
Test status
Simulation time 12587670120 ps
CPU time 24.54 seconds
Started Jul 21 05:37:27 PM PDT 24
Finished Jul 21 05:37:52 PM PDT 24
Peak memory 218124 kb
Host smart-cdd2e6de-026c-432c-9fa3-2c0f658a53e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727768495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2727768495
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2632571581
Short name T588
Test name
Test status
Simulation time 71297437 ps
CPU time 2.67 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 209660 kb
Host smart-f42ba35c-625a-4210-a296-e1043999531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632571581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2632571581
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3166462992
Short name T435
Test name
Test status
Simulation time 54474835 ps
CPU time 0.82 seconds
Started Jul 21 05:36:29 PM PDT 24
Finished Jul 21 05:36:30 PM PDT 24
Peak memory 205844 kb
Host smart-26d23c05-7111-4e0f-8994-661d88e18243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166462992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3166462992
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.21879018
Short name T141
Test name
Test status
Simulation time 2027069089 ps
CPU time 103.3 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:38:03 PM PDT 24
Peak memory 214860 kb
Host smart-3c750c8c-1d91-49d7-b76d-a34585b46610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21879018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.21879018
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3572091901
Short name T38
Test name
Test status
Simulation time 620690490 ps
CPU time 3.82 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 214424 kb
Host smart-3a93e275-710b-407a-ae12-462c83b585df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572091901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3572091901
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1616575408
Short name T673
Test name
Test status
Simulation time 177553308 ps
CPU time 3.94 seconds
Started Jul 21 05:36:25 PM PDT 24
Finished Jul 21 05:36:30 PM PDT 24
Peak memory 218064 kb
Host smart-b87a95ca-89d1-487f-a78a-ce395d7e78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616575408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1616575408
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.735396606
Short name T544
Test name
Test status
Simulation time 119754683 ps
CPU time 3.64 seconds
Started Jul 21 05:36:29 PM PDT 24
Finished Jul 21 05:36:33 PM PDT 24
Peak memory 209652 kb
Host smart-2c480585-b2a3-41dd-97f3-cfd4b674783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735396606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.735396606
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2733372864
Short name T724
Test name
Test status
Simulation time 2490010178 ps
CPU time 50.39 seconds
Started Jul 21 05:36:23 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 214168 kb
Host smart-8a0c1810-1203-47e4-bc7c-3a77086c18f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733372864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2733372864
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2273760495
Short name T104
Test name
Test status
Simulation time 1000669158 ps
CPU time 10.02 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:37 PM PDT 24
Peak memory 231076 kb
Host smart-9cfb8e45-a53a-4db3-b7a7-3b93e96bcd3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273760495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2273760495
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1660261509
Short name T641
Test name
Test status
Simulation time 730204939 ps
CPU time 24.47 seconds
Started Jul 21 05:36:22 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 208676 kb
Host smart-9e8599f1-9915-4301-ab3a-1bbe0ece482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660261509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1660261509
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2828901848
Short name T763
Test name
Test status
Simulation time 1289393977 ps
CPU time 4.67 seconds
Started Jul 21 05:36:23 PM PDT 24
Finished Jul 21 05:36:28 PM PDT 24
Peak memory 208080 kb
Host smart-80434185-ff38-40ae-979a-b23a550e98b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828901848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2828901848
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3756008715
Short name T478
Test name
Test status
Simulation time 556192782 ps
CPU time 6.28 seconds
Started Jul 21 05:36:22 PM PDT 24
Finished Jul 21 05:36:29 PM PDT 24
Peak memory 206716 kb
Host smart-7a6d791a-7430-49e9-9446-6b69bbbcd21d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756008715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3756008715
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2679589337
Short name T851
Test name
Test status
Simulation time 182918379 ps
CPU time 2.82 seconds
Started Jul 21 05:36:20 PM PDT 24
Finished Jul 21 05:36:23 PM PDT 24
Peak memory 206612 kb
Host smart-e09c1c86-c106-48a3-aac2-790ee15ae37b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679589337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2679589337
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.532597286
Short name T337
Test name
Test status
Simulation time 517530517 ps
CPU time 12.13 seconds
Started Jul 21 05:36:30 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 208036 kb
Host smart-3d71d659-3896-461e-b8a3-a619eed20969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532597286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.532597286
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1331116246
Short name T132
Test name
Test status
Simulation time 259949790 ps
CPU time 2.51 seconds
Started Jul 21 05:36:21 PM PDT 24
Finished Jul 21 05:36:24 PM PDT 24
Peak memory 206496 kb
Host smart-932c26ba-252f-45cb-8942-ac7d8d95ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331116246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1331116246
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.931813226
Short name T226
Test name
Test status
Simulation time 4082994718 ps
CPU time 74.15 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 215340 kb
Host smart-0d90fdac-136a-4e6c-9157-ab0f4f0ab877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931813226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.931813226
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1001726408
Short name T354
Test name
Test status
Simulation time 762848814 ps
CPU time 23.99 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 208796 kb
Host smart-b1ccafed-4cb4-45b8-8470-79e6ce1a01a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001726408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1001726408
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.908792221
Short name T865
Test name
Test status
Simulation time 67764672 ps
CPU time 2.33 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:29 PM PDT 24
Peak memory 210100 kb
Host smart-de6e830d-8775-412b-9aa7-f2510a85fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908792221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.908792221
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1744208240
Short name T421
Test name
Test status
Simulation time 55330715 ps
CPU time 0.79 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:33 PM PDT 24
Peak memory 206004 kb
Host smart-27aa0082-cad0-4cd0-af5d-45483ef9121b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744208240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1744208240
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1249130406
Short name T243
Test name
Test status
Simulation time 49159068 ps
CPU time 3.36 seconds
Started Jul 21 05:37:33 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 214072 kb
Host smart-512c729f-ba8e-4c6a-bd2a-5638665ad656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249130406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1249130406
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1105308479
Short name T845
Test name
Test status
Simulation time 1198443209 ps
CPU time 16.73 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 214448 kb
Host smart-79b183cc-da57-43a7-b666-daa99b3cad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105308479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1105308479
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4180076424
Short name T256
Test name
Test status
Simulation time 461206362 ps
CPU time 11.07 seconds
Started Jul 21 05:37:31 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 208252 kb
Host smart-fc7f1fb6-90e3-42fb-8603-59c642a8203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180076424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4180076424
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1097800646
Short name T615
Test name
Test status
Simulation time 2718496632 ps
CPU time 6.9 seconds
Started Jul 21 05:37:33 PM PDT 24
Finished Jul 21 05:37:40 PM PDT 24
Peak memory 220164 kb
Host smart-fad1878e-f717-4095-a6a3-e0ffade971c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097800646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1097800646
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3734183759
Short name T385
Test name
Test status
Simulation time 93747232 ps
CPU time 4.19 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 214020 kb
Host smart-37e10b05-9626-4a75-a3da-f6b4148831e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734183759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3734183759
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3515411120
Short name T58
Test name
Test status
Simulation time 105669263 ps
CPU time 2.89 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:36 PM PDT 24
Peak memory 214080 kb
Host smart-16573e92-c9f2-4a07-901e-9441aa484900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515411120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3515411120
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.804598554
Short name T754
Test name
Test status
Simulation time 162534965 ps
CPU time 3.58 seconds
Started Jul 21 05:37:33 PM PDT 24
Finished Jul 21 05:37:37 PM PDT 24
Peak memory 207576 kb
Host smart-b9cfdfb5-ffdb-45c1-b9d0-c1f5531c6fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804598554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.804598554
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1867132324
Short name T790
Test name
Test status
Simulation time 128621644 ps
CPU time 3.19 seconds
Started Jul 21 05:37:31 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 208536 kb
Host smart-4e0edbd5-612d-4a59-a572-a11a3b02f3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867132324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1867132324
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.278928629
Short name T455
Test name
Test status
Simulation time 171812409 ps
CPU time 4.57 seconds
Started Jul 21 05:37:35 PM PDT 24
Finished Jul 21 05:37:40 PM PDT 24
Peak memory 207524 kb
Host smart-0f6c4384-2aa5-4642-9520-fcbe73ea1d8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278928629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.278928629
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.763454997
Short name T594
Test name
Test status
Simulation time 107379605 ps
CPU time 2.86 seconds
Started Jul 21 05:37:33 PM PDT 24
Finished Jul 21 05:37:36 PM PDT 24
Peak memory 206740 kb
Host smart-021648a0-ddde-4843-84d5-ec370c9b8b42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763454997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.763454997
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3537560838
Short name T431
Test name
Test status
Simulation time 238335083 ps
CPU time 2.75 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:38 PM PDT 24
Peak memory 206600 kb
Host smart-7a0fabd2-47e5-406c-b989-9615a3bf95d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537560838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3537560838
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1872496888
Short name T852
Test name
Test status
Simulation time 56775076 ps
CPU time 2.99 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:36 PM PDT 24
Peak memory 209068 kb
Host smart-35246ea2-0c96-4348-93fc-03bc39ccc7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872496888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1872496888
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2683576672
Short name T662
Test name
Test status
Simulation time 1006468545 ps
CPU time 4.53 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:39 PM PDT 24
Peak memory 207740 kb
Host smart-9e2a45ff-6cb4-4aea-9860-c57869d67c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683576672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2683576672
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1591031593
Short name T340
Test name
Test status
Simulation time 3534560272 ps
CPU time 22.49 seconds
Started Jul 21 05:37:34 PM PDT 24
Finished Jul 21 05:37:57 PM PDT 24
Peak memory 209836 kb
Host smart-421b5b04-eb3e-4ff1-a638-0c87cfeb4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591031593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1591031593
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3384457146
Short name T597
Test name
Test status
Simulation time 632786671 ps
CPU time 5.83 seconds
Started Jul 21 05:37:35 PM PDT 24
Finished Jul 21 05:37:42 PM PDT 24
Peak memory 210824 kb
Host smart-bb337b91-b8c1-4e35-a8ea-d938ab2d16ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384457146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3384457146
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1754412763
Short name T778
Test name
Test status
Simulation time 11528311 ps
CPU time 0.75 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:39 PM PDT 24
Peak memory 205848 kb
Host smart-cd2136c5-a0f2-4fdb-99cd-8133daf3d889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754412763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1754412763
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.811856620
Short name T242
Test name
Test status
Simulation time 232458066 ps
CPU time 4.34 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:44 PM PDT 24
Peak memory 214992 kb
Host smart-9b25c438-0395-416c-9f7f-cd36284eb219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811856620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.811856620
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3576542759
Short name T35
Test name
Test status
Simulation time 37732163 ps
CPU time 2.44 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:41 PM PDT 24
Peak memory 218332 kb
Host smart-7b54eea9-d93d-480e-a906-2270d57d49ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576542759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3576542759
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2722767504
Short name T61
Test name
Test status
Simulation time 443130996 ps
CPU time 12.77 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:52 PM PDT 24
Peak memory 209020 kb
Host smart-daaeda8f-7ff3-4c0f-b72b-ba348acf90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722767504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2722767504
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2206934208
Short name T346
Test name
Test status
Simulation time 199786552 ps
CPU time 3.17 seconds
Started Jul 21 05:37:43 PM PDT 24
Finished Jul 21 05:37:47 PM PDT 24
Peak memory 222172 kb
Host smart-855b44e2-100e-4d98-96b0-faabd512ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206934208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2206934208
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2381961491
Short name T262
Test name
Test status
Simulation time 97187473 ps
CPU time 4.2 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 214096 kb
Host smart-d8d9fe2b-7d56-4923-b53f-5d9209fd000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381961491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2381961491
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1064466278
Short name T307
Test name
Test status
Simulation time 291888025 ps
CPU time 4.01 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 214088 kb
Host smart-ae221479-f9e2-486d-beeb-572a4c034538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064466278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1064466278
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4147386380
Short name T460
Test name
Test status
Simulation time 1534275389 ps
CPU time 10.88 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 209032 kb
Host smart-b826913c-4832-45aa-b0a3-1315266a239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147386380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4147386380
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1828619687
Short name T916
Test name
Test status
Simulation time 83934329 ps
CPU time 3.14 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 208244 kb
Host smart-ac30b6fb-d287-4043-8fed-1a85732498e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828619687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1828619687
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3805168115
Short name T335
Test name
Test status
Simulation time 149985715 ps
CPU time 3.75 seconds
Started Jul 21 05:37:37 PM PDT 24
Finished Jul 21 05:37:41 PM PDT 24
Peak memory 206656 kb
Host smart-2332e9b8-d93c-4cdd-9f05-621beba48a4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805168115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3805168115
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2663334877
Short name T784
Test name
Test status
Simulation time 638731314 ps
CPU time 4.18 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 207896 kb
Host smart-a3d26943-66c3-4fd9-8061-f2147a94f640
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663334877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2663334877
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2138864580
Short name T767
Test name
Test status
Simulation time 36505229 ps
CPU time 2.49 seconds
Started Jul 21 05:37:41 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 207052 kb
Host smart-665dcb40-f126-4609-a0a7-0a77c4003c10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138864580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2138864580
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3365574731
Short name T717
Test name
Test status
Simulation time 110496866 ps
CPU time 3.31 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 214972 kb
Host smart-4f9651c8-bdde-4a79-b6ad-bc84513416f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365574731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3365574731
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.714240231
Short name T879
Test name
Test status
Simulation time 59462994 ps
CPU time 2.44 seconds
Started Jul 21 05:37:32 PM PDT 24
Finished Jul 21 05:37:35 PM PDT 24
Peak memory 206748 kb
Host smart-a03b6431-d9e6-45bc-a890-3d4df6923b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714240231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.714240231
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1792416502
Short name T202
Test name
Test status
Simulation time 1849343335 ps
CPU time 24.11 seconds
Started Jul 21 05:37:43 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 214836 kb
Host smart-f6af333d-109e-4e5a-b94f-398697983c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792416502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1792416502
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2474461149
Short name T587
Test name
Test status
Simulation time 303685923 ps
CPU time 8.36 seconds
Started Jul 21 05:37:41 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 208540 kb
Host smart-91342d1d-c544-4778-bb7e-5b0bde3554eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474461149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2474461149
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.187987379
Short name T439
Test name
Test status
Simulation time 160383107 ps
CPU time 1.92 seconds
Started Jul 21 05:37:42 PM PDT 24
Finished Jul 21 05:37:45 PM PDT 24
Peak memory 209692 kb
Host smart-f7df0d81-2da6-4ea8-8f99-b1c279f07bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187987379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.187987379
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.301849051
Short name T522
Test name
Test status
Simulation time 30140835 ps
CPU time 0.72 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:48 PM PDT 24
Peak memory 205916 kb
Host smart-c507692b-ecbd-4327-bf85-4e9469500db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301849051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.301849051
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.204924257
Short name T379
Test name
Test status
Simulation time 58025042 ps
CPU time 4.38 seconds
Started Jul 21 05:37:35 PM PDT 24
Finished Jul 21 05:37:40 PM PDT 24
Peak memory 215368 kb
Host smart-7fb06b3d-5610-489f-8a6b-3bc30e297dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204924257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.204924257
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2382005812
Short name T817
Test name
Test status
Simulation time 257998016 ps
CPU time 2.95 seconds
Started Jul 21 05:37:44 PM PDT 24
Finished Jul 21 05:37:48 PM PDT 24
Peak memory 208916 kb
Host smart-9e3b0078-29f9-4fc2-8e72-5d173c3b2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382005812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2382005812
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3216661238
Short name T890
Test name
Test status
Simulation time 285702333 ps
CPU time 2.37 seconds
Started Jul 21 05:37:44 PM PDT 24
Finished Jul 21 05:37:47 PM PDT 24
Peak memory 207500 kb
Host smart-31bd39bf-da7e-4653-8fbd-befd4627b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216661238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3216661238
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4251741691
Short name T305
Test name
Test status
Simulation time 93801050 ps
CPU time 2.47 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 214016 kb
Host smart-a992c375-238b-4f16-bf9f-3fa46500be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251741691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4251741691
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1740779530
Short name T52
Test name
Test status
Simulation time 195135233 ps
CPU time 5.77 seconds
Started Jul 21 05:37:47 PM PDT 24
Finished Jul 21 05:37:54 PM PDT 24
Peak memory 209608 kb
Host smart-ce3b70e0-1251-4afc-a493-706059e6c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740779530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1740779530
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3034254982
Short name T649
Test name
Test status
Simulation time 193499856 ps
CPU time 2.87 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:42 PM PDT 24
Peak memory 207432 kb
Host smart-b4e0e815-d4eb-454d-b24b-c85ab82177c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034254982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3034254982
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3636806394
Short name T474
Test name
Test status
Simulation time 2856725868 ps
CPU time 18.91 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 208496 kb
Host smart-10f5a5e7-e533-42c2-abd5-aff432f598e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636806394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3636806394
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.123668183
Short name T771
Test name
Test status
Simulation time 99899386 ps
CPU time 4.57 seconds
Started Jul 21 05:37:39 PM PDT 24
Finished Jul 21 05:37:44 PM PDT 24
Peak memory 208680 kb
Host smart-c0bfe0b8-79f9-4bb9-996f-92983b8e4e0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123668183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.123668183
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.871593875
Short name T698
Test name
Test status
Simulation time 312376011 ps
CPU time 2.76 seconds
Started Jul 21 05:37:41 PM PDT 24
Finished Jul 21 05:37:44 PM PDT 24
Peak memory 208508 kb
Host smart-4fc07b77-6c34-46cf-9f1a-6c42303105bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871593875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.871593875
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1063556069
Short name T750
Test name
Test status
Simulation time 245231509 ps
CPU time 3.4 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:41 PM PDT 24
Peak memory 206944 kb
Host smart-ac05e016-88c3-43ef-8357-2248549bba1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063556069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1063556069
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3074621707
Short name T766
Test name
Test status
Simulation time 73919391 ps
CPU time 3.02 seconds
Started Jul 21 05:37:44 PM PDT 24
Finished Jul 21 05:37:47 PM PDT 24
Peak memory 222096 kb
Host smart-e603567c-0ed6-40a6-bd25-97a0c467d6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074621707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3074621707
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.78397790
Short name T657
Test name
Test status
Simulation time 58819989 ps
CPU time 2.26 seconds
Started Jul 21 05:37:38 PM PDT 24
Finished Jul 21 05:37:41 PM PDT 24
Peak memory 206576 kb
Host smart-f52acaca-8ccd-4d88-8860-d0906a09f5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78397790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.78397790
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.287865800
Short name T822
Test name
Test status
Simulation time 3803506629 ps
CPU time 25.76 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:38:12 PM PDT 24
Peak memory 215424 kb
Host smart-431f2a3c-4ce4-4051-913d-714716e5a394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287865800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.287865800
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4254618225
Short name T525
Test name
Test status
Simulation time 337096942 ps
CPU time 11.68 seconds
Started Jul 21 05:37:47 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 219648 kb
Host smart-8ac8d4aa-2443-40d6-9e57-3e1e7b90b348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254618225 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4254618225
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1235890232
Short name T680
Test name
Test status
Simulation time 456819510 ps
CPU time 3.48 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 206996 kb
Host smart-def52892-1fad-480a-bb50-cedf9d78054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235890232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1235890232
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2371304051
Short name T593
Test name
Test status
Simulation time 18233153 ps
CPU time 0.77 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:46 PM PDT 24
Peak memory 205852 kb
Host smart-854f4fbf-3c5f-491c-9383-11e10279dffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371304051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2371304051
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4209498255
Short name T410
Test name
Test status
Simulation time 44138199 ps
CPU time 2.92 seconds
Started Jul 21 05:37:47 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 214104 kb
Host smart-1e08692b-36db-4f23-98f7-e193aa562475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209498255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4209498255
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3279918989
Short name T78
Test name
Test status
Simulation time 15303207 ps
CPU time 1.31 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 207200 kb
Host smart-65c74dd7-1bef-43e0-ab53-6e21e901632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279918989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3279918989
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.38535325
Short name T96
Test name
Test status
Simulation time 378174283 ps
CPU time 4.48 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 213716 kb
Host smart-0fd6b073-e990-4d4d-8e44-8d4f65e8f109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38535325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.38535325
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.295867096
Short name T282
Test name
Test status
Simulation time 103247350 ps
CPU time 4.95 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:52 PM PDT 24
Peak memory 214000 kb
Host smart-f057eaf4-14a1-45db-bbc2-a36ffe9488c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295867096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.295867096
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3206513765
Short name T72
Test name
Test status
Simulation time 122812257 ps
CPU time 5.45 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:37:54 PM PDT 24
Peak memory 219952 kb
Host smart-e91a5d1c-faa4-4907-a49c-dc00ea90b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206513765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3206513765
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3600834298
Short name T476
Test name
Test status
Simulation time 140954517 ps
CPU time 5.46 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:37:55 PM PDT 24
Peak memory 209080 kb
Host smart-39f34681-5b36-4cbc-afa1-0995b6c8447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600834298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3600834298
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2248203483
Short name T562
Test name
Test status
Simulation time 2711328707 ps
CPU time 16.7 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:38:03 PM PDT 24
Peak memory 208092 kb
Host smart-a91eef53-1286-4b54-8228-138a0de49040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248203483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2248203483
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.121461284
Short name T433
Test name
Test status
Simulation time 486900826 ps
CPU time 5.33 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 206780 kb
Host smart-7cb8cb45-f74a-4089-bc5f-776e026b84d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121461284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.121461284
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.948447899
Short name T17
Test name
Test status
Simulation time 90853995 ps
CPU time 1.91 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 208412 kb
Host smart-1f34e475-a66e-4cec-9a9e-0550e6d6a841
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948447899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.948447899
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3052336655
Short name T818
Test name
Test status
Simulation time 20668510 ps
CPU time 1.81 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:48 PM PDT 24
Peak memory 206636 kb
Host smart-32cd78c9-d261-49f5-a5b3-9403359608a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052336655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3052336655
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1464772891
Short name T254
Test name
Test status
Simulation time 83754570 ps
CPU time 4.22 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 208688 kb
Host smart-6b329b43-d401-45fa-8108-c9a4c7f04dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464772891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1464772891
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3351993023
Short name T667
Test name
Test status
Simulation time 97107167 ps
CPU time 3.58 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 208400 kb
Host smart-491a2e29-c791-492f-8995-e1a9fda2a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351993023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3351993023
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4000116887
Short name T30
Test name
Test status
Simulation time 1727447246 ps
CPU time 52.57 seconds
Started Jul 21 05:37:43 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 216708 kb
Host smart-d5818c07-8677-4607-ab3f-2c5fd3fd43eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000116887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4000116887
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3613710656
Short name T509
Test name
Test status
Simulation time 1716488672 ps
CPU time 40.56 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 209140 kb
Host smart-bee15c25-eeeb-4a74-8abf-4635c7d2607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613710656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3613710656
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.435791815
Short name T859
Test name
Test status
Simulation time 89359946 ps
CPU time 2.66 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 210004 kb
Host smart-4c9e98bd-6fdc-4a47-a5f4-2b384a26edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435791815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.435791815
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.543719835
Short name T863
Test name
Test status
Simulation time 12490360 ps
CPU time 0.79 seconds
Started Jul 21 05:37:58 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 205812 kb
Host smart-3f895b35-1702-4611-b079-08474903e29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543719835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.543719835
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.918139068
Short name T760
Test name
Test status
Simulation time 40978237 ps
CPU time 3.37 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:37:52 PM PDT 24
Peak memory 215068 kb
Host smart-10c18d81-49bf-4d41-bb64-171bd230749a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918139068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.918139068
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1053445441
Short name T47
Test name
Test status
Simulation time 509638845 ps
CPU time 7.73 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:55 PM PDT 24
Peak memory 210244 kb
Host smart-b883021a-dfe9-4373-9063-7128bb6db69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053445441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1053445441
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.420282104
Short name T259
Test name
Test status
Simulation time 4497639415 ps
CPU time 28.81 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 214308 kb
Host smart-d0262205-ae4c-46ad-b795-8272134ba0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420282104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.420282104
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2372190263
Short name T502
Test name
Test status
Simulation time 81842837 ps
CPU time 1.71 seconds
Started Jul 21 05:37:47 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 214132 kb
Host smart-020e5ac1-782a-4074-b591-1e068310e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372190263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2372190263
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3985018113
Short name T521
Test name
Test status
Simulation time 55180336 ps
CPU time 2.06 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 214488 kb
Host smart-19a0d1f8-db6c-48c6-8c61-e2ba0c5017a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985018113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3985018113
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.375853188
Short name T632
Test name
Test status
Simulation time 755532605 ps
CPU time 7.34 seconds
Started Jul 21 05:37:43 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 208492 kb
Host smart-4195dc29-4cf6-43ba-a9fc-0b60660c3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375853188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.375853188
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.307764543
Short name T504
Test name
Test status
Simulation time 1219104895 ps
CPU time 28.57 seconds
Started Jul 21 05:37:48 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 208652 kb
Host smart-497c0644-681e-4130-b6d0-b7b612f39a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307764543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.307764543
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1103416064
Short name T909
Test name
Test status
Simulation time 39994657 ps
CPU time 2.4 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 206708 kb
Host smart-79425be4-2186-4b11-adf3-731cb884aea9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103416064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1103416064
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4026419716
Short name T725
Test name
Test status
Simulation time 100699715 ps
CPU time 2.78 seconds
Started Jul 21 05:37:45 PM PDT 24
Finished Jul 21 05:37:50 PM PDT 24
Peak memory 206680 kb
Host smart-5a6bb2c1-0245-4725-99b6-f0aca8e4d057
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026419716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4026419716
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3901376185
Short name T671
Test name
Test status
Simulation time 122595869 ps
CPU time 4.47 seconds
Started Jul 21 05:37:49 PM PDT 24
Finished Jul 21 05:37:54 PM PDT 24
Peak memory 206768 kb
Host smart-bb74fc9c-8621-4678-aa74-a6bfd21ed9c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901376185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3901376185
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3122222970
Short name T505
Test name
Test status
Simulation time 459048879 ps
CPU time 2.4 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 207188 kb
Host smart-325f1922-a27d-4556-8d21-de94c8bbdf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122222970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3122222970
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1173056162
Short name T128
Test name
Test status
Simulation time 1671676501 ps
CPU time 25.94 seconds
Started Jul 21 05:37:50 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 207932 kb
Host smart-c71f0ddd-6003-4a06-9601-767399f3abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173056162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1173056162
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2565248374
Short name T82
Test name
Test status
Simulation time 3087779908 ps
CPU time 18.04 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:38:12 PM PDT 24
Peak memory 216128 kb
Host smart-1c60d3da-e700-41df-bce4-6f4d472b9b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565248374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2565248374
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.954915000
Short name T730
Test name
Test status
Simulation time 61908604 ps
CPU time 3.56 seconds
Started Jul 21 05:37:46 PM PDT 24
Finished Jul 21 05:37:51 PM PDT 24
Peak memory 207900 kb
Host smart-2d79bb96-0fc7-42ee-b531-7ac720282730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954915000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.954915000
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2816262438
Short name T41
Test name
Test status
Simulation time 32756183 ps
CPU time 1.25 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 208336 kb
Host smart-2850b1ec-e51b-4446-aaf8-142ce418fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816262438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2816262438
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3413599788
Short name T741
Test name
Test status
Simulation time 8584989 ps
CPU time 0.82 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:37:56 PM PDT 24
Peak memory 205840 kb
Host smart-0db19cf7-9d67-4e3a-87bd-bb5e679d6722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413599788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3413599788
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.948663707
Short name T416
Test name
Test status
Simulation time 568435076 ps
CPU time 31.13 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 214096 kb
Host smart-c474e668-d9f3-4864-8473-5f6166438290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948663707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.948663707
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.112722204
Short name T318
Test name
Test status
Simulation time 352226905 ps
CPU time 2.23 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:04 PM PDT 24
Peak memory 209624 kb
Host smart-556331ab-9a56-4b18-837a-a6ddcd28c475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112722204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.112722204
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.51233121
Short name T215
Test name
Test status
Simulation time 201962718 ps
CPU time 5.64 seconds
Started Jul 21 05:37:52 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 220684 kb
Host smart-445cd8f5-1955-4844-881b-b6847cf4fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51233121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.51233121
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3660400518
Short name T893
Test name
Test status
Simulation time 3245263957 ps
CPU time 32.77 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 215108 kb
Host smart-65c8b1e2-8b2b-4216-ae14-42c8603613a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660400518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3660400518
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.484336826
Short name T737
Test name
Test status
Simulation time 211013126 ps
CPU time 2.74 seconds
Started Jul 21 05:37:52 PM PDT 24
Finished Jul 21 05:37:56 PM PDT 24
Peak memory 219504 kb
Host smart-79184375-a7a7-4eb1-81df-c7176ca70b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484336826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.484336826
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4144329384
Short name T400
Test name
Test status
Simulation time 132589587 ps
CPU time 6.18 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 209204 kb
Host smart-0fa96eed-0169-44d2-bace-b9414dba554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144329384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4144329384
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2412064360
Short name T563
Test name
Test status
Simulation time 1910685877 ps
CPU time 39.05 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 208780 kb
Host smart-b9384871-2bbc-4cc9-9961-245856279ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412064360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2412064360
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3888715769
Short name T90
Test name
Test status
Simulation time 97448007 ps
CPU time 2.59 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 207216 kb
Host smart-98f7d8f2-390f-49ea-91d0-28b86fce3adf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888715769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3888715769
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2942735970
Short name T614
Test name
Test status
Simulation time 107662942 ps
CPU time 3.77 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 206548 kb
Host smart-6002c080-a569-440c-8442-a8f1932f9ec9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942735970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2942735970
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2806383332
Short name T361
Test name
Test status
Simulation time 560364808 ps
CPU time 4.8 seconds
Started Jul 21 05:37:52 PM PDT 24
Finished Jul 21 05:37:57 PM PDT 24
Peak memory 208356 kb
Host smart-b00aaa63-1791-47be-a4ba-eff7901c0d20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806383332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2806383332
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.355026186
Short name T368
Test name
Test status
Simulation time 304750303 ps
CPU time 2.53 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:02 PM PDT 24
Peak memory 217924 kb
Host smart-68aa1a87-b548-4571-a765-3fe02cb86fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355026186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.355026186
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1412963501
Short name T534
Test name
Test status
Simulation time 151662381 ps
CPU time 2.64 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:37:56 PM PDT 24
Peak memory 208664 kb
Host smart-523b841b-8412-4ca2-ac47-b5a0568e6cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412963501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1412963501
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3001500279
Short name T718
Test name
Test status
Simulation time 3770189497 ps
CPU time 48.81 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:38:45 PM PDT 24
Peak memory 222236 kb
Host smart-2b493e5c-88de-4278-8f43-26656050cce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001500279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3001500279
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.221459288
Short name T560
Test name
Test status
Simulation time 384064628 ps
CPU time 4.62 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 208744 kb
Host smart-c984aa67-ea24-4f4f-bfc7-e12ca0bc4a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221459288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.221459288
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4280337757
Short name T761
Test name
Test status
Simulation time 2039587734 ps
CPU time 5.34 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 209908 kb
Host smart-e3d7a05c-4da3-4e96-8750-115bca3a3b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280337757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4280337757
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.462027500
Short name T554
Test name
Test status
Simulation time 162922184 ps
CPU time 0.84 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:03 PM PDT 24
Peak memory 205836 kb
Host smart-6ace98c4-7f95-41ef-a7e6-e7ca3a4381bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462027500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.462027500
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.759632490
Short name T550
Test name
Test status
Simulation time 56880243 ps
CPU time 2.76 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 208664 kb
Host smart-63087ee9-cdcd-4187-a9c4-6ec75fe7e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759632490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.759632490
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3949756982
Short name T246
Test name
Test status
Simulation time 25405756 ps
CPU time 1.69 seconds
Started Jul 21 05:37:55 PM PDT 24
Finished Jul 21 05:37:57 PM PDT 24
Peak memory 214092 kb
Host smart-75404bcd-235d-41e6-8c3c-5c696101a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949756982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3949756982
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3444396421
Short name T20
Test name
Test status
Simulation time 59877913 ps
CPU time 3.1 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 213996 kb
Host smart-cf7d6a05-0347-4a8a-9fcc-7a8558e4204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444396421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3444396421
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1654488510
Short name T696
Test name
Test status
Simulation time 51750187 ps
CPU time 3.11 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:37:59 PM PDT 24
Peak memory 207260 kb
Host smart-22593e41-7aca-4dd8-93da-1c93f87ddf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654488510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1654488510
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1873854855
Short name T616
Test name
Test status
Simulation time 300733787 ps
CPU time 6.06 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 208720 kb
Host smart-6d8dea47-f551-4586-a64f-8c21ecc7328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873854855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1873854855
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.459756049
Short name T313
Test name
Test status
Simulation time 5867433754 ps
CPU time 60.68 seconds
Started Jul 21 05:37:52 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 208800 kb
Host smart-60c9ec60-fade-48ef-8ad3-21bf3eb301ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459756049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.459756049
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2643232568
Short name T491
Test name
Test status
Simulation time 38471864 ps
CPU time 2.49 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:02 PM PDT 24
Peak memory 208504 kb
Host smart-9af50a17-30cd-4c0d-9650-40f79c14e002
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643232568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2643232568
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.330485728
Short name T272
Test name
Test status
Simulation time 174981101 ps
CPU time 5.19 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 208328 kb
Host smart-76a5ee9e-f1d0-4aab-86f9-e96fefca59ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330485728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.330485728
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3657662701
Short name T646
Test name
Test status
Simulation time 54337098 ps
CPU time 2.84 seconds
Started Jul 21 05:37:52 PM PDT 24
Finished Jul 21 05:37:56 PM PDT 24
Peak memory 208612 kb
Host smart-4ac42e4c-4b4a-453a-a89b-4f7ce999a3b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657662701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3657662701
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4087866416
Short name T740
Test name
Test status
Simulation time 93065298 ps
CPU time 1.53 seconds
Started Jul 21 05:37:54 PM PDT 24
Finished Jul 21 05:37:56 PM PDT 24
Peak memory 214932 kb
Host smart-fcccbe48-6d18-41a5-9950-954da0cd97f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087866416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4087866416
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3114075132
Short name T685
Test name
Test status
Simulation time 27544415 ps
CPU time 2.08 seconds
Started Jul 21 05:37:55 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 208112 kb
Host smart-496c019e-5915-419a-a01e-4782503e71f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114075132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3114075132
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1108176723
Short name T125
Test name
Test status
Simulation time 179207003 ps
CPU time 6.76 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 222372 kb
Host smart-d0a536f6-012c-42cc-8790-d89129a42351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108176723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1108176723
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3996965553
Short name T239
Test name
Test status
Simulation time 1140031349 ps
CPU time 16.49 seconds
Started Jul 21 05:37:56 PM PDT 24
Finished Jul 21 05:38:13 PM PDT 24
Peak memory 208628 kb
Host smart-c1499328-49e5-4eb0-b8b7-a32f6caade0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996965553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3996965553
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1316970373
Short name T840
Test name
Test status
Simulation time 735732162 ps
CPU time 4.1 seconds
Started Jul 21 05:37:53 PM PDT 24
Finished Jul 21 05:37:58 PM PDT 24
Peak memory 210108 kb
Host smart-6661f96f-e198-4b3c-97a1-5211371411fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316970373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1316970373
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.4060622132
Short name T533
Test name
Test status
Simulation time 11763955 ps
CPU time 0.79 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:03 PM PDT 24
Peak memory 205852 kb
Host smart-4e61f116-3c13-4d59-a9c1-7423a475b669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060622132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.4060622132
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3559190627
Short name T76
Test name
Test status
Simulation time 196263075 ps
CPU time 1.76 seconds
Started Jul 21 05:38:00 PM PDT 24
Finished Jul 21 05:38:02 PM PDT 24
Peak memory 209428 kb
Host smart-ae79efdc-f552-4380-8882-c35c28fa66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559190627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3559190627
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.343515031
Short name T69
Test name
Test status
Simulation time 95204010 ps
CPU time 4.23 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 209844 kb
Host smart-ad2d5000-abd5-408e-88d5-ea6c17a3b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343515031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.343515031
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.685188905
Short name T216
Test name
Test status
Simulation time 536075077 ps
CPU time 5.27 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 220512 kb
Host smart-baf8b07c-d1c7-45f9-9a06-dddb4414d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685188905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.685188905
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1213165620
Short name T260
Test name
Test status
Simulation time 97051904 ps
CPU time 1.79 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:05 PM PDT 24
Peak memory 214020 kb
Host smart-ae3db0b8-c8c2-495b-901f-892f08e4c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213165620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1213165620
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3468809572
Short name T495
Test name
Test status
Simulation time 321423797 ps
CPU time 3.62 seconds
Started Jul 21 05:38:00 PM PDT 24
Finished Jul 21 05:38:04 PM PDT 24
Peak memory 220248 kb
Host smart-ffeee4ac-ba86-4dff-b2ad-cdb8ada2a8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468809572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3468809572
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.407716944
Short name T324
Test name
Test status
Simulation time 6484087103 ps
CPU time 8.82 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:12 PM PDT 24
Peak memory 214220 kb
Host smart-1dca2485-0792-47d8-b33a-0246cf4b3e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407716944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.407716944
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2913503243
Short name T719
Test name
Test status
Simulation time 194359354 ps
CPU time 3.68 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:04 PM PDT 24
Peak memory 206596 kb
Host smart-957b2bd5-a51b-4ac7-b053-5c26afa6db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913503243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2913503243
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4198556551
Short name T516
Test name
Test status
Simulation time 2240266440 ps
CPU time 28.93 seconds
Started Jul 21 05:37:58 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 207804 kb
Host smart-984e0369-78aa-46e7-be7c-aca478c916c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198556551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4198556551
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.614847002
Short name T908
Test name
Test status
Simulation time 60959088 ps
CPU time 2.43 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 208220 kb
Host smart-6329f67e-7718-447d-ac66-158bf1cb4d84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614847002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.614847002
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4112626108
Short name T599
Test name
Test status
Simulation time 20176136 ps
CPU time 1.48 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:01 PM PDT 24
Peak memory 207264 kb
Host smart-67e0ac5d-1c8c-41df-b2fd-8e402028b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112626108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4112626108
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.4179523187
Short name T722
Test name
Test status
Simulation time 780029195 ps
CPU time 3.12 seconds
Started Jul 21 05:37:57 PM PDT 24
Finished Jul 21 05:38:01 PM PDT 24
Peak memory 208112 kb
Host smart-1cb7058a-62a9-40db-a05d-ceafa1001823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179523187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4179523187
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3093956662
Short name T321
Test name
Test status
Simulation time 636208062 ps
CPU time 15.98 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:19 PM PDT 24
Peak memory 221052 kb
Host smart-4f72310e-4382-4f79-a9f7-ae09f1d12777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093956662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3093956662
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4025098997
Short name T350
Test name
Test status
Simulation time 142239430 ps
CPU time 4.15 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 206852 kb
Host smart-4a3a3543-e54b-477c-a9c3-b2d9f21cc0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025098997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4025098997
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3876354611
Short name T512
Test name
Test status
Simulation time 1463389435 ps
CPU time 4.66 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 210864 kb
Host smart-acf5785d-2824-4526-9a4d-13cd1e61df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876354611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3876354611
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1659820332
Short name T102
Test name
Test status
Simulation time 22045402 ps
CPU time 0.83 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 205792 kb
Host smart-1e59a623-579c-43c2-b334-e3fecf883640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659820332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1659820332
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2051584442
Short name T437
Test name
Test status
Simulation time 1478915076 ps
CPU time 10.25 seconds
Started Jul 21 05:38:04 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 209296 kb
Host smart-9ece6df4-c70c-4b67-8609-b3c22b51f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051584442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2051584442
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3888229461
Short name T438
Test name
Test status
Simulation time 111753722 ps
CPU time 2.61 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:03 PM PDT 24
Peak memory 208472 kb
Host smart-16d741fa-da13-4686-9946-aaf7d8a73b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888229461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3888229461
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.715476910
Short name T366
Test name
Test status
Simulation time 41018875 ps
CPU time 1.7 seconds
Started Jul 21 05:37:58 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 214020 kb
Host smart-ba08cb48-f3d3-4099-88b1-e3e9e5b35773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715476910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.715476910
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.249804025
Short name T561
Test name
Test status
Simulation time 2891380203 ps
CPU time 6.67 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 210436 kb
Host smart-f2c62100-eb13-40d2-b712-830624261ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249804025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.249804025
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3190037059
Short name T905
Test name
Test status
Simulation time 164815243 ps
CPU time 5.74 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:12 PM PDT 24
Peak memory 208232 kb
Host smart-780c588c-51be-4c65-ae5d-53582f4c72f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190037059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3190037059
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2062646302
Short name T885
Test name
Test status
Simulation time 83443681 ps
CPU time 3.93 seconds
Started Jul 21 05:37:59 PM PDT 24
Finished Jul 21 05:38:04 PM PDT 24
Peak memory 208264 kb
Host smart-4a555901-3eca-4e9f-a93b-40bbbfc777ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062646302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2062646302
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.365773896
Short name T701
Test name
Test status
Simulation time 104310376 ps
CPU time 2.96 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:05 PM PDT 24
Peak memory 208340 kb
Host smart-bbae985a-0bbd-415d-a993-6c96f6ed9a83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365773896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.365773896
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.586506417
Short name T211
Test name
Test status
Simulation time 471203561 ps
CPU time 4.85 seconds
Started Jul 21 05:38:05 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 208288 kb
Host smart-7153af3e-b723-4443-9676-2c96a29ec4e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586506417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.586506417
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1348339597
Short name T253
Test name
Test status
Simulation time 581170779 ps
CPU time 8.04 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 207680 kb
Host smart-2f26e5e7-b98c-411c-8df4-db13d84b18d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348339597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1348339597
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.790842747
Short name T613
Test name
Test status
Simulation time 1610922625 ps
CPU time 5.36 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 214140 kb
Host smart-635314dd-07a4-497e-a7c2-5f359a53417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790842747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.790842747
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3788523798
Short name T837
Test name
Test status
Simulation time 93007465 ps
CPU time 3.6 seconds
Started Jul 21 05:38:02 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 208288 kb
Host smart-6507502e-8339-4177-bbc0-cc7141734898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788523798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3788523798
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3396384035
Short name T228
Test name
Test status
Simulation time 5296756095 ps
CPU time 38.92 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 222248 kb
Host smart-510ec459-56a1-44d2-b9f3-1ffacd83df7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396384035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3396384035
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3707334024
Short name T889
Test name
Test status
Simulation time 503916686 ps
CPU time 9.36 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:18 PM PDT 24
Peak memory 220412 kb
Host smart-d5b5b012-9d56-45b2-8558-1232e29f8aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707334024 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3707334024
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.484492204
Short name T520
Test name
Test status
Simulation time 378421875 ps
CPU time 4.87 seconds
Started Jul 21 05:38:01 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 207980 kb
Host smart-bbba1540-dcab-4d2a-a256-4e493fcd0ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484492204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.484492204
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.781835232
Short name T639
Test name
Test status
Simulation time 264846806 ps
CPU time 2.32 seconds
Started Jul 21 05:38:03 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 209696 kb
Host smart-8f1b139f-a07b-4344-81dc-4af9326ecba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781835232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.781835232
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1472730061
Short name T665
Test name
Test status
Simulation time 35036375 ps
CPU time 0.79 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 205928 kb
Host smart-20350ebc-1940-42db-bff1-c679f11786ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472730061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1472730061
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3370714262
Short name T249
Test name
Test status
Simulation time 86704081 ps
CPU time 5.71 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:12 PM PDT 24
Peak memory 214768 kb
Host smart-aacc37f8-1a29-4a56-9a88-9f2e26ba8c5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370714262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3370714262
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4288603972
Short name T915
Test name
Test status
Simulation time 200168955 ps
CPU time 3.45 seconds
Started Jul 21 05:38:05 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 207776 kb
Host smart-4e60f3fa-fdf7-4bf5-ac47-7acfb0144d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288603972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4288603972
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3394041708
Short name T492
Test name
Test status
Simulation time 62790079 ps
CPU time 3.18 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:11 PM PDT 24
Peak memory 210180 kb
Host smart-555ce80c-1bcd-4dcf-a239-c36883338243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394041708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3394041708
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3198902745
Short name T27
Test name
Test status
Simulation time 3067240262 ps
CPU time 7.88 seconds
Started Jul 21 05:38:05 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 214196 kb
Host smart-2203e19a-234f-4c74-8db1-68964ecda962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198902745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3198902745
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3586962002
Short name T348
Test name
Test status
Simulation time 85502806 ps
CPU time 2.02 seconds
Started Jul 21 05:38:04 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 214088 kb
Host smart-ce4f0555-a36d-4ae6-a4d6-30d9e015c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586962002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3586962002
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1362637218
Short name T223
Test name
Test status
Simulation time 126331090 ps
CPU time 3.09 seconds
Started Jul 21 05:38:05 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 209948 kb
Host smart-a45c61ec-3aca-4eb7-85fa-6ba890047b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362637218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1362637218
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.212562842
Short name T651
Test name
Test status
Simulation time 150436150 ps
CPU time 6.27 seconds
Started Jul 21 05:38:08 PM PDT 24
Finished Jul 21 05:38:15 PM PDT 24
Peak memory 207752 kb
Host smart-8daf69f7-9061-4415-b6f1-10faeec8644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212562842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.212562842
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1108828163
Short name T463
Test name
Test status
Simulation time 154459864 ps
CPU time 2.84 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:13 PM PDT 24
Peak memory 205820 kb
Host smart-d038aaf7-617e-461d-8017-1f106bda1ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108828163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1108828163
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2254121733
Short name T690
Test name
Test status
Simulation time 84387381 ps
CPU time 1.95 seconds
Started Jul 21 05:38:04 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 207096 kb
Host smart-b8d7c17b-7d85-4bc9-a68c-f3d1e231d736
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254121733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2254121733
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3747021468
Short name T677
Test name
Test status
Simulation time 41541141 ps
CPU time 2.51 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:09 PM PDT 24
Peak memory 207232 kb
Host smart-2f0d336e-71f8-4c0d-a48b-c3dd21cf62dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747021468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3747021468
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3473082437
Short name T331
Test name
Test status
Simulation time 635201453 ps
CPU time 10.06 seconds
Started Jul 21 05:38:09 PM PDT 24
Finished Jul 21 05:38:19 PM PDT 24
Peak memory 208244 kb
Host smart-fa09cd58-9354-4293-af43-1552e0edb0d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473082437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3473082437
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4288328930
Short name T513
Test name
Test status
Simulation time 99957676 ps
CPU time 4.32 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:15 PM PDT 24
Peak memory 214004 kb
Host smart-9dac44a8-99c0-4bfd-91c2-7ee1b0a1e3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288328930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4288328930
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3152328560
Short name T882
Test name
Test status
Simulation time 152339874 ps
CPU time 2.72 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:11 PM PDT 24
Peak memory 206456 kb
Host smart-d1dad92b-74bc-4569-8933-fbe5855ddc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152328560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3152328560
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3422750796
Short name T497
Test name
Test status
Simulation time 143431333 ps
CPU time 5.01 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 208924 kb
Host smart-c7712de1-69f6-4279-9ee8-32a7330b2d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422750796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3422750796
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2504444400
Short name T462
Test name
Test status
Simulation time 29105309 ps
CPU time 1.6 seconds
Started Jul 21 05:38:08 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 209560 kb
Host smart-640c568e-6dd4-45be-ad0d-6b9e8b3564ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504444400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2504444400
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2594696994
Short name T539
Test name
Test status
Simulation time 12803611 ps
CPU time 0.77 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:28 PM PDT 24
Peak memory 205832 kb
Host smart-1375f67d-7f1a-45ce-a636-51bb024fc7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594696994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2594696994
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1419388681
Short name T338
Test name
Test status
Simulation time 859907209 ps
CPU time 4.21 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 208800 kb
Host smart-ccdd2392-85ae-4712-9c8c-6d49673c4166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419388681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1419388681
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1691378666
Short name T93
Test name
Test status
Simulation time 92702075 ps
CPU time 3.43 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 214008 kb
Host smart-69bde507-6132-43dd-99c2-d2d13ad47504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691378666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1691378666
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2442645682
Short name T498
Test name
Test status
Simulation time 37704689 ps
CPU time 2.54 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:30 PM PDT 24
Peak memory 222168 kb
Host smart-a260587d-5be6-493c-b295-4161b868a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442645682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2442645682
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3294613799
Short name T224
Test name
Test status
Simulation time 233874162 ps
CPU time 2.28 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:29 PM PDT 24
Peak memory 214068 kb
Host smart-e28c2cc3-8394-4aae-9d95-66ee84303f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294613799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3294613799
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.863651684
Short name T373
Test name
Test status
Simulation time 662141891 ps
CPU time 8.86 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 209180 kb
Host smart-1b3e677d-e7fa-4480-b686-0592851fbae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863651684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.863651684
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2377490244
Short name T15
Test name
Test status
Simulation time 10765307925 ps
CPU time 16.03 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:44 PM PDT 24
Peak memory 232628 kb
Host smart-babe49b1-f77c-426c-89f3-fef80533a539
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377490244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2377490244
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1522234838
Short name T709
Test name
Test status
Simulation time 40834045 ps
CPU time 2.58 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 208480 kb
Host smart-88545310-b423-4d90-ae7e-0692c5f74997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522234838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1522234838
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.178092588
Short name T530
Test name
Test status
Simulation time 83916413 ps
CPU time 3.63 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 207752 kb
Host smart-757f2ff2-837e-4d75-8f20-5aa91c064aac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178092588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.178092588
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2312508591
Short name T746
Test name
Test status
Simulation time 548857193 ps
CPU time 3.33 seconds
Started Jul 21 05:36:29 PM PDT 24
Finished Jul 21 05:36:33 PM PDT 24
Peak memory 208372 kb
Host smart-7e8ae342-014b-4bfd-8e0a-9d6feafb94b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312508591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2312508591
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4202821823
Short name T426
Test name
Test status
Simulation time 114674660 ps
CPU time 3.87 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 207460 kb
Host smart-c3694299-1fd3-4338-9be0-d4e73f739cb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202821823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4202821823
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3508479055
Short name T133
Test name
Test status
Simulation time 307602508 ps
CPU time 3.88 seconds
Started Jul 21 05:36:25 PM PDT 24
Finished Jul 21 05:36:29 PM PDT 24
Peak memory 207520 kb
Host smart-77a00d52-6f9d-4b4b-9e11-282bf43af480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508479055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3508479055
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.592633253
Short name T443
Test name
Test status
Simulation time 122494180 ps
CPU time 4.1 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 208476 kb
Host smart-43976ad8-a108-4800-81f6-d72200a75322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592633253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.592633253
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2490326064
Short name T227
Test name
Test status
Simulation time 7668152481 ps
CPU time 44.04 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:37:10 PM PDT 24
Peak memory 217024 kb
Host smart-fcceccb9-c5e2-4b0f-ae01-d17edb9fa3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490326064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2490326064
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.914743559
Short name T895
Test name
Test status
Simulation time 2637650048 ps
CPU time 28.93 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 222520 kb
Host smart-e9245ea7-b058-4f4c-9ed8-9be5fa0b61f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914743559 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.914743559
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3104721879
Short name T477
Test name
Test status
Simulation time 224719092 ps
CPU time 4.77 seconds
Started Jul 21 05:36:26 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 207300 kb
Host smart-caf46412-3f16-4718-8146-aad2146c11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104721879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3104721879
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3668925907
Short name T820
Test name
Test status
Simulation time 354319717 ps
CPU time 6.11 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:35 PM PDT 24
Peak memory 210136 kb
Host smart-23c98877-c108-4715-b187-3e263602d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668925907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3668925907
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.905370110
Short name T669
Test name
Test status
Simulation time 25605012 ps
CPU time 0.82 seconds
Started Jul 21 05:38:15 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 205840 kb
Host smart-ab6c18d6-7b57-4b71-b28d-2a7712c32fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905370110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.905370110
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3224484007
Short name T404
Test name
Test status
Simulation time 148620181 ps
CPU time 6.97 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:15 PM PDT 24
Peak memory 215256 kb
Host smart-43689d7c-b6c6-4442-aeca-54d032abb7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224484007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3224484007
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1060577365
Short name T542
Test name
Test status
Simulation time 65634954 ps
CPU time 3.33 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 215928 kb
Host smart-d73c0e76-b3c1-4a02-8524-6e7c946b7dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060577365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1060577365
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3804572704
Short name T874
Test name
Test status
Simulation time 218142422 ps
CPU time 2.68 seconds
Started Jul 21 05:38:08 PM PDT 24
Finished Jul 21 05:38:11 PM PDT 24
Peak memory 208852 kb
Host smart-eb5d8fde-2298-48a6-8ca6-942e751f9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804572704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3804572704
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_random.2138924004
Short name T199
Test name
Test status
Simulation time 188366236 ps
CPU time 3.9 seconds
Started Jul 21 05:38:06 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 209356 kb
Host smart-8fd6c5ec-7f4f-451e-a24b-c32af62fb77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138924004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2138924004
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1366633684
Short name T861
Test name
Test status
Simulation time 135268398 ps
CPU time 5.61 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 206692 kb
Host smart-25786316-fe4e-4b75-aa3a-6c39e37748c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366633684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1366633684
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2548199373
Short name T666
Test name
Test status
Simulation time 98072787 ps
CPU time 2.84 seconds
Started Jul 21 05:38:07 PM PDT 24
Finished Jul 21 05:38:10 PM PDT 24
Peak memory 206700 kb
Host smart-98a65466-b2d9-44a2-81d6-e6d11b643d64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548199373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2548199373
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2443893743
Short name T591
Test name
Test status
Simulation time 84205742 ps
CPU time 3.46 seconds
Started Jul 21 05:38:04 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 206616 kb
Host smart-49acce2d-efa1-436d-bc63-d04b881969c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443893743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2443893743
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2857685479
Short name T480
Test name
Test status
Simulation time 274764831 ps
CPU time 1.87 seconds
Started Jul 21 05:38:09 PM PDT 24
Finished Jul 21 05:38:11 PM PDT 24
Peak memory 206696 kb
Host smart-dc1bbe19-39c4-4cb9-8d63-c2fcc38dff66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857685479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2857685479
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3094080710
Short name T756
Test name
Test status
Simulation time 337177129 ps
CPU time 1.75 seconds
Started Jul 21 05:38:04 PM PDT 24
Finished Jul 21 05:38:06 PM PDT 24
Peak memory 208356 kb
Host smart-06cc4a8a-2c4d-4012-9e22-eb03ec68be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094080710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3094080710
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1408622072
Short name T496
Test name
Test status
Simulation time 72571622 ps
CPU time 2.32 seconds
Started Jul 21 05:38:05 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 206680 kb
Host smart-53635f80-7986-41c1-8dc3-7f6b416b4686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408622072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1408622072
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3193690195
Short name T812
Test name
Test status
Simulation time 1151434082 ps
CPU time 11.34 seconds
Started Jul 21 05:38:12 PM PDT 24
Finished Jul 21 05:38:24 PM PDT 24
Peak memory 222252 kb
Host smart-a75e8b61-6e3b-4efc-a539-113b60a7fdfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193690195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3193690195
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2872769986
Short name T372
Test name
Test status
Simulation time 812846696 ps
CPU time 6.67 seconds
Started Jul 21 05:38:10 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 209536 kb
Host smart-3e3c161d-20f5-4d7d-961a-95265aacb62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872769986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2872769986
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1417402736
Short name T831
Test name
Test status
Simulation time 79960628 ps
CPU time 1.98 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 210176 kb
Host smart-c134ed4b-0a8b-49e3-a947-eac941e8338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417402736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1417402736
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4267522198
Short name T434
Test name
Test status
Simulation time 14418813 ps
CPU time 0.73 seconds
Started Jul 21 05:38:12 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 205848 kb
Host smart-b227b309-2312-408c-9fe3-27c543258249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267522198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4267522198
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2394272802
Short name T12
Test name
Test status
Simulation time 424232451 ps
CPU time 3.42 seconds
Started Jul 21 05:38:18 PM PDT 24
Finished Jul 21 05:38:22 PM PDT 24
Peak memory 222608 kb
Host smart-eb15c559-28f0-4402-ba79-d7e7db462b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394272802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2394272802
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.353152030
Short name T375
Test name
Test status
Simulation time 39204398 ps
CPU time 2.59 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:16 PM PDT 24
Peak memory 207200 kb
Host smart-edb4046f-661e-47bc-a65f-c69dee31acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353152030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.353152030
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4009084560
Short name T98
Test name
Test status
Simulation time 865983887 ps
CPU time 17.47 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:31 PM PDT 24
Peak memory 214056 kb
Host smart-cc5834e2-dca9-4d4d-836e-cbdb8551fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009084560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4009084560
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3921940568
Short name T264
Test name
Test status
Simulation time 258181013 ps
CPU time 3.4 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 214008 kb
Host smart-3ee81230-66ad-4a0b-9409-e6cb808290c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921940568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3921940568
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3861514925
Short name T269
Test name
Test status
Simulation time 35798090 ps
CPU time 2.61 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:23 PM PDT 24
Peak memory 219988 kb
Host smart-08fe9c59-0982-445a-b080-034318c30436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861514925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3861514925
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4169916835
Short name T29
Test name
Test status
Simulation time 161955208 ps
CPU time 5.61 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 210176 kb
Host smart-7568db2a-131b-40b7-a5f2-38820a4dd1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169916835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4169916835
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3086875488
Short name T727
Test name
Test status
Simulation time 205672232 ps
CPU time 2.82 seconds
Started Jul 21 05:38:14 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 206528 kb
Host smart-de85650f-6b40-43eb-a510-bb44d5d531b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086875488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3086875488
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3337465281
Short name T578
Test name
Test status
Simulation time 40151080 ps
CPU time 1.85 seconds
Started Jul 21 05:38:16 PM PDT 24
Finished Jul 21 05:38:18 PM PDT 24
Peak memory 206500 kb
Host smart-9d4837fd-528d-43b9-ba23-578adb017231
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337465281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3337465281
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3871057994
Short name T465
Test name
Test status
Simulation time 412495682 ps
CPU time 8.73 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:31 PM PDT 24
Peak memory 208488 kb
Host smart-77b9c87c-7aa8-48ef-b7db-a349c1a87d1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871057994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3871057994
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1903473066
Short name T720
Test name
Test status
Simulation time 164755317 ps
CPU time 2.77 seconds
Started Jul 21 05:38:12 PM PDT 24
Finished Jul 21 05:38:15 PM PDT 24
Peak memory 208496 kb
Host smart-69b0eaa2-f85f-4eb5-b9fa-051f496ba18c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903473066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1903473066
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1017504676
Short name T85
Test name
Test status
Simulation time 110769565 ps
CPU time 4.48 seconds
Started Jul 21 05:38:18 PM PDT 24
Finished Jul 21 05:38:22 PM PDT 24
Peak memory 208572 kb
Host smart-2fe3f0c5-2999-4894-963d-e5d9fda93fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017504676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1017504676
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.643460371
Short name T704
Test name
Test status
Simulation time 55349959 ps
CPU time 2.64 seconds
Started Jul 21 05:38:15 PM PDT 24
Finished Jul 21 05:38:18 PM PDT 24
Peak memory 208184 kb
Host smart-0d7f6d2b-048e-4c2f-bd91-eb4884120029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643460371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.643460371
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2352207739
Short name T519
Test name
Test status
Simulation time 1290032125 ps
CPU time 28.55 seconds
Started Jul 21 05:38:14 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 210156 kb
Host smart-1982a2fb-0088-44fa-979f-efde334eb390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352207739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2352207739
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1375578193
Short name T166
Test name
Test status
Simulation time 456525754 ps
CPU time 7.54 seconds
Started Jul 21 05:38:12 PM PDT 24
Finished Jul 21 05:38:20 PM PDT 24
Peak memory 210184 kb
Host smart-164fa8bd-f1e8-4ff0-b13b-a73a26bf12fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375578193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1375578193
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.216627926
Short name T826
Test name
Test status
Simulation time 182949788 ps
CPU time 1.04 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:23 PM PDT 24
Peak memory 205912 kb
Host smart-08ca2ff6-0d28-42c8-beb2-ce4f4ce89d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216627926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.216627926
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.454843825
Short name T237
Test name
Test status
Simulation time 612038909 ps
CPU time 4.54 seconds
Started Jul 21 05:38:14 PM PDT 24
Finished Jul 21 05:38:19 PM PDT 24
Peak memory 214836 kb
Host smart-d0d38bf8-7a7a-47ac-9d5e-657e222bcbd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454843825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.454843825
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2770915947
Short name T428
Test name
Test status
Simulation time 80558991 ps
CPU time 2.58 seconds
Started Jul 21 05:38:23 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 216300 kb
Host smart-172e3edb-432a-4d77-82fa-f9a855de436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770915947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2770915947
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1714917182
Short name T883
Test name
Test status
Simulation time 89681268 ps
CPU time 2.81 seconds
Started Jul 21 05:38:16 PM PDT 24
Finished Jul 21 05:38:19 PM PDT 24
Peak memory 214072 kb
Host smart-2946d21c-537d-40c3-98b4-03f3b5455fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714917182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1714917182
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1920040361
Short name T854
Test name
Test status
Simulation time 68645595 ps
CPU time 2.62 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 219224 kb
Host smart-ab206511-2c04-45d0-a3b7-37173b3e7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920040361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1920040361
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.998463629
Short name T67
Test name
Test status
Simulation time 272248044 ps
CPU time 3.77 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:17 PM PDT 24
Peak memory 209412 kb
Host smart-1d3340ab-9e20-4d26-ab1c-8be2e3e5aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998463629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.998463629
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2222380208
Short name T606
Test name
Test status
Simulation time 928964764 ps
CPU time 18.02 seconds
Started Jul 21 05:38:16 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 208816 kb
Host smart-06bf83f9-1cd6-4e39-9e84-54d3b27f017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222380208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2222380208
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1991485934
Short name T793
Test name
Test status
Simulation time 2525798843 ps
CPU time 16.23 seconds
Started Jul 21 05:38:15 PM PDT 24
Finished Jul 21 05:38:32 PM PDT 24
Peak memory 207836 kb
Host smart-d7f7c805-50ea-4b36-981c-c4d984dbf38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991485934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1991485934
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2362009253
Short name T627
Test name
Test status
Simulation time 103922500 ps
CPU time 4.15 seconds
Started Jul 21 05:38:15 PM PDT 24
Finished Jul 21 05:38:20 PM PDT 24
Peak memory 207696 kb
Host smart-fc729637-9ae8-4b6f-99ef-ad1f06fe3cd6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362009253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2362009253
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.42027395
Short name T430
Test name
Test status
Simulation time 310633991 ps
CPU time 3.81 seconds
Started Jul 21 05:38:14 PM PDT 24
Finished Jul 21 05:38:19 PM PDT 24
Peak memory 208872 kb
Host smart-9a5654c5-0da1-49db-bf02-022ad790048c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42027395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.42027395
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3358742011
Short name T510
Test name
Test status
Simulation time 1065846325 ps
CPU time 11.51 seconds
Started Jul 21 05:38:12 PM PDT 24
Finished Jul 21 05:38:24 PM PDT 24
Peak memory 207656 kb
Host smart-dddd78d7-6096-436a-a10f-9d26870e5d59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358742011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3358742011
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.334252701
Short name T3
Test name
Test status
Simulation time 98661719 ps
CPU time 1.97 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 207804 kb
Host smart-b3dd1d3c-48af-4940-9db3-254a26ffb887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334252701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.334252701
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.477019720
Short name T565
Test name
Test status
Simulation time 153209787 ps
CPU time 2.23 seconds
Started Jul 21 05:38:11 PM PDT 24
Finished Jul 21 05:38:14 PM PDT 24
Peak memory 207700 kb
Host smart-642673e0-1e35-4ddf-be42-0bb71bd08dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477019720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.477019720
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3660905882
Short name T349
Test name
Test status
Simulation time 180140207 ps
CPU time 2.67 seconds
Started Jul 21 05:38:23 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 208852 kb
Host smart-6efd4895-0237-4e04-b7fb-27e38944f553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660905882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3660905882
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.976499965
Short name T620
Test name
Test status
Simulation time 162572215 ps
CPU time 3.86 seconds
Started Jul 21 05:38:13 PM PDT 24
Finished Jul 21 05:38:18 PM PDT 24
Peak memory 214132 kb
Host smart-cbaac93d-6bf0-4898-bc85-de73a80a6264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976499965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.976499965
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1539683324
Short name T130
Test name
Test status
Simulation time 1022108079 ps
CPU time 22.21 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:47 PM PDT 24
Peak memory 210132 kb
Host smart-32d149ce-b97c-4871-8bbb-93c8925a4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539683324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1539683324
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3780459982
Short name T429
Test name
Test status
Simulation time 11944710 ps
CPU time 0.85 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 205832 kb
Host smart-09e0be21-f36b-4caa-a3df-730cfb14c5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780459982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3780459982
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1496237451
Short name T24
Test name
Test status
Simulation time 47251383 ps
CPU time 2.41 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:24 PM PDT 24
Peak memory 215676 kb
Host smart-49d7fa95-bc60-4630-8708-792bcab28db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496237451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1496237451
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1088909562
Short name T636
Test name
Test status
Simulation time 183623341 ps
CPU time 5.33 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 208092 kb
Host smart-35a9bb4d-cc25-4980-a8b6-eea5ab86efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088909562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1088909562
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4131903077
Short name T775
Test name
Test status
Simulation time 35639794 ps
CPU time 2.15 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:23 PM PDT 24
Peak memory 214116 kb
Host smart-0b654534-a1f2-4a51-930b-8bbb504a3c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131903077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4131903077
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.890620148
Short name T668
Test name
Test status
Simulation time 31990055 ps
CPU time 1.8 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 206016 kb
Host smart-21cffc49-b8b2-4b89-a04d-f1f57e2d2220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890620148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.890620148
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1623816382
Short name T781
Test name
Test status
Simulation time 66631665 ps
CPU time 3.98 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 209876 kb
Host smart-06083133-8312-49de-9c31-59b349fb7a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623816382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1623816382
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3714529045
Short name T450
Test name
Test status
Simulation time 189144638 ps
CPU time 4.93 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 208532 kb
Host smart-99997e21-cfae-4cfb-96c2-ecd694c92115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714529045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3714529045
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3105624880
Short name T734
Test name
Test status
Simulation time 129311384 ps
CPU time 3.87 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 208444 kb
Host smart-4437bb53-b060-4f37-a70e-594784c77a05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105624880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3105624880
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3559239323
Short name T381
Test name
Test status
Simulation time 113006008 ps
CPU time 3.85 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 206512 kb
Host smart-94605fe7-eda1-4c40-bcec-86fc32f0a61c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559239323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3559239323
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2360285397
Short name T835
Test name
Test status
Simulation time 53354026 ps
CPU time 2.11 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:22 PM PDT 24
Peak memory 208632 kb
Host smart-5ae32423-f905-4ada-8c3e-5aee2e34f371
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360285397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2360285397
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1530953379
Short name T862
Test name
Test status
Simulation time 79225188 ps
CPU time 2.45 seconds
Started Jul 21 05:38:23 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 214084 kb
Host smart-94da6417-b477-4163-a812-445bc138dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530953379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1530953379
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3462998648
Short name T543
Test name
Test status
Simulation time 105620420 ps
CPU time 2.54 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:23 PM PDT 24
Peak memory 206692 kb
Host smart-e4c4d67d-d7c5-4c0b-9399-a03b4a1f48b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462998648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3462998648
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3934788484
Short name T843
Test name
Test status
Simulation time 688427353 ps
CPU time 26.16 seconds
Started Jul 21 05:38:23 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 215036 kb
Host smart-241cfe9d-21eb-4315-a87c-171b9e9d090b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934788484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3934788484
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3746047612
Short name T864
Test name
Test status
Simulation time 174726698 ps
CPU time 9.07 seconds
Started Jul 21 05:38:23 PM PDT 24
Finished Jul 21 05:38:32 PM PDT 24
Peak memory 220072 kb
Host smart-8ce61880-2c17-4cde-9c2a-0aadad2f8bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746047612 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3746047612
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.230778650
Short name T607
Test name
Test status
Simulation time 181110139 ps
CPU time 5.29 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:26 PM PDT 24
Peak memory 208804 kb
Host smart-fec82407-8f14-4db5-9531-e664d341919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230778650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.230778650
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.924910628
Short name T739
Test name
Test status
Simulation time 61696433 ps
CPU time 2.27 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:23 PM PDT 24
Peak memory 209756 kb
Host smart-958189ab-cb08-4b31-b45d-ca9d55aa4e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924910628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.924910628
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3254659786
Short name T785
Test name
Test status
Simulation time 11447627 ps
CPU time 0.78 seconds
Started Jul 21 05:38:29 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 205804 kb
Host smart-cecab71a-7fbc-426a-8093-267bca7bb53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254659786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3254659786
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.338239872
Short name T824
Test name
Test status
Simulation time 1217823493 ps
CPU time 29.37 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 220548 kb
Host smart-e9f37de4-5307-4cf5-b9a5-56927bf9b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338239872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.338239872
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3276173121
Short name T691
Test name
Test status
Simulation time 51740267 ps
CPU time 2.67 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 209680 kb
Host smart-7f23f561-2885-4c94-a526-97faf9208612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276173121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3276173121
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1704613501
Short name T266
Test name
Test status
Simulation time 53686930 ps
CPU time 2.15 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 220632 kb
Host smart-d93e6573-782f-4df0-8228-ad9d2cedf464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704613501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1704613501
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.844679972
Short name T327
Test name
Test status
Simulation time 592611049 ps
CPU time 3.85 seconds
Started Jul 21 05:38:37 PM PDT 24
Finished Jul 21 05:38:41 PM PDT 24
Peak memory 222304 kb
Host smart-6f15a61f-972c-4583-ab5b-05cf61d590b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844679972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.844679972
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3438198084
Short name T823
Test name
Test status
Simulation time 307830249 ps
CPU time 4.12 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:38:32 PM PDT 24
Peak memory 214788 kb
Host smart-e07c6ade-295c-4d69-ae24-d23019967455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438198084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3438198084
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.440455104
Short name T531
Test name
Test status
Simulation time 498394907 ps
CPU time 6.32 seconds
Started Jul 21 05:38:18 PM PDT 24
Finished Jul 21 05:38:25 PM PDT 24
Peak memory 218028 kb
Host smart-02386189-16a5-4489-99db-422122dbbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440455104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.440455104
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1605965456
Short name T453
Test name
Test status
Simulation time 281351524 ps
CPU time 9.7 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 207204 kb
Host smart-04439be8-e75f-458c-b3b7-59a8fbdd0937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605965456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1605965456
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1257004478
Short name T672
Test name
Test status
Simulation time 100785605 ps
CPU time 4.38 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 208136 kb
Host smart-dcaf7e20-47c4-4378-a33c-8fcb919f9037
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257004478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1257004478
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1166353660
Short name T2
Test name
Test status
Simulation time 548307398 ps
CPU time 5.87 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 208364 kb
Host smart-e5703a29-e4d9-44cb-afbd-ead22981a6e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166353660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1166353660
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2547536540
Short name T768
Test name
Test status
Simulation time 549306343 ps
CPU time 13.45 seconds
Started Jul 21 05:38:20 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 208592 kb
Host smart-885162a3-10bc-4b32-b096-37e5c3ebbf39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547536540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2547536540
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2013961294
Short name T277
Test name
Test status
Simulation time 557919893 ps
CPU time 14.97 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 214004 kb
Host smart-014d895f-c860-4c59-a5c8-529519565937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013961294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2013961294
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2494485896
Short name T731
Test name
Test status
Simulation time 2414623052 ps
CPU time 22.37 seconds
Started Jul 21 05:38:22 PM PDT 24
Finished Jul 21 05:38:45 PM PDT 24
Peak memory 208212 kb
Host smart-241509b1-5d0b-4f1a-8b67-2cd8c8771c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494485896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2494485896
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1066411665
Short name T195
Test name
Test status
Simulation time 2870556583 ps
CPU time 10.81 seconds
Started Jul 21 05:38:36 PM PDT 24
Finished Jul 21 05:38:48 PM PDT 24
Peak memory 218796 kb
Host smart-9b12ca99-fea6-432c-b0e8-5e88753f24e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066411665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1066411665
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1325065572
Short name T355
Test name
Test status
Simulation time 2911688792 ps
CPU time 21 seconds
Started Jul 21 05:38:21 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 208344 kb
Host smart-4e267587-5c04-4210-afe0-e798941f80b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325065572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1325065572
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1883934977
Short name T200
Test name
Test status
Simulation time 69170622 ps
CPU time 1.82 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:27 PM PDT 24
Peak memory 210228 kb
Host smart-76c344bc-39c7-49e1-a98c-238ff6088e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883934977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1883934977
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4004579146
Short name T418
Test name
Test status
Simulation time 21189896 ps
CPU time 0.84 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 205812 kb
Host smart-65c18613-8f93-41d7-9339-d0a37422fe3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004579146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4004579146
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3590070346
Short name T868
Test name
Test status
Simulation time 189035181 ps
CPU time 3.9 seconds
Started Jul 21 05:38:36 PM PDT 24
Finished Jul 21 05:38:40 PM PDT 24
Peak memory 214204 kb
Host smart-633cba97-6238-4edb-a4e4-b4eb1a599004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590070346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3590070346
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3237642627
Short name T816
Test name
Test status
Simulation time 302321405 ps
CPU time 4.77 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 214336 kb
Host smart-01ff9a96-5ab5-4d0c-985b-018b98cccf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237642627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3237642627
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1285830627
Short name T360
Test name
Test status
Simulation time 631760044 ps
CPU time 5.66 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:31 PM PDT 24
Peak memory 207776 kb
Host smart-2d56e54f-b695-4a5f-850e-795e8cf00dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285830627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1285830627
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.467477248
Short name T891
Test name
Test status
Simulation time 31048601 ps
CPU time 2.16 seconds
Started Jul 21 05:38:31 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 213968 kb
Host smart-ea9b85c5-8b2f-4b8b-9f35-4a9d182108ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467477248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.467477248
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4280983424
Short name T774
Test name
Test status
Simulation time 45552669 ps
CPU time 3.36 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 222280 kb
Host smart-d4f0cb73-2ff6-4fb0-8d5a-2e124e08a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280983424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4280983424
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3192198955
Short name T276
Test name
Test status
Simulation time 110535917 ps
CPU time 5.28 seconds
Started Jul 21 05:38:27 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 222196 kb
Host smart-799c9711-09c1-4afb-a167-3ca59e05e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192198955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3192198955
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2034454334
Short name T770
Test name
Test status
Simulation time 1210674922 ps
CPU time 27.31 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 207800 kb
Host smart-08618ed9-c85f-4fa2-adfc-d0825c4d8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034454334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2034454334
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1868773118
Short name T742
Test name
Test status
Simulation time 859267345 ps
CPU time 7.14 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 207644 kb
Host smart-07440f4e-04fc-45ff-8a9c-54306fa7d186
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868773118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1868773118
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1529332377
Short name T440
Test name
Test status
Simulation time 207497119 ps
CPU time 7.93 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:35 PM PDT 24
Peak memory 207904 kb
Host smart-d81533eb-dcf2-42b0-bbc6-6bf1970ac982
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529332377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1529332377
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2369504015
Short name T572
Test name
Test status
Simulation time 348404920 ps
CPU time 5.83 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 208456 kb
Host smart-d10689b2-e946-47f3-ad2a-0b0b3207187f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369504015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2369504015
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2216543796
Short name T815
Test name
Test status
Simulation time 589340942 ps
CPU time 3.26 seconds
Started Jul 21 05:38:29 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 215660 kb
Host smart-6fdf7c2c-cc5e-481a-a441-8d1509a7eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216543796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2216543796
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.881796557
Short name T748
Test name
Test status
Simulation time 169879220 ps
CPU time 5.49 seconds
Started Jul 21 05:38:28 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 206640 kb
Host smart-1fb17248-c84d-43c2-beef-ad95c69cf50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881796557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.881796557
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1764532144
Short name T325
Test name
Test status
Simulation time 1420536411 ps
CPU time 8.83 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:35 PM PDT 24
Peak memory 208848 kb
Host smart-1220a969-1d07-42e6-a104-993ac4c8181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764532144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1764532144
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.265014635
Short name T189
Test name
Test status
Simulation time 83179071 ps
CPU time 3.43 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 210236 kb
Host smart-bf5cdb58-13a9-4740-a9dc-424ce212b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265014635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.265014635
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4220264162
Short name T445
Test name
Test status
Simulation time 34144270 ps
CPU time 1.03 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 205932 kb
Host smart-90b98912-d005-42f1-a422-bfc353d2b07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220264162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4220264162
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2228133075
Short name T36
Test name
Test status
Simulation time 317901661 ps
CPU time 3.43 seconds
Started Jul 21 05:38:27 PM PDT 24
Finished Jul 21 05:38:31 PM PDT 24
Peak memory 209784 kb
Host smart-4d4c51c3-c1e5-481b-ad3d-6ce1fdec9983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228133075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2228133075
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4130992216
Short name T343
Test name
Test status
Simulation time 1849331121 ps
CPU time 24.63 seconds
Started Jul 21 05:38:36 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 218036 kb
Host smart-a03a5fc6-5e5a-471b-9ff0-aab810501382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130992216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4130992216
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4054470851
Short name T283
Test name
Test status
Simulation time 109677495 ps
CPU time 4.03 seconds
Started Jul 21 05:38:24 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 213968 kb
Host smart-d33081c8-664d-4c11-b98a-8309b54e0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054470851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4054470851
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1045248005
Short name T647
Test name
Test status
Simulation time 63598900 ps
CPU time 2.28 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:28 PM PDT 24
Peak memory 208816 kb
Host smart-4c715e9f-3ae4-4692-a00e-48b817a819bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045248005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1045248005
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3852800170
Short name T682
Test name
Test status
Simulation time 51524390 ps
CPU time 3.79 seconds
Started Jul 21 05:38:36 PM PDT 24
Finished Jul 21 05:38:41 PM PDT 24
Peak memory 207364 kb
Host smart-749136a1-e5bd-4b30-85b4-96301f637d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852800170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3852800170
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.348453615
Short name T557
Test name
Test status
Simulation time 203409643 ps
CPU time 2.65 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:29 PM PDT 24
Peak memory 206708 kb
Host smart-c345916c-6954-4d06-a72a-2928b52db405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348453615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.348453615
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2220222673
Short name T644
Test name
Test status
Simulation time 405072455 ps
CPU time 5.92 seconds
Started Jul 21 05:38:25 PM PDT 24
Finished Jul 21 05:38:32 PM PDT 24
Peak memory 207732 kb
Host smart-c22a871c-4d07-4d13-977e-525863731777
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220222673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2220222673
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4117542939
Short name T867
Test name
Test status
Simulation time 218903926 ps
CPU time 7.19 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 208464 kb
Host smart-2854bd53-2c2c-4257-93a3-53af4f51c3e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117542939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4117542939
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4022615578
Short name T123
Test name
Test status
Simulation time 55917253 ps
CPU time 2.63 seconds
Started Jul 21 05:38:31 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 207828 kb
Host smart-438c8b83-0eef-44de-8688-367b0e54aed0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022615578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4022615578
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1568006615
Short name T134
Test name
Test status
Simulation time 201117707 ps
CPU time 3.31 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:30 PM PDT 24
Peak memory 214076 kb
Host smart-d70b1cdf-9efe-4d4c-a000-90fcff72687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568006615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1568006615
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2373700442
Short name T446
Test name
Test status
Simulation time 55879869 ps
CPU time 2.26 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:35 PM PDT 24
Peak memory 206676 kb
Host smart-96b0270c-5d53-477e-8d2a-03b681ec2298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373700442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2373700442
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.673152413
Short name T834
Test name
Test status
Simulation time 2533806529 ps
CPU time 22.42 seconds
Started Jul 21 05:38:29 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 214220 kb
Host smart-69d8245c-6a41-4788-9fa0-8bca739e3761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673152413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.673152413
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.405963166
Short name T894
Test name
Test status
Simulation time 1098879007 ps
CPU time 11.52 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 222272 kb
Host smart-1aa92ea7-5e79-45e3-bb01-39b5e533a6c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405963166 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.405963166
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.30159073
Short name T877
Test name
Test status
Simulation time 106972552 ps
CPU time 3.7 seconds
Started Jul 21 05:38:26 PM PDT 24
Finished Jul 21 05:38:31 PM PDT 24
Peak memory 210148 kb
Host smart-47900308-4922-4ed7-bf0b-5d96fac31e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30159073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.30159073
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1693203463
Short name T716
Test name
Test status
Simulation time 13024782 ps
CPU time 0.73 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 205852 kb
Host smart-a8b68bf5-0c0d-462e-b043-d308a8777011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693203463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1693203463
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2994093025
Short name T137
Test name
Test status
Simulation time 243755417 ps
CPU time 4.17 seconds
Started Jul 21 05:38:31 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 214156 kb
Host smart-c089e3a5-fe7a-4735-b412-57b5d71b4d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994093025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2994093025
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2829266826
Short name T32
Test name
Test status
Simulation time 111418117 ps
CPU time 4.76 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 209080 kb
Host smart-deff0f14-4066-4d60-84b1-3aed0829039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829266826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2829266826
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.365402008
Short name T653
Test name
Test status
Simulation time 37384691 ps
CPU time 1.95 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:34 PM PDT 24
Peak memory 208476 kb
Host smart-a2ba6942-d10a-4122-aac2-4b3f47f0a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365402008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.365402008
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.317138002
Short name T371
Test name
Test status
Simulation time 376326518 ps
CPU time 10.27 seconds
Started Jul 21 05:38:33 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 220676 kb
Host smart-601f1290-0f8d-49ef-8387-dd58a62f172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317138002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.317138002
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.314531858
Short name T850
Test name
Test status
Simulation time 150143054 ps
CPU time 2.3 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 214032 kb
Host smart-f25178de-7baf-4d52-91f7-6959c26364f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314531858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.314531858
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1352536947
Short name T535
Test name
Test status
Simulation time 533035139 ps
CPU time 2.89 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:38 PM PDT 24
Peak memory 208248 kb
Host smart-1b90f536-6ba2-4cba-9057-6542500fb50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352536947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1352536947
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.857840690
Short name T759
Test name
Test status
Simulation time 194931637 ps
CPU time 4.55 seconds
Started Jul 21 05:38:33 PM PDT 24
Finished Jul 21 05:38:38 PM PDT 24
Peak memory 207096 kb
Host smart-a5b03bbf-ff85-4155-8ac8-599c38778f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857840690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.857840690
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2613325229
Short name T248
Test name
Test status
Simulation time 177616706 ps
CPU time 3.7 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:39 PM PDT 24
Peak memory 208556 kb
Host smart-8426bbd2-3d47-4965-a780-f802fbea39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613325229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2613325229
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1864442627
Short name T585
Test name
Test status
Simulation time 60516352 ps
CPU time 3.19 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 206576 kb
Host smart-dda55ccf-d1e1-47aa-810a-b00287608b83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864442627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1864442627
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.111884494
Short name T794
Test name
Test status
Simulation time 90114795 ps
CPU time 4 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 208360 kb
Host smart-cac0f88f-0aab-4ce1-a205-d5298a2a567d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111884494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.111884494
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1458977350
Short name T773
Test name
Test status
Simulation time 5267579041 ps
CPU time 43.19 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:39:17 PM PDT 24
Peak memory 208628 kb
Host smart-26201125-6ded-40d3-80d8-ba68d660e3a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458977350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1458977350
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2942208891
Short name T493
Test name
Test status
Simulation time 60511824 ps
CPU time 2.91 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:35 PM PDT 24
Peak memory 208936 kb
Host smart-b8dadc95-ba1c-4afb-8b1d-f6689b21bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942208891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2942208891
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.610017743
Short name T424
Test name
Test status
Simulation time 41575390 ps
CPU time 1.67 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 206576 kb
Host smart-cd535d39-5073-42d1-a69e-33ae0d6d6b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610017743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.610017743
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.951002672
Short name T714
Test name
Test status
Simulation time 6024567666 ps
CPU time 38.46 seconds
Started Jul 21 05:38:31 PM PDT 24
Finished Jul 21 05:39:10 PM PDT 24
Peak memory 219868 kb
Host smart-2e67fe8e-51e9-4482-9291-cdc67b474701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951002672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.951002672
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3881388777
Short name T49
Test name
Test status
Simulation time 128124219 ps
CPU time 1.99 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 209660 kb
Host smart-ef53810d-a53c-4236-b859-ec91105c207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881388777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3881388777
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3692399448
Short name T623
Test name
Test status
Simulation time 190125393 ps
CPU time 0.83 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:40 PM PDT 24
Peak memory 205804 kb
Host smart-780013e9-4952-430d-8678-4815ff845386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692399448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3692399448
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1182174851
Short name T456
Test name
Test status
Simulation time 39286983 ps
CPU time 2.52 seconds
Started Jul 21 05:38:34 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 214072 kb
Host smart-8b47fe3c-386f-429e-bbcf-28153643a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182174851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1182174851
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1008960802
Short name T538
Test name
Test status
Simulation time 279599297 ps
CPU time 3.51 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 214008 kb
Host smart-ef02db65-e99c-4335-bdb0-207eca45abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008960802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1008960802
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1785163769
Short name T281
Test name
Test status
Simulation time 1277290084 ps
CPU time 3.34 seconds
Started Jul 21 05:38:38 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 213944 kb
Host smart-06d6e874-ec68-485a-8286-99b7296911ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785163769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1785163769
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1446016179
Short name T903
Test name
Test status
Simulation time 116350824 ps
CPU time 3.08 seconds
Started Jul 21 05:38:38 PM PDT 24
Finished Jul 21 05:38:41 PM PDT 24
Peak memory 214032 kb
Host smart-5abde9bc-1881-4f21-8d3b-c2d10df0c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446016179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1446016179
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3358052296
Short name T458
Test name
Test status
Simulation time 402736755 ps
CPU time 6.66 seconds
Started Jul 21 05:38:35 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 209460 kb
Host smart-fe0809d3-8134-4c66-9eb5-640cff4f3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358052296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3358052296
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1497990343
Short name T369
Test name
Test status
Simulation time 159132868 ps
CPU time 4.16 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:37 PM PDT 24
Peak memory 208260 kb
Host smart-717eb3d9-6391-4458-8197-0712fc7282a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497990343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1497990343
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2138156456
Short name T514
Test name
Test status
Simulation time 328171477 ps
CPU time 11.33 seconds
Started Jul 21 05:38:35 PM PDT 24
Finished Jul 21 05:38:47 PM PDT 24
Peak memory 208664 kb
Host smart-7197fcb5-b5d1-4d11-95b9-67206f02f623
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138156456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2138156456
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3700173560
Short name T541
Test name
Test status
Simulation time 64704299 ps
CPU time 2.63 seconds
Started Jul 21 05:38:32 PM PDT 24
Finished Jul 21 05:38:36 PM PDT 24
Peak memory 208576 kb
Host smart-3b4f5aac-912c-4c82-98f9-91de7c12c544
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700173560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3700173560
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.973253138
Short name T652
Test name
Test status
Simulation time 223076718 ps
CPU time 2.6 seconds
Started Jul 21 05:38:37 PM PDT 24
Finished Jul 21 05:38:40 PM PDT 24
Peak memory 206916 kb
Host smart-b7a2cbf6-24a4-4ca8-8585-ec095962a10e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973253138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.973253138
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.902467875
Short name T584
Test name
Test status
Simulation time 498684054 ps
CPU time 3.66 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 207228 kb
Host smart-79e248d5-40f2-4efc-be1a-80367ec764fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902467875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.902467875
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3504069774
Short name T711
Test name
Test status
Simulation time 563430154 ps
CPU time 9.05 seconds
Started Jul 21 05:38:31 PM PDT 24
Finished Jul 21 05:38:40 PM PDT 24
Peak memory 208076 kb
Host smart-0bbc5cfa-11b7-43f4-8817-4afcbbba06e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504069774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3504069774
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2886702200
Short name T648
Test name
Test status
Simulation time 1854434322 ps
CPU time 51.51 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 214780 kb
Host smart-04a794c0-236e-40e4-8d53-3ead64bb5c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886702200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2886702200
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4288054579
Short name T913
Test name
Test status
Simulation time 8891207824 ps
CPU time 18.4 seconds
Started Jul 21 05:38:44 PM PDT 24
Finished Jul 21 05:39:02 PM PDT 24
Peak memory 209180 kb
Host smart-7b8e5e60-fe63-4c55-91bf-7238bd1f4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288054579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4288054579
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1617846396
Short name T795
Test name
Test status
Simulation time 196452273 ps
CPU time 2.48 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 209692 kb
Host smart-6f4f55f3-14ee-4200-8145-de9fb8817599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617846396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1617846396
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.12172090
Short name T634
Test name
Test status
Simulation time 81854762 ps
CPU time 0.76 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 205836 kb
Host smart-3ea573c5-0e40-47f8-b556-406aff6e72ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12172090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.12172090
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.416210458
Short name T409
Test name
Test status
Simulation time 805215630 ps
CPU time 10.89 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 214072 kb
Host smart-175a4e81-ad3c-42ec-8ad3-bc90cebbcff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416210458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.416210458
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2839451208
Short name T316
Test name
Test status
Simulation time 68787160 ps
CPU time 2.06 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 207808 kb
Host smart-22a57328-b2d4-4eb2-acf7-039ebb9456fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839451208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2839451208
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.873379446
Short name T914
Test name
Test status
Simulation time 199740076 ps
CPU time 2.49 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 214152 kb
Host smart-9e9d5967-050e-42cb-be9f-75d3e6395284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873379446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.873379446
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4175643228
Short name T869
Test name
Test status
Simulation time 97660290 ps
CPU time 2.07 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:41 PM PDT 24
Peak memory 214032 kb
Host smart-f78ef9b2-fae6-42de-8b13-e9da21b35484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175643228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4175643228
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2884145771
Short name T515
Test name
Test status
Simulation time 76301466 ps
CPU time 1.79 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 205832 kb
Host smart-dfcbe266-0746-43d9-b0f1-3b995dbc8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884145771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2884145771
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3198682604
Short name T89
Test name
Test status
Simulation time 677474873 ps
CPU time 9.79 seconds
Started Jul 21 05:38:38 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 208684 kb
Host smart-d4d8d69d-2a01-4d0d-b262-07402995b1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198682604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3198682604
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2956223113
Short name T706
Test name
Test status
Simulation time 182799385 ps
CPU time 4.58 seconds
Started Jul 21 05:38:44 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 206600 kb
Host smart-8b545e7a-0873-43a7-9af3-ba8027fb705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956223113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2956223113
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1069129924
Short name T692
Test name
Test status
Simulation time 53198909 ps
CPU time 2.84 seconds
Started Jul 21 05:38:38 PM PDT 24
Finished Jul 21 05:38:41 PM PDT 24
Peak memory 208240 kb
Host smart-0632a296-65ee-44a8-bcf8-0e54d113ea9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069129924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1069129924
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3959433026
Short name T779
Test name
Test status
Simulation time 296510802 ps
CPU time 4.04 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 208552 kb
Host smart-49b37bb5-8140-4cd5-8723-3567ccc784a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959433026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3959433026
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1056526347
Short name T111
Test name
Test status
Simulation time 99520826 ps
CPU time 3.76 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 206632 kb
Host smart-245322e4-3a12-4323-a422-85464cb858b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056526347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1056526347
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.831922183
Short name T559
Test name
Test status
Simulation time 113773240 ps
CPU time 2.84 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 208304 kb
Host smart-2ae08430-0a88-48b0-af66-2719fc8d602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831922183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.831922183
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3496636727
Short name T122
Test name
Test status
Simulation time 111426160 ps
CPU time 2.69 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:44 PM PDT 24
Peak memory 206596 kb
Host smart-4af6075d-0d5b-43a0-8980-d49ace6a4e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496636727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3496636727
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1377289077
Short name T234
Test name
Test status
Simulation time 1531602121 ps
CPU time 31.91 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 221052 kb
Host smart-87c25ba1-c7d5-458a-83b2-608676d58d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377289077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1377289077
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3956783339
Short name T621
Test name
Test status
Simulation time 105689887 ps
CPU time 3.53 seconds
Started Jul 21 05:38:41 PM PDT 24
Finished Jul 21 05:38:45 PM PDT 24
Peak memory 210024 kb
Host smart-14bfe0a7-b5b5-4bd8-8519-55eaf774cd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956783339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3956783339
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3832849467
Short name T738
Test name
Test status
Simulation time 65746288 ps
CPU time 2.58 seconds
Started Jul 21 05:38:40 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 210064 kb
Host smart-d6b6e360-726b-44c3-bd0f-03541c9edced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832849467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3832849467
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1018181344
Short name T629
Test name
Test status
Simulation time 20913485 ps
CPU time 0.85 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:33 PM PDT 24
Peak memory 205724 kb
Host smart-c2153e83-9425-4326-9393-627f543ae8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018181344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1018181344
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1463047966
Short name T138
Test name
Test status
Simulation time 51910431 ps
CPU time 3.81 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:37 PM PDT 24
Peak memory 214016 kb
Host smart-d7f108f0-c9e0-4da4-90fc-8b2b79a69606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463047966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1463047966
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.904287622
Short name T80
Test name
Test status
Simulation time 1108268093 ps
CPU time 2.79 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:37 PM PDT 24
Peak memory 218072 kb
Host smart-1bfbafe1-8728-4213-9459-5f55247f2666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904287622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.904287622
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3714119172
Short name T95
Test name
Test status
Simulation time 190266153 ps
CPU time 7.6 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:41 PM PDT 24
Peak memory 222208 kb
Host smart-9444857c-e268-4343-9c03-58e998ed77c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714119172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3714119172
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1497510088
Short name T735
Test name
Test status
Simulation time 470492348 ps
CPU time 4.47 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:37 PM PDT 24
Peak memory 221188 kb
Host smart-89db7aa9-9594-4e8d-b899-4c05f5900abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497510088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1497510088
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2001667649
Short name T695
Test name
Test status
Simulation time 238912135 ps
CPU time 4.86 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 222156 kb
Host smart-6fd69fb0-c0d9-4ceb-90d7-118ace828f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001667649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2001667649
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3304994694
Short name T50
Test name
Test status
Simulation time 1827099721 ps
CPU time 11.3 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 235152 kb
Host smart-f0db53e8-191d-48fe-ac5d-f4d35f770a0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304994694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3304994694
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1031112374
Short name T675
Test name
Test status
Simulation time 69549404 ps
CPU time 3.74 seconds
Started Jul 21 05:36:27 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 208052 kb
Host smart-36e24556-65c1-455b-acd3-ff9956f1c515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031112374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1031112374
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.608235193
Short name T900
Test name
Test status
Simulation time 369548346 ps
CPU time 4.32 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:41 PM PDT 24
Peak memory 208828 kb
Host smart-efbb310c-e956-4c8a-80fa-33ff19dcd130
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608235193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.608235193
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.621078579
Short name T323
Test name
Test status
Simulation time 94334042 ps
CPU time 4 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:41 PM PDT 24
Peak memory 208524 kb
Host smart-b145655e-73ee-4f90-8654-f826f462d275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621078579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.621078579
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3226056718
Short name T705
Test name
Test status
Simulation time 733520834 ps
CPU time 6.92 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:41 PM PDT 24
Peak memory 208404 kb
Host smart-3e95441f-4782-47db-ac28-860a47d20dfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226056718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3226056718
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3737723422
Short name T683
Test name
Test status
Simulation time 289719325 ps
CPU time 4.84 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:40 PM PDT 24
Peak memory 208740 kb
Host smart-e6635fc7-9799-4ffb-a4e7-f7d4326f7ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737723422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3737723422
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3129265695
Short name T643
Test name
Test status
Simulation time 533062575 ps
CPU time 3.28 seconds
Started Jul 21 05:36:28 PM PDT 24
Finished Jul 21 05:36:32 PM PDT 24
Peak memory 207844 kb
Host smart-42666123-3ee7-4fae-81d8-ccedc36ce61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129265695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3129265695
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.805958096
Short name T697
Test name
Test status
Simulation time 397721635 ps
CPU time 4.98 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:40 PM PDT 24
Peak memory 209452 kb
Host smart-d6e121ce-228f-462f-b0e6-c18c9bd841d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805958096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.805958096
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2817687038
Short name T449
Test name
Test status
Simulation time 98563505 ps
CPU time 2.21 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 209760 kb
Host smart-57ab9ef9-2310-4c92-bccc-274e1d1d0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817687038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2817687038
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.914917417
Short name T425
Test name
Test status
Simulation time 37309646 ps
CPU time 0.8 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 205816 kb
Host smart-591f78fb-6ae3-4c91-a699-0f26d040ff37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914917417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.914917417
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2727231836
Short name T899
Test name
Test status
Simulation time 57301063 ps
CPU time 2.53 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 214048 kb
Host smart-175226f5-46bd-44f0-9876-ac6482dbb40d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727231836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2727231836
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3018961125
Short name T830
Test name
Test status
Simulation time 134968033 ps
CPU time 3.11 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 209404 kb
Host smart-551447da-deb6-4180-b0d9-54844b8b0eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018961125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3018961125
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.151622314
Short name T798
Test name
Test status
Simulation time 272478505 ps
CPU time 2.72 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 214116 kb
Host smart-de6f033c-feea-4995-8155-75c8e61b241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151622314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.151622314
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.904853435
Short name T482
Test name
Test status
Simulation time 332855360 ps
CPU time 4.69 seconds
Started Jul 21 05:38:44 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 219864 kb
Host smart-628b2b45-8675-4245-a428-45abfb008a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904853435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.904853435
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.743658722
Short name T776
Test name
Test status
Simulation time 147985135 ps
CPU time 6.1 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 218268 kb
Host smart-fca5cd80-ac84-4033-8fb7-aaaa6e8da639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743658722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.743658722
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4148804106
Short name T847
Test name
Test status
Simulation time 110974543 ps
CPU time 3.89 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 208088 kb
Host smart-8083e764-4b55-4e6c-9f02-fca84771b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148804106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4148804106
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4236069566
Short name T846
Test name
Test status
Simulation time 47990869 ps
CPU time 2.89 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 206580 kb
Host smart-e2e21c14-a8c5-4bae-91dc-ac7cb5e6e4d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236069566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4236069566
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.474168628
Short name T394
Test name
Test status
Simulation time 195510125 ps
CPU time 2.78 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 206700 kb
Host smart-fca2ece3-c2a2-469d-8b73-bbd108453746
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474168628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.474168628
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.331182493
Short name T828
Test name
Test status
Simulation time 44608755 ps
CPU time 2.4 seconds
Started Jul 21 05:38:45 PM PDT 24
Finished Jul 21 05:38:48 PM PDT 24
Peak memory 208444 kb
Host smart-a2fad24a-d7a9-46fe-9775-841eb1b8a269
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331182493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.331182493
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3144224510
Short name T566
Test name
Test status
Simulation time 90945659 ps
CPU time 3.33 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 220184 kb
Host smart-9e13f00e-91f3-4fea-bba3-7f3151d9e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144224510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3144224510
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.785360653
Short name T661
Test name
Test status
Simulation time 54218706 ps
CPU time 2.76 seconds
Started Jul 21 05:38:39 PM PDT 24
Finished Jul 21 05:38:43 PM PDT 24
Peak memory 206736 kb
Host smart-312cd750-4051-47e1-9e03-2774afe39f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785360653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.785360653
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2447709522
Short name T77
Test name
Test status
Simulation time 272642609 ps
CPU time 17.57 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 222452 kb
Host smart-e5b34b9e-779d-43cb-832c-9d49148766f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447709522 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2447709522
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2105867218
Short name T278
Test name
Test status
Simulation time 64492948 ps
CPU time 3.92 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 207492 kb
Host smart-87051aa2-d845-4576-a698-7306ff72fe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105867218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2105867218
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1095050783
Short name T205
Test name
Test status
Simulation time 119830846 ps
CPU time 2.92 seconds
Started Jul 21 05:38:45 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 210060 kb
Host smart-0c5c654a-c2d5-486f-a242-512c3c51ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095050783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1095050783
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4293314097
Short name T467
Test name
Test status
Simulation time 9789552 ps
CPU time 0.81 seconds
Started Jul 21 05:38:45 PM PDT 24
Finished Jul 21 05:38:46 PM PDT 24
Peak memory 205824 kb
Host smart-73426623-e5d2-4e9c-b548-62b95b433c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293314097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4293314097
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4182115957
Short name T45
Test name
Test status
Simulation time 237280776 ps
CPU time 2.65 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 208928 kb
Host smart-7cbf7206-a9ed-4133-aa41-ad5e9806969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182115957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4182115957
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4285424911
Short name T322
Test name
Test status
Simulation time 38083777 ps
CPU time 2.67 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 214136 kb
Host smart-9eccd4c9-0b4b-4600-8876-34bf6701a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285424911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4285424911
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3317600386
Short name T94
Test name
Test status
Simulation time 66451907 ps
CPU time 2.19 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 222236 kb
Host smart-7f22ec71-142e-412e-a378-be4b90080b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317600386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3317600386
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3219209253
Short name T749
Test name
Test status
Simulation time 99352017 ps
CPU time 2.96 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 214012 kb
Host smart-8ecae710-ea46-4a51-bc30-36404d4bd5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219209253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3219209253
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.322079668
Short name T351
Test name
Test status
Simulation time 916673385 ps
CPU time 3.97 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 209060 kb
Host smart-d768179e-d005-4026-bfc0-879ee5c74c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322079668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.322079668
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3174237951
Short name T207
Test name
Test status
Simulation time 672145431 ps
CPU time 14.96 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:39:02 PM PDT 24
Peak memory 209916 kb
Host smart-60e8c081-fc45-47dc-8bd1-9b0143a9b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174237951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3174237951
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1216549897
Short name T575
Test name
Test status
Simulation time 53709863 ps
CPU time 2.79 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 208012 kb
Host smart-479308b1-ed18-413f-afbf-0aa5766b8285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216549897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1216549897
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3042598103
Short name T40
Test name
Test status
Simulation time 61993612 ps
CPU time 1.72 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 206684 kb
Host smart-e87e84fd-9071-4878-a87d-fa7e92e073ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042598103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3042598103
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1048512460
Short name T252
Test name
Test status
Simulation time 55576751 ps
CPU time 2.81 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 208424 kb
Host smart-6bf7a0f7-5d7e-4814-9a20-547a8fd18d6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048512460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1048512460
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3249295217
Short name T876
Test name
Test status
Simulation time 200395015 ps
CPU time 4.74 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 208544 kb
Host smart-84d78b8d-38c2-4287-a146-96946ecf6fc4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249295217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3249295217
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2561548451
Short name T545
Test name
Test status
Simulation time 40375160 ps
CPU time 2.71 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 209596 kb
Host smart-a38df8ff-27af-4143-beb1-165b34bdfc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561548451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2561548451
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4194369963
Short name T129
Test name
Test status
Simulation time 168267935 ps
CPU time 4.57 seconds
Started Jul 21 05:38:45 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 206896 kb
Host smart-8071df17-1103-44c8-ae5c-8bc10db028d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194369963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4194369963
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2947923537
Short name T710
Test name
Test status
Simulation time 744418943 ps
CPU time 10.68 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:39:00 PM PDT 24
Peak memory 222308 kb
Host smart-d865ad38-2a17-4764-834a-ff95d345f608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947923537 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2947923537
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.109934974
Short name T386
Test name
Test status
Simulation time 387351598 ps
CPU time 4.63 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 209036 kb
Host smart-93584651-5db8-4bcc-b95e-b04f3dcec2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109934974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.109934974
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2740681471
Short name T417
Test name
Test status
Simulation time 35978932 ps
CPU time 0.81 seconds
Started Jul 21 05:38:45 PM PDT 24
Finished Jul 21 05:38:47 PM PDT 24
Peak memory 205820 kb
Host smart-21170c67-60a0-4bc4-908c-0d7c1ba04f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740681471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2740681471
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1354610549
Short name T339
Test name
Test status
Simulation time 722815087 ps
CPU time 3.56 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 214096 kb
Host smart-7003b780-b7da-456f-b902-e4c21e1d0d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354610549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1354610549
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.407255207
Short name T392
Test name
Test status
Simulation time 40382927 ps
CPU time 2.39 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 208824 kb
Host smart-895b7947-ea7a-4d2a-a364-5942be3159dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407255207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.407255207
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2631334029
Short name T676
Test name
Test status
Simulation time 89170285 ps
CPU time 2.38 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 214168 kb
Host smart-ba89151f-9bbd-4228-993f-b012a7ed1beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631334029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2631334029
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.224587915
Short name T486
Test name
Test status
Simulation time 841755266 ps
CPU time 7.21 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 213976 kb
Host smart-cc29bbbb-2a04-411e-8f0a-a99e290f3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224587915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.224587915
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3301529956
Short name T384
Test name
Test status
Simulation time 574741377 ps
CPU time 2.8 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 222192 kb
Host smart-04684c4a-e448-462d-93c9-73cf6290fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301529956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3301529956
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2316924531
Short name T51
Test name
Test status
Simulation time 44921907 ps
CPU time 2.43 seconds
Started Jul 21 05:38:50 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 214048 kb
Host smart-c0d8228e-29b6-4bce-a2f0-7e8c90e77185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316924531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2316924531
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3145953555
Short name T407
Test name
Test status
Simulation time 258398790 ps
CPU time 4.55 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 207588 kb
Host smart-9b1eda98-88ec-4fc5-b194-efbfdd0e4ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145953555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3145953555
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3387559980
Short name T582
Test name
Test status
Simulation time 228323537 ps
CPU time 2.65 seconds
Started Jul 21 05:38:46 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 206568 kb
Host smart-42d501e8-256c-459a-9450-d696f3bbb099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387559980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3387559980
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3941901629
Short name T637
Test name
Test status
Simulation time 145774783 ps
CPU time 2.93 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 208668 kb
Host smart-7afc2394-e4ff-4170-bb96-f836b8c893b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941901629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3941901629
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2219139261
Short name T576
Test name
Test status
Simulation time 1617566220 ps
CPU time 32.86 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:39:21 PM PDT 24
Peak memory 208716 kb
Host smart-e0ba6328-5a7f-4f20-89ba-024c1fa6eb6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219139261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2219139261
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2909691365
Short name T870
Test name
Test status
Simulation time 10126301364 ps
CPU time 42.51 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 208992 kb
Host smart-a4604b3f-091c-4a2b-bd0a-c455c12c1a64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909691365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2909691365
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2051477505
Short name T729
Test name
Test status
Simulation time 115172345 ps
CPU time 2.63 seconds
Started Jul 21 05:38:44 PM PDT 24
Finished Jul 21 05:38:47 PM PDT 24
Peak memory 215504 kb
Host smart-60f03310-302c-4968-8b14-a1d00f021712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051477505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2051477505
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3508483792
Short name T811
Test name
Test status
Simulation time 124196223 ps
CPU time 3.69 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 206556 kb
Host smart-f002831a-241e-4a6f-b3bc-2a326d58bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508483792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3508483792
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2286009403
Short name T105
Test name
Test status
Simulation time 392233729 ps
CPU time 6.84 seconds
Started Jul 21 05:38:49 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 222312 kb
Host smart-f6410f83-cc0b-4767-8f6c-726172828f5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286009403 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2286009403
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.4015879678
Short name T257
Test name
Test status
Simulation time 115443914 ps
CPU time 5.2 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 214112 kb
Host smart-ab22706d-0ce5-4667-9eba-90e388a40d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015879678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.4015879678
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3876049216
Short name T71
Test name
Test status
Simulation time 4102292974 ps
CPU time 23.37 seconds
Started Jul 21 05:38:48 PM PDT 24
Finished Jul 21 05:39:12 PM PDT 24
Peak memory 211592 kb
Host smart-7ada51c1-e114-421c-a954-b95f608b68dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876049216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3876049216
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4129181347
Short name T804
Test name
Test status
Simulation time 54149428 ps
CPU time 0.79 seconds
Started Jul 21 05:38:50 PM PDT 24
Finished Jul 21 05:38:52 PM PDT 24
Peak memory 205804 kb
Host smart-2641b7b6-3030-40b3-bf5a-395847ad2f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129181347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4129181347
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1387062111
Short name T413
Test name
Test status
Simulation time 40187617 ps
CPU time 2.9 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 214080 kb
Host smart-0c774549-6f86-4a17-a028-b5b42c1ddf8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387062111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1387062111
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3835357307
Short name T849
Test name
Test status
Simulation time 301444418 ps
CPU time 2.26 seconds
Started Jul 21 05:38:59 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 209012 kb
Host smart-2665bbb3-68cb-4874-b7b1-f14b864b5993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835357307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3835357307
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3655221127
Short name T841
Test name
Test status
Simulation time 178569377 ps
CPU time 6 seconds
Started Jul 21 05:38:50 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 208764 kb
Host smart-16de47ef-267c-443a-84bd-4f4866cd29f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655221127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3655221127
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3382367332
Short name T86
Test name
Test status
Simulation time 237698546 ps
CPU time 2.27 seconds
Started Jul 21 05:38:50 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 214060 kb
Host smart-58b251ce-1181-4b94-a181-1703dc7b74d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382367332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3382367332
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1921475403
Short name T887
Test name
Test status
Simulation time 115449453 ps
CPU time 2.24 seconds
Started Jul 21 05:38:54 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 213952 kb
Host smart-c1771e70-061e-4459-844b-f4f6ffdf6e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921475403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1921475403
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.687517346
Short name T401
Test name
Test status
Simulation time 224281113 ps
CPU time 4.9 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 209788 kb
Host smart-1d0ed145-9b2b-41e7-8b73-08ea70f67320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687517346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.687517346
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1299795873
Short name T127
Test name
Test status
Simulation time 1141925091 ps
CPU time 28.74 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 208732 kb
Host smart-82af7ba6-509e-455b-8a59-c4aa798a9afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299795873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1299795873
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2519356515
Short name T310
Test name
Test status
Simulation time 296607475 ps
CPU time 3.17 seconds
Started Jul 21 05:38:56 PM PDT 24
Finished Jul 21 05:39:00 PM PDT 24
Peak memory 206872 kb
Host smart-be9ff6da-3e7c-4d35-95dd-72e8f2c373c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519356515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2519356515
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.330203168
Short name T210
Test name
Test status
Simulation time 120845696 ps
CPU time 2.11 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 207048 kb
Host smart-f4009c75-3532-4fee-ae0c-df6f8711b48d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330203168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.330203168
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2357300153
Short name T451
Test name
Test status
Simulation time 251976929 ps
CPU time 2.79 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 208828 kb
Host smart-dd16690d-4366-456e-8dfd-9919120815c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357300153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2357300153
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.904166740
Short name T314
Test name
Test status
Simulation time 167970807 ps
CPU time 3.8 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 208240 kb
Host smart-5fe4e57c-4a19-403e-9c92-d9e64c1c66fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904166740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.904166740
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2372822921
Short name T745
Test name
Test status
Simulation time 182099063 ps
CPU time 1.43 seconds
Started Jul 21 05:38:54 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 207224 kb
Host smart-c0a1194e-a947-410a-8277-ead8eaa06aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372822921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2372822921
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.327665977
Short name T571
Test name
Test status
Simulation time 321811281 ps
CPU time 3.2 seconds
Started Jul 21 05:38:47 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 208236 kb
Host smart-f01eb794-4956-48e1-a24a-f220a502c880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327665977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.327665977
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2064083298
Short name T289
Test name
Test status
Simulation time 566290828 ps
CPU time 11.45 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 219624 kb
Host smart-0cd0dcf4-b2a9-4aac-bcfc-878becc2ee98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064083298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2064083298
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3589412673
Short name T603
Test name
Test status
Simulation time 2505708008 ps
CPU time 6.64 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 214164 kb
Host smart-0a49955c-ea1c-4f4e-8827-aaab97ee5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589412673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3589412673
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.13256354
Short name T713
Test name
Test status
Simulation time 46305065 ps
CPU time 0.89 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:38:59 PM PDT 24
Peak memory 205820 kb
Host smart-44e4b996-04a7-453b-8a8a-047542677913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.13256354
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1195324082
Short name T136
Test name
Test status
Simulation time 112934219 ps
CPU time 2.49 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 214080 kb
Host smart-7cbceac4-8f21-4931-a33c-9a8d06b31397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195324082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1195324082
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3069196878
Short name T611
Test name
Test status
Simulation time 26029561 ps
CPU time 1.5 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:53 PM PDT 24
Peak memory 209096 kb
Host smart-cfb2a11a-e804-4e2f-bb5f-cfff489ee9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069196878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3069196878
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3526457688
Short name T564
Test name
Test status
Simulation time 143716132 ps
CPU time 3.59 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 214084 kb
Host smart-c228d4bc-d189-4302-927a-41e05716b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526457688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3526457688
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1221802431
Short name T330
Test name
Test status
Simulation time 105308669 ps
CPU time 3.42 seconds
Started Jul 21 05:38:54 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 218956 kb
Host smart-1c6ebc4e-2607-4c29-8602-a314c411f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221802431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1221802431
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3510499926
Short name T650
Test name
Test status
Simulation time 317910815 ps
CPU time 3.37 seconds
Started Jul 21 05:38:54 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 208500 kb
Host smart-1990b8ce-aac1-408d-be5c-fd70aa3d4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510499926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3510499926
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4141056205
Short name T208
Test name
Test status
Simulation time 33062989 ps
CPU time 2.27 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 207356 kb
Host smart-f87b53ee-f4c4-4732-8cec-bc12f79dafc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141056205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4141056205
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2961616420
Short name T702
Test name
Test status
Simulation time 6198382077 ps
CPU time 59.17 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 208392 kb
Host smart-0e524e14-86af-42cd-b774-9f8d72d4c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961616420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2961616420
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1815463569
Short name T484
Test name
Test status
Simulation time 56225484 ps
CPU time 2.74 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 206688 kb
Host smart-86dc006d-77d6-4169-88ec-694081e14485
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815463569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1815463569
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1776767100
Short name T910
Test name
Test status
Simulation time 202066344 ps
CPU time 2.97 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 208584 kb
Host smart-72466df2-90c5-4cd5-bd90-6010daa28140
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776767100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1776767100
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.238441596
Short name T728
Test name
Test status
Simulation time 454474361 ps
CPU time 3.41 seconds
Started Jul 21 05:38:54 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 208564 kb
Host smart-f235e600-cac8-48d8-8741-0a1622b4a540
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238441596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.238441596
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.751718201
Short name T398
Test name
Test status
Simulation time 37808928 ps
CPU time 2.21 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:38:55 PM PDT 24
Peak memory 214920 kb
Host smart-26cc185f-33c3-4c63-bc2a-69b14971dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751718201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.751718201
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1160924532
Short name T397
Test name
Test status
Simulation time 1226173295 ps
CPU time 13.87 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:39:07 PM PDT 24
Peak memory 207528 kb
Host smart-60b6e886-cd77-4b00-9c8b-3688902a0b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160924532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1160924532
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2150491078
Short name T362
Test name
Test status
Simulation time 1095147938 ps
CPU time 8.84 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:39:03 PM PDT 24
Peak memory 216140 kb
Host smart-7e12d44a-3c1d-42bc-a8a1-e233e63dc870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150491078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2150491078
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.96919797
Short name T206
Test name
Test status
Simulation time 165887200 ps
CPU time 6.3 seconds
Started Jul 21 05:38:51 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 208648 kb
Host smart-1aa4a3df-9d00-4f4e-b0ab-c0a706b1855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96919797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.96919797
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.447503168
Short name T389
Test name
Test status
Simulation time 165283389 ps
CPU time 2.12 seconds
Started Jul 21 05:38:53 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 209840 kb
Host smart-b2e768f9-a544-4e71-b492-31776abb2a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447503168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.447503168
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1226821011
Short name T508
Test name
Test status
Simulation time 50798326 ps
CPU time 0.77 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:38:58 PM PDT 24
Peak memory 205764 kb
Host smart-cc747806-ef99-4854-a83e-3a7efd7f1983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226821011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1226821011
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3794144800
Short name T380
Test name
Test status
Simulation time 1421412075 ps
CPU time 17.1 seconds
Started Jul 21 05:38:56 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 214028 kb
Host smart-89143e0e-9ffe-400f-a31f-903534520327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794144800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3794144800
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2634953801
Short name T688
Test name
Test status
Simulation time 801073702 ps
CPU time 3.09 seconds
Started Jul 21 05:38:56 PM PDT 24
Finished Jul 21 05:39:00 PM PDT 24
Peak memory 218104 kb
Host smart-fe0ea1a8-5ff4-478c-8f06-c0438749544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634953801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2634953801
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.13048409
Short name T836
Test name
Test status
Simulation time 214974552 ps
CPU time 7.91 seconds
Started Jul 21 05:39:02 PM PDT 24
Finished Jul 21 05:39:10 PM PDT 24
Peak memory 214092 kb
Host smart-73c647f1-c01c-4ca9-a281-52751e5a2802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13048409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.13048409
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2220851967
Short name T265
Test name
Test status
Simulation time 117918033 ps
CPU time 5.64 seconds
Started Jul 21 05:38:59 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 222144 kb
Host smart-b3500651-c145-4596-a7c7-e1e8933c0dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220851967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2220851967
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2418533009
Short name T654
Test name
Test status
Simulation time 878171088 ps
CPU time 3.44 seconds
Started Jul 21 05:38:59 PM PDT 24
Finished Jul 21 05:39:03 PM PDT 24
Peak memory 214032 kb
Host smart-71256c6d-5e5a-47df-8b4f-f212f8e210aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418533009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2418533009
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.132907711
Short name T612
Test name
Test status
Simulation time 469477487 ps
CPU time 3.95 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 209636 kb
Host smart-d300ebbe-7072-43b2-bd69-a588bf1152be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132907711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.132907711
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1210251560
Short name T821
Test name
Test status
Simulation time 84242784 ps
CPU time 2.57 seconds
Started Jul 21 05:39:00 PM PDT 24
Finished Jul 21 05:39:03 PM PDT 24
Peak memory 208472 kb
Host smart-96820c23-aa0e-416f-b270-39dc70b32bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210251560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1210251560
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2770564219
Short name T537
Test name
Test status
Simulation time 151683558 ps
CPU time 5.1 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:39:03 PM PDT 24
Peak memory 208456 kb
Host smart-395e4d45-58d4-424a-b36e-b9e3441a23fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770564219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2770564219
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3943764461
Short name T907
Test name
Test status
Simulation time 1991932307 ps
CPU time 35.46 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:39:29 PM PDT 24
Peak memory 208340 kb
Host smart-c4d18019-0ecf-4853-b9ff-97a91ada5bd8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943764461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3943764461
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3819160780
Short name T809
Test name
Test status
Simulation time 90521370 ps
CPU time 2.63 seconds
Started Jul 21 05:39:00 PM PDT 24
Finished Jul 21 05:39:03 PM PDT 24
Peak memory 206792 kb
Host smart-abb8a037-2242-47c1-9ce8-6a3168ea28e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819160780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3819160780
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2548453889
Short name T258
Test name
Test status
Simulation time 1072658893 ps
CPU time 9.47 seconds
Started Jul 21 05:39:02 PM PDT 24
Finished Jul 21 05:39:12 PM PDT 24
Peak memory 208096 kb
Host smart-90fabf93-57a3-4efd-a258-e5e194b7e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548453889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2548453889
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2996703293
Short name T595
Test name
Test status
Simulation time 130253173 ps
CPU time 2.93 seconds
Started Jul 21 05:38:52 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 208300 kb
Host smart-daa5fefd-d437-49dd-ae4e-4b851a0dc920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996703293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2996703293
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3055238178
Short name T630
Test name
Test status
Simulation time 932573062 ps
CPU time 9.34 seconds
Started Jul 21 05:38:55 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 220264 kb
Host smart-0227161a-7384-4fa6-8be0-d3f5bc589fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055238178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3055238178
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1987366311
Short name T780
Test name
Test status
Simulation time 1772518175 ps
CPU time 44.64 seconds
Started Jul 21 05:39:01 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 208408 kb
Host smart-fa38acd2-1ae7-421a-b1c9-250ca6767c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987366311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1987366311
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2527849920
Short name T70
Test name
Test status
Simulation time 916542327 ps
CPU time 3.04 seconds
Started Jul 21 05:39:02 PM PDT 24
Finished Jul 21 05:39:05 PM PDT 24
Peak memory 209552 kb
Host smart-1ab1eac3-b696-448f-adf8-76133ba3eb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527849920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2527849920
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3593695770
Short name T635
Test name
Test status
Simulation time 37377863 ps
CPU time 0.81 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:06 PM PDT 24
Peak memory 205980 kb
Host smart-5d04391b-c58d-49d7-978e-1f24a8befe2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593695770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3593695770
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1896761335
Short name T297
Test name
Test status
Simulation time 216675817 ps
CPU time 4.28 seconds
Started Jul 21 05:38:59 PM PDT 24
Finished Jul 21 05:39:04 PM PDT 24
Peak memory 214484 kb
Host smart-2c005c66-5391-477b-b713-19c594369993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896761335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1896761335
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1758986370
Short name T765
Test name
Test status
Simulation time 392410892 ps
CPU time 5.38 seconds
Started Jul 21 05:39:09 PM PDT 24
Finished Jul 21 05:39:15 PM PDT 24
Peak memory 214320 kb
Host smart-9eebef40-c91c-49c7-ba19-0f40afad606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758986370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1758986370
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2502558683
Short name T570
Test name
Test status
Simulation time 2597779095 ps
CPU time 14.96 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 208528 kb
Host smart-83bbfc1c-0c91-4d5f-9910-866efe1d8261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502558683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2502558683
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2618395650
Short name T503
Test name
Test status
Simulation time 90759644 ps
CPU time 4.46 seconds
Started Jul 21 05:39:07 PM PDT 24
Finished Jul 21 05:39:12 PM PDT 24
Peak memory 218040 kb
Host smart-e232c7ba-a9bf-407c-818e-733522fb3acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618395650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2618395650
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.854553136
Short name T347
Test name
Test status
Simulation time 122743478 ps
CPU time 4.65 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:10 PM PDT 24
Peak memory 220880 kb
Host smart-6e368364-cbd3-480b-b89d-27b9b76d3aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854553136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.854553136
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.29846719
Short name T447
Test name
Test status
Simulation time 329846443 ps
CPU time 3.84 seconds
Started Jul 21 05:39:10 PM PDT 24
Finished Jul 21 05:39:15 PM PDT 24
Peak memory 209048 kb
Host smart-04423b1b-0f1c-4693-92d6-a20a81c3e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29846719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.29846719
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2464629576
Short name T800
Test name
Test status
Simulation time 201005681 ps
CPU time 3.51 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:39:02 PM PDT 24
Peak memory 207404 kb
Host smart-49810968-e659-4746-a139-692714bb9e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464629576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2464629576
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.704454888
Short name T271
Test name
Test status
Simulation time 432779358 ps
CPU time 5.54 seconds
Started Jul 21 05:39:00 PM PDT 24
Finished Jul 21 05:39:06 PM PDT 24
Peak memory 208040 kb
Host smart-8a8c2dcb-b4d3-4795-8636-cf861dc0f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704454888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.704454888
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2342506793
Short name T762
Test name
Test status
Simulation time 2620631937 ps
CPU time 51.16 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:39:49 PM PDT 24
Peak memory 209164 kb
Host smart-d6024e88-095d-4f89-921c-d82dca9f51dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342506793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2342506793
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.496146298
Short name T517
Test name
Test status
Simulation time 146169762 ps
CPU time 3.22 seconds
Started Jul 21 05:38:56 PM PDT 24
Finished Jul 21 05:38:59 PM PDT 24
Peak memory 206712 kb
Host smart-b6a3dc46-c364-4972-ab00-b2e101fd3a43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496146298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.496146298
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3259168531
Short name T382
Test name
Test status
Simulation time 128636367 ps
CPU time 2.45 seconds
Started Jul 21 05:38:58 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 206760 kb
Host smart-3b0ebf12-479d-43d7-924a-7079c86f7064
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259168531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3259168531
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2960385512
Short name T250
Test name
Test status
Simulation time 34341619 ps
CPU time 1.94 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:08 PM PDT 24
Peak memory 208764 kb
Host smart-09acda15-e81d-4e79-a86a-f26322d9468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960385512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2960385512
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3816385469
Short name T427
Test name
Test status
Simulation time 740067494 ps
CPU time 3.53 seconds
Started Jul 21 05:38:57 PM PDT 24
Finished Jul 21 05:39:01 PM PDT 24
Peak memory 207560 kb
Host smart-ca873cbf-5689-4fbe-b531-29b0894ce97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816385469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3816385469
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3208077688
Short name T881
Test name
Test status
Simulation time 757168807 ps
CPU time 20.87 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 215292 kb
Host smart-f42b22a4-ad4f-494b-adf1-b14ec344ec67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208077688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3208077688
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.240063183
Short name T755
Test name
Test status
Simulation time 238154558 ps
CPU time 7.27 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 222352 kb
Host smart-e5025221-7ad6-433d-8ada-3910fbead6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240063183 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.240063183
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2610368208
Short name T855
Test name
Test status
Simulation time 246813051 ps
CPU time 5.63 seconds
Started Jul 21 05:39:02 PM PDT 24
Finished Jul 21 05:39:08 PM PDT 24
Peak memory 209500 kb
Host smart-19145db5-b444-4ac5-9ce0-dd99c2260373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610368208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2610368208
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1635966602
Short name T64
Test name
Test status
Simulation time 529834066 ps
CPU time 2.96 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 209572 kb
Host smart-ff4c6cc8-b32c-45f0-a923-43f7d2a22025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635966602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1635966602
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1637127434
Short name T494
Test name
Test status
Simulation time 11664041 ps
CPU time 0.87 seconds
Started Jul 21 05:39:03 PM PDT 24
Finished Jul 21 05:39:04 PM PDT 24
Peak memory 205872 kb
Host smart-ae4816e1-8743-4b59-8048-f0e2505a824d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637127434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1637127434
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3479892949
Short name T391
Test name
Test status
Simulation time 37053594 ps
CPU time 2.96 seconds
Started Jul 21 05:39:04 PM PDT 24
Finished Jul 21 05:39:07 PM PDT 24
Peak memory 214152 kb
Host smart-f6e04516-f149-4588-bd0d-08f6ecd3f785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479892949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3479892949
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.61976785
Short name T489
Test name
Test status
Simulation time 338123936 ps
CPU time 2.66 seconds
Started Jul 21 05:39:10 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 207216 kb
Host smart-e981bba0-3adf-4b0a-ae34-16fea9dec407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61976785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.61976785
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3180023010
Short name T44
Test name
Test status
Simulation time 283015532 ps
CPU time 2.86 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 214128 kb
Host smart-48c60011-7789-4b6a-a4f2-94dcafc8fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180023010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3180023010
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1730331329
Short name T247
Test name
Test status
Simulation time 61182029 ps
CPU time 3.15 seconds
Started Jul 21 05:39:07 PM PDT 24
Finished Jul 21 05:39:11 PM PDT 24
Peak memory 213992 kb
Host smart-1abdd917-a895-401e-a598-0517d5880561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730331329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1730331329
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.305506280
Short name T221
Test name
Test status
Simulation time 44105280 ps
CPU time 2.88 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 209296 kb
Host smart-63b2c785-233d-4d17-9308-5d8ba6c56036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305506280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.305506280
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.468752051
Short name T733
Test name
Test status
Simulation time 98087725 ps
CPU time 4.54 seconds
Started Jul 21 05:39:07 PM PDT 24
Finished Jul 21 05:39:12 PM PDT 24
Peak memory 209900 kb
Host smart-eadc4e3a-92d4-4c35-84a1-1b88ebfa45c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468752051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.468752051
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2639769926
Short name T686
Test name
Test status
Simulation time 304541661 ps
CPU time 6.42 seconds
Started Jul 21 05:39:04 PM PDT 24
Finished Jul 21 05:39:11 PM PDT 24
Peak memory 206632 kb
Host smart-f9711d98-7976-46d9-b697-5d38e0022ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639769926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2639769926
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.46334735
Short name T18
Test name
Test status
Simulation time 3219297936 ps
CPU time 54.69 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:40:01 PM PDT 24
Peak memory 208352 kb
Host smart-383df316-238a-44fc-a685-49c5a1e182f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46334735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.46334735
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3355023471
Short name T638
Test name
Test status
Simulation time 76855118 ps
CPU time 3.58 seconds
Started Jul 21 05:39:10 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 208744 kb
Host smart-e820280c-1643-4dc5-9347-86bda11eb64c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355023471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3355023471
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1695341929
Short name T501
Test name
Test status
Simulation time 32689944 ps
CPU time 2.39 seconds
Started Jul 21 05:39:03 PM PDT 24
Finished Jul 21 05:39:06 PM PDT 24
Peak memory 206708 kb
Host smart-f81cae66-60dc-4631-ae89-d02d60ff4c43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695341929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1695341929
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2622339897
Short name T291
Test name
Test status
Simulation time 94698025 ps
CPU time 3.76 seconds
Started Jul 21 05:39:07 PM PDT 24
Finished Jul 21 05:39:11 PM PDT 24
Peak memory 218016 kb
Host smart-75a43291-f31f-4bb7-9243-0ecff8d4b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622339897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2622339897
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2990008280
Short name T399
Test name
Test status
Simulation time 312005698 ps
CPU time 3.26 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:15 PM PDT 24
Peak memory 208360 kb
Host smart-e30e4317-86bc-42c7-982f-7cbbe6b61eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990008280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2990008280
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.4065135241
Short name T596
Test name
Test status
Simulation time 404806675 ps
CPU time 14.04 seconds
Started Jul 21 05:39:04 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 222420 kb
Host smart-d191ba12-2c70-4fe5-ae71-acbcc3148374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065135241 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.4065135241
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2964217829
Short name T499
Test name
Test status
Simulation time 1068449149 ps
CPU time 8.07 seconds
Started Jul 21 05:39:04 PM PDT 24
Finished Jul 21 05:39:13 PM PDT 24
Peak memory 209632 kb
Host smart-c579c843-ab17-4e08-a923-07b42348cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964217829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2964217829
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2970096454
Short name T171
Test name
Test status
Simulation time 579282746 ps
CPU time 8.92 seconds
Started Jul 21 05:39:08 PM PDT 24
Finished Jul 21 05:39:18 PM PDT 24
Peak memory 210188 kb
Host smart-b2efa753-cf3f-4f81-b1e6-b051eaf1d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970096454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2970096454
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3918471633
Short name T536
Test name
Test status
Simulation time 50805015 ps
CPU time 1 seconds
Started Jul 21 05:39:22 PM PDT 24
Finished Jul 21 05:39:23 PM PDT 24
Peak memory 205992 kb
Host smart-661ab915-d14a-4d9c-afc0-4658ea0e6af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918471633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3918471633
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1306795155
Short name T873
Test name
Test status
Simulation time 919879503 ps
CPU time 2.24 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 208420 kb
Host smart-a00915b5-49e7-48bf-ab12-8e3f8d5760a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306795155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1306795155
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2445591619
Short name T699
Test name
Test status
Simulation time 49984739 ps
CPU time 1.95 seconds
Started Jul 21 05:39:03 PM PDT 24
Finished Jul 21 05:39:06 PM PDT 24
Peak memory 209168 kb
Host smart-51247b25-614e-4845-896f-98f84b3ba9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445591619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2445591619
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3601197650
Short name T110
Test name
Test status
Simulation time 132310655 ps
CPU time 1.81 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:13 PM PDT 24
Peak memory 214164 kb
Host smart-de5ad628-5140-41e5-94c3-ac2bfcd44d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601197650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3601197650
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.762677592
Short name T367
Test name
Test status
Simulation time 1843421638 ps
CPU time 3.35 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 213992 kb
Host smart-3eb8d4ba-a102-40b7-bb34-e43c9ec001c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762677592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.762677592
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2832378738
Short name T222
Test name
Test status
Simulation time 137273771 ps
CPU time 6.95 seconds
Started Jul 21 05:39:13 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 222260 kb
Host smart-73d15e0c-d2cc-4200-be91-b11286a21f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832378738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2832378738
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2840734839
Short name T393
Test name
Test status
Simulation time 145984287 ps
CPU time 3.7 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:10 PM PDT 24
Peak memory 222188 kb
Host smart-0897cd5a-3bb3-40fb-9dd7-f4195bbdad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840734839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2840734839
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.729201555
Short name T604
Test name
Test status
Simulation time 137993773 ps
CPU time 4.86 seconds
Started Jul 21 05:39:09 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 208444 kb
Host smart-2839e5ba-4d5a-4bd1-a2fc-83c78bde60be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729201555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.729201555
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3855691897
Short name T475
Test name
Test status
Simulation time 73273066 ps
CPU time 2.49 seconds
Started Jul 21 05:39:04 PM PDT 24
Finished Jul 21 05:39:08 PM PDT 24
Peak memory 206696 kb
Host smart-614168ec-8643-474d-a16e-28da4f2835ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855691897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3855691897
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2166511725
Short name T664
Test name
Test status
Simulation time 176388895 ps
CPU time 7.04 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:13 PM PDT 24
Peak memory 208124 kb
Host smart-26fb0baf-ddeb-426a-99a8-9f4de60a3467
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166511725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2166511725
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2357773694
Short name T523
Test name
Test status
Simulation time 518617960 ps
CPU time 10.37 seconds
Started Jul 21 05:39:05 PM PDT 24
Finished Jul 21 05:39:16 PM PDT 24
Peak memory 207816 kb
Host smart-d51e8f03-cee3-430d-b25c-90c4de87a431
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357773694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2357773694
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4050142564
Short name T681
Test name
Test status
Simulation time 69869689 ps
CPU time 2.82 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 209500 kb
Host smart-29970787-a1bc-4e7b-962f-5ffcd1cb5766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050142564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4050142564
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.149693663
Short name T403
Test name
Test status
Simulation time 334365082 ps
CPU time 2.4 seconds
Started Jul 21 05:39:06 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 205824 kb
Host smart-d8520416-a851-47e2-a288-6c47a33fa66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149693663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.149693663
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1776114174
Short name T880
Test name
Test status
Simulation time 4290376557 ps
CPU time 22.14 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 209432 kb
Host smart-0664152c-3343-403b-ae37-ea56ab01fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776114174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1776114174
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2175833286
Short name T608
Test name
Test status
Simulation time 70063929 ps
CPU time 1.64 seconds
Started Jul 21 05:39:09 PM PDT 24
Finished Jul 21 05:39:11 PM PDT 24
Peak memory 209640 kb
Host smart-b7b8fc0e-2fa4-460d-bf58-b92f4a1d45fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175833286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2175833286
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1494824706
Short name T526
Test name
Test status
Simulation time 24308974 ps
CPU time 0.86 seconds
Started Jul 21 05:39:12 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 205832 kb
Host smart-962e88e1-197a-483e-ac33-70b94a39d6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494824706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1494824706
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2354557146
Short name T374
Test name
Test status
Simulation time 99522176 ps
CPU time 4.04 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 214012 kb
Host smart-2dda069e-36d7-4ba2-be05-5b3eff05a08c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354557146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2354557146
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1141359442
Short name T803
Test name
Test status
Simulation time 781598252 ps
CPU time 3.5 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 209696 kb
Host smart-fa7cb659-ab56-48bf-b75f-eacff23f7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141359442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1141359442
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2985025760
Short name T329
Test name
Test status
Simulation time 93287216 ps
CPU time 2.19 seconds
Started Jul 21 05:39:19 PM PDT 24
Finished Jul 21 05:39:22 PM PDT 24
Peak memory 214084 kb
Host smart-67945726-6920-439e-8b8a-3214946d802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985025760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2985025760
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2074622733
Short name T700
Test name
Test status
Simulation time 117696559 ps
CPU time 4.6 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:21 PM PDT 24
Peak memory 214392 kb
Host smart-27bd3eec-4d83-4181-83e7-0d22c5152e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074622733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2074622733
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.800195731
Short name T853
Test name
Test status
Simulation time 1243770994 ps
CPU time 17.39 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 218508 kb
Host smart-9ffa7d6f-24a4-48e5-a2ee-1ce0c13c6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800195731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.800195731
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2224436025
Short name T298
Test name
Test status
Simulation time 444400862 ps
CPU time 9.3 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 207884 kb
Host smart-7e898018-3006-48e3-ac04-3f53ea97917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224436025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2224436025
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3472491882
Short name T555
Test name
Test status
Simulation time 250277619 ps
CPU time 6.77 seconds
Started Jul 21 05:39:19 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 208144 kb
Host smart-5fefacac-f469-42ef-b1b5-ec5aa40813cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472491882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3472491882
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3033062581
Short name T441
Test name
Test status
Simulation time 605658419 ps
CPU time 3.47 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 208352 kb
Host smart-daa05d71-4774-4148-9aba-d626b3a9fed0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033062581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3033062581
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.730974899
Short name T871
Test name
Test status
Simulation time 466589314 ps
CPU time 4.21 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 208756 kb
Host smart-c61d107b-2ecf-48f2-8f83-c3fc66664ed0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730974899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.730974899
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.955967715
Short name T819
Test name
Test status
Simulation time 961779280 ps
CPU time 4.78 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 208616 kb
Host smart-867e6c0e-ac60-4557-bfb2-1c06298260ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955967715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.955967715
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2831357322
Short name T628
Test name
Test status
Simulation time 190465950 ps
CPU time 2.22 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:23 PM PDT 24
Peak memory 207260 kb
Host smart-bd830bfc-d377-441c-8e84-c21727547882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831357322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2831357322
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4146334967
Short name T633
Test name
Test status
Simulation time 243666988 ps
CPU time 4.89 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 206544 kb
Host smart-5516521e-492f-4bc1-bc7e-c0a88f695898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146334967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4146334967
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2473585764
Short name T906
Test name
Test status
Simulation time 506261851 ps
CPU time 3.8 seconds
Started Jul 21 05:39:18 PM PDT 24
Finished Jul 21 05:39:22 PM PDT 24
Peak memory 214072 kb
Host smart-650ab55a-6788-433a-b492-26f3779136e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473585764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2473585764
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2911491658
Short name T670
Test name
Test status
Simulation time 591554639 ps
CPU time 2.45 seconds
Started Jul 21 05:39:16 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 209988 kb
Host smart-f54b3864-8595-4ad8-8691-95828b583b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911491658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2911491658
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.559810492
Short name T678
Test name
Test status
Simulation time 55488164 ps
CPU time 0.82 seconds
Started Jul 21 05:36:35 PM PDT 24
Finished Jul 21 05:36:36 PM PDT 24
Peak memory 205820 kb
Host smart-475cbc93-5bba-492e-b32e-279617d2bdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559810492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.559810492
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1250312387
Short name T22
Test name
Test status
Simulation time 82858745 ps
CPU time 2.67 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:40 PM PDT 24
Peak memory 208448 kb
Host smart-8a52b7c8-4238-46b1-b6ce-b3a707feaede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250312387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1250312387
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.648044784
Short name T79
Test name
Test status
Simulation time 1694809949 ps
CPU time 3.52 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 208812 kb
Host smart-63c3f3af-eada-4f53-b742-fcbab6d925a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648044784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.648044784
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2644023745
Short name T802
Test name
Test status
Simulation time 183714525 ps
CPU time 2.62 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 214096 kb
Host smart-abd1e4c7-d750-4806-91b2-e16eab9c53cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644023745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2644023745
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4018514281
Short name T267
Test name
Test status
Simulation time 229792569 ps
CPU time 2.53 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:36 PM PDT 24
Peak memory 214104 kb
Host smart-57a01364-6b7b-4217-bcf0-6f9db84604f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018514281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4018514281
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.446384675
Short name T7
Test name
Test status
Simulation time 696649423 ps
CPU time 4.98 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 214044 kb
Host smart-ed34c9a5-9d59-4129-be12-ef19e6114ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446384675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.446384675
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.503442028
Short name T609
Test name
Test status
Simulation time 249490526 ps
CPU time 7.48 seconds
Started Jul 21 05:36:35 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 207696 kb
Host smart-69975e58-307d-49ec-808b-cc1e72177f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503442028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.503442028
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2472972371
Short name T290
Test name
Test status
Simulation time 250343970 ps
CPU time 2.67 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 207068 kb
Host smart-e0e38004-0d11-4c40-ad5f-22a844ff87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472972371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2472972371
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1429931864
Short name T832
Test name
Test status
Simulation time 244663081 ps
CPU time 2.67 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:35 PM PDT 24
Peak memory 206464 kb
Host smart-3fd2d768-6fd1-4137-a54b-e4d8045bf454
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429931864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1429931864
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3571906324
Short name T602
Test name
Test status
Simulation time 34670829 ps
CPU time 2.38 seconds
Started Jul 21 05:36:37 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 206636 kb
Host smart-a0bc15c3-e8e0-4726-a6d2-913669accd68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571906324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3571906324
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2396165864
Short name T684
Test name
Test status
Simulation time 128338069 ps
CPU time 3 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:35 PM PDT 24
Peak memory 208276 kb
Host smart-80f00ae5-ebc5-4f02-8dba-fdfa523d96c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396165864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2396165864
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2122559321
Short name T109
Test name
Test status
Simulation time 110852639 ps
CPU time 2.48 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:36 PM PDT 24
Peak memory 217976 kb
Host smart-3db60cb3-85ce-4b11-a50f-a7c4ff3658f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122559321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2122559321
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3804830535
Short name T806
Test name
Test status
Simulation time 166103075 ps
CPU time 4.36 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:41 PM PDT 24
Peak memory 207700 kb
Host smart-d0ffd5ef-efe7-4243-b2d9-2afaa6119671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804830535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3804830535
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1083347890
Short name T306
Test name
Test status
Simulation time 723646677 ps
CPU time 10.22 seconds
Started Jul 21 05:36:35 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 222412 kb
Host smart-cdd3ae19-6058-424e-97b2-ffb053d9bb7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083347890 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1083347890
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3789304359
Short name T342
Test name
Test status
Simulation time 133201815 ps
CPU time 3.26 seconds
Started Jul 21 05:36:35 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 207760 kb
Host smart-e2ec4319-3805-4405-8830-3a9ccc82d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789304359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3789304359
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1099695959
Short name T209
Test name
Test status
Simulation time 69240923 ps
CPU time 1.86 seconds
Started Jul 21 05:36:32 PM PDT 24
Finished Jul 21 05:36:35 PM PDT 24
Peak memory 209704 kb
Host smart-da17b1ef-2e78-402c-8c77-6c952c9f0a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099695959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1099695959
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4294596102
Short name T736
Test name
Test status
Simulation time 45745426 ps
CPU time 0.75 seconds
Started Jul 21 05:36:36 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 205776 kb
Host smart-f8d6500f-cc74-49bc-8f16-a781f27e2757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294596102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4294596102
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1449689556
Short name T414
Test name
Test status
Simulation time 110718484 ps
CPU time 4.23 seconds
Started Jul 21 05:36:41 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 214872 kb
Host smart-a4478cbc-46ce-4cd4-a8ac-1549fee0bc4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449689556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1449689556
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2042358973
Short name T33
Test name
Test status
Simulation time 145393018 ps
CPU time 2.66 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:44 PM PDT 24
Peak memory 209952 kb
Host smart-c7ae3a18-81e1-4c22-81ea-6192c660ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042358973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2042358973
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2858611047
Short name T299
Test name
Test status
Simulation time 91170331 ps
CPU time 2.83 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:45 PM PDT 24
Peak memory 207712 kb
Host smart-a1dc809a-f41e-4c27-99ac-eefb4d0c5bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858611047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2858611047
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1216360774
Short name T469
Test name
Test status
Simulation time 125997292 ps
CPU time 3.26 seconds
Started Jul 21 05:36:38 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 222136 kb
Host smart-fe36a174-28fe-41aa-bfaa-b5cdbf691ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216360774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1216360774
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1661573193
Short name T301
Test name
Test status
Simulation time 156007725 ps
CPU time 2.99 seconds
Started Jul 21 05:36:38 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 214036 kb
Host smart-17e28e1b-2f1e-458f-896e-a15e79c4bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661573193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1661573193
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1767400545
Short name T378
Test name
Test status
Simulation time 473924776 ps
CPU time 4.53 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:48 PM PDT 24
Peak memory 214120 kb
Host smart-bd1675cd-f200-4f7f-82e2-c23707a2ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767400545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1767400545
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4007202366
Short name T334
Test name
Test status
Simulation time 1256077273 ps
CPU time 9.2 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:49 PM PDT 24
Peak memory 214020 kb
Host smart-3e6527d7-b658-4765-8664-9bbe4e9a531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007202366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4007202366
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1378780684
Short name T547
Test name
Test status
Simulation time 435760243 ps
CPU time 4.05 seconds
Started Jul 21 05:36:34 PM PDT 24
Finished Jul 21 05:36:39 PM PDT 24
Peak memory 207632 kb
Host smart-11e3c785-d117-4845-900a-d6f93ef634bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378780684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1378780684
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.834806604
Short name T796
Test name
Test status
Simulation time 424211723 ps
CPU time 4.28 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 206628 kb
Host smart-62f9e84f-2efd-4c86-b853-960aa9c9a4c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834806604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.834806604
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.315299851
Short name T911
Test name
Test status
Simulation time 75009607 ps
CPU time 3.39 seconds
Started Jul 21 05:36:33 PM PDT 24
Finished Jul 21 05:36:38 PM PDT 24
Peak memory 208268 kb
Host smart-a77486b1-fae8-4317-88f3-4bc0a2f4bcb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315299851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.315299851
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3352609097
Short name T600
Test name
Test status
Simulation time 235879695 ps
CPU time 5.4 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 206516 kb
Host smart-45f44e39-f129-421b-8c77-7debc06898c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352609097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3352609097
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2875021844
Short name T839
Test name
Test status
Simulation time 140935561 ps
CPU time 4.32 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:44 PM PDT 24
Peak memory 214056 kb
Host smart-adcc7d99-d716-40a7-9af7-211484334261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875021844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2875021844
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4277943039
Short name T532
Test name
Test status
Simulation time 1679620711 ps
CPU time 11.87 seconds
Started Jul 21 05:36:30 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 207704 kb
Host smart-89403cae-f7cf-4d84-a08b-692ba4aff83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277943039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4277943039
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1429205371
Short name T83
Test name
Test status
Simulation time 1095552384 ps
CPU time 34.29 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 222120 kb
Host smart-6c1e969e-709b-400a-80a5-06819cfba2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429205371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1429205371
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.198483490
Short name T107
Test name
Test status
Simulation time 280392647 ps
CPU time 10.85 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 218164 kb
Host smart-88d701a9-c70e-4db1-b1f7-2a81e2614b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198483490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.198483490
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.274163996
Short name T473
Test name
Test status
Simulation time 367290675 ps
CPU time 2.94 seconds
Started Jul 21 05:36:41 PM PDT 24
Finished Jul 21 05:36:44 PM PDT 24
Peak memory 210400 kb
Host smart-8d94fd9e-b356-44cf-80ff-7778bd5d0195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274163996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.274163996
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3270099367
Short name T574
Test name
Test status
Simulation time 82022829 ps
CPU time 0.88 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 205728 kb
Host smart-41a00b16-48b0-4484-9783-557a01345536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270099367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3270099367
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3923555054
Short name T139
Test name
Test status
Simulation time 243600939 ps
CPU time 10.99 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:50 PM PDT 24
Peak memory 214036 kb
Host smart-1e4e795d-cb93-4e51-a269-96b7d587bc47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923555054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3923555054
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3847473343
Short name T721
Test name
Test status
Simulation time 322894259 ps
CPU time 4.21 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 214428 kb
Host smart-fb1879a5-8e26-4be8-84bc-56b2faf108d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847473343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3847473343
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2294989735
Short name T56
Test name
Test status
Simulation time 137559213 ps
CPU time 3.1 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 218288 kb
Host smart-093dd868-3838-4053-a903-8798ede1d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294989735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2294989735
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2695170618
Short name T245
Test name
Test status
Simulation time 65632224 ps
CPU time 2.06 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:36:42 PM PDT 24
Peak memory 214060 kb
Host smart-3dd2775f-27b1-4ade-8ec0-8169a80b2f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695170618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2695170618
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.505484389
Short name T689
Test name
Test status
Simulation time 444663289 ps
CPU time 4.38 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 220336 kb
Host smart-0aa35590-b4bf-4bf9-b410-0a61238867f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505484389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.505484389
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2617367986
Short name T902
Test name
Test status
Simulation time 757412080 ps
CPU time 3.97 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:45 PM PDT 24
Peak memory 209328 kb
Host smart-0f9dc242-41dd-4bb0-9e39-a3948430d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617367986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2617367986
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2292050818
Short name T288
Test name
Test status
Simulation time 1060210527 ps
CPU time 23.66 seconds
Started Jul 21 05:36:39 PM PDT 24
Finished Jul 21 05:37:03 PM PDT 24
Peak memory 218304 kb
Host smart-7bb5d4eb-decb-453e-85ca-8472f828fce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292050818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2292050818
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2170579876
Short name T376
Test name
Test status
Simulation time 45276043 ps
CPU time 2.6 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 206508 kb
Host smart-7f093326-edaa-434c-a3c5-ecffc4ce1859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170579876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2170579876
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3926856014
Short name T897
Test name
Test status
Simulation time 87840128 ps
CPU time 3.25 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 206572 kb
Host smart-e42185fa-97bf-4019-b6d7-e4341643ec04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926856014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3926856014
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.218373245
Short name T568
Test name
Test status
Simulation time 5767621839 ps
CPU time 59.93 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:37:41 PM PDT 24
Peak memory 208960 kb
Host smart-0ab5785b-8476-4986-9302-33d3b024bd81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218373245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.218373245
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2118340154
Short name T833
Test name
Test status
Simulation time 558771986 ps
CPU time 2.56 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 206616 kb
Host smart-8d0bd098-ff9f-423d-96a8-6104eff2aed5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118340154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2118340154
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4027117322
Short name T703
Test name
Test status
Simulation time 162476748 ps
CPU time 1.66 seconds
Started Jul 21 05:36:40 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 207276 kb
Host smart-a39d4f14-695a-4e83-9fc3-866ff988f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027117322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4027117322
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1332790459
Short name T198
Test name
Test status
Simulation time 164953206 ps
CPU time 3.9 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 207736 kb
Host smart-7dfa854d-2ee8-4910-96da-ba0a486ef357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332790459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1332790459
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1940810015
Short name T326
Test name
Test status
Simulation time 1149171487 ps
CPU time 34.68 seconds
Started Jul 21 05:36:41 PM PDT 24
Finished Jul 21 05:37:16 PM PDT 24
Peak memory 222332 kb
Host smart-b979f133-a49f-441d-bb12-3120562d4f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940810015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1940810015
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.61374364
Short name T124
Test name
Test status
Simulation time 2191582575 ps
CPU time 13.34 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:59 PM PDT 24
Peak memory 220488 kb
Host smart-cd313fa4-51e1-4257-9b0a-030f2cfa42ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61374364 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.61374364
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2314930873
Short name T383
Test name
Test status
Simulation time 825939197 ps
CPU time 6.72 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:49 PM PDT 24
Peak memory 208748 kb
Host smart-d78d4cc1-c94a-4d14-9a1c-1d9b57436b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314930873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2314930873
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3575195398
Short name T180
Test name
Test status
Simulation time 46342151 ps
CPU time 2.23 seconds
Started Jul 21 05:36:42 PM PDT 24
Finished Jul 21 05:36:45 PM PDT 24
Peak memory 210024 kb
Host smart-92162992-7397-4be8-a7d9-535cd1a577e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575195398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3575195398
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3473919372
Short name T844
Test name
Test status
Simulation time 60229347 ps
CPU time 0.94 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 205848 kb
Host smart-3c31fd8c-1b42-40e4-a94e-e97870ae2021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473919372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3473919372
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.330215677
Short name T402
Test name
Test status
Simulation time 155956929 ps
CPU time 2.72 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:49 PM PDT 24
Peak memory 214084 kb
Host smart-8edef00f-d537-4c74-82ad-2581eaa2012d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330215677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.330215677
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1589925949
Short name T810
Test name
Test status
Simulation time 533228466 ps
CPU time 7.04 seconds
Started Jul 21 05:36:48 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 222500 kb
Host smart-5ed70572-a9bd-46bf-8145-d75461bb4cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589925949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1589925949
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3472529588
Short name T356
Test name
Test status
Simulation time 106987431 ps
CPU time 2.01 seconds
Started Jul 21 05:36:44 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 207272 kb
Host smart-d380553e-18ce-427a-8a6c-3bdf2e098e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472529588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3472529588
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4100949544
Short name T99
Test name
Test status
Simulation time 542584760 ps
CPU time 7.35 seconds
Started Jul 21 05:36:44 PM PDT 24
Finished Jul 21 05:36:52 PM PDT 24
Peak memory 208932 kb
Host smart-10984fa0-447e-4234-a59c-c05c62375fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100949544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4100949544
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1665670396
Short name T487
Test name
Test status
Simulation time 35023676 ps
CPU time 2.42 seconds
Started Jul 21 05:36:46 PM PDT 24
Finished Jul 21 05:36:49 PM PDT 24
Peak memory 215352 kb
Host smart-a49c0505-97d3-46d8-9b67-2c84da92b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665670396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1665670396
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1776704093
Short name T764
Test name
Test status
Simulation time 372691651 ps
CPU time 4.64 seconds
Started Jul 21 05:36:46 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 213976 kb
Host smart-4f2b1d73-c896-4ed0-bf1d-b252fb59d88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776704093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1776704093
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1326505660
Short name T694
Test name
Test status
Simulation time 346005281 ps
CPU time 3.73 seconds
Started Jul 21 05:36:48 PM PDT 24
Finished Jul 21 05:36:52 PM PDT 24
Peak memory 208044 kb
Host smart-8c8354ad-d9d8-49a9-885f-67db519bd1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326505660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1326505660
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2490872500
Short name T808
Test name
Test status
Simulation time 201882521 ps
CPU time 2.89 seconds
Started Jul 21 05:36:48 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 206768 kb
Host smart-c13ae161-b22e-4c39-8740-0716d5c59f26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490872500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2490872500
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.842873078
Short name T605
Test name
Test status
Simulation time 4309752522 ps
CPU time 22.97 seconds
Started Jul 21 05:36:46 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 208116 kb
Host smart-eb2862ff-34ad-4b57-a129-faab8e3ce33a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842873078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.842873078
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1625023797
Short name T786
Test name
Test status
Simulation time 452734071 ps
CPU time 3.98 seconds
Started Jul 21 05:36:44 PM PDT 24
Finished Jul 21 05:36:49 PM PDT 24
Peak memory 208744 kb
Host smart-0863b46c-37c6-4f1c-aad4-b787e36313b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625023797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1625023797
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3797586219
Short name T592
Test name
Test status
Simulation time 372350514 ps
CPU time 4.02 seconds
Started Jul 21 05:36:47 PM PDT 24
Finished Jul 21 05:36:52 PM PDT 24
Peak memory 215616 kb
Host smart-3b18c327-80bf-4137-9376-0cf304918edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797586219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3797586219
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1679889874
Short name T419
Test name
Test status
Simulation time 65932579 ps
CPU time 2.87 seconds
Started Jul 21 05:36:44 PM PDT 24
Finished Jul 21 05:36:47 PM PDT 24
Peak memory 206808 kb
Host smart-31a728b0-c4a8-414b-9dd7-5e65b13fe858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679889874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1679889874
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.488768444
Short name T126
Test name
Test status
Simulation time 587209546 ps
CPU time 12.63 seconds
Started Jul 21 05:36:43 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 222320 kb
Host smart-b5fe2de5-23d6-491b-80c1-7303635ade93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488768444 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.488768444
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.916938222
Short name T540
Test name
Test status
Simulation time 1840537318 ps
CPU time 22.09 seconds
Started Jul 21 05:36:47 PM PDT 24
Finished Jul 21 05:37:10 PM PDT 24
Peak memory 208820 kb
Host smart-6d8b9b9f-66a8-4e2c-b880-4fdfebfca8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916938222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.916938222
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3821080612
Short name T457
Test name
Test status
Simulation time 128003635 ps
CPU time 2.69 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 210552 kb
Host smart-70f4d66a-bcca-47e3-8943-b0994a1a5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821080612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3821080612
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1088803078
Short name T1
Test name
Test status
Simulation time 69811228 ps
CPU time 0.81 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:54 PM PDT 24
Peak memory 205772 kb
Host smart-6464aed2-81d4-434e-931a-cce165371d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088803078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1088803078
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1112797919
Short name T315
Test name
Test status
Simulation time 35588656 ps
CPU time 2.8 seconds
Started Jul 21 05:36:52 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 214904 kb
Host smart-167cd389-d859-46cc-87bf-155e7859272c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112797919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1112797919
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2288798373
Short name T546
Test name
Test status
Simulation time 151652420 ps
CPU time 2.4 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:56 PM PDT 24
Peak memory 221916 kb
Host smart-163971a4-5a0c-4342-9cd2-c13bcf53e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288798373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2288798373
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3189969079
Short name T791
Test name
Test status
Simulation time 335533129 ps
CPU time 4.24 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:58 PM PDT 24
Peak memory 209220 kb
Host smart-316ddcd7-8699-4daa-939c-7d58a4761084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189969079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3189969079
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.185056898
Short name T341
Test name
Test status
Simulation time 4436302331 ps
CPU time 8.72 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:54 PM PDT 24
Peak memory 220640 kb
Host smart-cfa0a1fc-1d91-4aaf-aa96-97d6d9bd1ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185056898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.185056898
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.327799853
Short name T364
Test name
Test status
Simulation time 250796932 ps
CPU time 3.81 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:57 PM PDT 24
Peak memory 214036 kb
Host smart-186a0569-d093-463a-bbcc-a5f89da773b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327799853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.327799853
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3926133246
Short name T106
Test name
Test status
Simulation time 794822049 ps
CPU time 1.97 seconds
Started Jul 21 05:36:45 PM PDT 24
Finished Jul 21 05:36:48 PM PDT 24
Peak memory 205876 kb
Host smart-e7e87490-12c0-4cbf-981b-c8f20d9b5c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926133246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3926133246
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2448388848
Short name T452
Test name
Test status
Simulation time 729951373 ps
CPU time 23.09 seconds
Started Jul 21 05:36:47 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 208512 kb
Host smart-8f1d1c39-185a-414f-acf0-6cb4c2e7c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448388848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2448388848
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2407461921
Short name T707
Test name
Test status
Simulation time 2759563612 ps
CPU time 19.09 seconds
Started Jul 21 05:36:54 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 208788 kb
Host smart-2a2810c8-597b-464a-a573-042199fbe9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407461921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2407461921
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1594739235
Short name T549
Test name
Test status
Simulation time 370461451 ps
CPU time 5.76 seconds
Started Jul 21 05:36:48 PM PDT 24
Finished Jul 21 05:36:55 PM PDT 24
Peak memory 207956 kb
Host smart-15c08f7f-f0c5-4dc0-a140-df4b82cbc7d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594739235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1594739235
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3213521292
Short name T4
Test name
Test status
Simulation time 237061462 ps
CPU time 5.22 seconds
Started Jul 21 05:36:46 PM PDT 24
Finished Jul 21 05:36:51 PM PDT 24
Peak memory 206656 kb
Host smart-9bd7b0ff-5ef2-4d1d-9eb8-fa0cb5752d7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213521292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3213521292
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1609961347
Short name T507
Test name
Test status
Simulation time 884184901 ps
CPU time 7.21 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:37:01 PM PDT 24
Peak memory 208116 kb
Host smart-d8f1d29b-c06f-442e-9442-79d9b4056f27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609961347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1609961347
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.4258009685
Short name T799
Test name
Test status
Simulation time 117181177 ps
CPU time 2.07 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:36:55 PM PDT 24
Peak memory 209476 kb
Host smart-2c8431ad-b2c5-416d-9e72-eadbf03749d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258009685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4258009685
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3737298917
Short name T483
Test name
Test status
Simulation time 2302405639 ps
CPU time 17.69 seconds
Started Jul 21 05:36:47 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 207648 kb
Host smart-fff6491b-a604-4d90-848d-9933a53a8288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737298917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3737298917
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2872646843
Short name T274
Test name
Test status
Simulation time 574903630 ps
CPU time 25.54 seconds
Started Jul 21 05:36:53 PM PDT 24
Finished Jul 21 05:37:20 PM PDT 24
Peak memory 222268 kb
Host smart-a14074be-bf43-4fc4-8fd9-f6eaa57d696f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872646843 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2872646843
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.657930769
Short name T293
Test name
Test status
Simulation time 313809738 ps
CPU time 10.81 seconds
Started Jul 21 05:36:43 PM PDT 24
Finished Jul 21 05:36:55 PM PDT 24
Peak memory 214088 kb
Host smart-7981a303-d945-4cd2-9756-d6239ac68ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657930769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.657930769
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3149695391
Short name T190
Test name
Test status
Simulation time 137867361 ps
CPU time 3.24 seconds
Started Jul 21 05:36:56 PM PDT 24
Finished Jul 21 05:37:00 PM PDT 24
Peak memory 209800 kb
Host smart-a4c5015e-0bdc-44b9-a5bd-a43b1fc3a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149695391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3149695391
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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