Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4884

1

T1

4

T2

3

T4

3

auto[1]

569

1

T4

5

T5

1

T18

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4884

1

T1

4

T2

3

T4

3

auto[1]

569

1

T4

5

T5

1

T18

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4889

1

T1

4

T2

3

T4

8

auto[1]

564

1

T5

1

T18

1

T27

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4889

1

T1

4

T2

3

T4

8

auto[1]

564

1

T5

1

T18

1

T27

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T15	1		T18	1		T88	1
auto[OpGenId]	1196	1			T2	1		T15	1		T16	2
auto[OpGenSwOut]	1141	1			T1	1		T2	1		T5	1
auto[OpGenHwOut]	2641	1			T1	3		T2	1		T4	8
auto[OpDisable]	80	1			T49	1		T50	1		T28	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T15	1		T18	1		T88	1
auto[OpGenId]	1196	1			T2	1		T15	1		T16	2
auto[OpGenSwOut]	1141	1			T1	1		T2	1		T5	1
auto[OpGenHwOut]	2641	1			T1	3		T2	1		T4	8
auto[OpDisable]	80	1			T49	1		T50	1		T28	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4902

1

T1

3

T2

3

T4

8

auto[1]

551

1

T1

1

T16

1

T35

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4902

1

T1

3

T2

3

T4

8

auto[1]

551

1

T1

1

T16

1

T35

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5181

1

T1

4

T2

3

T4

8

auto[1]

272

1

T129

10

T130

14

T151

10

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1869	1			T1	1		T2	1		T4	1
auto[1]	710	1			T1	1		T16	1		T35	2
auto[2]	690	1			T2	1		T4	1		T18	1
auto[3]	711	1			T4	4		T15	1		T35	2
auto[4]	374	1			T1	1		T4	1		T35	1
auto[5]	320	1			T35	1		T27	2		T49	2
auto[6]	389	1			T17	1		T89	1		T222	1
auto[7]	390	1			T1	1		T2	1		T4	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1473	1			T1	2		T2	1		T4	2
clear_one[1]	710	1			T1	1		T16	1		T35	2
clear_one[2]	690	1			T2	1		T4	1		T18	1
clear_one[3]	711	1			T4	4		T15	1		T35	2
clear_none	1869	1			T1	1		T2	1		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1037	1			T2	3		T17	2		T35	5
auto[StInit]	661	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	564	1			T1	1		T4	1		T18	1
auto[StOwnerIntKey]	524	1			T4	1		T5	1		T18	1
auto[StOwnerKey]	474	1			T4	1		T18	1		T35	1
auto[StDisabled]	1906	1			T1	2		T4	4		T16	1
auto[StInvalid]	287	1			T15	3		T17	3		T37	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1037	1			T2	3		T17	2		T35	5
auto[StInit]	661	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	564	1			T1	1		T4	1		T18	1
auto[StOwnerIntKey]	524	1			T4	1		T5	1		T18	1
auto[StOwnerKey]	474	1			T4	1		T18	1		T35	1
auto[StDisabled]	1906	1			T1	2		T4	4		T16	1
auto[StInvalid]	287	1			T15	3		T17	3		T37	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled] , auto[StInvalid]]	[auto[OpDisable]]	--	--	6
[auto[5] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[5] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[5] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[5] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T129	2		T266	1		T267	1
auto[0]	auto[StReset]	auto[OpGenId]	171	1			T2	1		T27	1		T88	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	155	1			T17	2		T88	1		T37	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T35	1		T89	2		T90	1
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T130	1		T151	1		T7	1
auto[0]	auto[StInit]	auto[OpGenId]	103	1			T16	1		T19	1		T59	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	110	1			T1	1		T5	1		T18	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	176	1			T4	1		T49	1		T55	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T62	1		T26	1		T268	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	42	1			T47	1		T229	1		T269	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	57	1			T129	1		T28	2		T85	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	73	1			T164	1		T149	1		T270	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T271	1		T64	1		T212	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T163	1		T223	1		T272	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	27	1			T62	2		T234	1		T273	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T5	1		T28	1		T65	2
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T129	1		T65	1		T274	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T234	1		T70	1		T275	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T7	1		T276	1		T213	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	53	1			T18	1		T83	1		T84	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T130	3		T225	2		T277	1
auto[0]	auto[StDisabled]	auto[OpGenId]	71	1			T163	1		T151	2		T7	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T151	2		T62	1		T74	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T90	1		T149	1		T28	4
auto[0]	auto[StDisabled]	auto[OpDisable]	25	1			T50	1		T28	1		T7	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T15	1		T278	1		T279	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T17	1		T99	1		T97	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T15	1		T96	1		T91	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T24	1		T99	1		T280	1
auto[1]	auto[StReset]	auto[OpAdvance]	2	1			T281	2		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	10	1			T39	1		T282	1		T283	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	26	1			T59	1		T72	1		T230	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	45	1			T35	2		T89	1		T226	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T212	1		T78	1		T284	1
auto[1]	auto[StInit]	auto[OpGenId]	11	1			T83	1		T147	2		T285	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T28	1		T48	1		T95	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T286	1		T287	1		T288	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T289	1		T290	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T65	1		T291	1		T138	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T124	1		T292	1		T206	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T89	1		T82	1		T293	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T85	1		T269	1		T7	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T62	1		T26	1		T212	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T62	1		T294	1		T70	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T239	1		T228	1		T295	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T296	1		T297	1		T78	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	23	1			T28	1		T116	1		T70	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T224	1		T8	1		T277	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T87	1		T62	1		T298	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	30	1			T223	1		T269	1		T62	1
auto[1]	auto[StDisabled]	auto[OpGenId]	64	1			T16	1		T88	1		T62	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T88	2		T224	1		T299	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T1	1		T89	1		T270	1
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T234	1		T75	1		T68	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T300	1		T301	1		T302	2
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T38	1		T99	1		T280	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T38	1		T279	1		T303	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T38	1		T92	1		T280	1
auto[2]	auto[StReset]	auto[OpGenId]	28	1			T165	1		T59	1		T230	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	13	1			T59	1		T70	1		T105	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	54	1			T2	1		T304	1		T99	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T88	1		T225	1		T26	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T65	1		T305	1		T213	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	3	1			T306	1		T307	1		T308	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T35	1		T89	1		T90	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T8	1		T309	1		T310	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T236	1		T311	1		T147	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T28	1		T312	1		T313	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T18	1		T35	1		T240	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T265	1		T310	1		T254	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T87	1		T62	1		T64	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T59	1		T62	1		T70	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T35	1		T304	1		T314	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T315	1		T8	1		T124	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T152	1		T65	1		T238	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T316	1		T139	1		T264	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T225	1		T239	1		T236	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T152	1		T62	1		T235	1
auto[2]	auto[StDisabled]	auto[OpGenId]	61	1			T50	1		T222	1		T28	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T152	1		T224	1		T7	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T4	1		T35	2		T88	1
auto[2]	auto[StDisabled]	auto[OpDisable]	13	1			T70	1		T137	1		T80	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T93	1		T317	1		T318	1
auto[2]	auto[StInvalid]	auto[OpGenId]	8	1			T37	1		T39	1		T96	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T94	1		T271	1		T297	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T37	1		T282	1		T271	1
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T234	1		T105	1		T64	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T7	1		T111	1		T116	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T35	1		T90	1		T165	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T212	1		T78	1		T107	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T299	1		T70	2		T64	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	5	1			T319	1		T100	1		T103	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T293	1		T320	1		T64	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T321	1		T267	1		-	-
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T105	1		T208	1		T264	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T7	1		T70	1		T322	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T4	1		T90	1		T222	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T151	1		T292	1		T120	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T152	2		T238	1		T323	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T49	1		T62	1		T7	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T4	1		T90	1		T164	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T324	1		T68	1		T325	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T62	1		T65	2		T71	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T151	3		T72	1		T326	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T35	1		T149	1		T270	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T225	1		T235	1		T147	1
auto[3]	auto[StDisabled]	auto[OpGenId]	56	1			T164	1		T59	1		T83	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T222	1		T150	1		T83	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	174	1			T4	2		T27	1		T89	2
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T327	1		T70	1		T212	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T111	1		T328	1		T282	1
auto[3]	auto[StInvalid]	auto[OpGenId]	22	1			T15	1		T39	1		T93	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T329	1		T330	1		T331	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T332	1		T278	1		T333	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T38	1		T62	1		T99	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T299	1		T62	1		T7	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	28	1			T89	2		T299	1		T334	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T335	1		T336	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	11	1			T62	2		T70	1		T120	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T7	1		T25	1		T243	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T165	1		T304	1		T234	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T337	1		T338	1		T120	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	1	1			T200	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T232	1		T62	1		T137	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T84	1		T314	1		T339	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T340	1		T341	1		T342	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T63	1		T70	1		T105	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T28	1		T70	1		T343	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T344	1		T345	1		T346	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T70	1		T347	1		T348	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T312	1		T349	1		T350	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T28	1		T7	1		T212	2
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T62	1		T26	1		T144	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T230	1		T7	1		T154	1
auto[4]	auto[StDisabled]	auto[OpGenId]	34	1			T55	1		T229	1		T299	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T62	1		T7	1		T154	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T1	1		T4	1		T35	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T51	1		T94	1		T332	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T95	1		T271	1		T92	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T37	1		T39	1		T351	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T99	1		T94	1		T328	1
auto[5]	auto[StReset]	auto[OpGenId]	3	1			T7	1		T31	1		T257	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	5	1			T27	1		T83	1		T212	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T62	1		T10	1		T288	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T352	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T353	1		T33	1		T354	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T137	1		T355	2		T356	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T237	1		T7	1		T25	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T139	1		T357	1		T358	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T359	1		T264	1		T360	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T361	1		T362	1		T363	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T27	1		T70	1		T52	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T364	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T72	1		T365	1		T366	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T299	1		T64	1		T367	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	11	1			T298	1		T368	1		T369	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T242	1		T263	1		T370	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	2	1			T64	1		T371	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T28	1		T229	1		T154	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T89	1		T90	1		T372	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T238	1		T296	1		T276	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T49	1		T7	1		T268	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T163	1		T164	1		T154	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T35	1		T149	1		T240	2
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T49	1		T76	1		T373	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T38	1		T24	1		T143	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T279	1		T374	1		T375	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T94	1		T376	1		T377	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T97	2		T282	1		T98	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T7	1		T378	1		T264	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T379	1		T116	1		T205	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	28	1			T62	1		T7	1		T304	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T380	1		T381	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T28	1		T297	1		T321	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T102	1		T382	1		T259	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	16	1			T224	1		T295	1		T8	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T238	1		T68	1		T254	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T130	2		T65	1		T323	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T323	1		T383	1		T263	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T130	3		T155	1		T304	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T130	2		T68	1		T247	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T222	1		T154	1		T384	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T285	1		T385	1		T373	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T89	1		T130	1		T28	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T62	1		T276	1		T264	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T130	1		T70	1		T205	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T386	1		T247	1		T387	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T8	1		T146	1		T314	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T62	1		T7	1		T233	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T130	1		T150	1		T87	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T130	1		T151	1		T62	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	95	1			T130	2		T270	1		T239	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T70	1		T77	1		T264	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T280	1		T388	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T96	1		T99	1		T282	2
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T39	1		T24	1		T271	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T17	1		T96	2		T95	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T88	1		T147	1		T78	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T2	1		T237	1		T138	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	30	1			T35	1		T48	1		T294	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T389	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T21	1		T76	1		T390	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T7	1		T111	1		T102	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	17	1			T144	1		T391	1		T392	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T393	2		T394	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T294	1		T234	1		T349	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T83	1		T72	1		T62	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T1	1		T334	1		T146	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T18	1		T151	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T155	1		T124	1		T395	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T28	1		T155	1		T8	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T149	1		T240	1		T293	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	14	1			T294	1		T64	2		T68	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T223	1		T155	1		T396	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T4	1		T27	1		T62	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	7	1			T292	1		T213	1		T266	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T129	1		T131	1		T230	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T129	5		T150	1		T72	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T89	1		T129	3		T84	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T28	1		T216	1		T70	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T329	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T17	1		T51	1		T99	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T99	1		T97	1		T280	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T143	1		T332	1		T329	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1473

1

T1

2

T2

1

T4

2

clear_one[1]

auto[0]

auto[0]

auto[0]

406

1

T35

2

T89

1

T226

1

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T1

1

T16

1

T28

2

clear_one[1]

auto[0]

auto[1]

auto[0]

117

1

T89

2

T82

1

T72

1

clear_one[1]

auto[0]

auto[1]

auto[1]

58

1

T88

3

T87

1

T62

2

clear_one[2]

auto[0]

auto[0]

auto[0]

407

1

T2

1

T35

1

T88

1

clear_one[2]

auto[0]

auto[0]

auto[1]

111

1

T35

4

T88

1

T225

1

clear_one[2]

auto[1]

auto[0]

auto[0]

135

1

T4

1

T18

1

T50

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T28

1

T83

1

T152

4

clear_one[3]

auto[0]

auto[0]

auto[0]

403

1

T15

1

T35

2

T90

1

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T89

2

T90

2

T149

2

clear_one[3]

auto[1]

auto[0]

auto[0]

138

1

T4

4

T49

1

T164

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T27

1

T62

1

T7

1

clear_none

auto[0]

auto[0]

auto[0]

1367

1

T1

1

T2

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

123

1

T164

1

T28

2

T151

3

clear_none

auto[0]

auto[1]

auto[0]

131

1

T90

1

T149

2

T28

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T28

1

T151

2

T62

1

clear_none

auto[1]

auto[0]

auto[0]

124

1

T50

1

T47

1

T270

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T83

1

T152

1

T7

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T5

1

T18

1

T62

1

clear_none

auto[1]

auto[1]

auto[1]

28

1

T28

1

T62

1

T65

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1374	1			T1	2		T2	1		T4	2
clear_all	auto[1]	99	1			T129	7		T130	11		T151	1
clear_one[1]	auto[0]	671	1			T1	1		T16	1		T35	2
clear_one[1]	auto[1]	39	1			T269	2		T154	1		T147	1
clear_one[2]	auto[0]	661	1			T2	1		T4	1		T18	1
clear_one[2]	auto[1]	29	1			T152	3		T235	6		T380	1
clear_one[3]	auto[0]	689	1			T4	4		T15	1		T35	2
clear_one[3]	auto[1]	22	1			T151	4		T152	3		T235	7
clear_none	auto[0]	1786	1			T1	1		T2	1		T4	1
clear_none	auto[1]	83	1			T129	3		T130	3		T151	5