Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11400

1

T1

4

T2

9

T4

6

auto[Attestation]

7974

1

T1

4

T4

2

T5

10

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2839	1			T1	1		T2	1		T5	2
auto[Aes]	3417	1			T2	2		T4	8		T5	5
auto[Kmac]	3438	1			T1	2		T2	3		T5	3
auto[Otbn]	3489	1			T1	3		T2	2		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7914	1			T1	8		T2	1		T4	8
auto[OpGenId]	6191	1			T1	2		T2	1		T5	4
auto[OpGenSwOut]	6010	1			T1	2		T2	6		T5	5
auto[OpGenHwOut]	7173	1			T1	4		T2	2		T4	8
auto[OpDisable]	153	1			T16	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10976

1

T1

8

T2

1

T4

8

auto[OpDoneFail]

16465

1

T1

8

T2

9

T4

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6663	1			T1	1		T2	10		T4	1
auto[StInit]	3761	1			T1	2		T4	2		T5	4
auto[StCreatorRootKey]	3338	1			T1	2		T4	2		T5	6
auto[StOwnerIntKey]	2867	1			T1	2		T4	2		T5	8
auto[StOwnerKey]	2495	1			T1	2		T4	2		T6	2
auto[StDisabled]	8317	1			T1	7		T4	7		T6	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	312	1			T2	1		T6	1		T34	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T1	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T221	1		T222	1		T62	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T6	1		T28	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T28	1		T62	1		T154	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	242	1			T27	1		T88	1		T164	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T2	1		T6	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	92	1			T5	1		T39	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	67	1			T18	1		T50	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T166	1		T222	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	46	1			T151	1		T224	1		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	200	1			T6	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	298	1			T2	2		T17	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	95	1			T5	1		T34	1		T226	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T49	1		T227	1		T223	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T129	1		T82	1		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T151	1		T7	2		T228	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	205	1			T34	1		T27	2		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	308	1			T2	2		T6	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	83	1			T49	1		T163	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T5	1		T88	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T49	1		T130	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	65	1			T18	1		T34	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	242	1			T88	1		T221	1		T130	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	85	1			T62	4		T7	3		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T17	2		T28	2		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	113	1			T5	1		T18	1		T165	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T129	1		T165	1		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T27	1		T150	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	214	1			T18	3		T34	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	91	1			T62	6		T7	4		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T72	1		T229	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T34	1		T27	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	70	1			T59	1		T28	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T221	1		T28	1		T231	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	217	1			T18	1		T88	1		T164	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T62	2		T7	2		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T16	1		T131	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T28	1		T232	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T49	1		T28	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T233	1		T141	1		T234	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	233	1			T18	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	93	1			T62	3		T7	2		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T222	1		T46	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T27	1		T55	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T1	1		T5	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	52	1			T7	1		T71	1		T235	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	247	1			T16	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T17	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	87	1			T49	1		T47	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T27	1		T165	1		T150	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T5	1		T88	1		T164	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T223	1		T62	1		T236	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	195	1			T18	1		T88	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	521	1			T2	1		T88	1		T163	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T4	1		T27	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	113	1			T47	1		T237	1		T7	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T4	1		T49	1		T165	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	76	1			T4	1		T223	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	279	1			T4	3		T18	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	461	1			T2	1		T17	2		T89	13
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T49	1		T89	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T1	1		T89	1		T165	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T89	1		T165	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	90	1			T89	1		T130	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	319	1			T18	1		T88	1		T89	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	533	1			T35	16		T88	1		T163	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	106	1			T35	1		T165	2		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T35	1		T88	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T35	1		T130	1		T82	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T88	1		T28	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	294	1			T1	1		T18	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T62	8		T7	1		T65	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	87	1			T16	1		T164	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T152	1		T72	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T16	1		T88	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T27	1		T223	1		T238	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	174	1			T27	1		T163	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T62	2		T65	2		T8	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T55	1		T86	1		T239	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	113	1			T4	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	104	1			T5	3		T16	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T18	1		T164	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	302	1			T4	1		T163	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	46	1			T62	1		T7	1		T65	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T30	1		T59	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T18	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T5	2		T90	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T18	1		T27	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	276	1			T1	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T62	1		T7	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T222	1		T87	1		T240	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	125	1			T16	1		T164	1		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T16	1		T226	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	82	1			T35	1		T87	1		T240	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	270	1			T1	1		T35	3		T222	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T6	1		T221	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	679	1			T1	1		T2	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T50	1		T166	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	631	1			T2	1		T5	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	225	1			T49	1		T129	1		T227	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	621	1			T2	2		T5	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T5	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	652	1			T2	2		T6	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	227	1			T5	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	415	1			T17	2		T18	3		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	214	1			T34	1		T27	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	421	1			T18	1		T88	1		T164	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	212	1			T49	1		T28	2		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	447	1			T16	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T1	1		T5	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	463	1			T16	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T5	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	601	1			T17	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	258	1			T4	2		T49	1		T165	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	928	1			T2	1		T4	4		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	299	1			T1	1		T89	3		T165	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	926	1			T2	1		T17	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T35	2		T88	2		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	944	1			T1	1		T18	1		T35	18
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	187	1			T16	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	342	1			T16	1		T27	1		T163	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	298	1			T4	1		T5	4		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	484	1			T4	1		T163	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	263	1			T5	2		T18	2		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	445	1			T1	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T16	2		T35	1		T164	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	456	1			T1	1		T35	3		T222	2