Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33617

1

T1

21

T2

10

T4

23

auto[1]

284

1

T129

13

T130

5

T131

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33625	1			T1	21		T2	10		T4	23
auto[134217728:268435455]	7	1			T152	1		T415	1		T371	1
auto[268435456:402653183]	9	1			T151	1		T155	1		T235	1
auto[402653184:536870911]	11	1			T129	1		T380	1		T292	1
auto[536870912:671088639]	7	1			T131	1		T269	1		T349	1
auto[671088640:805306367]	5	1			T151	1		T235	1		T371	1
auto[805306368:939524095]	3	1			T129	1		T155	1		T416	1
auto[939524096:1073741823]	12	1			T152	1		T155	1		T349	1
auto[1073741824:1207959551]	11	1			T129	1		T152	1		T269	1
auto[1207959552:1342177279]	6	1			T130	1		T235	1		T380	1
auto[1342177280:1476395007]	13	1			T131	1		T152	1		T155	1
auto[1476395008:1610612735]	12	1			T130	1		T235	1		T147	1
auto[1610612736:1744830463]	5	1			T349	1		T371	1		T417	1
auto[1744830464:1879048191]	13	1			T152	1		T147	1		T371	1
auto[1879048192:2013265919]	13	1			T155	1		T380	1		T292	1
auto[2013265920:2147483647]	7	1			T154	1		T235	3		T390	2
auto[2147483648:2281701375]	10	1			T129	1		T206	1		T371	1
auto[2281701376:2415919103]	3	1			T206	1		T390	1		T389	1
auto[2415919104:2550136831]	8	1			T151	1		T152	1		T154	1
auto[2550136832:2684354559]	14	1			T129	3		T130	1		T131	1
auto[2684354560:2818572287]	11	1			T131	1		T151	1		T230	1
auto[2818572288:2952790015]	9	1			T151	1		T230	1		T154	1
auto[2952790016:3087007743]	9	1			T130	1		T147	1		T266	1
auto[3087007744:3221225471]	9	1			T147	1		T418	1		T419	1
auto[3221225472:3355443199]	14	1			T129	1		T154	1		T155	1
auto[3355443200:3489660927]	5	1			T129	1		T151	1		T361	1
auto[3489660928:3623878655]	5	1			T151	1		T371	2		T420	1
auto[3623878656:3758096383]	7	1			T130	1		T152	3		T419	1
auto[3758096384:3892314111]	7	1			T380	2		T292	1		T421	1
auto[3892314112:4026531839]	9	1			T129	1		T380	1		T273	1
auto[4026531840:4160749567]	9	1			T129	1		T152	1		T273	1
auto[4160749568:4294967295]	13	1			T129	1		T147	1		T361	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33617	1			T1	21		T2	10		T4	23
auto[0:134217727]	auto[1]	8	1			T129	1		T147	1		T292	1
auto[134217728:268435455]	auto[1]	7	1			T152	1		T415	1		T371	1
auto[268435456:402653183]	auto[1]	9	1			T151	1		T155	1		T235	1
auto[402653184:536870911]	auto[1]	11	1			T129	1		T380	1		T292	1
auto[536870912:671088639]	auto[1]	7	1			T131	1		T269	1		T349	1
auto[671088640:805306367]	auto[1]	5	1			T151	1		T235	1		T371	1
auto[805306368:939524095]	auto[1]	3	1			T129	1		T155	1		T416	1
auto[939524096:1073741823]	auto[1]	12	1			T152	1		T155	1		T349	1
auto[1073741824:1207959551]	auto[1]	11	1			T129	1		T152	1		T269	1
auto[1207959552:1342177279]	auto[1]	6	1			T130	1		T235	1		T380	1
auto[1342177280:1476395007]	auto[1]	13	1			T131	1		T152	1		T155	1
auto[1476395008:1610612735]	auto[1]	12	1			T130	1		T235	1		T147	1
auto[1610612736:1744830463]	auto[1]	5	1			T349	1		T371	1		T417	1
auto[1744830464:1879048191]	auto[1]	13	1			T152	1		T147	1		T371	1
auto[1879048192:2013265919]	auto[1]	13	1			T155	1		T380	1		T292	1
auto[2013265920:2147483647]	auto[1]	7	1			T154	1		T235	3		T390	2
auto[2147483648:2281701375]	auto[1]	10	1			T129	1		T206	1		T371	1
auto[2281701376:2415919103]	auto[1]	3	1			T206	1		T390	1		T389	1
auto[2415919104:2550136831]	auto[1]	8	1			T151	1		T152	1		T154	1
auto[2550136832:2684354559]	auto[1]	14	1			T129	3		T130	1		T131	1
auto[2684354560:2818572287]	auto[1]	11	1			T131	1		T151	1		T230	1
auto[2818572288:2952790015]	auto[1]	9	1			T151	1		T230	1		T154	1
auto[2952790016:3087007743]	auto[1]	9	1			T130	1		T147	1		T266	1
auto[3087007744:3221225471]	auto[1]	9	1			T147	1		T418	1		T419	1
auto[3221225472:3355443199]	auto[1]	14	1			T129	1		T154	1		T155	1
auto[3355443200:3489660927]	auto[1]	5	1			T129	1		T151	1		T361	1
auto[3489660928:3623878655]	auto[1]	5	1			T151	1		T371	2		T420	1
auto[3623878656:3758096383]	auto[1]	7	1			T130	1		T152	3		T419	1
auto[3758096384:3892314111]	auto[1]	7	1			T380	2		T292	1		T421	1
auto[3892314112:4026531839]	auto[1]	9	1			T129	1		T380	1		T273	1
auto[4026531840:4160749567]	auto[1]	9	1			T129	1		T152	1		T273	1
auto[4160749568:4294967295]	auto[1]	13	1			T129	1		T147	1		T361	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1523

1

T2

6

T15

4

T17

3

auto[1]

1777

1

T2

2

T5

2

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T18	1		T49	1		T130	1
auto[134217728:268435455]	82	1			T17	1		T18	1		T62	1
auto[268435456:402653183]	101	1			T2	1		T18	1		T28	1
auto[402653184:536870911]	108	1			T2	1		T15	1		T88	1
auto[536870912:671088639]	93	1			T51	1		T150	1		T28	2
auto[671088640:805306367]	108	1			T15	1		T17	1		T36	1
auto[805306368:939524095]	106	1			T2	1		T88	1		T37	1
auto[939524096:1073741823]	100	1			T28	1		T152	1		T62	1
auto[1073741824:1207959551]	108	1			T88	1		T49	1		T165	1
auto[1207959552:1342177279]	93	1			T2	2		T5	1		T18	1
auto[1342177280:1476395007]	99	1			T50	1		T85	1		T86	1
auto[1476395008:1610612735]	111	1			T226	1		T131	1		T28	1
auto[1610612736:1744830463]	101	1			T18	1		T59	1		T39	1
auto[1744830464:1879048191]	107	1			T20	1		T38	2		T86	1
auto[1879048192:2013265919]	118	1			T2	1		T15	1		T88	2
auto[2013265920:2147483647]	95	1			T2	2		T50	1		T38	1
auto[2147483648:2281701375]	118	1			T88	1		T59	1		T38	1
auto[2281701376:2415919103]	91	1			T16	1		T27	1		T36	1
auto[2415919104:2550136831]	99	1			T17	2		T19	1		T51	1
auto[2550136832:2684354559]	103	1			T129	1		T37	2		T222	1
auto[2684354560:2818572287]	94	1			T165	1		T38	1		T87	1
auto[2818572288:2952790015]	102	1			T18	1		T88	1		T165	1
auto[2952790016:3087007743]	101	1			T131	1		T47	1		T232	1
auto[3087007744:3221225471]	112	1			T5	1		T15	1		T17	1
auto[3221225472:3355443199]	118	1			T18	1		T27	1		T39	3
auto[3355443200:3489660927]	95	1			T47	1		T86	1		T230	1
auto[3489660928:3623878655]	101	1			T130	1		T150	1		T152	1
auto[3623878656:3758096383]	110	1			T47	1		T39	1		T28	1
auto[3758096384:3892314111]	112	1			T88	1		T130	1		T150	1
auto[3892314112:4026531839]	99	1			T165	1		T30	1		T222	1
auto[4026531840:4160749567]	112	1			T130	1		T38	1		T39	1
auto[4160749568:4294967295]	102	1			T222	1		T150	1		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T39	1		T153	1		T7	1
auto[0:134217727]	auto[1]	62	1			T18	1		T49	1		T130	1
auto[134217728:268435455]	auto[0]	38	1			T17	1		T7	1		T10	1
auto[134217728:268435455]	auto[1]	44	1			T18	1		T62	1		T235	1
auto[268435456:402653183]	auto[0]	45	1			T2	1		T28	1		T225	1
auto[268435456:402653183]	auto[1]	56	1			T18	1		T224	1		T7	2
auto[402653184:536870911]	auto[0]	53	1			T2	1		T15	1		T88	1
auto[402653184:536870911]	auto[1]	55	1			T87	1		T72	1		T62	1
auto[536870912:671088639]	auto[0]	41	1			T28	2		T62	1		T7	1
auto[536870912:671088639]	auto[1]	52	1			T51	1		T150	1		T87	1
auto[671088640:805306367]	auto[0]	45	1			T15	1		T59	1		T316	1
auto[671088640:805306367]	auto[1]	63	1			T17	1		T36	1		T222	1
auto[805306368:939524095]	auto[0]	49	1			T2	1		T88	1		T37	1
auto[805306368:939524095]	auto[1]	57	1			T225	1		T232	1		T230	2
auto[939524096:1073741823]	auto[0]	51	1			T62	1		T7	1		T93	2
auto[939524096:1073741823]	auto[1]	49	1			T28	1		T152	1		T7	2
auto[1073741824:1207959551]	auto[0]	49	1			T88	1		T165	1		T46	1
auto[1073741824:1207959551]	auto[1]	59	1			T49	1		T59	1		T152	1
auto[1207959552:1342177279]	auto[0]	47	1			T2	2		T130	1		T29	2
auto[1207959552:1342177279]	auto[1]	46	1			T5	1		T18	1		T51	1
auto[1342177280:1476395007]	auto[0]	37	1			T225	1		T62	2		T379	1
auto[1342177280:1476395007]	auto[1]	62	1			T50	1		T85	1		T86	1
auto[1476395008:1610612735]	auto[0]	50	1			T226	1		T28	1		T48	1
auto[1476395008:1610612735]	auto[1]	61	1			T131	1		T48	1		T224	1
auto[1610612736:1744830463]	auto[0]	45	1			T59	1		T39	1		T86	2
auto[1610612736:1744830463]	auto[1]	56	1			T18	1		T7	1		T422	1
auto[1744830464:1879048191]	auto[0]	48	1			T20	1		T38	1		T86	1
auto[1744830464:1879048191]	auto[1]	59	1			T38	1		T72	2		T62	1
auto[1879048192:2013265919]	auto[0]	48	1			T15	1		T88	1		T131	1
auto[1879048192:2013265919]	auto[1]	70	1			T2	1		T88	1		T51	1
auto[2013265920:2147483647]	auto[0]	43	1			T2	1		T38	1		T218	1
auto[2013265920:2147483647]	auto[1]	52	1			T2	1		T50	1		T96	1
auto[2147483648:2281701375]	auto[0]	46	1			T88	1		T59	1		T82	1
auto[2147483648:2281701375]	auto[1]	72	1			T38	1		T72	1		T269	1
auto[2281701376:2415919103]	auto[0]	51	1			T27	1		T129	1		T131	1
auto[2281701376:2415919103]	auto[1]	40	1			T16	1		T36	1		T28	1
auto[2415919104:2550136831]	auto[0]	42	1			T17	2		T59	1		T28	2
auto[2415919104:2550136831]	auto[1]	57	1			T19	1		T51	1		T82	1
auto[2550136832:2684354559]	auto[0]	50	1			T129	1		T37	1		T222	1
auto[2550136832:2684354559]	auto[1]	53	1			T37	1		T131	1		T59	1
auto[2684354560:2818572287]	auto[0]	45	1			T165	1		T38	1		T225	1
auto[2684354560:2818572287]	auto[1]	49	1			T87	1		T153	1		T62	2
auto[2818572288:2952790015]	auto[0]	44	1			T88	1		T37	1		T226	1
auto[2818572288:2952790015]	auto[1]	58	1			T18	1		T165	1		T151	1
auto[2952790016:3087007743]	auto[0]	49	1			T232	1		T62	1		T7	1
auto[2952790016:3087007743]	auto[1]	52	1			T131	1		T47	1		T230	1
auto[3087007744:3221225471]	auto[0]	58	1			T15	1		T165	1		T37	1
auto[3087007744:3221225471]	auto[1]	54	1			T5	1		T17	1		T18	1
auto[3221225472:3355443199]	auto[0]	51	1			T27	1		T39	2		T28	1
auto[3221225472:3355443199]	auto[1]	67	1			T18	1		T39	1		T7	1
auto[3355443200:3489660927]	auto[0]	45	1			T47	1		T86	1		T319	1
auto[3355443200:3489660927]	auto[1]	50	1			T230	1		T62	1		T95	1
auto[3489660928:3623878655]	auto[0]	46	1			T150	1		T72	1		T153	1
auto[3489660928:3623878655]	auto[1]	55	1			T130	1		T152	1		T72	1
auto[3623878656:3758096383]	auto[0]	60	1			T47	1		T39	1		T224	1
auto[3623878656:3758096383]	auto[1]	50	1			T28	1		T7	1		T26	1
auto[3758096384:3892314111]	auto[0]	55	1			T29	1		T28	1		T225	1
auto[3758096384:3892314111]	auto[1]	57	1			T88	1		T130	1		T150	1
auto[3892314112:4026531839]	auto[0]	42	1			T87	1		T224	1		T72	1
auto[3892314112:4026531839]	auto[1]	57	1			T165	1		T30	1		T222	1
auto[4026531840:4160749567]	auto[0]	61	1			T130	1		T38	1		T39	1
auto[4026531840:4160749567]	auto[1]	51	1			T269	1		T62	1		T7	1
auto[4160749568:4294967295]	auto[0]	50	1			T222	1		T38	1		T48	1
auto[4160749568:4294967295]	auto[1]	52	1			T150	1		T47	1		T62	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1512

1

T2

7

T15

4

T17

3

auto[1]

1787

1

T2

1

T5

2

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T18	1		T20	1		T59	1
auto[134217728:268435455]	96	1			T37	1		T48	2		T85	1
auto[268435456:402653183]	96	1			T2	1		T165	1		T55	1
auto[402653184:536870911]	104	1			T165	1		T86	1		T72	1
auto[536870912:671088639]	117	1			T15	1		T50	1		T59	1
auto[671088640:805306367]	79	1			T18	1		T165	1		T226	1
auto[805306368:939524095]	104	1			T18	1		T165	1		T59	1
auto[939524096:1073741823]	125	1			T18	1		T150	1		T47	1
auto[1073741824:1207959551]	100	1			T2	1		T27	1		T88	1
auto[1207959552:1342177279]	123	1			T88	1		T222	1		T151	1
auto[1342177280:1476395007]	105	1			T88	1		T222	2		T130	2
auto[1476395008:1610612735]	103	1			T18	1		T27	1		T55	1
auto[1610612736:1744830463]	102	1			T17	1		T51	1		T29	1
auto[1744830464:1879048191]	99	1			T16	1		T152	1		T223	1
auto[1879048192:2013265919]	109	1			T17	1		T88	1		T30	1
auto[2013265920:2147483647]	108	1			T2	1		T17	1		T50	1
auto[2147483648:2281701375]	105	1			T129	1		T226	1		T38	1
auto[2281701376:2415919103]	106	1			T165	1		T39	1		T28	1
auto[2415919104:2550136831]	94	1			T88	1		T39	1		T152	1
auto[2550136832:2684354559]	107	1			T5	2		T15	1		T18	2
auto[2684354560:2818572287]	117	1			T17	1		T49	1		T59	1
auto[2818572288:2952790015]	116	1			T36	1		T51	1		T38	2
auto[2952790016:3087007743]	112	1			T18	1		T130	1		T131	1
auto[3087007744:3221225471]	94	1			T2	1		T226	1		T131	1
auto[3221225472:3355443199]	92	1			T15	1		T88	1		T28	3
auto[3355443200:3489660927]	115	1			T88	1		T131	1		T38	1
auto[3489660928:3623878655]	92	1			T150	2		T39	1		T28	3
auto[3623878656:3758096383]	91	1			T2	1		T150	1		T28	2
auto[3758096384:3892314111]	107	1			T2	1		T37	1		T131	1
auto[3892314112:4026531839]	88	1			T15	1		T17	1		T37	1
auto[4026531840:4160749567]	98	1			T2	1		T19	1		T39	1
auto[4160749568:4294967295]	91	1			T2	1		T88	1		T37	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T20	1		T39	1		T29	2
auto[0:134217727]	auto[1]	60	1			T18	1		T59	1		T28	1
auto[134217728:268435455]	auto[0]	49	1			T37	1		T48	1		T224	1
auto[134217728:268435455]	auto[1]	47	1			T48	1		T85	1		T225	1
auto[268435456:402653183]	auto[0]	45	1			T2	1		T55	1		T28	1
auto[268435456:402653183]	auto[1]	51	1			T165	1		T272	1		T62	1
auto[402653184:536870911]	auto[0]	43	1			T165	1		T86	1		T225	1
auto[402653184:536870911]	auto[1]	61	1			T72	1		T230	1		T7	1
auto[536870912:671088639]	auto[0]	43	1			T15	1		T59	1		T31	1
auto[536870912:671088639]	auto[1]	74	1			T50	1		T82	1		T230	1
auto[671088640:805306367]	auto[0]	34	1			T165	1		T130	1		T86	1
auto[671088640:805306367]	auto[1]	45	1			T18	1		T226	1		T62	1
auto[805306368:939524095]	auto[0]	54	1			T165	1		T59	1		T39	1
auto[805306368:939524095]	auto[1]	50	1			T18	1		T38	1		T224	1
auto[939524096:1073741823]	auto[0]	61	1			T47	1		T38	1		T86	1
auto[939524096:1073741823]	auto[1]	64	1			T18	1		T150	1		T224	2
auto[1073741824:1207959551]	auto[0]	54	1			T27	1		T88	1		T37	1
auto[1073741824:1207959551]	auto[1]	46	1			T2	1		T49	1		T36	1
auto[1207959552:1342177279]	auto[0]	48	1			T88	1		T62	1		T7	1
auto[1207959552:1342177279]	auto[1]	75	1			T222	1		T151	1		T62	1
auto[1342177280:1476395007]	auto[0]	41	1			T88	1		T62	1		T422	1
auto[1342177280:1476395007]	auto[1]	64	1			T222	2		T130	2		T131	1
auto[1476395008:1610612735]	auto[0]	52	1			T27	1		T47	1		T48	1
auto[1476395008:1610612735]	auto[1]	51	1			T18	1		T55	1		T51	1
auto[1610612736:1744830463]	auto[0]	40	1			T17	1		T86	1		T237	1
auto[1610612736:1744830463]	auto[1]	62	1			T51	1		T29	1		T152	1
auto[1744830464:1879048191]	auto[0]	35	1			T223	1		T62	1		T7	2
auto[1744830464:1879048191]	auto[1]	64	1			T16	1		T152	1		T269	1
auto[1879048192:2013265919]	auto[0]	46	1			T88	1		T38	1		T62	1
auto[1879048192:2013265919]	auto[1]	63	1			T17	1		T30	1		T87	1
auto[2013265920:2147483647]	auto[0]	52	1			T2	1		T28	1		T62	2
auto[2013265920:2147483647]	auto[1]	56	1			T17	1		T50	1		T130	1
auto[2147483648:2281701375]	auto[0]	47	1			T129	1		T226	1		T39	1
auto[2147483648:2281701375]	auto[1]	58	1			T38	1		T269	1		T62	1
auto[2281701376:2415919103]	auto[0]	57	1			T39	1		T48	1		T86	1
auto[2281701376:2415919103]	auto[1]	49	1			T165	1		T28	1		T72	1
auto[2415919104:2550136831]	auto[0]	46	1			T88	1		T39	1		T232	1
auto[2415919104:2550136831]	auto[1]	48	1			T152	1		T62	1		T154	1
auto[2550136832:2684354559]	auto[0]	57	1			T15	1		T46	1		T51	1
auto[2550136832:2684354559]	auto[1]	50	1			T5	2		T18	2		T87	1
auto[2684354560:2818572287]	auto[0]	57	1			T17	1		T153	1		T62	1
auto[2684354560:2818572287]	auto[1]	60	1			T49	1		T59	1		T38	1
auto[2818572288:2952790015]	auto[0]	50	1			T38	2		T28	1		T82	1
auto[2818572288:2952790015]	auto[1]	66	1			T36	1		T51	1		T62	1
auto[2952790016:3087007743]	auto[0]	56	1			T82	1		T62	2		T155	1
auto[2952790016:3087007743]	auto[1]	56	1			T18	1		T130	1		T131	1
auto[3087007744:3221225471]	auto[0]	43	1			T2	1		T226	1		T47	1
auto[3087007744:3221225471]	auto[1]	51	1			T131	1		T59	1		T62	2
auto[3221225472:3355443199]	auto[0]	40	1			T15	1		T88	1		T28	3
auto[3221225472:3355443199]	auto[1]	52	1			T224	1		T154	1		T74	1
auto[3355443200:3489660927]	auto[0]	56	1			T131	1		T38	1		T237	1
auto[3355443200:3489660927]	auto[1]	59	1			T88	1		T28	1		T230	1
auto[3489660928:3623878655]	auto[0]	36	1			T39	1		T28	1		T7	2
auto[3489660928:3623878655]	auto[1]	56	1			T150	2		T28	2		T223	1
auto[3623878656:3758096383]	auto[0]	45	1			T2	1		T28	1		T7	2
auto[3623878656:3758096383]	auto[1]	46	1			T150	1		T28	1		T223	1
auto[3758096384:3892314111]	auto[0]	49	1			T2	1		T37	1		T59	1
auto[3758096384:3892314111]	auto[1]	58	1			T131	1		T269	1		T7	1
auto[3892314112:4026531839]	auto[0]	45	1			T15	1		T17	1		T37	1
auto[3892314112:4026531839]	auto[1]	43	1			T51	1		T86	1		T62	3
auto[4026531840:4160749567]	auto[0]	42	1			T2	1		T39	1		T48	1
auto[4026531840:4160749567]	auto[1]	56	1			T19	1		T224	1		T72	1
auto[4160749568:4294967295]	auto[0]	45	1			T2	1		T88	1		T37	1
auto[4160749568:4294967295]	auto[1]	46	1			T93	1		T111	1		T309	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T2

7

T15

4

T17

4

auto[1]

1741

1

T2

1

T5

2

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T15	1		T17	1		T88	1
auto[134217728:268435455]	94	1			T5	1		T36	1		T47	2
auto[268435456:402653183]	107	1			T20	1		T39	1		T224	1
auto[402653184:536870911]	101	1			T5	1		T18	1		T37	1
auto[536870912:671088639]	120	1			T16	1		T129	1		T130	1
auto[671088640:805306367]	99	1			T165	1		T131	1		T59	1
auto[805306368:939524095]	100	1			T2	1		T222	1		T130	1
auto[939524096:1073741823]	94	1			T2	1		T17	1		T39	1
auto[1073741824:1207959551]	82	1			T2	1		T18	1		T222	1
auto[1207959552:1342177279]	110	1			T18	1		T88	3		T19	1
auto[1342177280:1476395007]	109	1			T17	1		T88	1		T150	1
auto[1476395008:1610612735]	99	1			T2	1		T39	1		T48	1
auto[1610612736:1744830463]	104	1			T18	1		T49	1		T50	1
auto[1744830464:1879048191]	113	1			T30	1		T59	1		T28	3
auto[1879048192:2013265919]	98	1			T165	1		T37	1		T28	1
auto[2013265920:2147483647]	106	1			T15	1		T88	1		T165	1
auto[2147483648:2281701375]	107	1			T37	1		T38	3		T39	1
auto[2281701376:2415919103]	104	1			T2	1		T27	1		T49	1
auto[2415919104:2550136831]	104	1			T15	1		T165	1		T226	1
auto[2550136832:2684354559]	96	1			T18	2		T88	1		T62	1
auto[2684354560:2818572287]	94	1			T165	1		T237	1		T224	1
auto[2818572288:2952790015]	105	1			T17	1		T153	1		T7	3
auto[2952790016:3087007743]	112	1			T226	1		T28	1		T86	1
auto[3087007744:3221225471]	108	1			T2	1		T27	1		T28	1
auto[3221225472:3355443199]	110	1			T130	1		T51	1		T29	1
auto[3355443200:3489660927]	128	1			T15	1		T17	1		T88	1
auto[3489660928:3623878655]	97	1			T36	1		T226	1		T28	2
auto[3623878656:3758096383]	87	1			T222	1		T55	1		T51	1
auto[3758096384:3892314111]	97	1			T2	1		T18	1		T222	1
auto[3892314112:4026531839]	108	1			T18	1		T50	1		T51	1
auto[4026531840:4160749567]	98	1			T55	1		T39	1		T28	1
auto[4160749568:4294967295]	106	1			T2	1		T46	1		T59	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T15	1		T17	1		T88	1
auto[0:134217727]	auto[1]	48	1			T225	1		T154	1		T155	1
auto[134217728:268435455]	auto[0]	39	1			T47	2		T28	1		T48	1
auto[134217728:268435455]	auto[1]	55	1			T5	1		T36	1		T269	1
auto[268435456:402653183]	auto[0]	56	1			T20	1		T39	1		T224	1
auto[268435456:402653183]	auto[1]	51	1			T8	1		T234	2		T70	3
auto[402653184:536870911]	auto[0]	44	1			T37	1		T59	1		T38	1
auto[402653184:536870911]	auto[1]	57	1			T5	1		T18	1		T59	1
auto[536870912:671088639]	auto[0]	56	1			T129	1		T39	1		T28	1
auto[536870912:671088639]	auto[1]	64	1			T16	1		T130	1		T51	1
auto[671088640:805306367]	auto[0]	49	1			T59	1		T153	1		T232	1
auto[671088640:805306367]	auto[1]	50	1			T165	1		T131	1		T72	1
auto[805306368:939524095]	auto[0]	54	1			T2	1		T222	1		T38	1
auto[805306368:939524095]	auto[1]	46	1			T130	1		T47	1		T72	2
auto[939524096:1073741823]	auto[0]	49	1			T39	1		T10	1		T96	1
auto[939524096:1073741823]	auto[1]	45	1			T2	1		T17	1		T72	1
auto[1073741824:1207959551]	auto[0]	37	1			T2	1		T39	1		T86	1
auto[1073741824:1207959551]	auto[1]	45	1			T18	1		T222	1		T235	1
auto[1207959552:1342177279]	auto[0]	47	1			T18	1		T88	2		T37	2
auto[1207959552:1342177279]	auto[1]	63	1			T88	1		T19	1		T51	1
auto[1342177280:1476395007]	auto[0]	58	1			T17	1		T88	1		T39	1
auto[1342177280:1476395007]	auto[1]	51	1			T150	1		T47	1		T223	1
auto[1476395008:1610612735]	auto[0]	55	1			T2	1		T39	1		T48	1
auto[1476395008:1610612735]	auto[1]	44	1			T87	2		T224	1		T230	1
auto[1610612736:1744830463]	auto[0]	58	1			T38	1		T62	2		T7	2
auto[1610612736:1744830463]	auto[1]	46	1			T18	1		T49	1		T50	1
auto[1744830464:1879048191]	auto[0]	51	1			T59	1		T28	2		T224	1
auto[1744830464:1879048191]	auto[1]	62	1			T30	1		T28	1		T151	1
auto[1879048192:2013265919]	auto[0]	40	1			T165	1		T28	1		T62	1
auto[1879048192:2013265919]	auto[1]	58	1			T37	1		T152	1		T72	1
auto[2013265920:2147483647]	auto[0]	51	1			T15	1		T88	1		T165	1
auto[2013265920:2147483647]	auto[1]	55	1			T130	1		T315	1		T233	1
auto[2147483648:2281701375]	auto[0]	54	1			T37	1		T38	2		T39	1
auto[2147483648:2281701375]	auto[1]	53	1			T38	1		T223	2		T62	1
auto[2281701376:2415919103]	auto[0]	44	1			T2	1		T27	1		T130	1
auto[2281701376:2415919103]	auto[1]	60	1			T49	1		T82	2		T62	2
auto[2415919104:2550136831]	auto[0]	54	1			T15	1		T226	1		T28	1
auto[2415919104:2550136831]	auto[1]	50	1			T165	1		T7	1		T65	3
auto[2550136832:2684354559]	auto[0]	46	1			T422	1		T24	1		T111	1
auto[2550136832:2684354559]	auto[1]	50	1			T18	2		T88	1		T62	1
auto[2684354560:2818572287]	auto[0]	43	1			T165	1		T237	1		T7	1
auto[2684354560:2818572287]	auto[1]	51	1			T224	1		T62	2		T7	2
auto[2818572288:2952790015]	auto[0]	49	1			T17	1		T153	1		T218	1
auto[2818572288:2952790015]	auto[1]	56	1			T7	3		T58	1		T63	1
auto[2952790016:3087007743]	auto[0]	54	1			T226	1		T28	1		T86	1
auto[2952790016:3087007743]	auto[1]	58	1			T224	2		T72	1		T62	1
auto[3087007744:3221225471]	auto[0]	57	1			T2	1		T27	1		T7	2
auto[3087007744:3221225471]	auto[1]	51	1			T28	1		T96	1		T91	1
auto[3221225472:3355443199]	auto[0]	47	1			T130	1		T151	1		T153	1
auto[3221225472:3355443199]	auto[1]	63	1			T51	1		T29	1		T48	1
auto[3355443200:3489660927]	auto[0]	56	1			T15	1		T17	1		T131	1
auto[3355443200:3489660927]	auto[1]	72	1			T88	1		T129	1		T28	1
auto[3489660928:3623878655]	auto[0]	40	1			T28	1		T62	1		T379	1
auto[3489660928:3623878655]	auto[1]	57	1			T36	1		T226	1		T28	1
auto[3623878656:3758096383]	auto[0]	39	1			T222	1		T55	1		T51	1
auto[3623878656:3758096383]	auto[1]	48	1			T62	1		T100	1		T277	1
auto[3758096384:3892314111]	auto[0]	46	1			T2	1		T131	1		T29	1
auto[3758096384:3892314111]	auto[1]	51	1			T18	1		T222	1		T131	1
auto[3892314112:4026531839]	auto[0]	46	1			T50	1		T29	1		T28	1
auto[3892314112:4026531839]	auto[1]	62	1			T18	1		T51	1		T131	1
auto[4026531840:4160749567]	auto[0]	40	1			T55	1		T39	1		T65	1
auto[4026531840:4160749567]	auto[1]	58	1			T28	1		T151	1		T62	2
auto[4160749568:4294967295]	auto[0]	45	1			T2	1		T46	1		T59	1
auto[4160749568:4294967295]	auto[1]	61	1			T59	1		T38	1		T223	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1540

1

T2

7

T15

4

T17

3

auto[1]

1759

1

T2

1

T5

2

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T5	1		T27	1		T46	1
auto[134217728:268435455]	95	1			T88	1		T37	1		T47	1
auto[268435456:402653183]	94	1			T20	1		T37	1		T86	1
auto[402653184:536870911]	100	1			T15	1		T18	1		T88	1
auto[536870912:671088639]	100	1			T15	1		T49	1		T37	1
auto[671088640:805306367]	112	1			T18	1		T47	1		T38	1
auto[805306368:939524095]	104	1			T30	1		T51	1		T38	1
auto[939524096:1073741823]	105	1			T88	2		T50	1		T130	1
auto[1073741824:1207959551]	111	1			T2	1		T222	1		T28	1
auto[1207959552:1342177279]	101	1			T17	1		T37	1		T222	1
auto[1342177280:1476395007]	109	1			T130	1		T28	1		T225	1
auto[1476395008:1610612735]	117	1			T17	1		T59	1		T150	2
auto[1610612736:1744830463]	111	1			T16	1		T222	1		T47	1
auto[1744830464:1879048191]	103	1			T17	1		T18	1		T223	1
auto[1879048192:2013265919]	91	1			T18	1		T88	1		T29	1
auto[2013265920:2147483647]	99	1			T18	1		T50	1		T129	1
auto[2147483648:2281701375]	113	1			T15	1		T165	1		T131	1
auto[2281701376:2415919103]	95	1			T51	2		T150	1		T38	2
auto[2415919104:2550136831]	88	1			T2	2		T18	1		T55	1
auto[2550136832:2684354559]	106	1			T5	1		T39	1		T28	1
auto[2684354560:2818572287]	96	1			T2	1		T225	1		T153	2
auto[2818572288:2952790015]	120	1			T15	1		T18	1		T165	1
auto[2952790016:3087007743]	100	1			T17	1		T18	1		T27	1
auto[3087007744:3221225471]	95	1			T19	1		T36	1		T39	2
auto[3221225472:3355443199]	118	1			T2	2		T165	1		T150	1
auto[3355443200:3489660927]	112	1			T17	1		T88	1		T131	1
auto[3489660928:3623878655]	100	1			T129	1		T222	1		T59	1
auto[3623878656:3758096383]	90	1			T130	1		T59	1		T28	1
auto[3758096384:3892314111]	110	1			T2	1		T226	1		T131	1
auto[3892314112:4026531839]	101	1			T2	1		T88	1		T130	1
auto[4026531840:4160749567]	128	1			T165	1		T37	1		T51	1
auto[4160749568:4294967295]	64	1			T88	1		T36	1		T165	1