Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2930

1

T2

5

T5

2

T15

4

auto[1]

245

1

T129

8

T130

7

T131

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T2	1		T50	1		T59	1
auto[134217728:268435455]	85	1			T222	2		T130	1		T38	1
auto[268435456:402653183]	108	1			T15	1		T17	2		T165	1
auto[402653184:536870911]	112	1			T5	1		T129	1		T130	2
auto[536870912:671088639]	111	1			T2	1		T165	2		T38	1
auto[671088640:805306367]	107	1			T17	1		T18	2		T88	1
auto[805306368:939524095]	94	1			T17	1		T36	1		T165	1
auto[939524096:1073741823]	95	1			T37	1		T150	1		T38	1
auto[1073741824:1207959551]	106	1			T18	1		T88	1		T129	1
auto[1207959552:1342177279]	96	1			T2	1		T222	1		T59	1
auto[1342177280:1476395007]	93	1			T18	1		T129	1		T226	1
auto[1476395008:1610612735]	76	1			T18	1		T37	2		T131	1
auto[1610612736:1744830463]	108	1			T55	1		T51	1		T38	1
auto[1744830464:1879048191]	100	1			T27	1		T237	1		T232	1
auto[1879048192:2013265919]	99	1			T129	2		T39	1		T28	2
auto[2013265920:2147483647]	117	1			T15	1		T130	1		T39	1
auto[2147483648:2281701375]	91	1			T18	1		T88	1		T49	1
auto[2281701376:2415919103]	98	1			T27	1		T129	2		T55	1
auto[2415919104:2550136831]	102	1			T129	1		T131	1		T39	1
auto[2550136832:2684354559]	94	1			T47	1		T38	1		T72	2
auto[2684354560:2818572287]	96	1			T2	1		T130	1		T59	1
auto[2818572288:2952790015]	85	1			T18	1		T39	1		T28	1
auto[2952790016:3087007743]	91	1			T130	1		T47	1		T151	1
auto[3087007744:3221225471]	106	1			T129	1		T37	1		T222	1
auto[3221225472:3355443199]	86	1			T18	1		T88	1		T19	1
auto[3355443200:3489660927]	106	1			T17	1		T88	1		T48	1
auto[3489660928:3623878655]	104	1			T5	1		T16	1		T50	1
auto[3623878656:3758096383]	97	1			T15	1		T150	1		T151	1
auto[3758096384:3892314111]	104	1			T15	1		T88	2		T226	1
auto[3892314112:4026531839]	104	1			T2	1		T88	1		T226	1
auto[4026531840:4160749567]	100	1			T59	1		T28	1		T225	1
auto[4160749568:4294967295]	111	1			T130	1		T39	1		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T2	1		T50	1		T59	1
auto[0:134217727]	auto[1]	8	1			T154	1		T390	1		T393	1
auto[134217728:268435455]	auto[0]	78	1			T222	2		T130	1		T38	1
auto[134217728:268435455]	auto[1]	7	1			T152	1		T273	1		T207	1
auto[268435456:402653183]	auto[0]	96	1			T15	1		T17	2		T165	1
auto[268435456:402653183]	auto[1]	12	1			T130	2		T131	1		T380	1
auto[402653184:536870911]	auto[0]	104	1			T5	1		T130	2		T28	1
auto[402653184:536870911]	auto[1]	8	1			T129	1		T238	1		T415	1
auto[536870912:671088639]	auto[0]	104	1			T2	1		T165	2		T38	1
auto[536870912:671088639]	auto[1]	7	1			T235	1		T323	1		T273	1
auto[671088640:805306367]	auto[0]	100	1			T17	1		T18	2		T88	1
auto[671088640:805306367]	auto[1]	7	1			T152	1		T380	1		T371	1
auto[805306368:939524095]	auto[0]	86	1			T17	1		T36	1		T165	1
auto[805306368:939524095]	auto[1]	8	1			T269	1		T147	1		T349	1
auto[939524096:1073741823]	auto[0]	88	1			T37	1		T150	1		T38	1
auto[939524096:1073741823]	auto[1]	7	1			T151	1		T155	1		T147	1
auto[1073741824:1207959551]	auto[0]	93	1			T18	1		T88	1		T165	1
auto[1073741824:1207959551]	auto[1]	13	1			T129	1		T151	1		T152	1
auto[1207959552:1342177279]	auto[0]	87	1			T2	1		T222	1		T59	1
auto[1207959552:1342177279]	auto[1]	9	1			T235	2		T418	2		T419	1
auto[1342177280:1476395007]	auto[0]	88	1			T18	1		T129	1		T226	1
auto[1342177280:1476395007]	auto[1]	5	1			T371	2		T420	1		T417	1
auto[1476395008:1610612735]	auto[0]	71	1			T18	1		T37	2		T39	1
auto[1476395008:1610612735]	auto[1]	5	1			T131	1		T151	1		T371	1
auto[1610612736:1744830463]	auto[0]	104	1			T55	1		T51	1		T38	1
auto[1610612736:1744830463]	auto[1]	4	1			T269	1		T361	1		T419	1
auto[1744830464:1879048191]	auto[0]	93	1			T27	1		T237	1		T232	1
auto[1744830464:1879048191]	auto[1]	7	1			T273	1		T361	1		T266	1
auto[1879048192:2013265919]	auto[0]	95	1			T39	1		T28	2		T82	1
auto[1879048192:2013265919]	auto[1]	4	1			T129	2		T431	1		T432	1
auto[2013265920:2147483647]	auto[0]	111	1			T15	1		T39	1		T29	1
auto[2013265920:2147483647]	auto[1]	6	1			T130	1		T147	1		T349	1
auto[2147483648:2281701375]	auto[0]	83	1			T18	1		T88	1		T49	1
auto[2147483648:2281701375]	auto[1]	8	1			T129	1		T130	1		T154	1
auto[2281701376:2415919103]	auto[0]	91	1			T27	1		T129	1		T55	1
auto[2281701376:2415919103]	auto[1]	7	1			T129	1		T147	1		T380	1
auto[2415919104:2550136831]	auto[0]	91	1			T131	1		T39	1		T87	1
auto[2415919104:2550136831]	auto[1]	11	1			T129	1		T152	1		T269	1
auto[2550136832:2684354559]	auto[0]	89	1			T47	1		T38	1		T72	2
auto[2550136832:2684354559]	auto[1]	5	1			T238	1		T427	1		T390	1
auto[2684354560:2818572287]	auto[0]	89	1			T2	1		T59	1		T39	1
auto[2684354560:2818572287]	auto[1]	7	1			T130	1		T235	1		T419	1
auto[2818572288:2952790015]	auto[0]	78	1			T18	1		T39	1		T28	1
auto[2818572288:2952790015]	auto[1]	7	1			T152	1		T390	1		T393	1
auto[2952790016:3087007743]	auto[0]	79	1			T47	1		T72	1		T225	1
auto[2952790016:3087007743]	auto[1]	12	1			T130	1		T151	1		T155	2
auto[3087007744:3221225471]	auto[0]	96	1			T37	1		T222	1		T51	1
auto[3087007744:3221225471]	auto[1]	10	1			T129	1		T155	1		T421	1
auto[3221225472:3355443199]	auto[0]	81	1			T18	1		T88	1		T19	1
auto[3221225472:3355443199]	auto[1]	5	1			T155	1		T235	1		T266	1
auto[3355443200:3489660927]	auto[0]	98	1			T17	1		T88	1		T48	1
auto[3355443200:3489660927]	auto[1]	8	1			T235	1		T276	1		T266	1
auto[3489660928:3623878655]	auto[0]	92	1			T5	1		T16	1		T50	1
auto[3489660928:3623878655]	auto[1]	12	1			T151	1		T152	1		T154	1
auto[3623878656:3758096383]	auto[0]	91	1			T15	1		T150	1		T152	1
auto[3623878656:3758096383]	auto[1]	6	1			T151	1		T310	1		T371	1
auto[3758096384:3892314111]	auto[0]	98	1			T15	1		T88	2		T226	1
auto[3758096384:3892314111]	auto[1]	6	1			T130	1		T276	1		T427	1
auto[3892314112:4026531839]	auto[0]	95	1			T2	1		T88	1		T226	1
auto[3892314112:4026531839]	auto[1]	9	1			T154	1		T235	1		T380	1
auto[4026531840:4160749567]	auto[0]	92	1			T59	1		T28	1		T225	1
auto[4026531840:4160749567]	auto[1]	8	1			T155	1		T380	1		T349	1
auto[4160749568:4294967295]	auto[0]	104	1			T130	1		T39	1		T28	1
auto[4160749568:4294967295]	auto[1]	7	1			T427	2		T390	1		T431	1