Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.07 98.43 100.00 99.11 98.41 91.14


Total test records in report: 1086
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T1010 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3237533334 Jul 22 06:10:47 PM PDT 24 Jul 22 06:10:49 PM PDT 24 76185208 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3170219291 Jul 22 06:10:37 PM PDT 24 Jul 22 06:10:43 PM PDT 24 723231105 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3954595987 Jul 22 06:10:32 PM PDT 24 Jul 22 06:10:35 PM PDT 24 150781485 ps
T1013 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3859279983 Jul 22 06:10:35 PM PDT 24 Jul 22 06:10:47 PM PDT 24 1419467078 ps
T1014 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1875200481 Jul 22 06:12:38 PM PDT 24 Jul 22 06:12:39 PM PDT 24 10369572 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.362028503 Jul 22 06:10:44 PM PDT 24 Jul 22 06:10:47 PM PDT 24 716510713 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1202417951 Jul 22 06:10:54 PM PDT 24 Jul 22 06:10:59 PM PDT 24 918269630 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.948316128 Jul 22 06:10:47 PM PDT 24 Jul 22 06:10:50 PM PDT 24 330739229 ps
T1018 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1493343984 Jul 22 06:11:56 PM PDT 24 Jul 22 06:11:57 PM PDT 24 22313052 ps
T1019 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1786703161 Jul 22 06:11:21 PM PDT 24 Jul 22 06:11:22 PM PDT 24 34789133 ps
T1020 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.904686996 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:53 PM PDT 24 323719673 ps
T1021 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.814347097 Jul 22 06:13:46 PM PDT 24 Jul 22 06:13:47 PM PDT 24 51130453 ps
T182 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3713594974 Jul 22 06:10:27 PM PDT 24 Jul 22 06:10:34 PM PDT 24 205885283 ps
T1022 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.605085226 Jul 22 06:10:47 PM PDT 24 Jul 22 06:10:49 PM PDT 24 22069509 ps
T1023 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3115523928 Jul 22 06:13:44 PM PDT 24 Jul 22 06:13:46 PM PDT 24 14868214 ps
T1024 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1278014096 Jul 22 06:11:02 PM PDT 24 Jul 22 06:11:04 PM PDT 24 28407975 ps
T1025 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2669278075 Jul 22 06:11:05 PM PDT 24 Jul 22 06:11:06 PM PDT 24 26988216 ps
T1026 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1682453440 Jul 22 06:13:45 PM PDT 24 Jul 22 06:13:47 PM PDT 24 15011508 ps
T185 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2701764026 Jul 22 06:10:53 PM PDT 24 Jul 22 06:11:00 PM PDT 24 838979045 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3133927394 Jul 22 06:10:45 PM PDT 24 Jul 22 06:10:46 PM PDT 24 66463960 ps
T1028 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.565147460 Jul 22 06:10:35 PM PDT 24 Jul 22 06:10:39 PM PDT 24 88656324 ps
T181 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.551053208 Jul 22 06:13:33 PM PDT 24 Jul 22 06:13:38 PM PDT 24 104619258 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4081425214 Jul 22 06:10:39 PM PDT 24 Jul 22 06:10:41 PM PDT 24 21898262 ps
T1030 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3484290099 Jul 22 06:10:52 PM PDT 24 Jul 22 06:10:54 PM PDT 24 47483549 ps
T1031 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2056594547 Jul 22 06:10:38 PM PDT 24 Jul 22 06:10:39 PM PDT 24 54197075 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3787612426 Jul 22 06:11:49 PM PDT 24 Jul 22 06:11:51 PM PDT 24 23509262 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1961644542 Jul 22 06:10:42 PM PDT 24 Jul 22 06:10:44 PM PDT 24 22405727 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.837257189 Jul 22 06:10:39 PM PDT 24 Jul 22 06:10:41 PM PDT 24 554899482 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1050413483 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:52 PM PDT 24 40755135 ps
T1036 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3669188678 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:55 PM PDT 24 757053942 ps
T1037 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.640597049 Jul 22 06:10:55 PM PDT 24 Jul 22 06:10:57 PM PDT 24 24983238 ps
T1038 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3484776487 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:50 PM PDT 24 98697462 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2153464274 Jul 22 06:11:41 PM PDT 24 Jul 22 06:11:44 PM PDT 24 47224163 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1096309300 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:53 PM PDT 24 26012790 ps
T1041 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2538519980 Jul 22 06:11:02 PM PDT 24 Jul 22 06:11:04 PM PDT 24 22650130 ps
T184 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3598950767 Jul 22 06:10:50 PM PDT 24 Jul 22 06:10:55 PM PDT 24 1025949947 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2432477483 Jul 22 06:10:34 PM PDT 24 Jul 22 06:10:35 PM PDT 24 19762905 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2843796605 Jul 22 06:10:24 PM PDT 24 Jul 22 06:10:26 PM PDT 24 64265272 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.877874216 Jul 22 06:10:36 PM PDT 24 Jul 22 06:10:44 PM PDT 24 123426909 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.441716686 Jul 22 06:10:34 PM PDT 24 Jul 22 06:10:42 PM PDT 24 280869063 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3680387041 Jul 22 06:11:49 PM PDT 24 Jul 22 06:11:51 PM PDT 24 23793927 ps
T1047 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.494786123 Jul 22 06:10:48 PM PDT 24 Jul 22 06:10:53 PM PDT 24 640424552 ps
T1048 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2056584719 Jul 22 06:13:23 PM PDT 24 Jul 22 06:13:25 PM PDT 24 19672845 ps
T1049 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3459586347 Jul 22 06:13:46 PM PDT 24 Jul 22 06:13:47 PM PDT 24 38594033 ps
T1050 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4031270372 Jul 22 06:11:02 PM PDT 24 Jul 22 06:11:04 PM PDT 24 27178968 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3249481634 Jul 22 06:10:40 PM PDT 24 Jul 22 06:10:43 PM PDT 24 63019159 ps
T1052 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1256619306 Jul 22 06:10:45 PM PDT 24 Jul 22 06:10:51 PM PDT 24 86534570 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1783841184 Jul 22 06:10:54 PM PDT 24 Jul 22 06:10:56 PM PDT 24 11813145 ps
T1054 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1624222432 Jul 22 06:11:02 PM PDT 24 Jul 22 06:11:04 PM PDT 24 66010932 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3598329446 Jul 22 06:10:43 PM PDT 24 Jul 22 06:10:44 PM PDT 24 8136516 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.246456415 Jul 22 06:10:36 PM PDT 24 Jul 22 06:10:39 PM PDT 24 59530553 ps
T1057 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2734648206 Jul 22 06:11:00 PM PDT 24 Jul 22 06:11:02 PM PDT 24 51823349 ps
T197 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3660186536 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:54 PM PDT 24 1031302908 ps
T1058 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1472590419 Jul 22 06:10:36 PM PDT 24 Jul 22 06:10:40 PM PDT 24 149741724 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1043030371 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:53 PM PDT 24 32099379 ps
T1060 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.145973493 Jul 22 06:11:00 PM PDT 24 Jul 22 06:11:01 PM PDT 24 24442541 ps
T1061 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1230323527 Jul 22 06:11:02 PM PDT 24 Jul 22 06:11:04 PM PDT 24 11712298 ps
T1062 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.626430442 Jul 22 06:11:05 PM PDT 24 Jul 22 06:11:06 PM PDT 24 10113687 ps
T1063 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1839129925 Jul 22 06:11:03 PM PDT 24 Jul 22 06:11:04 PM PDT 24 38399883 ps
T1064 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2595164732 Jul 22 06:10:51 PM PDT 24 Jul 22 06:10:52 PM PDT 24 16879236 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1558100137 Jul 22 06:10:30 PM PDT 24 Jul 22 06:10:32 PM PDT 24 57616123 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1518013851 Jul 22 06:10:46 PM PDT 24 Jul 22 06:10:47 PM PDT 24 20735231 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2564648236 Jul 22 06:12:19 PM PDT 24 Jul 22 06:12:21 PM PDT 24 33392491 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2024885656 Jul 22 06:10:35 PM PDT 24 Jul 22 06:10:37 PM PDT 24 43604424 ps
T1069 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2297605321 Jul 22 06:10:50 PM PDT 24 Jul 22 06:10:52 PM PDT 24 54224191 ps
T1070 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2052966150 Jul 22 06:10:53 PM PDT 24 Jul 22 06:10:57 PM PDT 24 41862514 ps
T180 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2552131392 Jul 22 06:10:44 PM PDT 24 Jul 22 06:10:53 PM PDT 24 2825271258 ps
T1071 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2313126117 Jul 22 06:10:55 PM PDT 24 Jul 22 06:10:56 PM PDT 24 12201752 ps
T1072 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1984878583 Jul 22 06:12:26 PM PDT 24 Jul 22 06:12:31 PM PDT 24 225598210 ps
T194 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2141460757 Jul 22 06:10:38 PM PDT 24 Jul 22 06:10:42 PM PDT 24 77775075 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2929198525 Jul 22 06:11:00 PM PDT 24 Jul 22 06:11:04 PM PDT 24 205439433 ps
T1074 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.772067399 Jul 22 06:10:55 PM PDT 24 Jul 22 06:11:04 PM PDT 24 2241224901 ps
T1075 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2472899445 Jul 22 06:10:26 PM PDT 24 Jul 22 06:10:33 PM PDT 24 245372051 ps
T1076 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3531071475 Jul 22 06:10:50 PM PDT 24 Jul 22 06:10:53 PM PDT 24 469474800 ps
T1077 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1869159795 Jul 22 06:10:48 PM PDT 24 Jul 22 06:10:49 PM PDT 24 43816096 ps
T1078 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4038420371 Jul 22 06:10:46 PM PDT 24 Jul 22 06:10:50 PM PDT 24 97579934 ps
T1079 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1720073788 Jul 22 06:10:38 PM PDT 24 Jul 22 06:10:39 PM PDT 24 25270511 ps
T1080 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1359824827 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:52 PM PDT 24 132435176 ps
T1081 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1540989661 Jul 22 06:10:30 PM PDT 24 Jul 22 06:10:34 PM PDT 24 117236893 ps
T1082 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1817909100 Jul 22 06:13:18 PM PDT 24 Jul 22 06:13:20 PM PDT 24 78431163 ps
T187 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3197458416 Jul 22 06:10:54 PM PDT 24 Jul 22 06:10:59 PM PDT 24 111089284 ps
T1083 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.794876977 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:54 PM PDT 24 211507380 ps
T1084 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1561054723 Jul 22 06:10:49 PM PDT 24 Jul 22 06:10:52 PM PDT 24 93088791 ps
T1085 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3222217583 Jul 22 06:11:01 PM PDT 24 Jul 22 06:11:02 PM PDT 24 9888713 ps
T1086 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4123456880 Jul 22 06:10:46 PM PDT 24 Jul 22 06:10:51 PM PDT 24 437557067 ps
T191 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.312827651 Jul 22 06:10:50 PM PDT 24 Jul 22 06:10:55 PM PDT 24 118220852 ps

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.342852565
Short name T18
Test name
Test status
Simulation time 1384029446 ps
CPU time 5.68 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:42 PM PDT 24
Peak memory 207608 kb
Host smart-aa2170f9-78c6-4b10-b2cf-bcc79312683f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342852565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.342852565
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1165252160
Short name T7
Test name
Test status
Simulation time 8305621276 ps
CPU time 122.16 seconds
Started Jul 22 07:15:59 PM PDT 24
Finished Jul 22 07:18:57 PM PDT 24
Peak memory 216944 kb
Host smart-245a0b8f-7a08-410f-8c1c-666b552fe91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165252160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1165252160
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.62982054
Short name T17
Test name
Test status
Simulation time 1778553613 ps
CPU time 5.06 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:05 PM PDT 24
Peak memory 214008 kb
Host smart-de505592-48c1-4170-b10a-4d692f250a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62982054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.62982054
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1652520411
Short name T62
Test name
Test status
Simulation time 5739062871 ps
CPU time 56.24 seconds
Started Jul 22 07:15:02 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 222316 kb
Host smart-963e5ffe-ce61-4955-98c2-eb59e5d64dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652520411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1652520411
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.133686971
Short name T45
Test name
Test status
Simulation time 273606489 ps
CPU time 7.42 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:39 PM PDT 24
Peak memory 237264 kb
Host smart-e1191fe2-bfa1-4a9b-82d7-dfc797ab1215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133686971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.133686971
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4119282188
Short name T148
Test name
Test status
Simulation time 328874380 ps
CPU time 10.94 seconds
Started Jul 22 07:13:51 PM PDT 24
Finished Jul 22 07:14:53 PM PDT 24
Peak memory 219604 kb
Host smart-c0aac33c-8236-4970-9be2-5e7a11cdbe34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119282188 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4119282188
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2149921524
Short name T68
Test name
Test status
Simulation time 917762500 ps
CPU time 35.29 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:57 PM PDT 24
Peak memory 214840 kb
Host smart-97ec0651-dd4a-4e74-a613-752a3e7d5501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149921524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2149921524
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2601762816
Short name T152
Test name
Test status
Simulation time 148769365 ps
CPU time 6.94 seconds
Started Jul 22 07:15:51 PM PDT 24
Finished Jul 22 07:16:46 PM PDT 24
Peak memory 214136 kb
Host smart-28f909cd-a7c1-4fc5-b8cb-2c9a386a202e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601762816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2601762816
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1746267408
Short name T37
Test name
Test status
Simulation time 373723279 ps
CPU time 2.5 seconds
Started Jul 22 07:15:58 PM PDT 24
Finished Jul 22 07:16:54 PM PDT 24
Peak memory 213996 kb
Host smart-c07c03e8-793e-4659-8064-5fbabbf7f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746267408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1746267408
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1446128850
Short name T10
Test name
Test status
Simulation time 369343241 ps
CPU time 3.29 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:21 PM PDT 24
Peak memory 214384 kb
Host smart-926de7a5-5168-4efe-b288-3e5010d37348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446128850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1446128850
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1903810523
Short name T125
Test name
Test status
Simulation time 355208691 ps
CPU time 5.01 seconds
Started Jul 22 06:10:32 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 214672 kb
Host smart-369ead61-4dfd-4be5-bd40-524cca9424e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903810523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1903810523
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.804748891
Short name T28
Test name
Test status
Simulation time 1170027469 ps
CPU time 23 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 222192 kb
Host smart-1b0da4d6-338e-4d30-adac-3183d07685f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804748891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.804748891
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2039857018
Short name T124
Test name
Test status
Simulation time 539143873 ps
CPU time 17.15 seconds
Started Jul 22 07:12:58 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 222432 kb
Host smart-45ea0c04-c435-452c-ad54-611698f10e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039857018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2039857018
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3390634582
Short name T130
Test name
Test status
Simulation time 1469943123 ps
CPU time 38.29 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:15:34 PM PDT 24
Peak memory 214180 kb
Host smart-a3e144ae-a2a7-4697-8366-c33d37a3ebe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390634582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3390634582
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2815043672
Short name T371
Test name
Test status
Simulation time 1699026148 ps
CPU time 49.87 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:17:16 PM PDT 24
Peak memory 213836 kb
Host smart-4d37b765-fe12-404b-8050-86ee1064ac3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815043672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2815043672
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1180556505
Short name T64
Test name
Test status
Simulation time 5892047013 ps
CPU time 64.13 seconds
Started Jul 22 07:13:08 PM PDT 24
Finished Jul 22 07:15:02 PM PDT 24
Peak memory 222476 kb
Host smart-9bbfc8f7-2b99-4591-a284-3418984a9dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180556505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1180556505
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2678620787
Short name T101
Test name
Test status
Simulation time 190175150 ps
CPU time 4.57 seconds
Started Jul 22 07:16:04 PM PDT 24
Finished Jul 22 07:17:07 PM PDT 24
Peak memory 214032 kb
Host smart-20cba540-1c02-4c16-9e4f-99b30632da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678620787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2678620787
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3606526293
Short name T151
Test name
Test status
Simulation time 1620934054 ps
CPU time 62.06 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:14:32 PM PDT 24
Peak memory 214524 kb
Host smart-3db94a22-1d3b-4f2e-972f-672eb70e13a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606526293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3606526293
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2115656509
Short name T65
Test name
Test status
Simulation time 1811044971 ps
CPU time 24.87 seconds
Started Jul 22 07:12:56 PM PDT 24
Finished Jul 22 07:14:10 PM PDT 24
Peak memory 216156 kb
Host smart-afb48bb6-c653-479d-8993-103de6eeaad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115656509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2115656509
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1236111368
Short name T19
Test name
Test status
Simulation time 75630734 ps
CPU time 1.64 seconds
Started Jul 22 07:13:16 PM PDT 24
Finished Jul 22 07:14:07 PM PDT 24
Peak memory 221532 kb
Host smart-be42cb4e-d643-4a86-820b-cd6e8dbd6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236111368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1236111368
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.965726780
Short name T235
Test name
Test status
Simulation time 2562427637 ps
CPU time 31.91 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:47 PM PDT 24
Peak memory 214404 kb
Host smart-52a3f69e-0661-493b-9531-1d67cbb41401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965726780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.965726780
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1339688466
Short name T66
Test name
Test status
Simulation time 373061703 ps
CPU time 1.92 seconds
Started Jul 22 07:15:01 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 209932 kb
Host smart-72d27379-4fa3-402b-a11a-7f9def5cf0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339688466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1339688466
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.138952554
Short name T133
Test name
Test status
Simulation time 246811009 ps
CPU time 2.79 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:31 PM PDT 24
Peak memory 214716 kb
Host smart-c197a06f-9d1b-4108-bbb9-7db4b17cff64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138952554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.138952554
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3781151640
Short name T234
Test name
Test status
Simulation time 358053058 ps
CPU time 18.8 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:34 PM PDT 24
Peak memory 220224 kb
Host smart-14f3b690-b33c-46d5-8a6d-97380fcac0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781151640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3781151640
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.539698323
Short name T341
Test name
Test status
Simulation time 5938636819 ps
CPU time 77.96 seconds
Started Jul 22 07:15:47 PM PDT 24
Finished Jul 22 07:17:52 PM PDT 24
Peak memory 214476 kb
Host smart-8ec9f083-3af0-4bff-877b-28c342b2da39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539698323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.539698323
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1555607802
Short name T40
Test name
Test status
Simulation time 479529078 ps
CPU time 7.36 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:12 PM PDT 24
Peak memory 214108 kb
Host smart-3db13acb-f0b7-4c3f-b0cc-2e20232c79ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555607802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1555607802
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3824935954
Short name T147
Test name
Test status
Simulation time 226703653 ps
CPU time 4.5 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 215296 kb
Host smart-fe8fd480-716c-48a0-82de-6499a251c103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824935954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3824935954
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1849741706
Short name T171
Test name
Test status
Simulation time 73387482 ps
CPU time 2.91 seconds
Started Jul 22 07:18:37 PM PDT 24
Finished Jul 22 07:19:28 PM PDT 24
Peak memory 215108 kb
Host smart-fca88789-1194-4317-8afd-d7dc27d838e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849741706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1849741706
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3488428059
Short name T219
Test name
Test status
Simulation time 14269112 ps
CPU time 0.76 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:15 PM PDT 24
Peak memory 205776 kb
Host smart-4de8c36c-65c8-4b58-958a-5082db4fe3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488428059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3488428059
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2432086489
Short name T70
Test name
Test status
Simulation time 4694962832 ps
CPU time 58.09 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 222260 kb
Host smart-059ec4f4-8009-4504-a0ab-356346a43708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432086489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2432086489
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.535428311
Short name T241
Test name
Test status
Simulation time 273673212 ps
CPU time 3.12 seconds
Started Jul 22 07:15:12 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 209544 kb
Host smart-306df638-fbfb-4eed-81d0-0e5b2fae7eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535428311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.535428311
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.320300859
Short name T110
Test name
Test status
Simulation time 38416970 ps
CPU time 2.68 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 222308 kb
Host smart-0cac4e12-2626-4923-b184-accc948dea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320300859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.320300859
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.808617187
Short name T310
Test name
Test status
Simulation time 50650462 ps
CPU time 3.3 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 214284 kb
Host smart-c521d29d-c9e7-4cab-82b3-93bfb1181f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808617187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.808617187
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1957025514
Short name T565
Test name
Test status
Simulation time 735730504 ps
CPU time 27.94 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:29 PM PDT 24
Peak memory 222424 kb
Host smart-6e4b8abc-3fe4-4991-86c7-0b6bf0886fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957025514 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1957025514
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2945721658
Short name T27
Test name
Test status
Simulation time 238069388 ps
CPU time 5.01 seconds
Started Jul 22 07:18:15 PM PDT 24
Finished Jul 22 07:19:13 PM PDT 24
Peak memory 209084 kb
Host smart-7450fee3-8a25-43e2-aa98-760476ab3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945721658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2945721658
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.30840498
Short name T179
Test name
Test status
Simulation time 183354240 ps
CPU time 4.15 seconds
Started Jul 22 06:11:48 PM PDT 24
Finished Jul 22 06:11:53 PM PDT 24
Peak memory 215760 kb
Host smart-6d969a46-1d92-44e5-9552-0b29f2152fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.30840498
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3138633699
Short name T431
Test name
Test status
Simulation time 495206059 ps
CPU time 3.78 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:17 PM PDT 24
Peak memory 214120 kb
Host smart-6453d8a9-3a1b-4672-8a1d-123017276f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138633699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3138633699
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.702733741
Short name T38
Test name
Test status
Simulation time 121522785 ps
CPU time 5.07 seconds
Started Jul 22 07:13:41 PM PDT 24
Finished Jul 22 07:14:41 PM PDT 24
Peak memory 214108 kb
Host smart-9f728d00-fce1-4f4c-ac90-af91adc42993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702733741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.702733741
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2104366520
Short name T33
Test name
Test status
Simulation time 210755449 ps
CPU time 4.23 seconds
Started Jul 22 07:16:12 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 222616 kb
Host smart-c2468dc7-bdb6-4a26-a3e6-6e42af3bb7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104366520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2104366520
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4101455283
Short name T267
Test name
Test status
Simulation time 715689928 ps
CPU time 10.01 seconds
Started Jul 22 07:14:04 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 213992 kb
Host smart-16ed999a-edd1-4086-887b-0d7ef7884843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101455283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4101455283
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.601193926
Short name T78
Test name
Test status
Simulation time 3438931973 ps
CPU time 41.21 seconds
Started Jul 22 07:13:40 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 215884 kb
Host smart-0e91dbb7-dde7-4fcf-8179-80ad59507c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601193926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.601193926
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2713847311
Short name T94
Test name
Test status
Simulation time 627986622 ps
CPU time 3 seconds
Started Jul 22 07:16:25 PM PDT 24
Finished Jul 22 07:17:31 PM PDT 24
Peak memory 222236 kb
Host smart-6ccd966c-41c0-4e39-a80c-dbf64ffdf93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713847311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2713847311
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1088457900
Short name T104
Test name
Test status
Simulation time 609253724 ps
CPU time 7 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:08 PM PDT 24
Peak memory 214060 kb
Host smart-ed158964-7e86-425c-8c27-8cd17b671f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088457900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1088457900
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1935766654
Short name T255
Test name
Test status
Simulation time 2409866564 ps
CPU time 24.59 seconds
Started Jul 22 07:12:58 PM PDT 24
Finished Jul 22 07:14:11 PM PDT 24
Peak memory 222168 kb
Host smart-268a0674-68ad-4ced-a0df-754db7338791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935766654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1935766654
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.642395159
Short name T898
Test name
Test status
Simulation time 2420211368 ps
CPU time 54.97 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:15:40 PM PDT 24
Peak memory 214836 kb
Host smart-efee648e-8c32-4969-9987-48ce3a779a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642395159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.642395159
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.193059608
Short name T242
Test name
Test status
Simulation time 1558550127 ps
CPU time 29.94 seconds
Started Jul 22 07:15:52 PM PDT 24
Finished Jul 22 07:17:11 PM PDT 24
Peak memory 221076 kb
Host smart-6e20bccc-e6f9-48c3-9d91-788f84373948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193059608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.193059608
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2552131392
Short name T180
Test name
Test status
Simulation time 2825271258 ps
CPU time 8.1 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214428 kb
Host smart-451759c9-d669-47a5-8cb0-d15fbdde26f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552131392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2552131392
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1028444576
Short name T196
Test name
Test status
Simulation time 431072384 ps
CPU time 3.72 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 214344 kb
Host smart-d55590dd-8a1d-40ec-ad88-a77e78eef686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028444576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1028444576
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2446523324
Short name T169
Test name
Test status
Simulation time 327459714 ps
CPU time 3.44 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 217508 kb
Host smart-21d119fc-e6ce-4f8a-8f53-b8722ba3da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446523324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2446523324
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1040143589
Short name T98
Test name
Test status
Simulation time 413509953 ps
CPU time 3.37 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 215064 kb
Host smart-56ab79da-8d80-4c11-b318-59e9b52e25ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040143589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1040143589
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1962895842
Short name T128
Test name
Test status
Simulation time 108332800 ps
CPU time 2.02 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 214664 kb
Host smart-9743e001-0063-45f9-888d-6d69051d4d7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962895842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1962895842
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.402708997
Short name T419
Test name
Test status
Simulation time 99231713 ps
CPU time 3.54 seconds
Started Jul 22 07:14:04 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 214084 kb
Host smart-8ccb7c5e-6b9c-4dd3-bd55-a1eff93a645f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402708997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.402708997
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1409229828
Short name T336
Test name
Test status
Simulation time 1855265495 ps
CPU time 64.4 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 222244 kb
Host smart-7bed2fc3-1883-4faa-a90f-9ec974277c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409229828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1409229828
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.767280918
Short name T329
Test name
Test status
Simulation time 34134760 ps
CPU time 1.91 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:00 PM PDT 24
Peak memory 219772 kb
Host smart-43b5b64f-e561-454f-af73-658ee8e7d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767280918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.767280918
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4008910766
Short name T417
Test name
Test status
Simulation time 71525179 ps
CPU time 4.27 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:07 PM PDT 24
Peak memory 215168 kb
Host smart-71f93f9e-c729-42ef-b98e-426e8afdc8e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008910766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4008910766
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1775294492
Short name T416
Test name
Test status
Simulation time 1171376998 ps
CPU time 7.57 seconds
Started Jul 22 07:15:47 PM PDT 24
Finished Jul 22 07:16:41 PM PDT 24
Peak memory 213972 kb
Host smart-e756ddd9-ad54-41fa-b8f5-43abb71f4525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775294492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1775294492
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2804106053
Short name T389
Test name
Test status
Simulation time 180694565 ps
CPU time 5.62 seconds
Started Jul 22 07:14:27 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 214084 kb
Host smart-401566cd-5196-4de0-af56-a255246bec94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804106053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2804106053
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1604535747
Short name T183
Test name
Test status
Simulation time 232125934 ps
CPU time 1.99 seconds
Started Jul 22 07:17:57 PM PDT 24
Finished Jul 22 07:18:48 PM PDT 24
Peak memory 209840 kb
Host smart-0291f283-a5fa-48f0-a3aa-735fd5bbd5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604535747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1604535747
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2798202926
Short name T122
Test name
Test status
Simulation time 96722981 ps
CPU time 1.85 seconds
Started Jul 22 07:12:59 PM PDT 24
Finished Jul 22 07:13:49 PM PDT 24
Peak memory 209408 kb
Host smart-0f341815-76a8-4760-9048-9b69c9740322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798202926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2798202926
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1553145368
Short name T167
Test name
Test status
Simulation time 72540382 ps
CPU time 2.53 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:13:32 PM PDT 24
Peak memory 216512 kb
Host smart-5afa4bbd-c274-40f6-b8f6-b3d946550bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553145368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1553145368
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3925619315
Short name T168
Test name
Test status
Simulation time 53662402 ps
CPU time 1.96 seconds
Started Jul 22 07:16:11 PM PDT 24
Finished Jul 22 07:17:16 PM PDT 24
Peak memory 216500 kb
Host smart-b44250d0-40c7-4d1c-ae58-6c7dc1307eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925619315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3925619315
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3178926689
Short name T170
Test name
Test status
Simulation time 40997225 ps
CPU time 2.32 seconds
Started Jul 22 07:13:04 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 217504 kb
Host smart-80bc4d6d-26a9-46de-b376-272a4622907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178926689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3178926689
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3576556229
Short name T213
Test name
Test status
Simulation time 1070286422 ps
CPU time 37.63 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:55 PM PDT 24
Peak memory 215316 kb
Host smart-24fffd32-0061-4b52-924c-cdd8902fed24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576556229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3576556229
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3131841827
Short name T72
Test name
Test status
Simulation time 527568947 ps
CPU time 7.36 seconds
Started Jul 22 07:13:51 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 222120 kb
Host smart-b639d18b-af05-48e6-8e25-dbb16b10973e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131841827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3131841827
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1430724818
Short name T355
Test name
Test status
Simulation time 578087267 ps
CPU time 12.48 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 223040 kb
Host smart-78440cea-631d-48d8-a579-7520b041a57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430724818 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1430724818
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3403946285
Short name T643
Test name
Test status
Simulation time 1511647886 ps
CPU time 3.74 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 214100 kb
Host smart-c16c0f63-7fa6-4dce-9359-a4b98592cfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403946285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3403946285
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3427038391
Short name T186
Test name
Test status
Simulation time 792833531 ps
CPU time 5.49 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:59 PM PDT 24
Peak memory 214376 kb
Host smart-a62b3620-d0c4-452c-ab85-29a5a637c320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427038391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3427038391
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3628824123
Short name T36
Test name
Test status
Simulation time 84670695 ps
CPU time 2.13 seconds
Started Jul 22 07:15:01 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 215264 kb
Host smart-15bcbef8-e734-4a66-94b8-23aa3cda823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628824123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3628824123
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.464210942
Short name T321
Test name
Test status
Simulation time 5304747245 ps
CPU time 31.74 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:45 PM PDT 24
Peak memory 215616 kb
Host smart-87d29ff7-7607-4dfb-803e-71c1c29d2071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464210942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.464210942
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.888453521
Short name T334
Test name
Test status
Simulation time 203237490 ps
CPU time 8 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:10 PM PDT 24
Peak memory 208800 kb
Host smart-7b536531-4792-4493-8ca5-5afa8f104bce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888453521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.888453521
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.77709469
Short name T380
Test name
Test status
Simulation time 3824200858 ps
CPU time 95.52 seconds
Started Jul 22 07:13:34 PM PDT 24
Finished Jul 22 07:16:00 PM PDT 24
Peak memory 218812 kb
Host smart-d2ac1d8c-597e-4af4-b715-e55aa2482915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77709469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.77709469
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.256877567
Short name T373
Test name
Test status
Simulation time 145691619 ps
CPU time 4.36 seconds
Started Jul 22 07:13:54 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 219500 kb
Host smart-7da5582f-efbd-47c0-89c4-67e19f1026cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256877567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.256877567
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4013991585
Short name T393
Test name
Test status
Simulation time 133526989 ps
CPU time 7.56 seconds
Started Jul 22 07:13:41 PM PDT 24
Finished Jul 22 07:14:43 PM PDT 24
Peak memory 214428 kb
Host smart-dd976d8d-9ab9-48ff-9560-f8108515e4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013991585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4013991585
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2257348359
Short name T102
Test name
Test status
Simulation time 1393482647 ps
CPU time 30.15 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:45 PM PDT 24
Peak memory 222288 kb
Host smart-ea11793f-9dbf-453b-9a82-6a5599ea95f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257348359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2257348359
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1396305946
Short name T280
Test name
Test status
Simulation time 385805951 ps
CPU time 3.13 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:45 PM PDT 24
Peak memory 214056 kb
Host smart-8e7ed63d-9f63-465d-ad40-36c01e3f2104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396305946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1396305946
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3880039405
Short name T301
Test name
Test status
Simulation time 798315320 ps
CPU time 4.26 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:25 PM PDT 24
Peak memory 214984 kb
Host smart-a9deb671-09f9-4962-bcce-247977c02aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880039405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3880039405
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3346244539
Short name T410
Test name
Test status
Simulation time 66224949 ps
CPU time 3.22 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 207716 kb
Host smart-d4f3c78e-778f-4d88-8ef0-0aea1f4aee02
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346244539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3346244539
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1264359429
Short name T247
Test name
Test status
Simulation time 10330163461 ps
CPU time 33.38 seconds
Started Jul 22 07:15:52 PM PDT 24
Finished Jul 22 07:17:14 PM PDT 24
Peak memory 216888 kb
Host smart-3a940124-d42e-47c1-9b62-2152fe8aa1b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264359429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1264359429
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1384603940
Short name T352
Test name
Test status
Simulation time 160649021 ps
CPU time 6.49 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 219984 kb
Host smart-0d3af801-3c94-48ca-b4c4-a6800e6adfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384603940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1384603940
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3713594974
Short name T182
Test name
Test status
Simulation time 205885283 ps
CPU time 5.74 seconds
Started Jul 22 06:10:27 PM PDT 24
Finished Jul 22 06:10:34 PM PDT 24
Peak memory 214896 kb
Host smart-4d931213-bb2d-45c9-beb6-6c97be385b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713594974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3713594974
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.648329238
Short name T176
Test name
Test status
Simulation time 243796346 ps
CPU time 3.03 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 206576 kb
Host smart-a446aa78-c75b-4a93-9a27-0d6f6bed97b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648329238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.648329238
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3598950767
Short name T184
Test name
Test status
Simulation time 1025949947 ps
CPU time 3.74 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:55 PM PDT 24
Peak memory 214416 kb
Host smart-2046d150-ea1d-4fcf-b0b7-25219f9f76ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598950767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3598950767
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.551053208
Short name T181
Test name
Test status
Simulation time 104619258 ps
CPU time 4.5 seconds
Started Jul 22 06:13:33 PM PDT 24
Finished Jul 22 06:13:38 PM PDT 24
Peak memory 214412 kb
Host smart-41aa3bb7-bbe6-4400-a478-2ee88b56f7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551053208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.551053208
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2701764026
Short name T185
Test name
Test status
Simulation time 838979045 ps
CPU time 5.69 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:11:00 PM PDT 24
Peak memory 206120 kb
Host smart-031a4c0c-2a59-4678-ad96-cd3cee109cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701764026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2701764026
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2141460757
Short name T194
Test name
Test status
Simulation time 77775075 ps
CPU time 3.39 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:42 PM PDT 24
Peak memory 214444 kb
Host smart-80de6bdc-8b01-424f-b14c-7d9bc85d5840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141460757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2141460757
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1068747668
Short name T23
Test name
Test status
Simulation time 201013886 ps
CPU time 3.63 seconds
Started Jul 22 07:12:49 PM PDT 24
Finished Jul 22 07:13:39 PM PDT 24
Peak memory 221632 kb
Host smart-78065840-e74b-450b-a162-3146be7a6f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068747668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1068747668
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.766317668
Short name T172
Test name
Test status
Simulation time 271805107 ps
CPU time 3.33 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 217976 kb
Host smart-1950a3d1-a0aa-4311-95ed-96a8dbfdd2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766317668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.766317668
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1705493056
Short name T71
Test name
Test status
Simulation time 95870892 ps
CPU time 4.69 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 222484 kb
Host smart-7e314740-e0f2-4587-ad89-80bfb1925229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705493056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1705493056
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1220512430
Short name T195
Test name
Test status
Simulation time 54487402 ps
CPU time 3.07 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:07 PM PDT 24
Peak memory 214372 kb
Host smart-d1bacab7-58e0-4415-a485-dcbad90c1b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220512430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1220512430
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3838439681
Short name T333
Test name
Test status
Simulation time 117067972 ps
CPU time 2.33 seconds
Started Jul 22 07:12:27 PM PDT 24
Finished Jul 22 07:13:12 PM PDT 24
Peak memory 213996 kb
Host smart-9924dd19-fcde-4f09-b484-ea14100ae6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838439681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3838439681
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.326970501
Short name T339
Test name
Test status
Simulation time 478493614 ps
CPU time 5.87 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 208240 kb
Host smart-a98b575b-c3ba-45e2-a32d-d0845e5a237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326970501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.326970501
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1618014450
Short name T307
Test name
Test status
Simulation time 89755089 ps
CPU time 3.02 seconds
Started Jul 22 07:13:16 PM PDT 24
Finished Jul 22 07:14:07 PM PDT 24
Peak memory 208380 kb
Host smart-9ea6ead8-8954-4d53-bbb8-00c87b082d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618014450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1618014450
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3304795031
Short name T90
Test name
Test status
Simulation time 111225923 ps
CPU time 4.61 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:21 PM PDT 24
Peak memory 208108 kb
Host smart-c74c07ef-8900-441a-a879-bcd3d6268a1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304795031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3304795031
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2795933460
Short name T331
Test name
Test status
Simulation time 1947832296 ps
CPU time 3.64 seconds
Started Jul 22 07:13:37 PM PDT 24
Finished Jul 22 07:14:36 PM PDT 24
Peak memory 214016 kb
Host smart-827b3ef2-cc97-42e6-b339-21215ad6935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795933460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2795933460
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3111409750
Short name T824
Test name
Test status
Simulation time 182522822 ps
CPU time 4.15 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:40 PM PDT 24
Peak memory 214028 kb
Host smart-1f79ddb4-5c97-43bb-a275-e3d4186de3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111409750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3111409750
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.796109858
Short name T249
Test name
Test status
Simulation time 195688709 ps
CPU time 1.55 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 209316 kb
Host smart-0aa6c8e1-7cad-4761-a99a-676c1cfa0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796109858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.796109858
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3311136594
Short name T256
Test name
Test status
Simulation time 178144804 ps
CPU time 3.22 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 222256 kb
Host smart-a2983411-61a3-4e38-9211-7089c1bbf8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311136594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3311136594
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1089872196
Short name T259
Test name
Test status
Simulation time 1212047582 ps
CPU time 38.49 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:55 PM PDT 24
Peak memory 222052 kb
Host smart-444bd5c5-92b0-4287-95bd-217290019eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089872196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1089872196
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2814848446
Short name T52
Test name
Test status
Simulation time 699172608 ps
CPU time 13.55 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:30 PM PDT 24
Peak memory 222232 kb
Host smart-8c47476e-679d-4bc4-868f-ef3802fe9a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814848446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2814848446
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_random.254089059
Short name T364
Test name
Test status
Simulation time 1853384446 ps
CPU time 14.08 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:42 PM PDT 24
Peak memory 208172 kb
Host smart-87e38add-c889-445d-a69c-7dbcafd5c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254089059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.254089059
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1909787539
Short name T428
Test name
Test status
Simulation time 56818801 ps
CPU time 4.13 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 214600 kb
Host smart-6e14bd9f-84f1-4e89-b0ec-f8ad26068a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909787539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1909787539
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.660509540
Short name T432
Test name
Test status
Simulation time 184369364 ps
CPU time 9.48 seconds
Started Jul 22 07:16:19 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 214528 kb
Host smart-8106eb9b-2fb7-40da-87f9-157be17b32a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660509540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.660509540
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3347120666
Short name T200
Test name
Test status
Simulation time 335727862 ps
CPU time 11.65 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:47 PM PDT 24
Peak memory 222352 kb
Host smart-3ae0e998-00d7-4bb5-ba44-ec7193c56acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347120666 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3347120666
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2924161667
Short name T281
Test name
Test status
Simulation time 36823572 ps
CPU time 2.76 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:37 PM PDT 24
Peak memory 215264 kb
Host smart-87be58aa-983c-4c4d-b4b8-73f7f1e7574f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924161667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2924161667
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1610771960
Short name T264
Test name
Test status
Simulation time 5101462270 ps
CPU time 45.83 seconds
Started Jul 22 07:16:25 PM PDT 24
Finished Jul 22 07:18:15 PM PDT 24
Peak memory 215624 kb
Host smart-90efac9d-efed-41a3-84b4-f5bcad2b8daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610771960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1610771960
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.438536211
Short name T173
Test name
Test status
Simulation time 380073318 ps
CPU time 3.75 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:30 PM PDT 24
Peak memory 222444 kb
Host smart-cecde6a7-1c06-4a05-a029-e0e934fb8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438536211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.438536211
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3165726261
Short name T973
Test name
Test status
Simulation time 236372580 ps
CPU time 9.02 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 206180 kb
Host smart-3c921797-3ebe-4574-b6bd-16538569c346
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165726261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
165726261
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3689041682
Short name T959
Test name
Test status
Simulation time 255256248 ps
CPU time 7.75 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:36 PM PDT 24
Peak memory 206228 kb
Host smart-f0c9a354-3845-4a84-94df-98ad1712a68c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689041682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
689041682
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2843796605
Short name T1043
Test name
Test status
Simulation time 64265272 ps
CPU time 1.16 seconds
Started Jul 22 06:10:24 PM PDT 24
Finished Jul 22 06:10:26 PM PDT 24
Peak memory 206148 kb
Host smart-86d92951-5b2f-42b5-a0d9-086b2ea9e89f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843796605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
843796605
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4291831662
Short name T988
Test name
Test status
Simulation time 54006288 ps
CPU time 1.71 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:30 PM PDT 24
Peak memory 214588 kb
Host smart-83f84fd8-a5d2-424d-afee-3074d5331c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291831662 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4291831662
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2297605321
Short name T1069
Test name
Test status
Simulation time 54224191 ps
CPU time 1.19 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 206172 kb
Host smart-27b0ce74-294a-4ac5-91ed-69ca1ee75a6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297605321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2297605321
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3787612426
Short name T1032
Test name
Test status
Simulation time 23509262 ps
CPU time 0.73 seconds
Started Jul 22 06:11:49 PM PDT 24
Finished Jul 22 06:11:51 PM PDT 24
Peak memory 205920 kb
Host smart-4c00dc5d-1d21-4e2d-ad7d-ea4ffe75407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787612426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3787612426
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1395139091
Short name T954
Test name
Test status
Simulation time 58192637 ps
CPU time 2.25 seconds
Started Jul 22 06:10:26 PM PDT 24
Finished Jul 22 06:10:29 PM PDT 24
Peak memory 206236 kb
Host smart-e0a919d2-ed3c-4d07-8c59-6da9cedb2252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395139091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1395139091
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.729474912
Short name T995
Test name
Test status
Simulation time 126704596 ps
CPU time 2.09 seconds
Started Jul 22 06:10:34 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 214536 kb
Host smart-3798b49e-493c-4803-a206-39d10d228f86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729474912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.729474912
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1813509375
Short name T126
Test name
Test status
Simulation time 495780031 ps
CPU time 6.2 seconds
Started Jul 22 06:10:27 PM PDT 24
Finished Jul 22 06:10:34 PM PDT 24
Peak memory 220336 kb
Host smart-fbd35266-bf59-41fa-ba56-45483e0d5669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813509375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1813509375
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3954595987
Short name T1012
Test name
Test status
Simulation time 150781485 ps
CPU time 3.14 seconds
Started Jul 22 06:10:32 PM PDT 24
Finished Jul 22 06:10:35 PM PDT 24
Peak memory 217584 kb
Host smart-2838905d-42e1-4a92-8ffa-1bf0eab52eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954595987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3954595987
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2791643130
Short name T957
Test name
Test status
Simulation time 159780586 ps
CPU time 4.61 seconds
Started Jul 22 06:10:31 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 206444 kb
Host smart-4f967dc2-4dbb-4a87-ae6c-950dfd6ca7c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791643130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
791643130
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1156623129
Short name T963
Test name
Test status
Simulation time 956694241 ps
CPU time 14.22 seconds
Started Jul 22 06:10:30 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 206104 kb
Host smart-0e4f55a9-d7a8-481b-adcb-9fe1f6dd7c89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156623129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
156623129
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2432477483
Short name T1042
Test name
Test status
Simulation time 19762905 ps
CPU time 1.09 seconds
Started Jul 22 06:10:34 PM PDT 24
Finished Jul 22 06:10:35 PM PDT 24
Peak memory 206224 kb
Host smart-dfd4a188-62fd-45aa-bcef-a2d194f57a0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432477483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
432477483
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3350556969
Short name T962
Test name
Test status
Simulation time 32577067 ps
CPU time 2.17 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:31 PM PDT 24
Peak memory 214528 kb
Host smart-957f53b2-f52d-4526-83cf-b4b282a68bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350556969 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3350556969
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3115523928
Short name T1023
Test name
Test status
Simulation time 14868214 ps
CPU time 1.08 seconds
Started Jul 22 06:13:44 PM PDT 24
Finished Jul 22 06:13:46 PM PDT 24
Peak memory 206156 kb
Host smart-6839bf60-6a72-4fc9-8588-4e2172d4061b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115523928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3115523928
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2897361944
Short name T967
Test name
Test status
Simulation time 53686907 ps
CPU time 0.87 seconds
Started Jul 22 06:10:24 PM PDT 24
Finished Jul 22 06:10:25 PM PDT 24
Peak memory 206032 kb
Host smart-12e6ede4-4972-4a68-b11e-05d107d1402c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897361944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2897361944
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1957953302
Short name T985
Test name
Test status
Simulation time 1612962825 ps
CPU time 2.69 seconds
Started Jul 22 06:10:28 PM PDT 24
Finished Jul 22 06:10:31 PM PDT 24
Peak memory 206236 kb
Host smart-64350dfa-0b61-470c-9081-85cc89948ea2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957953302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1957953302
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3170219291
Short name T1011
Test name
Test status
Simulation time 723231105 ps
CPU time 4.97 seconds
Started Jul 22 06:10:37 PM PDT 24
Finished Jul 22 06:10:43 PM PDT 24
Peak memory 214592 kb
Host smart-01f8dc4e-8959-472f-a799-e8c540cae526
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170219291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3170219291
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3885386024
Short name T978
Test name
Test status
Simulation time 4724731428 ps
CPU time 11.25 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:46 PM PDT 24
Peak memory 214760 kb
Host smart-780cbaf8-9f28-4ce9-b160-7d3ab7a41cfe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885386024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3885386024
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1540989661
Short name T1081
Test name
Test status
Simulation time 117236893 ps
CPU time 4.02 seconds
Started Jul 22 06:10:30 PM PDT 24
Finished Jul 22 06:10:34 PM PDT 24
Peak memory 217456 kb
Host smart-cb57b113-bbe6-42c2-b7cc-6c5a2a2c61e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540989661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1540989661
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1331034466
Short name T981
Test name
Test status
Simulation time 78555729 ps
CPU time 1.63 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 214400 kb
Host smart-5e53135c-35d1-47b4-a14c-288947fe2faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331034466 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1331034466
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3133927394
Short name T1027
Test name
Test status
Simulation time 66463960 ps
CPU time 0.9 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:46 PM PDT 24
Peak memory 206024 kb
Host smart-5ae6d14b-64d7-4089-bbc2-40ab95d0a71a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133927394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3133927394
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1518013851
Short name T1066
Test name
Test status
Simulation time 20735231 ps
CPU time 0.7 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 206056 kb
Host smart-764fc6e5-92d6-40c0-b3fa-9ae59fdde8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518013851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1518013851
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2829868337
Short name T161
Test name
Test status
Simulation time 38050501 ps
CPU time 1.37 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 206228 kb
Host smart-65c4f9d2-2c9e-4bcc-b21a-882254125797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829868337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2829868337
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.910228797
Short name T993
Test name
Test status
Simulation time 974912155 ps
CPU time 1.99 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214636 kb
Host smart-49de8d61-463d-465b-bed0-56e6a3db0407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910228797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.910228797
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3896639450
Short name T987
Test name
Test status
Simulation time 302445360 ps
CPU time 5.29 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 220576 kb
Host smart-a10d0e85-f9ef-4a01-a66f-17ce898181b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896639450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3896639450
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3601743842
Short name T975
Test name
Test status
Simulation time 35261493 ps
CPU time 2.8 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 214420 kb
Host smart-623ba16c-d753-478a-a3c3-d7fe00d32b45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601743842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3601743842
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.680365911
Short name T951
Test name
Test status
Simulation time 160880558 ps
CPU time 1.15 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:48 PM PDT 24
Peak memory 214536 kb
Host smart-d2715b97-c8b7-45fa-85b7-3710a1a62822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680365911 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.680365911
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.827885316
Short name T946
Test name
Test status
Simulation time 99131396 ps
CPU time 1.43 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:48 PM PDT 24
Peak memory 206144 kb
Host smart-74b38895-b6fa-47f8-9f22-2642b5bbc797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827885316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.827885316
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2056584719
Short name T1048
Test name
Test status
Simulation time 19672845 ps
CPU time 0.85 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 206008 kb
Host smart-66d13cbc-c0b2-4113-8a72-7e48e9d31a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056584719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2056584719
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1050413483
Short name T1035
Test name
Test status
Simulation time 40755135 ps
CPU time 1.65 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 206292 kb
Host smart-6015f70c-091d-4cdb-a0ec-adc4ead6efe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050413483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1050413483
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.948316128
Short name T1017
Test name
Test status
Simulation time 330739229 ps
CPU time 2.61 seconds
Started Jul 22 06:10:47 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 214680 kb
Host smart-58f793cd-c038-4d6e-bc9f-71039e0c3fc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948316128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.948316128
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1601625222
Short name T968
Test name
Test status
Simulation time 2721653007 ps
CPU time 7.14 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 214688 kb
Host smart-cb32bf3f-4e02-469a-8089-183d7bd4a723
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601625222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1601625222
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.904686996
Short name T1020
Test name
Test status
Simulation time 323719673 ps
CPU time 2.4 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214432 kb
Host smart-05427ac1-3dc7-4932-8256-2182589d2e61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904686996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.904686996
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1043030371
Short name T1059
Test name
Test status
Simulation time 32099379 ps
CPU time 2.27 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214500 kb
Host smart-60f5a869-68e1-4e60-9f1f-b76ba755d516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043030371 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1043030371
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2790462527
Short name T1004
Test name
Test status
Simulation time 17060908 ps
CPU time 1.02 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:46 PM PDT 24
Peak memory 206272 kb
Host smart-7fc6b67f-a78d-4d24-af2c-113cf564ebf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790462527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2790462527
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1869159795
Short name T1077
Test name
Test status
Simulation time 43816096 ps
CPU time 0.72 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 205884 kb
Host smart-7b417ef8-496e-481e-abf1-514c4efa9936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869159795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1869159795
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4038420371
Short name T1078
Test name
Test status
Simulation time 97579934 ps
CPU time 4.07 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 206152 kb
Host smart-c06a10a6-9e88-40f2-8b7a-7330e6078374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038420371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4038420371
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.865418647
Short name T132
Test name
Test status
Simulation time 94450881 ps
CPU time 1.5 seconds
Started Jul 22 06:10:43 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 214676 kb
Host smart-18e3a619-4fb5-40cd-9ea8-d93e1287db1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865418647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.865418647
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.494786123
Short name T1047
Test name
Test status
Simulation time 640424552 ps
CPU time 4.41 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214708 kb
Host smart-fa875bc7-5db1-4c22-aa0c-97f0a78636e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494786123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.494786123
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3602535440
Short name T929
Test name
Test status
Simulation time 64634531 ps
CPU time 2.45 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:51 PM PDT 24
Peak memory 214436 kb
Host smart-fd71fcce-28a4-44ce-88f9-f01dea5c456a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602535440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3602535440
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2669431650
Short name T945
Test name
Test status
Simulation time 850515602 ps
CPU time 5.94 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:59 PM PDT 24
Peak memory 214300 kb
Host smart-41085a98-8e73-4f71-a199-bcfeced2ab4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669431650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2669431650
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3484290099
Short name T1030
Test name
Test status
Simulation time 47483549 ps
CPU time 1.43 seconds
Started Jul 22 06:10:52 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 214436 kb
Host smart-c4fa451e-010c-47e4-a525-ec04f51614f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484290099 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3484290099
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2302908163
Short name T211
Test name
Test status
Simulation time 99047765 ps
CPU time 1.48 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 206192 kb
Host smart-704ded8f-6323-4ae3-b20c-36d7a6cbdd10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302908163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2302908163
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2463776981
Short name T927
Test name
Test status
Simulation time 8778310 ps
CPU time 0.72 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 205924 kb
Host smart-8e2913ed-1af8-4088-832f-066d14b8db20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463776981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2463776981
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2897749558
Short name T1005
Test name
Test status
Simulation time 24810468 ps
CPU time 1.3 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:46 PM PDT 24
Peak memory 206280 kb
Host smart-eedbc88a-8b9c-4227-8e58-65175db58d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897749558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2897749558
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4123456880
Short name T1086
Test name
Test status
Simulation time 437557067 ps
CPU time 4.06 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:51 PM PDT 24
Peak memory 214676 kb
Host smart-4bb80428-5bfa-47de-926e-a4d61d0b8c08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123456880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4123456880
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1256619306
Short name T1052
Test name
Test status
Simulation time 86534570 ps
CPU time 4.75 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:51 PM PDT 24
Peak memory 214768 kb
Host smart-6eb2251b-18aa-42b4-85ff-1bf3dc66532e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256619306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1256619306
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1885468194
Short name T956
Test name
Test status
Simulation time 564515676 ps
CPU time 2.19 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 214388 kb
Host smart-09919376-f01e-47ba-9e6b-fe44cb2471bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885468194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1885468194
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3998064676
Short name T941
Test name
Test status
Simulation time 216587008 ps
CPU time 1.74 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:51 PM PDT 24
Peak memory 214296 kb
Host smart-1e8d5f7d-c8f2-4e07-ba76-54df5d4263b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998064676 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3998064676
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.315221440
Short name T1003
Test name
Test status
Simulation time 115386490 ps
CPU time 1.17 seconds
Started Jul 22 06:10:48 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 206192 kb
Host smart-9b87b90a-afc3-4e7b-92d1-eb3db370c2b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315221440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.315221440
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2388809327
Short name T990
Test name
Test status
Simulation time 20428241 ps
CPU time 0.74 seconds
Started Jul 22 06:10:51 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 205884 kb
Host smart-7dc43d45-1a88-47d1-9a31-69f12668807a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388809327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2388809327
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1548802123
Short name T158
Test name
Test status
Simulation time 1175036072 ps
CPU time 2.9 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 206292 kb
Host smart-225b95ea-08b3-488d-96cb-808fbe8122da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548802123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1548802123
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.362028503
Short name T1015
Test name
Test status
Simulation time 716510713 ps
CPU time 2.41 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 214672 kb
Host smart-ce179b29-9131-4b36-a088-d86d2ed77e9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362028503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.362028503
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4099836879
Short name T970
Test name
Test status
Simulation time 450709584 ps
CPU time 12.46 seconds
Started Jul 22 06:10:44 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 214720 kb
Host smart-1c895819-bab1-4f1b-a2fb-4e40554f6985
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099836879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4099836879
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2533514498
Short name T958
Test name
Test status
Simulation time 519137264 ps
CPU time 4.3 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 214416 kb
Host smart-423b412c-d0ad-4d47-ad40-a41f6bd32034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533514498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2533514498
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3660186536
Short name T197
Test name
Test status
Simulation time 1031302908 ps
CPU time 3.62 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 214316 kb
Host smart-709b1ca0-710f-4f3f-92f1-2889ee5c0d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660186536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3660186536
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.444405125
Short name T203
Test name
Test status
Simulation time 114781317 ps
CPU time 1.14 seconds
Started Jul 22 06:10:52 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 214432 kb
Host smart-8b367b9c-6a15-4e7c-80cd-c448137ffe79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444405125 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.444405125
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3484776487
Short name T1038
Test name
Test status
Simulation time 98697462 ps
CPU time 0.88 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 206064 kb
Host smart-2e8dab46-46b2-496c-a6ce-9ab7df0b3efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484776487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3484776487
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2222887367
Short name T922
Test name
Test status
Simulation time 33000698 ps
CPU time 0.71 seconds
Started Jul 22 06:12:43 PM PDT 24
Finished Jul 22 06:12:45 PM PDT 24
Peak memory 206008 kb
Host smart-11a6c35a-8f22-4267-a927-b883531846f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222887367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2222887367
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.92057413
Short name T156
Test name
Test status
Simulation time 182688872 ps
CPU time 1.65 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 206348 kb
Host smart-2af2f71c-f8bb-4d51-8554-81f65864cc49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92057413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sam
e_csr_outstanding.92057413
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1561054723
Short name T1084
Test name
Test status
Simulation time 93088791 ps
CPU time 1.66 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 214680 kb
Host smart-9b8b9a33-15e8-40c6-8119-215daf2b4f2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561054723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1561054723
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3669188678
Short name T1036
Test name
Test status
Simulation time 757053942 ps
CPU time 5.87 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:55 PM PDT 24
Peak memory 214680 kb
Host smart-784ab7c8-f909-47a9-b20a-5f638a33a5a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669188678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3669188678
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1359824827
Short name T1080
Test name
Test status
Simulation time 132435176 ps
CPU time 2.63 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 214480 kb
Host smart-4cf30eff-0052-4b3d-a838-255b9221394e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359824827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1359824827
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.187551331
Short name T408
Test name
Test status
Simulation time 45920199 ps
CPU time 1.66 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:10:58 PM PDT 24
Peak memory 214472 kb
Host smart-5036d109-4346-4c20-9480-74e9ed0fc987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187551331 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.187551331
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1386487011
Short name T964
Test name
Test status
Simulation time 138029568 ps
CPU time 1.37 seconds
Started Jul 22 06:11:04 PM PDT 24
Finished Jul 22 06:11:06 PM PDT 24
Peak memory 206144 kb
Host smart-00ae1e59-78a7-4cc7-86ec-0573a46ca5c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386487011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1386487011
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3237533334
Short name T1010
Test name
Test status
Simulation time 76185208 ps
CPU time 0.81 seconds
Started Jul 22 06:10:47 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 205924 kb
Host smart-da2b13e1-6fde-4f73-aa1f-aeb460c30819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237533334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3237533334
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1202417951
Short name T1016
Test name
Test status
Simulation time 918269630 ps
CPU time 4.22 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:59 PM PDT 24
Peak memory 206192 kb
Host smart-5fcc19cb-5436-413f-9de1-8865c530d965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202417951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1202417951
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3531071475
Short name T1076
Test name
Test status
Simulation time 469474800 ps
CPU time 2.63 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214620 kb
Host smart-d13e28fe-e72e-4d57-aa1f-7266842df9ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531071475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3531071475
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.794876977
Short name T1083
Test name
Test status
Simulation time 211507380 ps
CPU time 4.98 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 214676 kb
Host smart-c7894b3d-f74e-4cb9-bcc8-019ecba1c426
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794876977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.794876977
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1096309300
Short name T1040
Test name
Test status
Simulation time 26012790 ps
CPU time 2.06 seconds
Started Jul 22 06:10:49 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214316 kb
Host smart-4412cd88-24ad-4df0-afa4-fd31f5a6d119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096309300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1096309300
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3477427619
Short name T979
Test name
Test status
Simulation time 67190392 ps
CPU time 2.05 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:06 PM PDT 24
Peak memory 214580 kb
Host smart-9bcba495-bc02-4e05-ad25-a9ed1dcb9191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477427619 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3477427619
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2163711071
Short name T1007
Test name
Test status
Simulation time 45937872 ps
CPU time 1.31 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 206080 kb
Host smart-445d7028-e253-4440-9255-cd0682a0244a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163711071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2163711071
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2358981264
Short name T931
Test name
Test status
Simulation time 38001424 ps
CPU time 0.82 seconds
Started Jul 22 06:11:00 PM PDT 24
Finished Jul 22 06:11:01 PM PDT 24
Peak memory 205924 kb
Host smart-6f721664-edfe-48d0-939c-107874cc7d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358981264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2358981264
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2138158350
Short name T943
Test name
Test status
Simulation time 19233500 ps
CPU time 1.59 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 206232 kb
Host smart-a9083d31-02d4-4c40-8489-e82f78844263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138158350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2138158350
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3970215232
Short name T949
Test name
Test status
Simulation time 129961177 ps
CPU time 2.23 seconds
Started Jul 22 06:11:00 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 214648 kb
Host smart-e44f3027-6791-4fc9-a19b-735ca23154be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970215232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3970215232
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2742791568
Short name T998
Test name
Test status
Simulation time 108389714 ps
CPU time 4.83 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:11:00 PM PDT 24
Peak memory 214584 kb
Host smart-a2ecebb8-e6f3-47cd-ac30-24f3a22f77bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742791568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2742791568
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1488169318
Short name T923
Test name
Test status
Simulation time 319196463 ps
CPU time 2.15 seconds
Started Jul 22 06:10:52 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 215452 kb
Host smart-bf16a023-227d-4cda-b8e0-3b3a882c7435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488169318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1488169318
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.842801443
Short name T938
Test name
Test status
Simulation time 160911558 ps
CPU time 2.19 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 219828 kb
Host smart-0fdfa913-2fe1-412c-a7bf-8a119a5edd07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842801443 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.842801443
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2595164732
Short name T1064
Test name
Test status
Simulation time 16879236 ps
CPU time 0.93 seconds
Started Jul 22 06:10:51 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 206068 kb
Host smart-a01fc774-dbc5-49fa-ae91-d0f558a73206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595164732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2595164732
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.262394934
Short name T928
Test name
Test status
Simulation time 23713579 ps
CPU time 0.85 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 206080 kb
Host smart-36ce5efb-1ad3-4199-9f8b-d907996f5a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262394934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.262394934
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2685759785
Short name T972
Test name
Test status
Simulation time 66687837 ps
CPU time 1.55 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 206372 kb
Host smart-655461ce-8e9d-4e46-96c8-4be90f2652cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685759785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2685759785
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.821683761
Short name T971
Test name
Test status
Simulation time 299650404 ps
CPU time 2.21 seconds
Started Jul 22 06:10:52 PM PDT 24
Finished Jul 22 06:10:55 PM PDT 24
Peak memory 214660 kb
Host smart-dd0f22ec-0571-4d81-89da-c1e2711a85b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821683761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.821683761
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2902652171
Short name T966
Test name
Test status
Simulation time 782285293 ps
CPU time 8.51 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:13 PM PDT 24
Peak memory 214664 kb
Host smart-53522d60-c74e-4c66-acfa-f97f32aa3528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902652171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2902652171
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2052966150
Short name T1070
Test name
Test status
Simulation time 41862514 ps
CPU time 2.01 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 214404 kb
Host smart-8ab9adad-f486-4500-9866-deb9c55476d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052966150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2052966150
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.663803141
Short name T178
Test name
Test status
Simulation time 18863434 ps
CPU time 1.14 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 214528 kb
Host smart-901672d4-e6d5-41e8-9759-2b424d1f3d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663803141 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.663803141
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.79335976
Short name T939
Test name
Test status
Simulation time 30045926 ps
CPU time 1.11 seconds
Started Jul 22 06:12:38 PM PDT 24
Finished Jul 22 06:12:39 PM PDT 24
Peak memory 206188 kb
Host smart-0a040415-b1f5-46d5-9e41-d9ba9edbf053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79335976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.79335976
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1783841184
Short name T1053
Test name
Test status
Simulation time 11813145 ps
CPU time 0.8 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 205948 kb
Host smart-a732e57f-7ac0-49d5-825a-6eff17e73298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783841184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1783841184
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1642871004
Short name T162
Test name
Test status
Simulation time 229631830 ps
CPU time 2.91 seconds
Started Jul 22 06:10:53 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 206228 kb
Host smart-92322af7-f854-4611-9ef0-7afc1413f44c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642871004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1642871004
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3267271087
Short name T136
Test name
Test status
Simulation time 324605600 ps
CPU time 2.49 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 214700 kb
Host smart-b65f3a56-f20c-466e-be80-614165cd53fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267271087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3267271087
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.772067399
Short name T1074
Test name
Test status
Simulation time 2241224901 ps
CPU time 9.11 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 214800 kb
Host smart-80baf361-80ee-4015-bcd7-53bace96af0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772067399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.772067399
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2929198525
Short name T1073
Test name
Test status
Simulation time 205439433 ps
CPU time 2.75 seconds
Started Jul 22 06:11:00 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 216616 kb
Host smart-7aafb26a-fc37-4226-b233-f133535a77ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929198525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2929198525
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3197458416
Short name T187
Test name
Test status
Simulation time 111089284 ps
CPU time 4.02 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:59 PM PDT 24
Peak memory 206152 kb
Host smart-81b4c2b4-f8d9-484f-a604-74c077a9d7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197458416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3197458416
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2472899445
Short name T1075
Test name
Test status
Simulation time 245372051 ps
CPU time 5.7 seconds
Started Jul 22 06:10:26 PM PDT 24
Finished Jul 22 06:10:33 PM PDT 24
Peak memory 206188 kb
Host smart-eddee591-f8c9-4ae2-9c92-df7af001563c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472899445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
472899445
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2495375828
Short name T961
Test name
Test status
Simulation time 672564959 ps
CPU time 15.85 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 206072 kb
Host smart-6fc211dd-105f-43a3-8a3f-82c8a678875f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495375828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
495375828
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1558100137
Short name T1065
Test name
Test status
Simulation time 57616123 ps
CPU time 0.87 seconds
Started Jul 22 06:10:30 PM PDT 24
Finished Jul 22 06:10:32 PM PDT 24
Peak memory 205928 kb
Host smart-c00cf89a-ab9d-42e5-9b98-7a7381cfd295
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558100137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
558100137
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2249055255
Short name T924
Test name
Test status
Simulation time 51795443 ps
CPU time 1.74 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 214376 kb
Host smart-54182a1c-fd33-49a4-8d80-2afdcc52b019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249055255 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2249055255
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3680387041
Short name T1046
Test name
Test status
Simulation time 23793927 ps
CPU time 1.21 seconds
Started Jul 22 06:11:49 PM PDT 24
Finished Jul 22 06:11:51 PM PDT 24
Peak memory 206072 kb
Host smart-7e005f0b-1b96-4f81-bb3e-f8feddb7e7dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680387041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3680387041
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2235180274
Short name T932
Test name
Test status
Simulation time 34929896 ps
CPU time 0.79 seconds
Started Jul 22 06:10:23 PM PDT 24
Finished Jul 22 06:10:24 PM PDT 24
Peak memory 205976 kb
Host smart-b9f9a6b2-e030-4267-a13f-edc0b938d128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235180274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2235180274
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2153464274
Short name T1039
Test name
Test status
Simulation time 47224163 ps
CPU time 1.63 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 206220 kb
Host smart-bc0b41db-d909-4485-a3a0-87beda8225e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153464274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2153464274
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1914170514
Short name T991
Test name
Test status
Simulation time 140290534 ps
CPU time 2.74 seconds
Started Jul 22 06:10:30 PM PDT 24
Finished Jul 22 06:10:33 PM PDT 24
Peak memory 214660 kb
Host smart-8e4a8109-9fcc-43e3-923b-9aeeed8dd810
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914170514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1914170514
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3867388162
Short name T934
Test name
Test status
Simulation time 61470985 ps
CPU time 2.73 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 214376 kb
Host smart-2eec55c2-9be2-41f0-91bf-3e3149e652d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867388162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3867388162
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2714822070
Short name T175
Test name
Test status
Simulation time 381873693 ps
CPU time 3.03 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 214372 kb
Host smart-d7d80b8d-1f00-4031-b69c-32d521d3c31e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714822070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2714822070
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2920351223
Short name T977
Test name
Test status
Simulation time 38653790 ps
CPU time 0.86 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:05 PM PDT 24
Peak memory 205944 kb
Host smart-fd8f0128-591f-419e-bfab-20d72695c261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920351223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2920351223
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3200674524
Short name T935
Test name
Test status
Simulation time 16803222 ps
CPU time 0.72 seconds
Started Jul 22 06:10:52 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 206000 kb
Host smart-d88b99d2-7917-4701-8ab2-58b6d1c73fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200674524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3200674524
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.644358748
Short name T936
Test name
Test status
Simulation time 14298649 ps
CPU time 0.81 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 205936 kb
Host smart-388b80b1-9b08-42f7-8a99-cfc4a5815b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644358748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.644358748
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2313126117
Short name T1071
Test name
Test status
Simulation time 12201752 ps
CPU time 0.82 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:10:56 PM PDT 24
Peak memory 205948 kb
Host smart-4188f5bf-830c-484f-a2b8-344f0bde720b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313126117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2313126117
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2734648206
Short name T1057
Test name
Test status
Simulation time 51823349 ps
CPU time 0.87 seconds
Started Jul 22 06:11:00 PM PDT 24
Finished Jul 22 06:11:02 PM PDT 24
Peak memory 206000 kb
Host smart-94860b12-f1d7-430f-ab24-1482bde06286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734648206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2734648206
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2813746143
Short name T926
Test name
Test status
Simulation time 7611484 ps
CPU time 0.71 seconds
Started Jul 22 06:10:54 PM PDT 24
Finished Jul 22 06:10:55 PM PDT 24
Peak memory 206048 kb
Host smart-ea4ce747-8664-446c-a5e3-c2cda0b28fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813746143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2813746143
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1875200481
Short name T1014
Test name
Test status
Simulation time 10369572 ps
CPU time 0.69 seconds
Started Jul 22 06:12:38 PM PDT 24
Finished Jul 22 06:12:39 PM PDT 24
Peak memory 205908 kb
Host smart-f65ccf96-1587-47fd-b00f-da0c55789d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875200481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1875200481
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.640597049
Short name T1037
Test name
Test status
Simulation time 24983238 ps
CPU time 0.76 seconds
Started Jul 22 06:10:55 PM PDT 24
Finished Jul 22 06:10:57 PM PDT 24
Peak memory 206000 kb
Host smart-dc33d03c-2609-49e3-8541-a6b8111876b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640597049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.640597049
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.145973493
Short name T1060
Test name
Test status
Simulation time 24442541 ps
CPU time 0.78 seconds
Started Jul 22 06:11:00 PM PDT 24
Finished Jul 22 06:11:01 PM PDT 24
Peak memory 205924 kb
Host smart-15b8f214-4794-47dc-b2df-e54b0c0251c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145973493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.145973493
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2912755386
Short name T984
Test name
Test status
Simulation time 12192330 ps
CPU time 0.72 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 205960 kb
Host smart-63eeb517-1b9b-4e60-9f3d-c95426ca0fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912755386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2912755386
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.877874216
Short name T1044
Test name
Test status
Simulation time 123426909 ps
CPU time 7.66 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 206180 kb
Host smart-8143970f-a940-4090-a4d7-77e62e348704
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877874216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.877874216
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1063770548
Short name T980
Test name
Test status
Simulation time 304074399 ps
CPU time 6.41 seconds
Started Jul 22 06:10:37 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 206308 kb
Host smart-69b42255-18dc-48df-94cf-525cfc716392
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063770548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
063770548
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2056594547
Short name T1031
Test name
Test status
Simulation time 54197075 ps
CPU time 0.92 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 206024 kb
Host smart-26b99192-6773-4e18-a5bd-abdde685c27e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056594547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
056594547
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2653721866
Short name T177
Test name
Test status
Simulation time 65665617 ps
CPU time 1.57 seconds
Started Jul 22 06:10:33 PM PDT 24
Finished Jul 22 06:10:35 PM PDT 24
Peak memory 214476 kb
Host smart-7a400947-9b05-43ba-8c29-06c0a5cd483f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653721866 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2653721866
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.246456415
Short name T1056
Test name
Test status
Simulation time 59530553 ps
CPU time 1.19 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 206152 kb
Host smart-3f761a99-845c-4caa-95fa-6fb23342d114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246456415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.246456415
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2152388636
Short name T930
Test name
Test status
Simulation time 12127414 ps
CPU time 0.75 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 206128 kb
Host smart-c28a480d-7a2e-4df0-af0b-1a6e1cb0a73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152388636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2152388636
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3977271981
Short name T974
Test name
Test status
Simulation time 1029266010 ps
CPU time 1.91 seconds
Started Jul 22 06:10:43 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 206152 kb
Host smart-ddef5772-877f-474f-a52f-3c1e6a5d0198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977271981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3977271981
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3859279983
Short name T1013
Test name
Test status
Simulation time 1419467078 ps
CPU time 11.84 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 214612 kb
Host smart-28fadad5-419a-44cb-a1ab-de1ba3553853
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859279983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3859279983
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.458461583
Short name T937
Test name
Test status
Simulation time 91374598 ps
CPU time 3.2 seconds
Started Jul 22 06:11:48 PM PDT 24
Finished Jul 22 06:11:52 PM PDT 24
Peak memory 214380 kb
Host smart-54ab4e54-4a70-46c0-a55f-ed717f11b707
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458461583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.458461583
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.312827651
Short name T191
Test name
Test status
Simulation time 118220852 ps
CPU time 3.69 seconds
Started Jul 22 06:10:50 PM PDT 24
Finished Jul 22 06:10:55 PM PDT 24
Peak memory 215816 kb
Host smart-e7510483-3ca7-4dd5-9b9a-5dc95eb493e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312827651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
312827651
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2650263731
Short name T925
Test name
Test status
Simulation time 29942993 ps
CPU time 0.7 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 206008 kb
Host smart-847dab04-273e-4957-8fea-42bf782a7f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650263731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2650263731
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1624222432
Short name T1054
Test name
Test status
Simulation time 66010932 ps
CPU time 0.84 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 205968 kb
Host smart-63cb1b3e-7d50-448a-a8f1-9895886bcfec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624222432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1624222432
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1493343984
Short name T1018
Test name
Test status
Simulation time 22313052 ps
CPU time 0.74 seconds
Started Jul 22 06:11:56 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 205904 kb
Host smart-60fe8fbe-73bd-4a8b-81c6-baf7291833fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493343984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1493343984
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2669278075
Short name T1025
Test name
Test status
Simulation time 26988216 ps
CPU time 0.7 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:06 PM PDT 24
Peak memory 206004 kb
Host smart-bc025df0-f8b7-4a76-9a24-7ca6747a6e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669278075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2669278075
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.626430442
Short name T1062
Test name
Test status
Simulation time 10113687 ps
CPU time 0.74 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:06 PM PDT 24
Peak memory 206004 kb
Host smart-45b555f8-08ee-40a8-8285-c9fa4891ff10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626430442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.626430442
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1839129925
Short name T1063
Test name
Test status
Simulation time 38399883 ps
CPU time 0.81 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 206024 kb
Host smart-542b8765-11bb-446e-9adc-a6a068c574cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839129925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1839129925
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3459586347
Short name T1049
Test name
Test status
Simulation time 38594033 ps
CPU time 0.75 seconds
Started Jul 22 06:13:46 PM PDT 24
Finished Jul 22 06:13:47 PM PDT 24
Peak memory 205840 kb
Host smart-c6b4999c-74c7-48c9-85e7-bdb0d6928328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459586347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3459586347
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.814347097
Short name T1021
Test name
Test status
Simulation time 51130453 ps
CPU time 0.77 seconds
Started Jul 22 06:13:46 PM PDT 24
Finished Jul 22 06:13:47 PM PDT 24
Peak memory 205916 kb
Host smart-d4e6fc91-c9f2-4705-957a-db6f88c55453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814347097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.814347097
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1643711792
Short name T948
Test name
Test status
Simulation time 8870847 ps
CPU time 0.81 seconds
Started Jul 22 06:13:15 PM PDT 24
Finished Jul 22 06:13:16 PM PDT 24
Peak memory 206012 kb
Host smart-2ba9bc66-1c94-42c5-a295-8a1be42f9144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643711792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1643711792
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1817909100
Short name T1082
Test name
Test status
Simulation time 78431163 ps
CPU time 0.7 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 206004 kb
Host smart-d0829ab5-4580-4582-a19b-474884c639c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817909100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1817909100
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1579457324
Short name T160
Test name
Test status
Simulation time 259310216 ps
CPU time 7.31 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 206136 kb
Host smart-a9be2770-82ca-428a-912b-1a362f7fe244
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579457324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
579457324
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2461309570
Short name T1008
Test name
Test status
Simulation time 1333308178 ps
CPU time 17.87 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 206244 kb
Host smart-92c16485-e28c-40e7-9ebb-3fb1729554f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461309570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
461309570
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2294526335
Short name T955
Test name
Test status
Simulation time 110120930 ps
CPU time 1.05 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 206224 kb
Host smart-58b49b35-9500-406b-8b47-d7a7e741083f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294526335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
294526335
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2564648236
Short name T1067
Test name
Test status
Simulation time 33392491 ps
CPU time 1.18 seconds
Started Jul 22 06:12:19 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 206260 kb
Host smart-43cd39d5-b632-4323-97aa-43f6105443ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564648236 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2564648236
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1961644542
Short name T1033
Test name
Test status
Simulation time 22405727 ps
CPU time 1.08 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 206228 kb
Host smart-96fdb0e6-24c9-4fd1-85ef-e69845e725a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961644542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1961644542
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1682453440
Short name T1026
Test name
Test status
Simulation time 15011508 ps
CPU time 0.88 seconds
Started Jul 22 06:13:45 PM PDT 24
Finished Jul 22 06:13:47 PM PDT 24
Peak memory 206072 kb
Host smart-26015f10-22a0-4907-81e5-5903bf725c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682453440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1682453440
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1169413938
Short name T965
Test name
Test status
Simulation time 30994649 ps
CPU time 1.95 seconds
Started Jul 22 06:12:19 PM PDT 24
Finished Jul 22 06:12:22 PM PDT 24
Peak memory 206260 kb
Host smart-3c4a66fa-3711-4395-ab6f-f32c7de4e9fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169413938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1169413938
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1012987292
Short name T992
Test name
Test status
Simulation time 465019092 ps
CPU time 2.78 seconds
Started Jul 22 06:10:40 PM PDT 24
Finished Jul 22 06:10:43 PM PDT 24
Peak memory 214612 kb
Host smart-cce755fd-1be1-44f2-8d79-a1454c674879
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012987292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1012987292
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.441716686
Short name T1045
Test name
Test status
Simulation time 280869063 ps
CPU time 6.55 seconds
Started Jul 22 06:10:34 PM PDT 24
Finished Jul 22 06:10:42 PM PDT 24
Peak memory 214668 kb
Host smart-2f2f8fc8-6ca8-4f48-b292-3fa014fe4be4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441716686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.441716686
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3249481634
Short name T1051
Test name
Test status
Simulation time 63019159 ps
CPU time 2.08 seconds
Started Jul 22 06:10:40 PM PDT 24
Finished Jul 22 06:10:43 PM PDT 24
Peak memory 214344 kb
Host smart-93d15108-12d9-4dd6-bc13-22c4dd28ad48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249481634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3249481634
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.24401137
Short name T1000
Test name
Test status
Simulation time 12340320 ps
CPU time 0.68 seconds
Started Jul 22 06:11:01 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 205932 kb
Host smart-3aeda9f7-c9c7-40ec-baab-fd8776743607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24401137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.24401137
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1278014096
Short name T1024
Test name
Test status
Simulation time 28407975 ps
CPU time 0.8 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 206008 kb
Host smart-2b2c22db-f248-4e87-a2d7-516d030388ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278014096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1278014096
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1099683474
Short name T976
Test name
Test status
Simulation time 16514509 ps
CPU time 0.73 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 206004 kb
Host smart-3ddf55f9-5e4f-4057-ac43-5a73d1cff1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099683474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1099683474
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4031270372
Short name T1050
Test name
Test status
Simulation time 27178968 ps
CPU time 0.7 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 206008 kb
Host smart-61c5d14d-0316-47e9-815d-b565c558ec6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031270372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4031270372
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2538519980
Short name T1041
Test name
Test status
Simulation time 22650130 ps
CPU time 0.81 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 205976 kb
Host smart-2374d390-06f6-4223-a04a-339c655302e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538519980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2538519980
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1045501617
Short name T933
Test name
Test status
Simulation time 10418597 ps
CPU time 0.83 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:06 PM PDT 24
Peak memory 206004 kb
Host smart-3bd47989-5c99-45a4-bd72-9820635a8ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045501617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1045501617
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4282503551
Short name T986
Test name
Test status
Simulation time 11840723 ps
CPU time 0.89 seconds
Started Jul 22 06:11:01 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 206012 kb
Host smart-14c57906-d34a-44dd-bc68-6f81c486b95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282503551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4282503551
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1230323527
Short name T1061
Test name
Test status
Simulation time 11712298 ps
CPU time 0.69 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:04 PM PDT 24
Peak memory 205892 kb
Host smart-75090f1b-3b12-414f-8538-cf51847f9696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230323527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1230323527
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.681078482
Short name T940
Test name
Test status
Simulation time 36951012 ps
CPU time 0.73 seconds
Started Jul 22 06:11:01 PM PDT 24
Finished Jul 22 06:11:02 PM PDT 24
Peak memory 205960 kb
Host smart-71ca924d-1529-4d16-9b05-720e3187f6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681078482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.681078482
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3222217583
Short name T1085
Test name
Test status
Simulation time 9888713 ps
CPU time 0.82 seconds
Started Jul 22 06:11:01 PM PDT 24
Finished Jul 22 06:11:02 PM PDT 24
Peak memory 206000 kb
Host smart-986c6077-16ff-43a2-9d20-ddb401e7bdd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222217583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3222217583
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2507995556
Short name T202
Test name
Test status
Simulation time 47601686 ps
CPU time 1.49 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 214436 kb
Host smart-c8178314-2d96-448d-9f1e-7d6109341905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507995556 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2507995556
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2024885656
Short name T1068
Test name
Test status
Simulation time 43604424 ps
CPU time 1.05 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 206140 kb
Host smart-d9609f61-1aa1-47a8-a69e-f92b72a59a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024885656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2024885656
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3666655596
Short name T997
Test name
Test status
Simulation time 43511865 ps
CPU time 0.7 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:40 PM PDT 24
Peak memory 205964 kb
Host smart-5881e4b8-0491-4c83-afbf-526f86598793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666655596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3666655596
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3541563420
Short name T159
Test name
Test status
Simulation time 56768746 ps
CPU time 1.45 seconds
Started Jul 22 06:12:23 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 206104 kb
Host smart-40ec65e0-dd55-4e07-87c9-8f79d178bf94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541563420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3541563420
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1339155222
Short name T952
Test name
Test status
Simulation time 344281599 ps
CPU time 3.6 seconds
Started Jul 22 06:10:37 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 214616 kb
Host smart-31d68735-40f4-42f6-a052-57811cdcd697
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339155222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1339155222
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1912492910
Short name T950
Test name
Test status
Simulation time 244844855 ps
CPU time 1.73 seconds
Started Jul 22 06:10:40 PM PDT 24
Finished Jul 22 06:10:42 PM PDT 24
Peak memory 214336 kb
Host smart-3415c4e6-a038-4358-a47e-eb28627f5e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912492910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1912492910
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4286688112
Short name T193
Test name
Test status
Simulation time 543734215 ps
CPU time 3.79 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 215396 kb
Host smart-1f1f64b0-90c1-4411-83c3-81014e6700a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286688112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4286688112
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1720073788
Short name T1079
Test name
Test status
Simulation time 25270511 ps
CPU time 1.54 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 214500 kb
Host smart-07b57593-2bc0-4764-ad0a-30e4b3a0ece9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720073788 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1720073788
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1743260404
Short name T989
Test name
Test status
Simulation time 114881764 ps
CPU time 1.05 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:40 PM PDT 24
Peak memory 206144 kb
Host smart-a37084fb-4cc5-445b-ad09-2e3332223e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743260404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1743260404
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.944682603
Short name T1006
Test name
Test status
Simulation time 11222294 ps
CPU time 0.74 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 205960 kb
Host smart-1d53f0de-61ed-40cb-b7c2-03da8f94189a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944682603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.944682603
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4081425214
Short name T1029
Test name
Test status
Simulation time 21898262 ps
CPU time 1.49 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 206200 kb
Host smart-f7011128-3dae-46fc-9d1e-8daf40b34cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081425214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4081425214
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2979507371
Short name T996
Test name
Test status
Simulation time 75512498 ps
CPU time 2.59 seconds
Started Jul 22 06:13:45 PM PDT 24
Finished Jul 22 06:13:48 PM PDT 24
Peak memory 214676 kb
Host smart-c2ddaaa3-0e94-423d-9aea-0f30215993b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979507371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2979507371
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.565147460
Short name T1028
Test name
Test status
Simulation time 88656324 ps
CPU time 3.2 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 220580 kb
Host smart-ec1eac42-f990-40ee-bd3e-04048fa8c0cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565147460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.565147460
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1984878583
Short name T1072
Test name
Test status
Simulation time 225598210 ps
CPU time 4.24 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:12:31 PM PDT 24
Peak memory 214268 kb
Host smart-f50e414c-53ab-4a71-879d-db7d4366251a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984878583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1984878583
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.837257189
Short name T1034
Test name
Test status
Simulation time 554899482 ps
CPU time 1.37 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 214532 kb
Host smart-f360b695-96d2-4387-95ff-1b739a7eb38a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837257189 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.837257189
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3275988777
Short name T1009
Test name
Test status
Simulation time 26249715 ps
CPU time 1.14 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 206160 kb
Host smart-6fe8d05e-230d-4240-88b9-8583c32a4ebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275988777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3275988777
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3230809012
Short name T999
Test name
Test status
Simulation time 30469759 ps
CPU time 0.78 seconds
Started Jul 22 06:13:44 PM PDT 24
Finished Jul 22 06:13:45 PM PDT 24
Peak memory 206004 kb
Host smart-95881cc2-0db3-47a1-85a1-b6e6a78fedfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230809012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3230809012
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3040909573
Short name T982
Test name
Test status
Simulation time 30405425 ps
CPU time 1.89 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 206208 kb
Host smart-9cb93274-d85a-4b16-be6e-0d4102864bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040909573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3040909573
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3719255064
Short name T135
Test name
Test status
Simulation time 477258203 ps
CPU time 3.57 seconds
Started Jul 22 06:10:38 PM PDT 24
Finished Jul 22 06:10:43 PM PDT 24
Peak memory 218904 kb
Host smart-bf33fa76-d64f-421b-ac86-2ca02c88a426
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719255064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3719255064
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2905221055
Short name T134
Test name
Test status
Simulation time 475513380 ps
CPU time 6.52 seconds
Started Jul 22 06:13:44 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 214672 kb
Host smart-6e1c51e3-4a74-46e4-b0a1-ddd0f600d339
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905221055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2905221055
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1472590419
Short name T1058
Test name
Test status
Simulation time 149741724 ps
CPU time 3.44 seconds
Started Jul 22 06:10:36 PM PDT 24
Finished Jul 22 06:10:40 PM PDT 24
Peak memory 214440 kb
Host smart-bd429f48-cbea-42a5-80bd-f220c800c211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472590419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1472590419
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1684692511
Short name T189
Test name
Test status
Simulation time 55216909 ps
CPU time 2.48 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:42 PM PDT 24
Peak memory 206160 kb
Host smart-180fe2d7-8c74-4b82-b71f-cfdb9dfb9b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684692511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1684692511
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3856197
Short name T960
Test name
Test status
Simulation time 35889506 ps
CPU time 2.1 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 214456 kb
Host smart-ec1acff5-b583-43ab-86d0-0d87cd1b76e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856197 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3856197
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3275361465
Short name T942
Test name
Test status
Simulation time 64610568 ps
CPU time 0.88 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:40 PM PDT 24
Peak memory 206128 kb
Host smart-0f3fe674-9e66-4056-bf13-c0395bded994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275361465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3275361465
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3269797842
Short name T994
Test name
Test status
Simulation time 13446883 ps
CPU time 0.73 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 205860 kb
Host smart-be4ae63c-3d64-43ec-801b-8566a5952072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269797842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3269797842
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3230765792
Short name T1001
Test name
Test status
Simulation time 94259260 ps
CPU time 1.41 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 206224 kb
Host smart-d462573f-69c8-458a-98dd-340d4538fab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230765792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3230765792
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2602171313
Short name T983
Test name
Test status
Simulation time 224680108 ps
CPU time 3.39 seconds
Started Jul 22 06:10:42 PM PDT 24
Finished Jul 22 06:10:46 PM PDT 24
Peak memory 214576 kb
Host smart-c76490bf-6557-46dc-ba44-b344296e7575
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602171313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2602171313
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3721569968
Short name T127
Test name
Test status
Simulation time 228706734 ps
CPU time 7.81 seconds
Started Jul 22 06:10:39 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 220824 kb
Host smart-1d90bc6e-f671-4163-a9ef-a46f9f6452c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721569968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3721569968
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1924243045
Short name T944
Test name
Test status
Simulation time 320980461 ps
CPU time 2.92 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 214428 kb
Host smart-0cb0dc39-782b-4db3-b74b-4555f199bdd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924243045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1924243045
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2071474687
Short name T190
Test name
Test status
Simulation time 98353848 ps
CPU time 3.06 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:12:30 PM PDT 24
Peak memory 206192 kb
Host smart-8da33b1d-60a8-487d-8eb6-013e8801a3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071474687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2071474687
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3747466689
Short name T953
Test name
Test status
Simulation time 77322896 ps
CPU time 1.63 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:47 PM PDT 24
Peak memory 206316 kb
Host smart-92bc00ea-cd72-438e-af48-cfadec06229f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747466689 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3747466689
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1786703161
Short name T1019
Test name
Test status
Simulation time 34789133 ps
CPU time 1.19 seconds
Started Jul 22 06:11:21 PM PDT 24
Finished Jul 22 06:11:22 PM PDT 24
Peak memory 206168 kb
Host smart-9874f9e8-74bd-4a92-bfbe-fd08362e86d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786703161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1786703161
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3598329446
Short name T1055
Test name
Test status
Simulation time 8136516 ps
CPU time 0.75 seconds
Started Jul 22 06:10:43 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 205976 kb
Host smart-7afb9aab-bb76-4671-8e24-094bdf22de3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598329446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3598329446
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1787574730
Short name T157
Test name
Test status
Simulation time 253703878 ps
CPU time 2.55 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:48 PM PDT 24
Peak memory 206212 kb
Host smart-1fbd088c-12c4-4009-b30a-6c2b25caeed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787574730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1787574730
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.47245526
Short name T1002
Test name
Test status
Simulation time 97278893 ps
CPU time 1.42 seconds
Started Jul 22 06:10:47 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 214588 kb
Host smart-2395bcc8-42c0-461f-98b8-6dba39c31297
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47245526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_
reg_errors.47245526
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2052623372
Short name T969
Test name
Test status
Simulation time 197820137 ps
CPU time 6.61 seconds
Started Jul 22 06:10:46 PM PDT 24
Finished Jul 22 06:10:53 PM PDT 24
Peak memory 214572 kb
Host smart-53c38f55-8880-4019-bcb5-a58d892e8f69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052623372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2052623372
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.605085226
Short name T1022
Test name
Test status
Simulation time 22069509 ps
CPU time 1.67 seconds
Started Jul 22 06:10:47 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 214440 kb
Host smart-0c7ae070-73c8-45b4-926e-cc341636b04d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605085226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.605085226
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4202389
Short name T947
Test name
Test status
Simulation time 113328572 ps
CPU time 4.68 seconds
Started Jul 22 06:10:45 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 206168 kb
Host smart-c5356157-8e54-4de3-90e8-7489a1c82778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.4202389
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3142875993
Short name T22
Test name
Test status
Simulation time 235351732 ps
CPU time 1.78 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:17 PM PDT 24
Peak memory 208172 kb
Host smart-6ea0b73d-3d51-4909-a012-34bbefca2863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142875993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3142875993
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.194314955
Short name T327
Test name
Test status
Simulation time 50517883 ps
CPU time 2.12 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 208744 kb
Host smart-398a130b-b3b8-44d6-bdea-6a69b4755f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194314955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.194314955
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2126141901
Short name T388
Test name
Test status
Simulation time 76249201 ps
CPU time 2.84 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 222264 kb
Host smart-1675af42-c2be-4513-8005-10d3168780e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126141901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2126141901
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.263730847
Short name T741
Test name
Test status
Simulation time 603266767 ps
CPU time 4.45 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:21 PM PDT 24
Peak memory 209636 kb
Host smart-437ca770-54dc-43aa-b0f5-f2545555c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263730847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.263730847
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1037666732
Short name T150
Test name
Test status
Simulation time 297297187 ps
CPU time 4.99 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:19 PM PDT 24
Peak memory 208064 kb
Host smart-09682037-9004-42c2-b25d-57a3d4da8740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037666732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1037666732
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1740296004
Short name T44
Test name
Test status
Simulation time 1829943038 ps
CPU time 15.83 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:30 PM PDT 24
Peak memory 232152 kb
Host smart-5bba040c-ffb4-45a2-85b7-ab6a2847542e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740296004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1740296004
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.667459435
Short name T83
Test name
Test status
Simulation time 2285740577 ps
CPU time 7.82 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 208556 kb
Host smart-fdaf4357-292e-4f74-9f18-cdf165836360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667459435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.667459435
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4164654294
Short name T698
Test name
Test status
Simulation time 552536195 ps
CPU time 5.33 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:20 PM PDT 24
Peak memory 207680 kb
Host smart-fec8634b-f32d-4aad-8287-a44b5f9bfeec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164654294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4164654294
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1725584244
Short name T615
Test name
Test status
Simulation time 171656844 ps
CPU time 4.03 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:17 PM PDT 24
Peak memory 206592 kb
Host smart-631ceccb-7878-4346-b462-c312cb571b9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725584244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1725584244
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.297692091
Short name T644
Test name
Test status
Simulation time 625155434 ps
CPU time 3.14 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 206748 kb
Host smart-318fee22-c2dd-43ab-8684-9c5169d4d174
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297692091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.297692091
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.899087069
Short name T422
Test name
Test status
Simulation time 211345098 ps
CPU time 2.35 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:17 PM PDT 24
Peak memory 208828 kb
Host smart-fd96cf46-7c63-4bcc-871a-7d00b1b01a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899087069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.899087069
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3498190977
Short name T221
Test name
Test status
Simulation time 108612600 ps
CPU time 2.8 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 206640 kb
Host smart-bec7bd32-89fa-4525-8858-f878bd7b7b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498190977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3498190977
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1394779318
Short name T253
Test name
Test status
Simulation time 2035474539 ps
CPU time 45.28 seconds
Started Jul 22 07:12:32 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 216328 kb
Host smart-200ee170-af02-40e5-a970-2f45c95d037c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394779318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1394779318
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4125989044
Short name T652
Test name
Test status
Simulation time 146288835 ps
CPU time 4.68 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 207356 kb
Host smart-1f9a9c51-8052-48f6-9597-f6d76fd8d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125989044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4125989044
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1553500175
Short name T403
Test name
Test status
Simulation time 119793843 ps
CPU time 1.66 seconds
Started Jul 22 07:12:32 PM PDT 24
Finished Jul 22 07:13:20 PM PDT 24
Peak memory 209628 kb
Host smart-257eed1b-1c7e-4a76-9336-a74432b771eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553500175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1553500175
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1872356374
Short name T654
Test name
Test status
Simulation time 7562628 ps
CPU time 0.78 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:15 PM PDT 24
Peak memory 205848 kb
Host smart-2a08e310-b08c-439a-a674-0195ecfbaf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872356374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1872356374
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3020759064
Short name T858
Test name
Test status
Simulation time 141670368 ps
CPU time 2.45 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 214156 kb
Host smart-adac33f7-1fac-46db-99e5-caad615cc3fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020759064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3020759064
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2327606944
Short name T782
Test name
Test status
Simulation time 147757259 ps
CPU time 2.21 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 222564 kb
Host smart-5b854636-4fb5-4463-86ff-8e2ba64b133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327606944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2327606944
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.687219054
Short name T322
Test name
Test status
Simulation time 76376012 ps
CPU time 1.85 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 207380 kb
Host smart-902bf0bb-21b0-4ea0-b371-d70a54b4a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687219054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.687219054
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1782967981
Short name T330
Test name
Test status
Simulation time 70298746 ps
CPU time 3.49 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:19 PM PDT 24
Peak memory 214000 kb
Host smart-8357f468-0110-4369-b12b-e933c70aaede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782967981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1782967981
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1682412543
Short name T48
Test name
Test status
Simulation time 857369405 ps
CPU time 5.3 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:19 PM PDT 24
Peak memory 219508 kb
Host smart-fc83a8f7-e0e1-43a1-b07e-fdb8fc16fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682412543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1682412543
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1594645377
Short name T337
Test name
Test status
Simulation time 273084573 ps
CPU time 9.66 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 214056 kb
Host smart-323d14fa-0778-4b42-af82-3ba3f4b5e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594645377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1594645377
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2109280112
Short name T13
Test name
Test status
Simulation time 1109739169 ps
CPU time 9.28 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 230848 kb
Host smart-cd30e9fa-15b5-40de-8b60-624e0d8f4a12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109280112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2109280112
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3523254511
Short name T236
Test name
Test status
Simulation time 31169537 ps
CPU time 2.29 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 206720 kb
Host smart-c9134194-a30e-4ff5-8446-80dab3b636cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523254511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3523254511
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3610428954
Short name T603
Test name
Test status
Simulation time 75667069 ps
CPU time 2.54 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 208240 kb
Host smart-fadf2119-f113-49b0-97a0-2af50eb01750
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610428954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3610428954
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4141651939
Short name T286
Test name
Test status
Simulation time 191334507 ps
CPU time 3.41 seconds
Started Jul 22 07:12:53 PM PDT 24
Finished Jul 22 07:13:43 PM PDT 24
Peak memory 208316 kb
Host smart-beeba0dd-78e4-46b5-9d52-36f69361144e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141651939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4141651939
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.643646512
Short name T786
Test name
Test status
Simulation time 108871803 ps
CPU time 2.17 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 208420 kb
Host smart-bb8448be-dbed-4b31-adb2-1c73301bba67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643646512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.643646512
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1554389586
Short name T237
Test name
Test status
Simulation time 119933546 ps
CPU time 3.14 seconds
Started Jul 22 07:12:32 PM PDT 24
Finished Jul 22 07:13:21 PM PDT 24
Peak memory 214020 kb
Host smart-7f45edc2-a932-42fa-8176-ae51bd108a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554389586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1554389586
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2577644693
Short name T578
Test name
Test status
Simulation time 4379403375 ps
CPU time 21.63 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 208632 kb
Host smart-bd59bfb7-ce3a-41aa-8f69-b960ea9c57b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577644693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2577644693
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3998208723
Short name T139
Test name
Test status
Simulation time 2088295082 ps
CPU time 22.64 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:38 PM PDT 24
Peak memory 222368 kb
Host smart-c8a32417-01d1-4df8-a2b6-72ac399ab22c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998208723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3998208723
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.760708939
Short name T755
Test name
Test status
Simulation time 928299513 ps
CPU time 4.98 seconds
Started Jul 22 07:12:53 PM PDT 24
Finished Jul 22 07:13:45 PM PDT 24
Peak memory 208752 kb
Host smart-ae43b16c-3c22-4518-b050-f7dcd699f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760708939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.760708939
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4262552331
Short name T400
Test name
Test status
Simulation time 123769738 ps
CPU time 3.01 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 210024 kb
Host smart-54858ee6-4e00-49a5-ba0a-97bc89afe901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262552331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4262552331
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4205037211
Short name T914
Test name
Test status
Simulation time 14966913 ps
CPU time 0.72 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:18 PM PDT 24
Peak memory 205808 kb
Host smart-b6aa94ea-8abe-4314-82cd-f22fc420c1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205037211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4205037211
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.61217287
Short name T111
Test name
Test status
Simulation time 286453464 ps
CPU time 2.93 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:04 PM PDT 24
Peak memory 221700 kb
Host smart-bdc1d9ae-a3fd-4e3c-b35c-99948d10ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61217287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.61217287
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4248764476
Short name T319
Test name
Test status
Simulation time 355291623 ps
CPU time 3.95 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:04 PM PDT 24
Peak memory 210016 kb
Host smart-512c7292-b8ae-4e39-9545-608a197fd72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248764476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4248764476
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.474609065
Short name T909
Test name
Test status
Simulation time 93754438 ps
CPU time 4.03 seconds
Started Jul 22 07:13:16 PM PDT 24
Finished Jul 22 07:14:09 PM PDT 24
Peak memory 218072 kb
Host smart-1ba3a020-5bbd-4b5e-8aea-8988e61422c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474609065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.474609065
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.548583882
Short name T558
Test name
Test status
Simulation time 4394573503 ps
CPU time 27.39 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:30 PM PDT 24
Peak memory 208404 kb
Host smart-0a3545c2-0ef8-4460-931e-3e07f247f320
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548583882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.548583882
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2560575054
Short name T638
Test name
Test status
Simulation time 1853495488 ps
CPU time 8.95 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:11 PM PDT 24
Peak memory 208804 kb
Host smart-7a51d1db-cbe1-46ca-a687-ef73356ca26a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560575054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2560575054
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3992989453
Short name T226
Test name
Test status
Simulation time 247789768 ps
CPU time 2.61 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 214100 kb
Host smart-b9abe742-512e-4591-8e48-3664274c10d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992989453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3992989453
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3357132601
Short name T821
Test name
Test status
Simulation time 102980612 ps
CPU time 2.04 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 208244 kb
Host smart-d15c2e44-42f9-42d7-86c1-443e6ea665bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357132601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3357132601
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4132777318
Short name T357
Test name
Test status
Simulation time 169103624 ps
CPU time 11.5 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:31 PM PDT 24
Peak memory 220548 kb
Host smart-bd911dac-52a0-494b-949e-2108496ce33b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132777318 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4132777318
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4280082991
Short name T557
Test name
Test status
Simulation time 207262419 ps
CPU time 4.45 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:05 PM PDT 24
Peak memory 209016 kb
Host smart-dd157591-9617-4254-a83f-6766edfb1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280082991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4280082991
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1258049606
Short name T891
Test name
Test status
Simulation time 86227679 ps
CPU time 1.74 seconds
Started Jul 22 07:13:33 PM PDT 24
Finished Jul 22 07:14:26 PM PDT 24
Peak memory 210088 kb
Host smart-50cc45f4-fae4-4a43-b77e-9f5e7533bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258049606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1258049606
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.559171101
Short name T439
Test name
Test status
Simulation time 203530312 ps
CPU time 0.76 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:21 PM PDT 24
Peak memory 205928 kb
Host smart-eae5e550-f030-418e-8b49-270ae5b049f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559171101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.559171101
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3842754303
Short name T29
Test name
Test status
Simulation time 2473160644 ps
CPU time 30.69 seconds
Started Jul 22 07:14:21 PM PDT 24
Finished Jul 22 07:15:30 PM PDT 24
Peak memory 214576 kb
Host smart-b0ba5f38-492f-441f-a71b-804ca2d4f6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842754303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3842754303
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.764957755
Short name T684
Test name
Test status
Simulation time 95457104 ps
CPU time 2.63 seconds
Started Jul 22 07:13:25 PM PDT 24
Finished Jul 22 07:14:19 PM PDT 24
Peak memory 207024 kb
Host smart-5eafb328-4ed4-4504-a9a0-df40b4d0e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764957755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.764957755
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2476430453
Short name T625
Test name
Test status
Simulation time 67599148 ps
CPU time 3.39 seconds
Started Jul 22 07:13:28 PM PDT 24
Finished Jul 22 07:14:23 PM PDT 24
Peak memory 214116 kb
Host smart-64764327-8f1b-41f8-aefd-f2287ea90b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476430453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2476430453
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4087760496
Short name T769
Test name
Test status
Simulation time 136737830 ps
CPU time 4.59 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:22 PM PDT 24
Peak memory 213960 kb
Host smart-ca6628e4-b7e2-4c21-af2e-a03ee7c85408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087760496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4087760496
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4153350808
Short name T764
Test name
Test status
Simulation time 36577747 ps
CPU time 2.38 seconds
Started Jul 22 07:13:32 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 207596 kb
Host smart-6d50fa6a-5cab-4617-ad04-09d5de0d444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153350808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4153350808
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.718840545
Short name T383
Test name
Test status
Simulation time 107598725 ps
CPU time 3.53 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:24 PM PDT 24
Peak memory 217760 kb
Host smart-dd606b2c-5843-459f-bba5-b9314cec98a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718840545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.718840545
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2515072613
Short name T781
Test name
Test status
Simulation time 177156523 ps
CPU time 2.58 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:19 PM PDT 24
Peak memory 206608 kb
Host smart-bab67d27-93f2-47d4-8f9b-e7fb70c0e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515072613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2515072613
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.228239848
Short name T829
Test name
Test status
Simulation time 151630444 ps
CPU time 2.12 seconds
Started Jul 22 07:13:51 PM PDT 24
Finished Jul 22 07:14:44 PM PDT 24
Peak memory 206748 kb
Host smart-f33928cd-43f8-401c-aac5-30856acc3766
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228239848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.228239848
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2913276574
Short name T344
Test name
Test status
Simulation time 160548014 ps
CPU time 1.76 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:20 PM PDT 24
Peak memory 206624 kb
Host smart-aa8c454a-23c2-4f07-ab3c-279c456ee134
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913276574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2913276574
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.157220297
Short name T513
Test name
Test status
Simulation time 306415974 ps
CPU time 3.42 seconds
Started Jul 22 07:13:24 PM PDT 24
Finished Jul 22 07:14:19 PM PDT 24
Peak memory 208256 kb
Host smart-0ad49087-eaff-4a75-b661-080d4a4169f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157220297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.157220297
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1707787448
Short name T573
Test name
Test status
Simulation time 58094682 ps
CPU time 2.43 seconds
Started Jul 22 07:13:33 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 215688 kb
Host smart-a2c18b29-945a-4282-91a3-61714a56817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707787448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1707787448
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1705543412
Short name T483
Test name
Test status
Simulation time 47819092 ps
CPU time 2.09 seconds
Started Jul 22 07:13:28 PM PDT 24
Finished Jul 22 07:14:22 PM PDT 24
Peak memory 206600 kb
Host smart-5935f255-a93d-4215-b7a7-fa15811714c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705543412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1705543412
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4190480956
Short name T842
Test name
Test status
Simulation time 216833818 ps
CPU time 7.83 seconds
Started Jul 22 07:13:30 PM PDT 24
Finished Jul 22 07:14:29 PM PDT 24
Peak memory 214848 kb
Host smart-c1214db8-8f19-4c0c-b1fc-927f4f6593bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190480956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4190480956
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1208876148
Short name T649
Test name
Test status
Simulation time 956545292 ps
CPU time 10.69 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:31 PM PDT 24
Peak memory 222328 kb
Host smart-95da8761-5a6a-4825-938e-e46a76576b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208876148 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1208876148
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.698916968
Short name T586
Test name
Test status
Simulation time 517646117 ps
CPU time 3.98 seconds
Started Jul 22 07:13:30 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 207864 kb
Host smart-136a6594-3afc-402e-b2f9-754bdc0e4955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698916968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.698916968
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1119145988
Short name T874
Test name
Test status
Simulation time 120087353 ps
CPU time 1.74 seconds
Started Jul 22 07:13:28 PM PDT 24
Finished Jul 22 07:14:21 PM PDT 24
Peak memory 209804 kb
Host smart-fff9d554-0d99-43b9-b592-e99636c6c8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119145988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1119145988
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3722305189
Short name T114
Test name
Test status
Simulation time 41589739 ps
CPU time 0.71 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:18 PM PDT 24
Peak memory 205808 kb
Host smart-c5c1e5e0-4b02-4540-8fe8-897a1ec34582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722305189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3722305189
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4071554992
Short name T199
Test name
Test status
Simulation time 232723838 ps
CPU time 2.84 seconds
Started Jul 22 07:13:26 PM PDT 24
Finished Jul 22 07:14:20 PM PDT 24
Peak memory 219088 kb
Host smart-5cb8a0ab-e613-43a0-b5cd-e0b3ca532a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071554992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4071554992
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3819401479
Short name T809
Test name
Test status
Simulation time 199524601 ps
CPU time 2.17 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:22 PM PDT 24
Peak memory 221956 kb
Host smart-4bd0d06a-d0b4-492c-9ba3-415d15a962c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819401479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3819401479
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3712910237
Short name T108
Test name
Test status
Simulation time 2176365063 ps
CPU time 5.97 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 214360 kb
Host smart-df5d9def-89a0-417b-b662-7c3d05bb455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712910237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3712910237
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.999774075
Short name T903
Test name
Test status
Simulation time 983036961 ps
CPU time 7.96 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:27 PM PDT 24
Peak memory 222204 kb
Host smart-7bdf5b43-c86a-44a7-a551-34fcf074b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999774075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.999774075
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.623459031
Short name T700
Test name
Test status
Simulation time 235960083 ps
CPU time 6.87 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:27 PM PDT 24
Peak memory 219784 kb
Host smart-712b3c86-f2cd-4651-93f9-f3e275c65b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623459031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.623459031
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3584943363
Short name T458
Test name
Test status
Simulation time 2793164919 ps
CPU time 7.6 seconds
Started Jul 22 07:13:33 PM PDT 24
Finished Jul 22 07:14:31 PM PDT 24
Peak memory 208180 kb
Host smart-539195be-4f68-4bb1-b28d-85aa53a96c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584943363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3584943363
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.381816186
Short name T305
Test name
Test status
Simulation time 371028414 ps
CPU time 4.45 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:22 PM PDT 24
Peak memory 207324 kb
Host smart-d65c4351-01ed-4f78-a6a6-cdf8be58f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381816186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.381816186
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1396767789
Short name T474
Test name
Test status
Simulation time 2426326678 ps
CPU time 30.15 seconds
Started Jul 22 07:13:30 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 208516 kb
Host smart-957ec373-da34-41fa-bcde-81d6c0236010
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396767789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1396767789
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.292792172
Short name T614
Test name
Test status
Simulation time 877700626 ps
CPU time 4.97 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 206600 kb
Host smart-c82f2b08-a616-473e-a9a3-95b87756d04a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292792172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.292792172
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.541164099
Short name T522
Test name
Test status
Simulation time 249511588 ps
CPU time 7.72 seconds
Started Jul 22 07:13:33 PM PDT 24
Finished Jul 22 07:14:30 PM PDT 24
Peak memory 208304 kb
Host smart-b23b97d9-bf88-4309-a9f3-35e94780e51f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541164099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.541164099
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2875707600
Short name T753
Test name
Test status
Simulation time 210721965 ps
CPU time 2.91 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:23 PM PDT 24
Peak memory 208896 kb
Host smart-e3236096-7680-4667-9c21-c7c41465f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875707600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2875707600
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1159841910
Short name T166
Test name
Test status
Simulation time 414307532 ps
CPU time 4.16 seconds
Started Jul 22 07:13:30 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 206656 kb
Host smart-233b3b41-373c-4596-9132-87eb117e1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159841910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1159841910
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3085508549
Short name T382
Test name
Test status
Simulation time 800539707 ps
CPU time 10.89 seconds
Started Jul 22 07:13:32 PM PDT 24
Finished Jul 22 07:14:34 PM PDT 24
Peak memory 216088 kb
Host smart-da0e35bd-8ffa-4180-8f24-f952fe91b03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085508549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3085508549
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1735090214
Short name T771
Test name
Test status
Simulation time 2161082795 ps
CPU time 9.86 seconds
Started Jul 22 07:13:28 PM PDT 24
Finished Jul 22 07:14:29 PM PDT 24
Peak memory 207456 kb
Host smart-1b9ce452-1596-48d9-b303-2036868152b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735090214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1735090214
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3460411749
Short name T595
Test name
Test status
Simulation time 199152188 ps
CPU time 2.06 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:14:23 PM PDT 24
Peak memory 209828 kb
Host smart-0e35ab55-c783-4edb-87a9-a8bc3c876788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460411749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3460411749
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1626806584
Short name T832
Test name
Test status
Simulation time 24950648 ps
CPU time 0.89 seconds
Started Jul 22 07:13:40 PM PDT 24
Finished Jul 22 07:14:36 PM PDT 24
Peak memory 205900 kb
Host smart-631f4899-662d-4427-923b-22718a104905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626806584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1626806584
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3651829041
Short name T206
Test name
Test status
Simulation time 61374155 ps
CPU time 4.32 seconds
Started Jul 22 07:13:32 PM PDT 24
Finished Jul 22 07:14:27 PM PDT 24
Peak memory 214048 kb
Host smart-d6f249f6-48b0-4c3a-a6ff-bf6312af05a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651829041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3651829041
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3096258049
Short name T245
Test name
Test status
Simulation time 57110434 ps
CPU time 2.41 seconds
Started Jul 22 07:13:51 PM PDT 24
Finished Jul 22 07:14:45 PM PDT 24
Peak memory 215420 kb
Host smart-670ca135-c1f1-4012-a091-0c9b5a91a3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096258049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3096258049
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3763862754
Short name T757
Test name
Test status
Simulation time 118102780 ps
CPU time 1.88 seconds
Started Jul 22 07:13:28 PM PDT 24
Finished Jul 22 07:14:22 PM PDT 24
Peak memory 209768 kb
Host smart-5a9903cb-7dfe-4b53-9527-6f4ea114c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763862754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3763862754
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1519352620
Short name T702
Test name
Test status
Simulation time 98687159 ps
CPU time 3.47 seconds
Started Jul 22 07:13:52 PM PDT 24
Finished Jul 22 07:14:46 PM PDT 24
Peak memory 208400 kb
Host smart-e195712a-d449-42b5-8571-392ef5cc3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519352620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1519352620
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1925240509
Short name T807
Test name
Test status
Simulation time 214636613 ps
CPU time 4.03 seconds
Started Jul 22 07:13:40 PM PDT 24
Finished Jul 22 07:14:40 PM PDT 24
Peak memory 214748 kb
Host smart-2d2fffdc-bf8c-404c-a119-5405298ee97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925240509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1925240509
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3376757378
Short name T659
Test name
Test status
Simulation time 231907716 ps
CPU time 3.77 seconds
Started Jul 22 07:13:32 PM PDT 24
Finished Jul 22 07:14:26 PM PDT 24
Peak memory 207516 kb
Host smart-ef6ef22d-af75-4159-8378-14245a3ee54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376757378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3376757378
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2221014877
Short name T848
Test name
Test status
Simulation time 194011317 ps
CPU time 2.69 seconds
Started Jul 22 07:13:30 PM PDT 24
Finished Jul 22 07:14:24 PM PDT 24
Peak memory 206584 kb
Host smart-1e06792a-7089-4b0c-a319-704bc97c3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221014877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2221014877
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3621633373
Short name T774
Test name
Test status
Simulation time 559517968 ps
CPU time 2.79 seconds
Started Jul 22 07:13:27 PM PDT 24
Finished Jul 22 07:14:21 PM PDT 24
Peak memory 208556 kb
Host smart-b5476cdd-c6a7-4286-ac96-ff8fbd3545bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621633373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3621633373
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.18973259
Short name T146
Test name
Test status
Simulation time 116089237 ps
CPU time 2.19 seconds
Started Jul 22 07:13:32 PM PDT 24
Finished Jul 22 07:14:25 PM PDT 24
Peak memory 206632 kb
Host smart-8774dc1d-616d-4a55-9ebc-cc536763d83d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18973259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.18973259
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3944747471
Short name T476
Test name
Test status
Simulation time 1800799929 ps
CPU time 22.18 seconds
Started Jul 22 07:13:49 PM PDT 24
Finished Jul 22 07:15:02 PM PDT 24
Peak memory 214116 kb
Host smart-a7d4ce17-ee6b-4f84-b87b-0243532c897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944747471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3944747471
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.965746565
Short name T626
Test name
Test status
Simulation time 2538402228 ps
CPU time 40.68 seconds
Started Jul 22 07:13:29 PM PDT 24
Finished Jul 22 07:15:01 PM PDT 24
Peak memory 207748 kb
Host smart-6e25f06f-8f9d-4ce7-b104-62b58284c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965746565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.965746565
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2982101504
Short name T803
Test name
Test status
Simulation time 145057576 ps
CPU time 1.5 seconds
Started Jul 22 07:13:46 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 209756 kb
Host smart-92e00321-32d3-4bac-91ee-1b294fd730ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982101504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2982101504
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.405340817
Short name T435
Test name
Test status
Simulation time 124545579 ps
CPU time 0.75 seconds
Started Jul 22 07:13:39 PM PDT 24
Finished Jul 22 07:14:35 PM PDT 24
Peak memory 205824 kb
Host smart-8a7e8fb9-f496-4e01-89c4-98f7010e0dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405340817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.405340817
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3920341472
Short name T131
Test name
Test status
Simulation time 134150947 ps
CPU time 2.84 seconds
Started Jul 22 07:13:39 PM PDT 24
Finished Jul 22 07:14:37 PM PDT 24
Peak memory 215156 kb
Host smart-3a1cbf94-0293-4fd8-bb7f-b471a084aab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920341472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3920341472
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3618186262
Short name T590
Test name
Test status
Simulation time 81091252 ps
CPU time 2.46 seconds
Started Jul 22 07:13:54 PM PDT 24
Finished Jul 22 07:14:46 PM PDT 24
Peak memory 214360 kb
Host smart-5de98819-88a7-4e3d-b3e0-a94efaf7f156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618186262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3618186262
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3479275031
Short name T660
Test name
Test status
Simulation time 83665940 ps
CPU time 1.83 seconds
Started Jul 22 07:13:39 PM PDT 24
Finished Jul 22 07:14:36 PM PDT 24
Peak memory 214096 kb
Host smart-0315d28b-a52b-4502-b932-2f49d916c56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479275031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3479275031
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.727888493
Short name T546
Test name
Test status
Simulation time 139454101 ps
CPU time 2.67 seconds
Started Jul 22 07:13:40 PM PDT 24
Finished Jul 22 07:14:38 PM PDT 24
Peak memory 209412 kb
Host smart-e11db274-c003-42f3-a5ff-185ab3c6e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727888493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.727888493
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.790009958
Short name T561
Test name
Test status
Simulation time 324253224 ps
CPU time 5.57 seconds
Started Jul 22 07:13:48 PM PDT 24
Finished Jul 22 07:14:45 PM PDT 24
Peak memory 208928 kb
Host smart-495668e6-1e73-4c10-abef-5318bb99005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790009958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.790009958
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2486937211
Short name T623
Test name
Test status
Simulation time 185478567 ps
CPU time 2.66 seconds
Started Jul 22 07:13:48 PM PDT 24
Finished Jul 22 07:14:42 PM PDT 24
Peak memory 208480 kb
Host smart-72b5b345-e90a-432c-a4f1-e255f352d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486937211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2486937211
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2735389104
Short name T620
Test name
Test status
Simulation time 88552773 ps
CPU time 3.58 seconds
Started Jul 22 07:13:45 PM PDT 24
Finished Jul 22 07:14:41 PM PDT 24
Peak memory 208324 kb
Host smart-f4cb41cb-869c-4c8d-88a5-d8e0b5708ac1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735389104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2735389104
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1281588425
Short name T785
Test name
Test status
Simulation time 26162155 ps
CPU time 2.14 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:38 PM PDT 24
Peak memory 208416 kb
Host smart-897f4cb8-f7f7-4222-ac98-5f039e8ecb7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281588425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1281588425
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1734616697
Short name T346
Test name
Test status
Simulation time 506277369 ps
CPU time 5.79 seconds
Started Jul 22 07:13:38 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 206728 kb
Host smart-311e204a-7246-4c1c-a130-cc508b4628de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734616697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1734616697
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2638675968
Short name T505
Test name
Test status
Simulation time 181107246 ps
CPU time 2.9 seconds
Started Jul 22 07:13:49 PM PDT 24
Finished Jul 22 07:14:43 PM PDT 24
Peak memory 218140 kb
Host smart-b7001acd-f271-4c5f-aaed-5c731dd67e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638675968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2638675968
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2770932952
Short name T6
Test name
Test status
Simulation time 854901459 ps
CPU time 2.81 seconds
Started Jul 22 07:13:53 PM PDT 24
Finished Jul 22 07:14:46 PM PDT 24
Peak memory 208420 kb
Host smart-33668767-017c-4164-883b-fdd99eb517a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770932952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2770932952
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3293125726
Short name T214
Test name
Test status
Simulation time 2682846449 ps
CPU time 59.42 seconds
Started Jul 22 07:14:37 PM PDT 24
Finished Jul 22 07:16:07 PM PDT 24
Peak memory 222340 kb
Host smart-7204ce0e-7cc4-468a-a1e6-da80014dbbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293125726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3293125726
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1189149870
Short name T53
Test name
Test status
Simulation time 428879094 ps
CPU time 15.96 seconds
Started Jul 22 07:13:51 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 220192 kb
Host smart-600b8794-9b4f-4f71-8d89-2c2a15570e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189149870 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1189149870
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.681839839
Short name T228
Test name
Test status
Simulation time 118265148 ps
CPU time 4.78 seconds
Started Jul 22 07:13:54 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 207928 kb
Host smart-e952a031-22da-4407-81d0-3ddd9c48b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681839839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.681839839
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.41004321
Short name T188
Test name
Test status
Simulation time 185723850 ps
CPU time 2.93 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 210180 kb
Host smart-62197ff8-3be2-485f-b194-78e2401ece2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41004321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.41004321
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3177087545
Short name T123
Test name
Test status
Simulation time 33786678 ps
CPU time 0.96 seconds
Started Jul 22 07:14:07 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 205928 kb
Host smart-939b5559-bdb8-4c3b-b721-c0debd565a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177087545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3177087545
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3041494767
Short name T77
Test name
Test status
Simulation time 505608100 ps
CPU time 2.97 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 208628 kb
Host smart-ecde7546-0500-49f9-9353-38c837ef969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041494767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3041494767
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1567130870
Short name T530
Test name
Test status
Simulation time 71933472 ps
CPU time 3.61 seconds
Started Jul 22 07:13:41 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 214148 kb
Host smart-c7b022d8-2c07-41c5-9aab-e83a5fd39cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567130870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1567130870
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2570328777
Short name T58
Test name
Test status
Simulation time 175762593 ps
CPU time 3.03 seconds
Started Jul 22 07:13:48 PM PDT 24
Finished Jul 22 07:14:42 PM PDT 24
Peak memory 219644 kb
Host smart-4310b6ed-4e86-43af-ba41-be8c92fed1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570328777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2570328777
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3144823994
Short name T386
Test name
Test status
Simulation time 362351674 ps
CPU time 9.75 seconds
Started Jul 22 07:13:39 PM PDT 24
Finished Jul 22 07:14:44 PM PDT 24
Peak memory 208992 kb
Host smart-86f4f482-25ec-467e-8a96-a828db64fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144823994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3144823994
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1365919281
Short name T629
Test name
Test status
Simulation time 517200397 ps
CPU time 3.9 seconds
Started Jul 22 07:13:39 PM PDT 24
Finished Jul 22 07:14:38 PM PDT 24
Peak memory 206456 kb
Host smart-09494b05-df60-4742-b029-070ca512316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365919281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1365919281
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1489846952
Short name T696
Test name
Test status
Simulation time 97512403 ps
CPU time 3.82 seconds
Started Jul 22 07:13:40 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 208000 kb
Host smart-66ece90e-c98c-48ab-9c2a-44d2f6d334ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489846952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1489846952
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1438746046
Short name T882
Test name
Test status
Simulation time 44329932 ps
CPU time 1.94 seconds
Started Jul 22 07:13:47 PM PDT 24
Finished Jul 22 07:14:40 PM PDT 24
Peak memory 207216 kb
Host smart-7bddf415-6bac-4edb-8d45-e19555a7915b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438746046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1438746046
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4257812448
Short name T580
Test name
Test status
Simulation time 328779753 ps
CPU time 4.14 seconds
Started Jul 22 07:13:48 PM PDT 24
Finished Jul 22 07:14:43 PM PDT 24
Peak memory 208820 kb
Host smart-16575de1-cc82-413f-a1ae-8c680a11f561
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257812448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4257812448
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3161767673
Short name T430
Test name
Test status
Simulation time 90831231 ps
CPU time 3.13 seconds
Started Jul 22 07:13:46 PM PDT 24
Finished Jul 22 07:14:41 PM PDT 24
Peak memory 208932 kb
Host smart-d9856de5-ddf8-4c2a-b352-c4d2861402f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161767673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3161767673
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1538398131
Short name T486
Test name
Test status
Simulation time 219053577 ps
CPU time 4.56 seconds
Started Jul 22 07:13:54 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 206448 kb
Host smart-5c6baa79-0797-4502-bf3d-8f4ab4bcb235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538398131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1538398131
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4218003293
Short name T312
Test name
Test status
Simulation time 423597099 ps
CPU time 3.77 seconds
Started Jul 22 07:13:42 PM PDT 24
Finished Jul 22 07:14:40 PM PDT 24
Peak memory 209088 kb
Host smart-836f1bbc-8dff-4021-a466-619c39672991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218003293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4218003293
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2131479569
Short name T399
Test name
Test status
Simulation time 28704687 ps
CPU time 1.25 seconds
Started Jul 22 07:13:50 PM PDT 24
Finished Jul 22 07:14:43 PM PDT 24
Peak memory 209428 kb
Host smart-cfa1a693-7a9f-4249-b488-7e47234f890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131479569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2131479569
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1362297789
Short name T648
Test name
Test status
Simulation time 24321272 ps
CPU time 0.77 seconds
Started Jul 22 07:13:57 PM PDT 24
Finished Jul 22 07:14:47 PM PDT 24
Peak memory 205896 kb
Host smart-90a5740c-d16b-43d4-9bc5-039fd26c4f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362297789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1362297789
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.885094538
Short name T869
Test name
Test status
Simulation time 133609579 ps
CPU time 4.96 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 218960 kb
Host smart-e16536d1-6b85-4beb-8d73-5fbab4a5f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885094538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.885094538
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.266719327
Short name T721
Test name
Test status
Simulation time 38170001 ps
CPU time 2.27 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 207552 kb
Host smart-070504b6-fdea-4561-99f1-f7abfe11df6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266719327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.266719327
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4077181807
Short name T689
Test name
Test status
Simulation time 43015720 ps
CPU time 1.89 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 214036 kb
Host smart-a4e42150-847e-419e-8627-5ae121389dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077181807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4077181807
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2734509655
Short name T15
Test name
Test status
Simulation time 30225235 ps
CPU time 1.95 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:14:47 PM PDT 24
Peak memory 213996 kb
Host smart-9e631c9b-8ec8-4adf-9d8e-e881400fa4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734509655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2734509655
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2239321233
Short name T759
Test name
Test status
Simulation time 106856828 ps
CPU time 4.3 seconds
Started Jul 22 07:13:57 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 208996 kb
Host smart-76ca49d9-fb22-4a88-a8ea-49602e872f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239321233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2239321233
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3609255852
Short name T668
Test name
Test status
Simulation time 245086604 ps
CPU time 6.88 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 208944 kb
Host smart-91eb9350-14d2-4b5e-8099-0efe4a9a7f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609255852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3609255852
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1955954812
Short name T604
Test name
Test status
Simulation time 102065451 ps
CPU time 3.47 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 206452 kb
Host smart-42bad9d9-2803-4c7a-a7e1-cf803683f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955954812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1955954812
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3028772013
Short name T675
Test name
Test status
Simulation time 2088954282 ps
CPU time 7.13 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 208484 kb
Host smart-d4d0dcad-2a89-4337-a2ec-c256ba6b0b82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028772013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3028772013
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2129043617
Short name T730
Test name
Test status
Simulation time 389280369 ps
CPU time 2.87 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:14:47 PM PDT 24
Peak memory 206640 kb
Host smart-31487d22-767a-4145-84b9-13a5a4fd2f89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129043617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2129043617
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1045660375
Short name T605
Test name
Test status
Simulation time 874808783 ps
CPU time 3.47 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 208640 kb
Host smart-be3736cf-04e8-477d-a2e0-181f8290033a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045660375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1045660375
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2556816566
Short name T567
Test name
Test status
Simulation time 219514272 ps
CPU time 4.51 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 208908 kb
Host smart-5821e4a9-b7d8-4942-87a6-671d4749c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556816566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2556816566
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2666762457
Short name T215
Test name
Test status
Simulation time 146488670 ps
CPU time 3.94 seconds
Started Jul 22 07:14:39 PM PDT 24
Finished Jul 22 07:15:13 PM PDT 24
Peak memory 206672 kb
Host smart-944b94f7-dbeb-41d3-9129-5f81842f622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666762457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2666762457
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.834642139
Short name T758
Test name
Test status
Simulation time 583260851 ps
CPU time 18.84 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:15:06 PM PDT 24
Peak memory 219756 kb
Host smart-9f6424a6-6cae-4f3c-9a35-f4a40f938828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834642139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.834642139
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3087990173
Short name T379
Test name
Test status
Simulation time 213427462 ps
CPU time 6.99 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:53 PM PDT 24
Peak memory 214188 kb
Host smart-6b6a21ed-8376-4e8a-a766-533eacd0a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087990173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3087990173
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4151886998
Short name T61
Test name
Test status
Simulation time 152447504 ps
CPU time 3.58 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 210388 kb
Host smart-4701947b-fa85-4206-abb0-086de9a5b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151886998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4151886998
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2604770003
Short name T442
Test name
Test status
Simulation time 17808608 ps
CPU time 0.84 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 205592 kb
Host smart-43753e3d-63de-4fa3-adff-a6b42690b138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604770003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2604770003
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4034225812
Short name T361
Test name
Test status
Simulation time 166198172 ps
CPU time 3.37 seconds
Started Jul 22 07:14:35 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 214772 kb
Host smart-bb50ec19-2757-4be5-9ab8-8a9a985db735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034225812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4034225812
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.4192602259
Short name T687
Test name
Test status
Simulation time 144887935 ps
CPU time 3.77 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 209028 kb
Host smart-433b186a-5152-4024-a283-4ebb2cb9824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192602259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4192602259
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1715988785
Short name T106
Test name
Test status
Simulation time 179089113 ps
CPU time 6.81 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 214060 kb
Host smart-ec64e653-a0ec-4265-abce-3e9e77b635ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715988785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1715988785
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4184077574
Short name T328
Test name
Test status
Simulation time 60485544 ps
CPU time 2.11 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 214032 kb
Host smart-2736f974-fdf5-42d8-b479-42b4eb380c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184077574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4184077574
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1205657461
Short name T463
Test name
Test status
Simulation time 56675685 ps
CPU time 1.42 seconds
Started Jul 22 07:14:02 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 206720 kb
Host smart-5f0f213b-9ca9-4190-8fc6-ac76944d8232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205657461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1205657461
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2650669522
Short name T507
Test name
Test status
Simulation time 350845953 ps
CPU time 3.85 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:52 PM PDT 24
Peak memory 207068 kb
Host smart-4f2a0a56-f129-48cf-81a1-e26e3154e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650669522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2650669522
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2219843457
Short name T627
Test name
Test status
Simulation time 89932374 ps
CPU time 2.23 seconds
Started Jul 22 07:13:57 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 205904 kb
Host smart-158e61ef-cec5-48c9-8f3f-a2acfafb3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219843457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2219843457
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3299691567
Short name T593
Test name
Test status
Simulation time 134968881 ps
CPU time 2.74 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 208796 kb
Host smart-a546b2ba-d740-4a59-89a8-2a0390518391
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299691567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3299691567
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2106338727
Short name T210
Test name
Test status
Simulation time 312549905 ps
CPU time 3.04 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 207228 kb
Host smart-19e7d15c-6674-4506-aba6-eb4285dba88f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106338727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2106338727
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2231126601
Short name T899
Test name
Test status
Simulation time 5323259603 ps
CPU time 36.38 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 208724 kb
Host smart-f687294b-9c2f-499d-b7c3-72ec1bdf0f0f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231126601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2231126601
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.4093520777
Short name T820
Test name
Test status
Simulation time 3405731147 ps
CPU time 17.03 seconds
Started Jul 22 07:14:02 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 209364 kb
Host smart-2a3b174c-f725-46db-8608-a5449ee74bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093520777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.4093520777
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3576758470
Short name T672
Test name
Test status
Simulation time 206949854 ps
CPU time 2.45 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 206656 kb
Host smart-ed6641a0-6451-4acb-8402-4c79f30bedd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576758470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3576758470
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.317756087
Short name T744
Test name
Test status
Simulation time 66443253 ps
CPU time 3.2 seconds
Started Jul 22 07:14:35 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 208040 kb
Host smart-08439055-5c35-48eb-86a1-07bd915d4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317756087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.317756087
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1984598652
Short name T555
Test name
Test status
Simulation time 213037374 ps
CPU time 3.1 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 210412 kb
Host smart-8d8476d2-df75-4492-8eed-474aaa886518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984598652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1984598652
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1186074295
Short name T119
Test name
Test status
Simulation time 76802303 ps
CPU time 0.78 seconds
Started Jul 22 07:14:13 PM PDT 24
Finished Jul 22 07:14:57 PM PDT 24
Peak memory 205852 kb
Host smart-f08b1a0d-1088-4fc1-9466-c80ee46c0b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186074295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1186074295
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3624373191
Short name T323
Test name
Test status
Simulation time 201733546 ps
CPU time 2.7 seconds
Started Jul 22 07:14:37 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 213828 kb
Host smart-2901a2ec-808c-4a42-8de9-48fee2d425d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624373191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3624373191
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2761120758
Short name T74
Test name
Test status
Simulation time 17845020 ps
CPU time 1.41 seconds
Started Jul 22 07:13:59 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 214236 kb
Host smart-b7338c5a-a648-42c4-ba1e-e0d147d927cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761120758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2761120758
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1632608907
Short name T381
Test name
Test status
Simulation time 511680312 ps
CPU time 5.72 seconds
Started Jul 22 07:14:36 PM PDT 24
Finished Jul 22 07:15:12 PM PDT 24
Peak memory 221644 kb
Host smart-57084cf7-cfa6-4fab-950c-a1e19c914e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632608907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1632608907
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1692328009
Short name T376
Test name
Test status
Simulation time 395231079 ps
CPU time 4.82 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:53 PM PDT 24
Peak memory 213928 kb
Host smart-63597506-4f4e-42ef-8227-36f75a38ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692328009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1692328009
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1645043535
Short name T677
Test name
Test status
Simulation time 475537193 ps
CPU time 2.5 seconds
Started Jul 22 07:13:56 PM PDT 24
Finished Jul 22 07:14:47 PM PDT 24
Peak memory 207236 kb
Host smart-f34f0d50-b006-49be-999e-e52a24124f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645043535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1645043535
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.866312347
Short name T542
Test name
Test status
Simulation time 156490295 ps
CPU time 5.29 seconds
Started Jul 22 07:14:37 PM PDT 24
Finished Jul 22 07:15:13 PM PDT 24
Peak memory 213836 kb
Host smart-692db237-2833-49f7-b196-2a4f27151231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866312347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.866312347
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.163565136
Short name T664
Test name
Test status
Simulation time 108140061 ps
CPU time 3 seconds
Started Jul 22 07:14:36 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 208452 kb
Host smart-16723696-0baa-42e6-b219-f459220c22b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163565136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.163565136
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4195383887
Short name T345
Test name
Test status
Simulation time 199909891 ps
CPU time 2.82 seconds
Started Jul 22 07:14:00 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 208656 kb
Host smart-0b824899-5a01-4cac-bdf7-f9832acdddd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195383887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4195383887
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2370701515
Short name T392
Test name
Test status
Simulation time 248400862 ps
CPU time 2.82 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 208772 kb
Host smart-4e2b34f3-8285-429b-b346-bbedef4e626d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370701515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2370701515
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.474483906
Short name T920
Test name
Test status
Simulation time 44542926 ps
CPU time 2.61 seconds
Started Jul 22 07:13:58 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 208624 kb
Host smart-3e8d0bea-2c65-4377-9dfd-e3c4d50f051b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474483906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.474483906
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4251009945
Short name T5
Test name
Test status
Simulation time 418347131 ps
CPU time 2.91 seconds
Started Jul 22 07:14:37 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 207736 kb
Host smart-e3203e7f-b926-4759-8710-4dedf74ab3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251009945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4251009945
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3985355226
Short name T204
Test name
Test status
Simulation time 280399103 ps
CPU time 3.07 seconds
Started Jul 22 07:13:57 PM PDT 24
Finished Jul 22 07:14:49 PM PDT 24
Peak memory 208372 kb
Host smart-8c055f41-bcad-42a8-8193-eb8230fb704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985355226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3985355226
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3571391996
Short name T634
Test name
Test status
Simulation time 871691894 ps
CPU time 10.28 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 208480 kb
Host smart-e3c1bd07-7857-4f89-b6c3-7876ae69344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571391996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3571391996
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1998881527
Short name T492
Test name
Test status
Simulation time 308205119 ps
CPU time 2.14 seconds
Started Jul 22 07:14:01 PM PDT 24
Finished Jul 22 07:14:50 PM PDT 24
Peak memory 209840 kb
Host smart-edc539f4-2723-4cce-bf31-219ee4f8a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998881527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1998881527
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.759069655
Short name T731
Test name
Test status
Simulation time 11544450 ps
CPU time 0.86 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 205852 kb
Host smart-f69dd35e-c361-407f-a5a4-41fef621602f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759069655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.759069655
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2673291634
Short name T258
Test name
Test status
Simulation time 2069917751 ps
CPU time 3.36 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 221432 kb
Host smart-36426c7b-3a0c-4758-9a85-29e17e1efd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673291634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2673291634
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3573190967
Short name T802
Test name
Test status
Simulation time 236337182 ps
CPU time 2.03 seconds
Started Jul 22 07:14:11 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 218004 kb
Host smart-fcee6122-cd9c-4684-80af-b53a5f64e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573190967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3573190967
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3714756214
Short name T645
Test name
Test status
Simulation time 386770759 ps
CPU time 2.14 seconds
Started Jul 22 07:14:13 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 214616 kb
Host smart-df66724b-ef5c-483c-aee5-dbdbde7de6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714756214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3714756214
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2801546073
Short name T302
Test name
Test status
Simulation time 1762088803 ps
CPU time 5.93 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:03 PM PDT 24
Peak memory 221336 kb
Host smart-0e88dc97-7670-489c-85bc-c30e9160a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801546073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2801546073
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1366219654
Short name T250
Test name
Test status
Simulation time 183293576 ps
CPU time 3.05 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 219676 kb
Host smart-9d3d64fa-9a9e-4e26-af73-473abadb2d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366219654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1366219654
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.310163560
Short name T87
Test name
Test status
Simulation time 725128095 ps
CPU time 8.07 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 207804 kb
Host smart-c17e368d-c3b9-45a3-a08d-bf0b9c0545eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310163560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.310163560
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1727171647
Short name T1
Test name
Test status
Simulation time 48737735 ps
CPU time 2.03 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 206588 kb
Host smart-4f0c6b93-a0d8-44b5-8e4d-5ea4dcd4934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727171647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1727171647
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.686005127
Short name T840
Test name
Test status
Simulation time 35942083 ps
CPU time 1.74 seconds
Started Jul 22 07:14:34 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 206684 kb
Host smart-f9221375-1ac6-47e8-8a92-dfa3448ab2c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686005127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.686005127
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.616148479
Short name T287
Test name
Test status
Simulation time 2739086389 ps
CPU time 29.77 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:15:26 PM PDT 24
Peak memory 208400 kb
Host smart-f313e356-3ddd-47d9-916b-d15a83e61826
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616148479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.616148479
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.105571341
Short name T777
Test name
Test status
Simulation time 89796552 ps
CPU time 3.25 seconds
Started Jul 22 07:14:38 PM PDT 24
Finished Jul 22 07:15:12 PM PDT 24
Peak memory 208460 kb
Host smart-fe2c2bb3-1ec5-4674-83f7-6f6b8b1f337d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105571341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.105571341
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3482026521
Short name T746
Test name
Test status
Simulation time 44582820 ps
CPU time 2.3 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 207988 kb
Host smart-d85d9432-f78a-43d8-978e-6c5d79dd77ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482026521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3482026521
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2854442505
Short name T526
Test name
Test status
Simulation time 21873042 ps
CPU time 1.73 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 208472 kb
Host smart-5981dd8e-4484-48e5-8598-1a0b0ca6a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854442505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2854442505
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2142030398
Short name T370
Test name
Test status
Simulation time 4617261779 ps
CPU time 18.6 seconds
Started Jul 22 07:14:12 PM PDT 24
Finished Jul 22 07:15:15 PM PDT 24
Peak memory 222244 kb
Host smart-dc361612-2ad6-4e8e-99df-74119c5cd2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142030398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2142030398
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2638921673
Short name T316
Test name
Test status
Simulation time 126156308 ps
CPU time 3.23 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 208704 kb
Host smart-7a2a6230-8dd0-4b83-ae7f-708683552dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638921673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2638921673
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3514795216
Short name T43
Test name
Test status
Simulation time 73146210 ps
CPU time 2.57 seconds
Started Jul 22 07:14:22 PM PDT 24
Finished Jul 22 07:15:02 PM PDT 24
Peak memory 209700 kb
Host smart-7cae05fe-c257-4b4b-b50a-0fb0198d34f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514795216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3514795216
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3417618408
Short name T787
Test name
Test status
Simulation time 12531479 ps
CPU time 0.76 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 205828 kb
Host smart-c1879ba0-80a5-4089-b60c-671863474422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417618408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3417618408
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1096222774
Short name T426
Test name
Test status
Simulation time 306069640 ps
CPU time 10.72 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:26 PM PDT 24
Peak memory 214996 kb
Host smart-3630e0ed-8f0b-4536-9c21-d9d5f53e2f78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096222774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1096222774
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2309692135
Short name T556
Test name
Test status
Simulation time 359279495 ps
CPU time 3.92 seconds
Started Jul 22 07:12:27 PM PDT 24
Finished Jul 22 07:13:15 PM PDT 24
Peak memory 209116 kb
Host smart-54398f03-27b5-4817-9a1d-9e5e9c277bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309692135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2309692135
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2967761707
Short name T740
Test name
Test status
Simulation time 83189989 ps
CPU time 3.84 seconds
Started Jul 22 07:12:46 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 220276 kb
Host smart-f05c0e25-b4ec-44c1-b103-ef86d9709980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967761707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2967761707
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2716768131
Short name T222
Test name
Test status
Simulation time 194070425 ps
CPU time 6.28 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:19 PM PDT 24
Peak memory 209016 kb
Host smart-a298884f-1227-4f12-b110-24d2c6f919c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716768131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2716768131
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3632436494
Short name T12
Test name
Test status
Simulation time 459583508 ps
CPU time 10.11 seconds
Started Jul 22 07:12:46 PM PDT 24
Finished Jul 22 07:13:44 PM PDT 24
Peak memory 233832 kb
Host smart-de2f8b82-da62-46bd-aef0-9764fee504d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632436494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3632436494
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1470208793
Short name T299
Test name
Test status
Simulation time 447093681 ps
CPU time 3.84 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 208648 kb
Host smart-31c9ff4f-959c-442b-a90c-63015f1363af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470208793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1470208793
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2698589478
Short name T911
Test name
Test status
Simulation time 19056856 ps
CPU time 1.71 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:15 PM PDT 24
Peak memory 206704 kb
Host smart-7b494c3b-8cfa-4c8d-a5ef-f6e34c6be15b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698589478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2698589478
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2265506815
Short name T847
Test name
Test status
Simulation time 168719449 ps
CPU time 2.47 seconds
Started Jul 22 07:12:30 PM PDT 24
Finished Jul 22 07:13:18 PM PDT 24
Peak memory 206520 kb
Host smart-69b31c21-7b96-4c3e-824f-73b4909a0a6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265506815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2265506815
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3521539032
Short name T859
Test name
Test status
Simulation time 358858631 ps
CPU time 2.24 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 209024 kb
Host smart-a1bcf5c8-ff11-42d0-ac8f-f7eaa43ee1ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521539032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3521539032
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3958049011
Short name T754
Test name
Test status
Simulation time 32689041 ps
CPU time 1.86 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:32 PM PDT 24
Peak memory 206588 kb
Host smart-d2f529f2-a5d3-4003-9e8c-47a384029604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958049011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3958049011
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1965327157
Short name T142
Test name
Test status
Simulation time 641969300 ps
CPU time 4.51 seconds
Started Jul 22 07:12:32 PM PDT 24
Finished Jul 22 07:13:22 PM PDT 24
Peak memory 208296 kb
Host smart-2611d5d5-6208-47a0-961e-70e062e57a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965327157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1965327157
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.4290453643
Short name T917
Test name
Test status
Simulation time 1238866663 ps
CPU time 31.31 seconds
Started Jul 22 07:13:08 PM PDT 24
Finished Jul 22 07:14:28 PM PDT 24
Peak memory 215252 kb
Host smart-b8d8b501-c1f9-4d69-8b16-fbcef29d8b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290453643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4290453643
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3320672643
Short name T536
Test name
Test status
Simulation time 176159186 ps
CPU time 3.21 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:16 PM PDT 24
Peak memory 218252 kb
Host smart-6f765c1c-6f46-43bc-80b7-116e9059c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320672643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3320672643
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.174507620
Short name T893
Test name
Test status
Simulation time 152206073 ps
CPU time 2.01 seconds
Started Jul 22 07:13:02 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 209716 kb
Host smart-61ed4e27-a4f1-431a-a74c-65fb0d904708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174507620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.174507620
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3271689948
Short name T612
Test name
Test status
Simulation time 131034212 ps
CPU time 0.7 seconds
Started Jul 22 07:14:15 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 205820 kb
Host smart-80e39bf2-4ae5-4de8-bc54-ec98332327fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271689948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3271689948
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2327321596
Short name T433
Test name
Test status
Simulation time 242527244 ps
CPU time 8.17 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 214256 kb
Host smart-9e04c92f-9e3a-4e2d-8833-14689dee8149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327321596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2327321596
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3755676747
Short name T32
Test name
Test status
Simulation time 46014997 ps
CPU time 1.71 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 214112 kb
Host smart-e8270596-ed0b-492e-90ce-f59dc38fd474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755676747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3755676747
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4042292414
Short name T717
Test name
Test status
Simulation time 31361488 ps
CPU time 1.63 seconds
Started Jul 22 07:14:13 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 207948 kb
Host smart-93da8f30-d8ef-4c9b-b006-f0dde267e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042292414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4042292414
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3890698489
Short name T725
Test name
Test status
Simulation time 255523582 ps
CPU time 5.39 seconds
Started Jul 22 07:14:26 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 214096 kb
Host smart-87fb5266-a2b2-40a7-bcc6-2af2c39c4f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890698489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3890698489
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1660283999
Short name T91
Test name
Test status
Simulation time 309416101 ps
CPU time 6.22 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:03 PM PDT 24
Peak memory 214156 kb
Host smart-fb2fd75d-8823-4a7e-bae3-692b13c086e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660283999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1660283999
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.787058208
Short name T63
Test name
Test status
Simulation time 160361577 ps
CPU time 2.97 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 219840 kb
Host smart-47eb1faf-f75e-4939-b8ac-c51f833308b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787058208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.787058208
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3301273089
Short name T326
Test name
Test status
Simulation time 78281389 ps
CPU time 2.82 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 209464 kb
Host smart-8ac9aebf-7cef-4682-a097-cc5cc58ed41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301273089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3301273089
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2030216080
Short name T900
Test name
Test status
Simulation time 3940104967 ps
CPU time 26.56 seconds
Started Jul 22 07:14:15 PM PDT 24
Finished Jul 22 07:15:24 PM PDT 24
Peak memory 208296 kb
Host smart-6464da0a-5fdf-423e-89f9-05aa77398fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030216080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2030216080
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1934201369
Short name T499
Test name
Test status
Simulation time 59279047 ps
CPU time 2.13 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 207060 kb
Host smart-b8e16c45-909b-4719-bffb-29c69c1268b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934201369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1934201369
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.238275124
Short name T913
Test name
Test status
Simulation time 198388452 ps
CPU time 2.87 seconds
Started Jul 22 07:14:15 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 206560 kb
Host smart-64a8ac79-bff0-427a-8400-8600be95b310
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238275124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.238275124
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3784701017
Short name T855
Test name
Test status
Simulation time 62376783 ps
CPU time 3.04 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 206712 kb
Host smart-76bc26b9-cfe5-432f-8d9c-6b9b2df774b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784701017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3784701017
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2060499481
Short name T360
Test name
Test status
Simulation time 142079143 ps
CPU time 2.78 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 209004 kb
Host smart-0d0871e2-4bea-47ba-beba-b8eafbe02f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060499481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2060499481
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2883927531
Short name T830
Test name
Test status
Simulation time 36946270 ps
CPU time 2.24 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 208000 kb
Host smart-f8325802-2f84-46f9-8fe1-a47ee7f1eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883927531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2883927531
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1618002184
Short name T257
Test name
Test status
Simulation time 2163692156 ps
CPU time 37.34 seconds
Started Jul 22 07:14:26 PM PDT 24
Finished Jul 22 07:15:41 PM PDT 24
Peak memory 216692 kb
Host smart-30819750-2352-4fad-bcf2-961512d133b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618002184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1618002184
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3073175306
Short name T839
Test name
Test status
Simulation time 285707630 ps
CPU time 7 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:04 PM PDT 24
Peak memory 214104 kb
Host smart-361359bc-8a4b-4394-a98c-e2d5f31d03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073175306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3073175306
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.479364434
Short name T406
Test name
Test status
Simulation time 335336675 ps
CPU time 2.48 seconds
Started Jul 22 07:14:26 PM PDT 24
Finished Jul 22 07:15:06 PM PDT 24
Peak memory 210312 kb
Host smart-80d3dfd2-e439-44e6-8797-d1d9ec39f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479364434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.479364434
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3856767963
Short name T616
Test name
Test status
Simulation time 63977419 ps
CPU time 0.88 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 205888 kb
Host smart-56ae059b-d3ff-4b8d-9e96-23557c138ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856767963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3856767963
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.157024841
Short name T415
Test name
Test status
Simulation time 61602735 ps
CPU time 3.77 seconds
Started Jul 22 07:14:17 PM PDT 24
Finished Jul 22 07:15:02 PM PDT 24
Peak memory 215256 kb
Host smart-86d13d50-4bbc-4119-a4a7-2a8def57b33f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157024841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.157024841
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2172908930
Short name T679
Test name
Test status
Simulation time 85165396 ps
CPU time 1.74 seconds
Started Jul 22 07:14:16 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 208692 kb
Host smart-d60b6b72-92bc-43b4-a9d3-cd48e6218412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172908930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2172908930
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3242320554
Short name T697
Test name
Test status
Simulation time 176160566 ps
CPU time 2.43 seconds
Started Jul 22 07:14:17 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 222104 kb
Host smart-97153518-2236-453f-8cda-d9f5ff8d3b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242320554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3242320554
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1440019703
Short name T796
Test name
Test status
Simulation time 381634379 ps
CPU time 2.78 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 215668 kb
Host smart-60674238-1442-4229-8a80-edfa2478c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440019703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1440019703
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3978747234
Short name T770
Test name
Test status
Simulation time 203637968 ps
CPU time 3.37 seconds
Started Jul 22 07:14:16 PM PDT 24
Finished Jul 22 07:15:01 PM PDT 24
Peak memory 218220 kb
Host smart-d7bd0bc8-42c4-446d-aa0a-ac39b471095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978747234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3978747234
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2179399762
Short name T596
Test name
Test status
Simulation time 118999659 ps
CPU time 3.21 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:06 PM PDT 24
Peak memory 208512 kb
Host smart-d9f2fb53-b796-4c22-a72b-b86ec8182d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179399762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2179399762
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3465707890
Short name T852
Test name
Test status
Simulation time 834752662 ps
CPU time 6.13 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:10 PM PDT 24
Peak memory 207796 kb
Host smart-c324566c-e908-4848-9a6d-da48845b35df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465707890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3465707890
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3541488858
Short name T862
Test name
Test status
Simulation time 251661906 ps
CPU time 4.15 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 206696 kb
Host smart-95b0c9ca-f403-4685-ad32-130365c9bca0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541488858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3541488858
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1921790432
Short name T454
Test name
Test status
Simulation time 70792845 ps
CPU time 1.71 seconds
Started Jul 22 07:14:17 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 206652 kb
Host smart-fdc47229-3988-4d26-af50-17995e2d65d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921790432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1921790432
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.771481500
Short name T309
Test name
Test status
Simulation time 38032235 ps
CPU time 2.62 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 218168 kb
Host smart-3ba78e30-c1fa-48ad-b55e-ac6a89f05d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771481500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.771481500
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3207108312
Short name T789
Test name
Test status
Simulation time 534453858 ps
CPU time 3.59 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:06 PM PDT 24
Peak memory 208424 kb
Host smart-bb52531a-57ef-4c70-a9bb-6b0df54cf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207108312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3207108312
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.172157913
Short name T866
Test name
Test status
Simulation time 8326357982 ps
CPU time 37.46 seconds
Started Jul 22 07:14:16 PM PDT 24
Finished Jul 22 07:15:35 PM PDT 24
Peak memory 208600 kb
Host smart-6b84dd32-cfdc-4edf-a640-740094e4ee75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172157913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.172157913
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1483446168
Short name T205
Test name
Test status
Simulation time 176221427 ps
CPU time 9.85 seconds
Started Jul 22 07:14:15 PM PDT 24
Finished Jul 22 07:15:06 PM PDT 24
Peak memory 222284 kb
Host smart-48b1d261-1874-40d2-9cd3-66791badebc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483446168 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1483446168
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3364682082
Short name T701
Test name
Test status
Simulation time 202538866 ps
CPU time 5.67 seconds
Started Jul 22 07:14:17 PM PDT 24
Finished Jul 22 07:15:03 PM PDT 24
Peak memory 207820 kb
Host smart-4f3c6b0f-137c-4e25-8265-d98e026960df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364682082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3364682082
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.198973398
Short name T57
Test name
Test status
Simulation time 73943841 ps
CPU time 3.1 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 209944 kb
Host smart-49e1bce4-3d3e-41ce-86af-27c0a3f443fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198973398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.198973398
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1547672143
Short name T749
Test name
Test status
Simulation time 25153169 ps
CPU time 0.69 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:15 PM PDT 24
Peak memory 205828 kb
Host smart-e16ab58c-f653-48ca-b259-e6f0682bb261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547672143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1547672143
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2473496524
Short name T425
Test name
Test status
Simulation time 162862504 ps
CPU time 7.81 seconds
Started Jul 22 07:14:57 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 213980 kb
Host smart-3152eb35-69fd-46c9-9fc7-ed662c453b35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473496524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2473496524
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3019781506
Short name T693
Test name
Test status
Simulation time 147311976 ps
CPU time 2.14 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 209200 kb
Host smart-187125da-ef38-470b-bea7-27daf65f2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019781506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3019781506
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.222365843
Short name T642
Test name
Test status
Simulation time 132241617 ps
CPU time 2.94 seconds
Started Jul 22 07:14:57 PM PDT 24
Finished Jul 22 07:15:16 PM PDT 24
Peak memory 214028 kb
Host smart-efad27b4-9fb5-41b3-bfbf-3a5eb6174e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222365843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.222365843
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2220708933
Short name T96
Test name
Test status
Simulation time 119625232 ps
CPU time 2.26 seconds
Started Jul 22 07:14:57 PM PDT 24
Finished Jul 22 07:15:15 PM PDT 24
Peak memory 213996 kb
Host smart-d355d589-059d-442e-afd0-8e60f74acb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220708933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2220708933
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1388391322
Short name T662
Test name
Test status
Simulation time 537983422 ps
CPU time 3.8 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 214128 kb
Host smart-f02a0eea-46e0-4864-b951-a67e2e5cd3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388391322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1388391322
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3946875637
Short name T846
Test name
Test status
Simulation time 39183448 ps
CPU time 2.74 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 214144 kb
Host smart-c4821b83-76df-4147-b239-0080bccf68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946875637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3946875637
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3914935806
Short name T285
Test name
Test status
Simulation time 1063132642 ps
CPU time 4.65 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 208268 kb
Host smart-5ef1342f-9fc6-4ec0-bcbf-e71321484323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914935806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3914935806
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.20168426
Short name T712
Test name
Test status
Simulation time 204069469 ps
CPU time 3.13 seconds
Started Jul 22 07:14:57 PM PDT 24
Finished Jul 22 07:15:16 PM PDT 24
Peak memory 208372 kb
Host smart-ced8377b-288a-4dab-a215-31614ad36b41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20168426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.20168426
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2324863631
Short name T579
Test name
Test status
Simulation time 157798994 ps
CPU time 2.71 seconds
Started Jul 22 07:14:18 PM PDT 24
Finished Jul 22 07:15:01 PM PDT 24
Peak memory 206580 kb
Host smart-ba003f78-a955-4b3f-840d-208aff9c2c73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324863631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2324863631
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3000053779
Short name T544
Test name
Test status
Simulation time 272111709 ps
CPU time 2.38 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 206692 kb
Host smart-dd1350c1-0d80-473e-8f16-a8b0bf22a86e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000053779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3000053779
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.902164716
Short name T685
Test name
Test status
Simulation time 152344061 ps
CPU time 2.84 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 210032 kb
Host smart-284d0183-479e-44a0-947f-bfb5297b8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902164716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.902164716
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1809980092
Short name T145
Test name
Test status
Simulation time 513042003 ps
CPU time 2.25 seconds
Started Jul 22 07:14:16 PM PDT 24
Finished Jul 22 07:15:00 PM PDT 24
Peak memory 208380 kb
Host smart-d5a27976-aad9-4638-8f69-2c26a580e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809980092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1809980092
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1709630588
Short name T208
Test name
Test status
Simulation time 1120833091 ps
CPU time 7.14 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:51 PM PDT 24
Peak memory 218136 kb
Host smart-aec0091a-261d-42fb-80b5-94df316bbce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709630588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1709630588
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2427701570
Short name T115
Test name
Test status
Simulation time 125354541 ps
CPU time 1.68 seconds
Started Jul 22 07:15:04 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 209884 kb
Host smart-7491045b-aaad-4ca6-9958-ff5035525a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427701570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2427701570
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1326043826
Short name T502
Test name
Test status
Simulation time 38761604 ps
CPU time 0.76 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:15:59 PM PDT 24
Peak memory 205832 kb
Host smart-e436d85d-bfd4-444b-bc9a-a94a24e4b855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326043826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1326043826
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.300877251
Short name T248
Test name
Test status
Simulation time 126192185 ps
CPU time 3.71 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 222468 kb
Host smart-1f4fc725-9d30-4328-b142-ceb12dbb2b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300877251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.300877251
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1729492731
Short name T501
Test name
Test status
Simulation time 1619534626 ps
CPU time 9.74 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:23 PM PDT 24
Peak memory 218076 kb
Host smart-1ad54e72-081b-497f-884e-358f5d95cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729492731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1729492731
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.959962021
Short name T95
Test name
Test status
Simulation time 504202247 ps
CPU time 5.7 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 214092 kb
Host smart-5ca00083-79a4-4822-8a9b-4090a11465d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959962021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.959962021
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4286950512
Short name T315
Test name
Test status
Simulation time 190280229 ps
CPU time 3.5 seconds
Started Jul 22 07:15:00 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 207440 kb
Host smart-285a9b92-0d9e-42a8-abac-5187effc29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286950512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4286950512
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2371667375
Short name T563
Test name
Test status
Simulation time 1201487927 ps
CPU time 7.98 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:22 PM PDT 24
Peak memory 209128 kb
Host smart-fd91208a-fc52-4399-ac2b-ed9cb2c0f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371667375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2371667375
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3524799414
Short name T308
Test name
Test status
Simulation time 188962387 ps
CPU time 6.11 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 208432 kb
Host smart-7ee7d424-317f-481c-a64d-43cf545e65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524799414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3524799414
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1927754562
Short name T527
Test name
Test status
Simulation time 257778028 ps
CPU time 4.13 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 207748 kb
Host smart-bf03c8b9-7590-45cc-a02d-1459b8b8f9ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927754562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1927754562
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.871189784
Short name T144
Test name
Test status
Simulation time 33721713 ps
CPU time 2.42 seconds
Started Jul 22 07:14:57 PM PDT 24
Finished Jul 22 07:15:16 PM PDT 24
Peak memory 208568 kb
Host smart-b6ef8a55-e5d1-458e-97d4-44ad18af085f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871189784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.871189784
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3880809064
Short name T295
Test name
Test status
Simulation time 7395859842 ps
CPU time 62.9 seconds
Started Jul 22 07:14:55 PM PDT 24
Finished Jul 22 07:16:15 PM PDT 24
Peak memory 208328 kb
Host smart-921a40ce-3ddd-40a5-bb02-8e8480d5066b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880809064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3880809064
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3229809520
Short name T849
Test name
Test status
Simulation time 56882541 ps
CPU time 1.88 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 207964 kb
Host smart-eb8da56c-bd7c-4e7d-9af5-8946ee246a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229809520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3229809520
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1063026380
Short name T517
Test name
Test status
Simulation time 107584118 ps
CPU time 2.34 seconds
Started Jul 22 07:14:54 PM PDT 24
Finished Jul 22 07:15:14 PM PDT 24
Peak memory 208388 kb
Host smart-179c4651-54a7-4dad-a4ce-3bd67308d771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063026380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1063026380
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4245962297
Short name T367
Test name
Test status
Simulation time 988875379 ps
CPU time 22.37 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:21 PM PDT 24
Peak memory 215932 kb
Host smart-e9eb56e8-8932-4656-82be-01c4fadf6ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245962297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4245962297
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3649122366
Short name T892
Test name
Test status
Simulation time 469768704 ps
CPU time 4.1 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 207652 kb
Host smart-d5ef5ee0-0cea-484e-922a-6c2e136eacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649122366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3649122366
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2535801820
Short name T56
Test name
Test status
Simulation time 2205930303 ps
CPU time 10.53 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:26 PM PDT 24
Peak memory 210816 kb
Host smart-b7f2eafc-761e-461b-a03c-8b34f2c04e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535801820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2535801820
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1545460952
Short name T440
Test name
Test status
Simulation time 14526373 ps
CPU time 0.88 seconds
Started Jul 22 07:15:01 PM PDT 24
Finished Jul 22 07:15:16 PM PDT 24
Peak memory 205832 kb
Host smart-49ceb052-aac3-40ad-a9c1-34e7949b5756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545460952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1545460952
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2488383918
Short name T420
Test name
Test status
Simulation time 1404127224 ps
CPU time 27.44 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:42 PM PDT 24
Peak memory 214052 kb
Host smart-24ae7d00-fe8a-48da-9aaf-52415e0a0e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488383918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2488383918
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3052907169
Short name T16
Test name
Test status
Simulation time 203280476 ps
CPU time 5.83 seconds
Started Jul 22 07:15:02 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 207904 kb
Host smart-da30b7f1-fd77-4850-8b8e-f171e45954de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052907169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3052907169
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3852567071
Short name T105
Test name
Test status
Simulation time 65484512 ps
CPU time 4.36 seconds
Started Jul 22 07:15:02 PM PDT 24
Finished Jul 22 07:15:20 PM PDT 24
Peak memory 222224 kb
Host smart-6252ff89-f05b-4cd8-b672-5d306450f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852567071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3852567071
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.640676594
Short name T640
Test name
Test status
Simulation time 102405478 ps
CPU time 1.99 seconds
Started Jul 22 07:15:01 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 213928 kb
Host smart-5be9ae9c-3288-4424-8c9b-406da47ab0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640676594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.640676594
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2211237497
Short name T46
Test name
Test status
Simulation time 244641816 ps
CPU time 7.61 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 216420 kb
Host smart-0110d427-bb73-4540-a2a1-d7873ed635f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211237497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2211237497
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2505480608
Short name T570
Test name
Test status
Simulation time 4764343814 ps
CPU time 60.08 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:16:15 PM PDT 24
Peak memory 214200 kb
Host smart-c3cf3e54-6f52-40b9-887d-2486e14e739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505480608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2505480608
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.252792234
Short name T768
Test name
Test status
Simulation time 165411825 ps
CPU time 2.92 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 206492 kb
Host smart-ba3665ea-323e-463e-96b5-108539b42064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252792234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.252792234
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4254745658
Short name T4
Test name
Test status
Simulation time 552402063 ps
CPU time 4.57 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:20 PM PDT 24
Peak memory 207640 kb
Host smart-f9e6c904-bbab-4e76-a150-06476424c1c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254745658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4254745658
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4041739950
Short name T751
Test name
Test status
Simulation time 243057069 ps
CPU time 2.93 seconds
Started Jul 22 07:15:00 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 207868 kb
Host smart-7c5dda35-d405-4d1f-8d52-5e753683a949
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041739950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4041739950
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1379695960
Short name T671
Test name
Test status
Simulation time 440388932 ps
CPU time 3.95 seconds
Started Jul 22 07:14:58 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 208772 kb
Host smart-3f765e64-39b0-42ae-9e81-e4785f21dcf9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379695960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1379695960
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.967607068
Short name T727
Test name
Test status
Simulation time 1606091628 ps
CPU time 15.14 seconds
Started Jul 22 07:15:00 PM PDT 24
Finished Jul 22 07:15:30 PM PDT 24
Peak memory 214084 kb
Host smart-8baa1424-6024-40e7-9782-bdd03b23f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967607068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.967607068
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2352583902
Short name T479
Test name
Test status
Simulation time 120737173 ps
CPU time 2.2 seconds
Started Jul 22 07:15:00 PM PDT 24
Finished Jul 22 07:15:17 PM PDT 24
Peak memory 208380 kb
Host smart-e538f80d-6d50-48e1-8484-085de9aa7dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352583902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2352583902
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4212120462
Short name T667
Test name
Test status
Simulation time 365812231 ps
CPU time 3.7 seconds
Started Jul 22 07:14:59 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 207136 kb
Host smart-f15af9c2-9c4f-479f-9c0b-3cd269b372c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212120462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4212120462
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.296025844
Short name T113
Test name
Test status
Simulation time 14318283 ps
CPU time 0.73 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:11 PM PDT 24
Peak memory 205848 kb
Host smart-cff9a5f9-3f3b-4f09-ba60-602ebea24daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296025844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.296025844
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3249464552
Short name T273
Test name
Test status
Simulation time 195396939 ps
CPU time 3.31 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:59 PM PDT 24
Peak memory 215148 kb
Host smart-6c366422-1a3d-4d70-bfcb-f547bd64e493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249464552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3249464552
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3146246547
Short name T836
Test name
Test status
Simulation time 467149420 ps
CPU time 6.68 seconds
Started Jul 22 07:15:29 PM PDT 24
Finished Jul 22 07:15:46 PM PDT 24
Peak memory 209104 kb
Host smart-849642bb-ce28-4a3d-9e6b-d296f671d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146246547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3146246547
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3640070635
Short name T865
Test name
Test status
Simulation time 162920286 ps
CPU time 3.04 seconds
Started Jul 22 07:15:29 PM PDT 24
Finished Jul 22 07:15:42 PM PDT 24
Peak memory 208888 kb
Host smart-018859ba-e0d4-417b-b516-b1d48aae7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640070635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3640070635
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3153024770
Short name T284
Test name
Test status
Simulation time 145278301 ps
CPU time 3.71 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:15:54 PM PDT 24
Peak memory 219656 kb
Host smart-5e42a99c-0981-4ba2-9935-dff10dfa3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153024770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3153024770
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3999926940
Short name T551
Test name
Test status
Simulation time 3266708341 ps
CPU time 47.11 seconds
Started Jul 22 07:14:55 PM PDT 24
Finished Jul 22 07:16:00 PM PDT 24
Peak memory 208564 kb
Host smart-4da6ab8c-4f31-4025-be1a-dd147975a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999926940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3999926940
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2793608100
Short name T906
Test name
Test status
Simulation time 202259605 ps
CPU time 3.6 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 206540 kb
Host smart-8b009904-c951-43ff-8c3d-158a6b918395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793608100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2793608100
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.346334002
Short name T676
Test name
Test status
Simulation time 410231013 ps
CPU time 6.48 seconds
Started Jul 22 07:15:02 PM PDT 24
Finished Jul 22 07:15:22 PM PDT 24
Peak memory 208544 kb
Host smart-8d8da433-73a3-4dda-90ac-29b7e6055901
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346334002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.346334002
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.617129902
Short name T815
Test name
Test status
Simulation time 27346804 ps
CPU time 2.16 seconds
Started Jul 22 07:15:02 PM PDT 24
Finished Jul 22 07:15:18 PM PDT 24
Peak memory 208352 kb
Host smart-34e4905f-42e1-4f0d-80da-b5e8a937d2a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617129902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.617129902
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3131666371
Short name T720
Test name
Test status
Simulation time 125981295 ps
CPU time 2.92 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:50 PM PDT 24
Peak memory 208352 kb
Host smart-b8e3a631-6831-466b-be23-ee21fc40df65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131666371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3131666371
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1499595859
Short name T412
Test name
Test status
Simulation time 36683515 ps
CPU time 1.47 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:15:55 PM PDT 24
Peak memory 215404 kb
Host smart-5444b7a0-12ca-4814-bad0-bb0cd72a5815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499595859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1499595859
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.131276646
Short name T610
Test name
Test status
Simulation time 151609269 ps
CPU time 3.48 seconds
Started Jul 22 07:15:03 PM PDT 24
Finished Jul 22 07:15:19 PM PDT 24
Peak memory 208472 kb
Host smart-be5ed3e9-36a0-4558-8c73-e6f093d4c2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131276646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.131276646
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3456239806
Short name T254
Test name
Test status
Simulation time 33262252869 ps
CPU time 313.49 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:20:54 PM PDT 24
Peak memory 222560 kb
Host smart-eb3ddab7-e082-4933-aa34-01059bb27809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456239806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3456239806
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1340606129
Short name T870
Test name
Test status
Simulation time 167310892 ps
CPU time 3.01 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:08 PM PDT 24
Peak memory 207116 kb
Host smart-99b0339b-39fc-43cf-9fa6-a167aedcac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340606129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1340606129
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3994321206
Short name T528
Test name
Test status
Simulation time 30201224 ps
CPU time 1.34 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:45 PM PDT 24
Peak memory 209332 kb
Host smart-6d6e53c3-2b9b-4504-a72b-1dec2bc8a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994321206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3994321206
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1598753754
Short name T691
Test name
Test status
Simulation time 40536523 ps
CPU time 0.79 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:47 PM PDT 24
Peak memory 205824 kb
Host smart-70ee0ac0-3708-46d8-b80b-1a4f1eb9ad7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598753754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1598753754
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2498511295
Short name T349
Test name
Test status
Simulation time 326752508 ps
CPU time 5.18 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:59 PM PDT 24
Peak memory 214824 kb
Host smart-d77a00c4-15e3-4a23-96a9-fef7e3799c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498511295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2498511295
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2651143760
Short name T582
Test name
Test status
Simulation time 493080296 ps
CPU time 11 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:16:05 PM PDT 24
Peak memory 222560 kb
Host smart-316999e8-e06b-4f18-8b64-dbd732e33f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651143760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2651143760
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3505966067
Short name T520
Test name
Test status
Simulation time 66260542 ps
CPU time 1.81 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:25 PM PDT 24
Peak memory 218284 kb
Host smart-1372ac8c-2eea-4ca5-b621-e0cc3cd0a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505966067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3505966067
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.859192957
Short name T812
Test name
Test status
Simulation time 4654837192 ps
CPU time 27.05 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:16:11 PM PDT 24
Peak memory 214124 kb
Host smart-cd8649e3-5cd6-43b1-ac16-d0af5f770ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859192957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.859192957
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3647668592
Short name T703
Test name
Test status
Simulation time 458573421 ps
CPU time 2.5 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:45 PM PDT 24
Peak memory 206000 kb
Host smart-2c175446-93d2-42fc-a36e-a2db3d095edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647668592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3647668592
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.237414807
Short name T607
Test name
Test status
Simulation time 462742546 ps
CPU time 4.93 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:14 PM PDT 24
Peak memory 209568 kb
Host smart-271c8d8e-d95c-4412-a54d-0081f5f647b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237414807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.237414807
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3818876458
Short name T233
Test name
Test status
Simulation time 2493295966 ps
CPU time 9.82 seconds
Started Jul 22 07:15:28 PM PDT 24
Finished Jul 22 07:15:44 PM PDT 24
Peak memory 209240 kb
Host smart-edb89691-e167-4135-aa80-07cda8cae750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818876458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3818876458
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3997004155
Short name T531
Test name
Test status
Simulation time 163821219 ps
CPU time 4.05 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:02 PM PDT 24
Peak memory 207856 kb
Host smart-95391cc3-71a6-4c48-8c79-3b1a2a44187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997004155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3997004155
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3277032983
Short name T414
Test name
Test status
Simulation time 34238698 ps
CPU time 2.3 seconds
Started Jul 22 07:15:29 PM PDT 24
Finished Jul 22 07:15:41 PM PDT 24
Peak memory 206788 kb
Host smart-7b0e15f0-b678-4cdb-8ea2-fbdcaf750eb8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277032983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3277032983
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.528457464
Short name T89
Test name
Test status
Simulation time 142797912 ps
CPU time 2.82 seconds
Started Jul 22 07:15:28 PM PDT 24
Finished Jul 22 07:15:35 PM PDT 24
Peak memory 208592 kb
Host smart-01e24002-6a4c-4f88-b078-edd829168a7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528457464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.528457464
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1891661230
Short name T35
Test name
Test status
Simulation time 811470826 ps
CPU time 8.21 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:15:59 PM PDT 24
Peak memory 208716 kb
Host smart-fa3e25c2-2484-4ea0-b9dd-e6cb097b9889
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891661230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1891661230
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1681305005
Short name T706
Test name
Test status
Simulation time 86268977 ps
CPU time 2.66 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:46 PM PDT 24
Peak memory 215088 kb
Host smart-c05db728-50f9-46a7-a470-5723f06ddb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681305005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1681305005
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1675709388
Short name T673
Test name
Test status
Simulation time 41873713 ps
CPU time 2.29 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:56 PM PDT 24
Peak memory 207916 kb
Host smart-02296433-ee61-4f96-9d1b-727f9ae6c478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675709388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1675709388
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.513222954
Short name T265
Test name
Test status
Simulation time 1067843701 ps
CPU time 26.22 seconds
Started Jul 22 07:17:49 PM PDT 24
Finished Jul 22 07:19:09 PM PDT 24
Peak memory 216076 kb
Host smart-e2a4a390-e194-43a6-8a80-d7432765e9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513222954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.513222954
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2792078233
Short name T493
Test name
Test status
Simulation time 298552195 ps
CPU time 4.99 seconds
Started Jul 22 07:15:29 PM PDT 24
Finished Jul 22 07:15:44 PM PDT 24
Peak memory 218004 kb
Host smart-1ce9a297-912f-4c22-b6ce-a9c00313df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792078233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2792078233
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3048583592
Short name T504
Test name
Test status
Simulation time 307535748 ps
CPU time 3.66 seconds
Started Jul 22 07:17:49 PM PDT 24
Finished Jul 22 07:18:46 PM PDT 24
Peak memory 210744 kb
Host smart-1b89d0fc-b8fb-4b8e-80c7-0c6260d504cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048583592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3048583592
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.810484489
Short name T447
Test name
Test status
Simulation time 48100956 ps
CPU time 0.69 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:47 PM PDT 24
Peak memory 205900 kb
Host smart-145a82f2-db3e-4947-a5f1-301344ee6965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810484489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.810484489
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.398679264
Short name T792
Test name
Test status
Simulation time 58526185 ps
CPU time 1.77 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:08 PM PDT 24
Peak memory 222468 kb
Host smart-6f0f3635-adf3-44a2-b4f5-d9689718a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398679264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.398679264
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.909704384
Short name T884
Test name
Test status
Simulation time 65336450 ps
CPU time 2.92 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:58 PM PDT 24
Peak memory 209752 kb
Host smart-4f6c0363-888c-4c24-b055-c5358aee56f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909704384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.909704384
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1588529726
Short name T112
Test name
Test status
Simulation time 522812135 ps
CPU time 4.96 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:10 PM PDT 24
Peak memory 219792 kb
Host smart-956b5f66-42d9-4438-9e9c-d4b8532ed12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588529726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1588529726
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.296434322
Short name T711
Test name
Test status
Simulation time 219177761 ps
CPU time 2.21 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:15 PM PDT 24
Peak memory 214152 kb
Host smart-8d712e7e-5aba-4c32-bfce-73170de3020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296434322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.296434322
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1485029212
Short name T514
Test name
Test status
Simulation time 529812994 ps
CPU time 3.31 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 210132 kb
Host smart-9bc86a80-f5a0-4f26-8bf2-4e7b4c54e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485029212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1485029212
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.639877083
Short name T268
Test name
Test status
Simulation time 494407197 ps
CPU time 5.34 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:04 PM PDT 24
Peak memory 207220 kb
Host smart-3b14d678-26f1-4e8b-b417-377ea770b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639877083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.639877083
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1254751230
Short name T359
Test name
Test status
Simulation time 51899430 ps
CPU time 2.89 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:47 PM PDT 24
Peak memory 206424 kb
Host smart-05134a43-7ffc-4b6c-afb4-84d3e1d66209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254751230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1254751230
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.870045626
Short name T548
Test name
Test status
Simulation time 74591170 ps
CPU time 3.03 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:00 PM PDT 24
Peak memory 206696 kb
Host smart-f1e7956b-8c4a-4eee-847c-d3ea30e39dfc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870045626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.870045626
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4104283255
Short name T524
Test name
Test status
Simulation time 97993203 ps
CPU time 4.18 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:13 PM PDT 24
Peak memory 208684 kb
Host smart-8f9c1b43-8804-4a14-b56c-d0361fee3d49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104283255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4104283255
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3646651933
Short name T368
Test name
Test status
Simulation time 48146308 ps
CPU time 2.59 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:49 PM PDT 24
Peak memory 208184 kb
Host smart-75ec8661-c00f-475a-bab6-896d6d19127b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646651933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3646651933
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2131658162
Short name T647
Test name
Test status
Simulation time 329053758 ps
CPU time 2.45 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:47 PM PDT 24
Peak memory 209800 kb
Host smart-8c0e06fd-7c71-4425-b202-4e042522c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131658162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2131658162
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3827857707
Short name T574
Test name
Test status
Simulation time 273815375 ps
CPU time 4.72 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:53 PM PDT 24
Peak memory 206884 kb
Host smart-ebc86496-beef-49a1-96c2-bc442b350c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827857707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3827857707
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3018764977
Short name T823
Test name
Test status
Simulation time 734260581 ps
CPU time 9.73 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:55 PM PDT 24
Peak memory 222264 kb
Host smart-b41ca1ff-1b28-4ed8-a9de-fbe648902768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018764977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3018764977
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1797639825
Short name T116
Test name
Test status
Simulation time 591614841 ps
CPU time 10.48 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:55 PM PDT 24
Peak memory 220244 kb
Host smart-6079e42e-5df7-413b-91d2-448a7d464200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797639825 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1797639825
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4005443460
Short name T523
Test name
Test status
Simulation time 70075157 ps
CPU time 2.73 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:48 PM PDT 24
Peak memory 214144 kb
Host smart-753fc2f1-ba5e-43a4-afa7-f3a86f2cc865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005443460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4005443460
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2123518277
Short name T606
Test name
Test status
Simulation time 45235338 ps
CPU time 2.39 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:08 PM PDT 24
Peak memory 209800 kb
Host smart-29135910-ed91-4f37-a9d2-533ab57e8e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123518277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2123518277
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4156165477
Short name T485
Test name
Test status
Simulation time 10710002 ps
CPU time 0.76 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:15:58 PM PDT 24
Peak memory 205896 kb
Host smart-3f0fddf0-9fbb-4678-ad13-fcafa51e7cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156165477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4156165477
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1445290695
Short name T921
Test name
Test status
Simulation time 166057920 ps
CPU time 4.97 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:14 PM PDT 24
Peak memory 215152 kb
Host smart-a627d58b-2692-49c8-a164-3047e0ceaf9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445290695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1445290695
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4003366985
Short name T73
Test name
Test status
Simulation time 498820099 ps
CPU time 8.81 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 214340 kb
Host smart-77ea86ac-5e4a-41d6-aa67-155590b1e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003366985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4003366985
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3697035445
Short name T50
Test name
Test status
Simulation time 71984687 ps
CPU time 2.64 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:06 PM PDT 24
Peak memory 207392 kb
Host smart-a79562e4-d851-483d-b874-a5514bd0b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697035445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3697035445
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2023336873
Short name T51
Test name
Test status
Simulation time 388915346 ps
CPU time 2.23 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:58 PM PDT 24
Peak memory 222124 kb
Host smart-7adcd7ae-c0bf-4e75-917f-efccdd7087bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023336873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2023336873
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2180876394
Short name T736
Test name
Test status
Simulation time 165241931 ps
CPU time 3.78 seconds
Started Jul 22 07:15:52 PM PDT 24
Finished Jul 22 07:16:44 PM PDT 24
Peak memory 214000 kb
Host smart-99610f34-797e-4554-9594-4b11416f4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180876394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2180876394
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3100081385
Short name T688
Test name
Test status
Simulation time 37274487 ps
CPU time 1.76 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:05 PM PDT 24
Peak memory 207900 kb
Host smart-2e931d90-2fef-4f44-bc31-49cc4bda6883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100081385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3100081385
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4148896010
Short name T797
Test name
Test status
Simulation time 111671014 ps
CPU time 2.47 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:05 PM PDT 24
Peak memory 206764 kb
Host smart-98ae6e03-3dff-4912-bc75-0e59836ba9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148896010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4148896010
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1752902833
Short name T121
Test name
Test status
Simulation time 366949573 ps
CPU time 3.19 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 206632 kb
Host smart-60ff1b35-7a00-43f3-972b-454862bf326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752902833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1752902833
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3986228071
Short name T480
Test name
Test status
Simulation time 701127218 ps
CPU time 5.01 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:24 PM PDT 24
Peak memory 208396 kb
Host smart-5ee810b3-186f-40e6-b057-01233774b079
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986228071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3986228071
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3620615465
Short name T466
Test name
Test status
Simulation time 60451182 ps
CPU time 3 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 206696 kb
Host smart-56709ccd-c43f-4338-a896-32183a586fec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620615465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3620615465
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1576150905
Short name T850
Test name
Test status
Simulation time 188069381 ps
CPU time 2.88 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:07 PM PDT 24
Peak memory 206512 kb
Host smart-a017c472-a6dc-4602-89a3-55cc60a6ebbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576150905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1576150905
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3736064627
Short name T916
Test name
Test status
Simulation time 225052016 ps
CPU time 5.39 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:19 PM PDT 24
Peak memory 209680 kb
Host smart-10405510-c4a1-41b9-b549-41315e118f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736064627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3736064627
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3027673912
Short name T902
Test name
Test status
Simulation time 419013326 ps
CPU time 2.91 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:11 PM PDT 24
Peak memory 208212 kb
Host smart-c247cbdf-268c-479d-9d64-2fb2811fa046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027673912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3027673912
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2996276802
Short name T80
Test name
Test status
Simulation time 6136156560 ps
CPU time 26.7 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:43 PM PDT 24
Peak memory 214952 kb
Host smart-a5f42ab7-58b0-4960-9a2d-3ef1a06f8825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996276802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2996276802
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2781756136
Short name T75
Test name
Test status
Simulation time 1126878594 ps
CPU time 11.04 seconds
Started Jul 22 07:15:51 PM PDT 24
Finished Jul 22 07:16:51 PM PDT 24
Peak memory 220144 kb
Host smart-2835b90c-c7cf-435f-8334-782d2a005342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781756136 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2781756136
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.4177208535
Short name T682
Test name
Test status
Simulation time 309198299 ps
CPU time 5.42 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:11 PM PDT 24
Peak memory 209728 kb
Host smart-2a44677d-3261-4d1a-aada-865d54f63d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177208535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4177208535
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1282709088
Short name T60
Test name
Test status
Simulation time 99821661 ps
CPU time 2.46 seconds
Started Jul 22 07:16:51 PM PDT 24
Finished Jul 22 07:18:00 PM PDT 24
Peak memory 209696 kb
Host smart-38947646-158c-49a3-9b8f-70827f5dedb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282709088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1282709088
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.644535525
Short name T818
Test name
Test status
Simulation time 181577116 ps
CPU time 0.84 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:56 PM PDT 24
Peak memory 205620 kb
Host smart-e2f9cd23-694b-4f13-a830-8051753bc8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644535525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.644535525
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2412818357
Short name T230
Test name
Test status
Simulation time 37313991 ps
CPU time 2.88 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:37 PM PDT 24
Peak memory 215444 kb
Host smart-28e0eb5b-3a57-46ed-b973-bfba9803103e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412818357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2412818357
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2055702627
Short name T244
Test name
Test status
Simulation time 137342194 ps
CPU time 1.77 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:21 PM PDT 24
Peak memory 208532 kb
Host smart-2cac8fd8-38e6-498d-98b0-8c1bd968a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055702627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2055702627
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1176297867
Short name T216
Test name
Test status
Simulation time 111959818 ps
CPU time 3.03 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:19 PM PDT 24
Peak memory 208036 kb
Host smart-bb71adf8-ec79-47bc-b49c-db7877a6aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176297867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1176297867
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2948842500
Short name T92
Test name
Test status
Simulation time 62956924 ps
CPU time 2.22 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:14 PM PDT 24
Peak memory 214080 kb
Host smart-25de4dce-d50d-46e0-85d0-8042ed6ed041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948842500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2948842500
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3101199718
Short name T694
Test name
Test status
Simulation time 44663611 ps
CPU time 2.69 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:19 PM PDT 24
Peak memory 222204 kb
Host smart-30b68183-0909-441e-b93d-f88b0c49297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101199718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3101199718
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1619342745
Short name T153
Test name
Test status
Simulation time 275263550 ps
CPU time 3.67 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 214076 kb
Host smart-7d107a2d-6c74-4e53-ba61-674d3e72975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619342745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1619342745
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1745717783
Short name T223
Test name
Test status
Simulation time 329233248 ps
CPU time 8 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:31 PM PDT 24
Peak memory 207920 kb
Host smart-0c519fc0-e1ba-4895-ae32-9edf23a6d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745717783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1745717783
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3680043856
Short name T534
Test name
Test status
Simulation time 267821778 ps
CPU time 4.8 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:03 PM PDT 24
Peak memory 207712 kb
Host smart-fbccf716-2100-43cb-8d7a-028d00930453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680043856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3680043856
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2351604721
Short name T845
Test name
Test status
Simulation time 575848523 ps
CPU time 4.44 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:37 PM PDT 24
Peak memory 208400 kb
Host smart-e014eae8-af02-4486-a46a-d820c71c55f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351604721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2351604721
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3807919139
Short name T766
Test name
Test status
Simulation time 116505562 ps
CPU time 3.88 seconds
Started Jul 22 07:16:27 PM PDT 24
Finished Jul 22 07:17:35 PM PDT 24
Peak memory 208536 kb
Host smart-f0232ec3-1902-447e-8c40-406c466c2e3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807919139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3807919139
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4085002002
Short name T585
Test name
Test status
Simulation time 1110345892 ps
CPU time 34.96 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:18:08 PM PDT 24
Peak memory 208776 kb
Host smart-3cef2b9a-a8c6-446c-9a38-932e47d651c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085002002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4085002002
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3210937929
Short name T82
Test name
Test status
Simulation time 162535094 ps
CPU time 3.35 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:16 PM PDT 24
Peak memory 217908 kb
Host smart-6008e5bf-1cd4-4d86-94a5-6fff9a32f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210937929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3210937929
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2670090751
Short name T509
Test name
Test status
Simulation time 60556834 ps
CPU time 2.49 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:02 PM PDT 24
Peak memory 207756 kb
Host smart-d382ee1a-eba6-49d8-a2e6-86738a49cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670090751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2670090751
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4102440657
Short name T353
Test name
Test status
Simulation time 587403030 ps
CPU time 14.68 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:30 PM PDT 24
Peak memory 219864 kb
Host smart-57a3941d-242d-4e9f-8442-fe3421f22114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102440657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4102440657
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2349695293
Short name T261
Test name
Test status
Simulation time 171040978 ps
CPU time 9.21 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:32 PM PDT 24
Peak memory 222304 kb
Host smart-20ae455a-0454-48c4-8b5a-8332f96f460f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349695293 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2349695293
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2625930330
Short name T140
Test name
Test status
Simulation time 144346803 ps
CPU time 4.69 seconds
Started Jul 22 07:15:47 PM PDT 24
Finished Jul 22 07:16:38 PM PDT 24
Peak memory 207516 kb
Host smart-c9e9fa97-29e9-4692-a0e2-6bdc3f0bb751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625930330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2625930330
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.526845558
Short name T398
Test name
Test status
Simulation time 86344132 ps
CPU time 1.81 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:25 PM PDT 24
Peak memory 209648 kb
Host smart-9f035075-e73d-496b-8bb2-f4011122225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526845558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.526845558
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2180794355
Short name T462
Test name
Test status
Simulation time 33648068 ps
CPU time 0.71 seconds
Started Jul 22 07:12:48 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 205804 kb
Host smart-1f5cd736-1aac-4761-9340-8d6911c25c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180794355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2180794355
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2970505501
Short name T798
Test name
Test status
Simulation time 20855955 ps
CPU time 1.71 seconds
Started Jul 22 07:13:07 PM PDT 24
Finished Jul 22 07:13:58 PM PDT 24
Peak memory 209596 kb
Host smart-93971c29-df2d-4885-8811-1fdf70984f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970505501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2970505501
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4255003188
Short name T397
Test name
Test status
Simulation time 95763059 ps
CPU time 4.09 seconds
Started Jul 22 07:12:48 PM PDT 24
Finished Jul 22 07:13:39 PM PDT 24
Peak memory 214120 kb
Host smart-1ce0ea95-d207-4d8f-806d-337ca23d7a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255003188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4255003188
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2651569838
Short name T760
Test name
Test status
Simulation time 33063012 ps
CPU time 1.56 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:32 PM PDT 24
Peak memory 214024 kb
Host smart-5e95b3c0-8eea-48e4-ab43-18c48e42a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651569838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2651569838
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2370069189
Short name T274
Test name
Test status
Simulation time 130181739 ps
CPU time 5.89 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 220324 kb
Host smart-4e07dfe9-cdd2-4e7d-a0a1-d5c01504d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370069189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2370069189
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.388407486
Short name T311
Test name
Test status
Simulation time 2219589255 ps
CPU time 67.91 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:14:38 PM PDT 24
Peak memory 209340 kb
Host smart-cb330bb1-7420-4ced-a158-ce20ededb066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388407486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.388407486
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3123690667
Short name T624
Test name
Test status
Simulation time 646286842 ps
CPU time 22.25 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 208264 kb
Host smart-98cfcba8-1314-4bac-8a3b-d5fc044bf08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123690667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3123690667
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2612271524
Short name T450
Test name
Test status
Simulation time 102187377 ps
CPU time 2.79 seconds
Started Jul 22 07:12:48 PM PDT 24
Finished Jul 22 07:13:38 PM PDT 24
Peak memory 208544 kb
Host smart-80474a06-d07e-4e06-b1a7-ec282e2372f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612271524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2612271524
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.744243509
Short name T489
Test name
Test status
Simulation time 197284002 ps
CPU time 2.65 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 206744 kb
Host smart-ac3f7891-0423-4ce0-acd9-0cb45273f647
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744243509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.744243509
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3699889658
Short name T372
Test name
Test status
Simulation time 41598764 ps
CPU time 2.4 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 206704 kb
Host smart-e18dd9d2-1225-45f2-a637-60ed6630edcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699889658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3699889658
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4039231679
Short name T409
Test name
Test status
Simulation time 75837519 ps
CPU time 1.89 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 207624 kb
Host smart-a9d4395d-a093-4b5b-a7bf-f5fc1b01949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039231679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4039231679
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2057737278
Short name T831
Test name
Test status
Simulation time 545322438 ps
CPU time 5.11 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:13:35 PM PDT 24
Peak memory 208024 kb
Host smart-4bb1d6b5-0d77-4ca5-b93d-2c9dcd7a4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057737278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2057737278
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3559368062
Short name T138
Test name
Test status
Simulation time 920267822 ps
CPU time 7.2 seconds
Started Jul 22 07:12:48 PM PDT 24
Finished Jul 22 07:13:42 PM PDT 24
Peak memory 222308 kb
Host smart-d3551d98-5299-4501-988b-be023da1b75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559368062 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3559368062
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2872375270
Short name T508
Test name
Test status
Simulation time 177168585 ps
CPU time 3.93 seconds
Started Jul 22 07:13:22 PM PDT 24
Finished Jul 22 07:14:18 PM PDT 24
Peak memory 208304 kb
Host smart-cc5ddd7a-0f89-4c7e-9651-a8488915569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872375270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2872375270
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3588868221
Short name T220
Test name
Test status
Simulation time 710456789 ps
CPU time 2.12 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:13:32 PM PDT 24
Peak memory 210000 kb
Host smart-4cd261a6-84be-44da-9c83-1068a41aa230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588868221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3588868221
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1103382592
Short name T609
Test name
Test status
Simulation time 48980332 ps
CPU time 0.7 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 205852 kb
Host smart-5fd71597-7c6d-44d9-b863-e0e1ce259d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103382592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1103382592
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1552974882
Short name T276
Test name
Test status
Simulation time 186299368 ps
CPU time 9.7 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:58 PM PDT 24
Peak memory 215132 kb
Host smart-6f6d5ed1-ee51-4a89-b308-1b2bbd382096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552974882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1552974882
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.563091492
Short name T765
Test name
Test status
Simulation time 173174023 ps
CPU time 3.71 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:02 PM PDT 24
Peak memory 214076 kb
Host smart-a2076506-e382-408d-b77e-da8b06558d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563091492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.563091492
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1556480195
Short name T59
Test name
Test status
Simulation time 37623795 ps
CPU time 2.57 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:51 PM PDT 24
Peak memory 209768 kb
Host smart-059531b4-b16d-4894-a82a-d465457da6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556480195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1556480195
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.510087817
Short name T317
Test name
Test status
Simulation time 115490115 ps
CPU time 3.81 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:15:56 PM PDT 24
Peak memory 214120 kb
Host smart-6866a762-c380-4da7-81f7-c4d3a4df6202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510087817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.510087817
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2454492832
Short name T278
Test name
Test status
Simulation time 285379556 ps
CPU time 2.49 seconds
Started Jul 22 07:15:28 PM PDT 24
Finished Jul 22 07:15:36 PM PDT 24
Peak memory 213996 kb
Host smart-bbf35178-eda9-46c8-b1a3-add1e8856691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454492832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2454492832
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3221362
Short name T918
Test name
Test status
Simulation time 91977727 ps
CPU time 2.42 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:49 PM PDT 24
Peak memory 214140 kb
Host smart-7ed3c52e-20bb-488a-a30d-f4413c2bc2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3221362
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4070653550
Short name T750
Test name
Test status
Simulation time 94852811 ps
CPU time 3.72 seconds
Started Jul 22 07:15:30 PM PDT 24
Finished Jul 22 07:15:49 PM PDT 24
Peak memory 207876 kb
Host smart-fe1d5211-0304-484b-9908-c34697013e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070653550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4070653550
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2175300266
Short name T283
Test name
Test status
Simulation time 6430253222 ps
CPU time 37.64 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:54 PM PDT 24
Peak memory 208532 kb
Host smart-cb9c5a5d-f8ab-403f-8ef7-0b1f2cb9da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175300266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2175300266
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2120119407
Short name T576
Test name
Test status
Simulation time 98646765 ps
CPU time 1.83 seconds
Started Jul 22 07:17:50 PM PDT 24
Finished Jul 22 07:18:45 PM PDT 24
Peak memory 207104 kb
Host smart-8c4f05f1-4bf1-4e15-a003-04640f28eb27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120119407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2120119407
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2894737662
Short name T844
Test name
Test status
Simulation time 65631812 ps
CPU time 3.11 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:26 PM PDT 24
Peak memory 207476 kb
Host smart-8c1090de-7a96-42b0-a84b-a4a32d307496
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894737662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2894737662
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1969371177
Short name T467
Test name
Test status
Simulation time 5400256054 ps
CPU time 61.33 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:17:10 PM PDT 24
Peak memory 208280 kb
Host smart-212a6651-7f77-43ba-b7bb-ce120d0274d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969371177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1969371177
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2940207264
Short name T363
Test name
Test status
Simulation time 33806221 ps
CPU time 2.1 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:48 PM PDT 24
Peak memory 218024 kb
Host smart-aa45fc95-79aa-4d1f-800d-a1d40ef9dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940207264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2940207264
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.252502976
Short name T443
Test name
Test status
Simulation time 411175306 ps
CPU time 2.69 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:26 PM PDT 24
Peak memory 208460 kb
Host smart-875228a2-83cc-4e21-9a83-db37190dedf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252502976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.252502976
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2255475719
Short name T540
Test name
Test status
Simulation time 293819728 ps
CPU time 9.45 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:20 PM PDT 24
Peak memory 207816 kb
Host smart-43ff4a5a-ddf6-4d7d-916c-7e534cf07c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255475719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2255475719
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3797273674
Short name T888
Test name
Test status
Simulation time 303285717 ps
CPU time 11.64 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:22 PM PDT 24
Peak memory 222212 kb
Host smart-1bda2c8b-d5a9-4e31-af31-6de51166ae5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797273674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3797273674
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.688507559
Short name T811
Test name
Test status
Simulation time 906578287 ps
CPU time 7.47 seconds
Started Jul 22 07:15:31 PM PDT 24
Finished Jul 22 07:15:53 PM PDT 24
Peak memory 207828 kb
Host smart-0fa29b1e-f6f3-479d-b601-8a4ea8030ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688507559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.688507559
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1678029790
Short name T174
Test name
Test status
Simulation time 109421548 ps
CPU time 2.7 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:22 PM PDT 24
Peak memory 210556 kb
Host smart-120f8309-6483-4069-a743-356f23fd0462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678029790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1678029790
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1224586305
Short name T464
Test name
Test status
Simulation time 50993387 ps
CPU time 0.84 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:06 PM PDT 24
Peak memory 205828 kb
Host smart-469d02fe-5016-4795-9646-31c5705d7b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224586305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1224586305
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1543863818
Short name T568
Test name
Test status
Simulation time 263789253 ps
CPU time 1.75 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:00 PM PDT 24
Peak memory 208156 kb
Host smart-cf23ca97-72e5-48a6-80a7-754b9726fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543863818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1543863818
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3956892192
Short name T602
Test name
Test status
Simulation time 1073409907 ps
CPU time 19.29 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:26 PM PDT 24
Peak memory 209552 kb
Host smart-73cde279-81b8-4cce-8817-3d1b9f94b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956892192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3956892192
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2679123656
Short name T554
Test name
Test status
Simulation time 297955382 ps
CPU time 3.49 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:20 PM PDT 24
Peak memory 214292 kb
Host smart-8ef4e810-bb14-45bd-ab66-d4cec7ac76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679123656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2679123656
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.448534160
Short name T841
Test name
Test status
Simulation time 734345141 ps
CPU time 3.67 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:22 PM PDT 24
Peak memory 215108 kb
Host smart-52a2fadb-c5b9-4376-886c-a7f007d17e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448534160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.448534160
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.626148854
Short name T690
Test name
Test status
Simulation time 168978034 ps
CPU time 2.98 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:08 PM PDT 24
Peak memory 206892 kb
Host smart-003aea2b-efb4-4420-8e85-ff204e5bf5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626148854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.626148854
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1085563349
Short name T541
Test name
Test status
Simulation time 2483487453 ps
CPU time 21.5 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:24 PM PDT 24
Peak memory 206796 kb
Host smart-8ed02331-c185-4559-bd52-c666f890d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085563349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1085563349
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1837422476
Short name T471
Test name
Test status
Simulation time 713865027 ps
CPU time 4.49 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:07 PM PDT 24
Peak memory 207724 kb
Host smart-5de85277-7a51-44ea-9886-2fa1942044db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837422476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1837422476
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.557699457
Short name T320
Test name
Test status
Simulation time 125729016 ps
CPU time 2.32 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:18 PM PDT 24
Peak memory 207348 kb
Host smart-5be0305d-b02f-4767-ac15-92071e10c134
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557699457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.557699457
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4254904391
Short name T304
Test name
Test status
Simulation time 78046616 ps
CPU time 2.78 seconds
Started Jul 22 07:15:36 PM PDT 24
Finished Jul 22 07:16:06 PM PDT 24
Peak memory 208760 kb
Host smart-4bbdad57-6ade-4244-9f38-5d6ea482b28f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254904391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4254904391
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.230708267
Short name T529
Test name
Test status
Simulation time 115173906 ps
CPU time 1.4 seconds
Started Jul 22 07:15:52 PM PDT 24
Finished Jul 22 07:16:43 PM PDT 24
Peak memory 208448 kb
Host smart-204641b5-2ab0-47e2-8c8a-9ac9ec5ac509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230708267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.230708267
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1039361647
Short name T117
Test name
Test status
Simulation time 1579233012 ps
CPU time 12.41 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 207732 kb
Host smart-36fe122f-06f0-4a75-81fe-06f35a6b598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039361647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1039361647
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1159978251
Short name T69
Test name
Test status
Simulation time 1144155913 ps
CPU time 13.59 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:16 PM PDT 24
Peak memory 222324 kb
Host smart-cdeb27be-8c2c-42a6-998f-f27746533f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159978251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1159978251
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1443495527
Short name T277
Test name
Test status
Simulation time 84569867 ps
CPU time 3.08 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:17 PM PDT 24
Peak memory 222072 kb
Host smart-889d57b6-5dea-4bef-8d29-b3e92955822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443495527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1443495527
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2956786371
Short name T404
Test name
Test status
Simulation time 197897803 ps
CPU time 2.62 seconds
Started Jul 22 07:15:35 PM PDT 24
Finished Jul 22 07:16:03 PM PDT 24
Peak memory 209992 kb
Host smart-2bec28e7-a537-483a-a7ab-40f44489da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956786371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2956786371
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3118702364
Short name T779
Test name
Test status
Simulation time 15394495 ps
CPU time 0.85 seconds
Started Jul 22 07:15:32 PM PDT 24
Finished Jul 22 07:15:55 PM PDT 24
Peak memory 205796 kb
Host smart-4f42be53-683d-4828-9444-95034731a7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118702364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3118702364
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.867268947
Short name T154
Test name
Test status
Simulation time 52842365 ps
CPU time 3.81 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:25 PM PDT 24
Peak memory 214092 kb
Host smart-075c2fe5-aefb-4fed-81a0-58d62b9b412a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867268947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.867268947
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3283229033
Short name T589
Test name
Test status
Simulation time 680236244 ps
CPU time 3.53 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:27 PM PDT 24
Peak memory 214140 kb
Host smart-3c2e7191-e81d-4cc0-9d24-c9dc789e7276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283229033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3283229033
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2383843505
Short name T810
Test name
Test status
Simulation time 203818454 ps
CPU time 2.03 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:18 PM PDT 24
Peak memory 209604 kb
Host smart-8df2523f-89b8-420f-93fe-55f887dd5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383843505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2383843505
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2022255086
Short name T25
Test name
Test status
Simulation time 58894315 ps
CPU time 3.23 seconds
Started Jul 22 07:15:14 PM PDT 24
Finished Jul 22 07:15:21 PM PDT 24
Peak memory 222208 kb
Host smart-ad1480d5-31ea-4807-bfaa-c58207455e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022255086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2022255086
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3554254093
Short name T93
Test name
Test status
Simulation time 156051620 ps
CPU time 3.54 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:20 PM PDT 24
Peak memory 213860 kb
Host smart-7863dcdc-c9c8-4d0a-ae22-8145376501a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554254093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3554254093
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.711955398
Short name T385
Test name
Test status
Simulation time 417777085 ps
CPU time 6.85 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:17 PM PDT 24
Peak memory 216776 kb
Host smart-34835354-2835-4989-a52c-b88cc23fdf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711955398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.711955398
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2711265190
Short name T710
Test name
Test status
Simulation time 59665837 ps
CPU time 2.42 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:11 PM PDT 24
Peak memory 208220 kb
Host smart-aaf432c4-e18a-449b-98b2-ce41ab80f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711265190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2711265190
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3956111896
Short name T343
Test name
Test status
Simulation time 4678841239 ps
CPU time 30 seconds
Started Jul 22 07:16:27 PM PDT 24
Finished Jul 22 07:18:02 PM PDT 24
Peak memory 208012 kb
Host smart-099a2570-f68c-4762-9278-2b667a5144e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956111896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3956111896
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1405235635
Short name T575
Test name
Test status
Simulation time 36535755 ps
CPU time 2.31 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 206616 kb
Host smart-048e7ae1-c4be-4153-912c-a1b8e2f8b8ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405235635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1405235635
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1593711956
Short name T535
Test name
Test status
Simulation time 70822070 ps
CPU time 2.14 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:12 PM PDT 24
Peak memory 208464 kb
Host smart-550ca7d3-71f8-4e2c-a5a8-dbe4b1245bd8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593711956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1593711956
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3821348546
Short name T455
Test name
Test status
Simulation time 184151008 ps
CPU time 3.79 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:14 PM PDT 24
Peak memory 206512 kb
Host smart-a6267115-9f03-4bd4-bfe4-772d5b4d9dc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821348546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3821348546
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.546891399
Short name T819
Test name
Test status
Simulation time 105653998 ps
CPU time 3.72 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:17 PM PDT 24
Peak memory 208900 kb
Host smart-942ca1ab-ce8d-49ca-b197-418c100efc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546891399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.546891399
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.668803467
Short name T81
Test name
Test status
Simulation time 693529444 ps
CPU time 4.28 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:16 PM PDT 24
Peak memory 206448 kb
Host smart-acf8e8bd-3967-4a9e-9d2a-603b1b6d291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668803467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.668803467
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3323901588
Short name T335
Test name
Test status
Simulation time 1726733810 ps
CPU time 5.1 seconds
Started Jul 22 07:15:38 PM PDT 24
Finished Jul 22 07:16:15 PM PDT 24
Peak memory 210352 kb
Host smart-6d1f2539-5793-4988-a47a-743658c1c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323901588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3323901588
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2320680913
Short name T655
Test name
Test status
Simulation time 183353650 ps
CPU time 3.33 seconds
Started Jul 22 07:15:37 PM PDT 24
Finished Jul 22 07:16:10 PM PDT 24
Peak memory 210220 kb
Host smart-67b25a08-99f2-42f9-976c-d4597945741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320680913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2320680913
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1922272697
Short name T591
Test name
Test status
Simulation time 85844917 ps
CPU time 0.79 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:43 PM PDT 24
Peak memory 205828 kb
Host smart-8693adc6-e46b-43b9-9a53-d8e4e7a7b9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922272697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1922272697
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3758643907
Short name T266
Test name
Test status
Simulation time 63170814 ps
CPU time 2.96 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:02 PM PDT 24
Peak memory 214124 kb
Host smart-7c495933-5179-42c6-9493-ccb20fd5f846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758643907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3758643907
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2011200476
Short name T618
Test name
Test status
Simulation time 203473617 ps
CPU time 4.13 seconds
Started Jul 22 07:17:57 PM PDT 24
Finished Jul 22 07:18:50 PM PDT 24
Peak memory 219420 kb
Host smart-c66aa755-36e4-4706-b0ee-dbd82bb17661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011200476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2011200476
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4062686779
Short name T79
Test name
Test status
Simulation time 118963595 ps
CPU time 2.92 seconds
Started Jul 22 07:15:39 PM PDT 24
Finished Jul 22 07:16:16 PM PDT 24
Peak memory 207736 kb
Host smart-58cf48aa-6610-4a1f-94ce-b24132ea2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062686779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4062686779
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.75988556
Short name T97
Test name
Test status
Simulation time 82741420 ps
CPU time 4.1 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:32 PM PDT 24
Peak memory 214032 kb
Host smart-3f7de766-f674-4a11-9703-09a3e1996afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75988556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.75988556
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1416800503
Short name T550
Test name
Test status
Simulation time 52860512 ps
CPU time 1.79 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:25 PM PDT 24
Peak memory 214060 kb
Host smart-e1bd5cf3-ba1d-4473-9fc1-910fc97d633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416800503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1416800503
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1311923173
Short name T396
Test name
Test status
Simulation time 624709038 ps
CPU time 4.82 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 208584 kb
Host smart-4d81a98e-dd45-4f93-8ae5-90c093d7bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311923173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1311923173
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3557869375
Short name T726
Test name
Test status
Simulation time 131736030 ps
CPU time 4.05 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:58 PM PDT 24
Peak memory 206540 kb
Host smart-ed424ecf-07fc-414f-a682-8c53f3a70b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557869375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3557869375
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2990045519
Short name T391
Test name
Test status
Simulation time 33683903 ps
CPU time 2.37 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:01 PM PDT 24
Peak memory 208332 kb
Host smart-e0b2ab5a-3b73-4dff-baf1-0ab03f811912
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990045519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2990045519
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1872532879
Short name T515
Test name
Test status
Simulation time 678429927 ps
CPU time 17.32 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:16:15 PM PDT 24
Peak memory 207820 kb
Host smart-258c8d50-0dbb-41ce-b8d4-74b9243d6f07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872532879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1872532879
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1186852831
Short name T788
Test name
Test status
Simulation time 695194741 ps
CPU time 5.19 seconds
Started Jul 22 07:15:34 PM PDT 24
Finished Jul 22 07:16:04 PM PDT 24
Peak memory 208328 kb
Host smart-42343be4-3c5b-48ef-83df-78602ebb5ecc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186852831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1186852831
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3722165318
Short name T566
Test name
Test status
Simulation time 356598421 ps
CPU time 2.75 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:36 PM PDT 24
Peak memory 215540 kb
Host smart-ca402c90-b70c-4ff1-8200-a98d1e60daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722165318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3722165318
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1527608607
Short name T477
Test name
Test status
Simulation time 194500377 ps
CPU time 4.57 seconds
Started Jul 22 07:15:33 PM PDT 24
Finished Jul 22 07:15:59 PM PDT 24
Peak memory 206536 kb
Host smart-85a8ee46-859e-4274-be9f-51f89d0e3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527608607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1527608607
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3175079088
Short name T511
Test name
Test status
Simulation time 33445061 ps
CPU time 2.52 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:21 PM PDT 24
Peak memory 214124 kb
Host smart-8a981683-b738-4e86-8ed7-e0b16b2ed094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175079088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3175079088
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1963018290
Short name T881
Test name
Test status
Simulation time 45846409 ps
CPU time 0.77 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:38 PM PDT 24
Peak memory 205820 kb
Host smart-58bebd65-0029-4961-8ca4-7d77da60d7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963018290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1963018290
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3801917893
Short name T756
Test name
Test status
Simulation time 44502890 ps
CPU time 3.05 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:26 PM PDT 24
Peak memory 215040 kb
Host smart-d0933f51-e1ed-4090-bd75-8fc1c3b54761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801917893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3801917893
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.946451218
Short name T31
Test name
Test status
Simulation time 186900238 ps
CPU time 3.03 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:26 PM PDT 24
Peak memory 215464 kb
Host smart-f4a60bfd-1d7c-4feb-9860-d3455b92c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946451218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.946451218
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1303314445
Short name T683
Test name
Test status
Simulation time 287139343 ps
CPU time 3.12 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:24 PM PDT 24
Peak memory 207164 kb
Host smart-61937050-2b0b-4eef-80f3-4eeaf21234f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303314445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1303314445
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2230601545
Short name T793
Test name
Test status
Simulation time 89600469 ps
CPU time 1.96 seconds
Started Jul 22 07:17:58 PM PDT 24
Finished Jul 22 07:18:49 PM PDT 24
Peak memory 214028 kb
Host smart-32c6c01a-3cca-4878-afc8-f715a8a68a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230601545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2230601545
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3760543506
Short name T532
Test name
Test status
Simulation time 289474188 ps
CPU time 3.43 seconds
Started Jul 22 07:15:41 PM PDT 24
Finished Jul 22 07:16:22 PM PDT 24
Peak memory 222284 kb
Host smart-88417816-8ed3-47e8-9afa-f4e2081ad80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760543506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3760543506
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.365037218
Short name T9
Test name
Test status
Simulation time 232060789 ps
CPU time 2.43 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:31 PM PDT 24
Peak memory 214136 kb
Host smart-62ae6007-1c18-47cb-9af7-723b877e170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365037218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.365037218
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2409086173
Short name T490
Test name
Test status
Simulation time 7780957961 ps
CPU time 60.19 seconds
Started Jul 22 07:15:47 PM PDT 24
Finished Jul 22 07:17:34 PM PDT 24
Peak memory 220076 kb
Host smart-32e6f47e-9660-48b1-8f51-92e0429882ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409086173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2409086173
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2444074820
Short name T478
Test name
Test status
Simulation time 123811395 ps
CPU time 2.88 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:24 PM PDT 24
Peak memory 208208 kb
Host smart-115fbdcc-6556-4fc9-847a-3b6cb7c21be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444074820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2444074820
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1760777200
Short name T878
Test name
Test status
Simulation time 6030071763 ps
CPU time 13.01 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:34 PM PDT 24
Peak memory 208916 kb
Host smart-a5a904bb-050a-4efe-b744-b31df1926420
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760777200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1760777200
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1000313376
Short name T646
Test name
Test status
Simulation time 258962717 ps
CPU time 3.27 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 206712 kb
Host smart-10493c3d-a6fd-4311-9334-5fb0d937f958
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000313376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1000313376
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1733243166
Short name T598
Test name
Test status
Simulation time 116543661 ps
CPU time 3.17 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:40 PM PDT 24
Peak memory 209312 kb
Host smart-711cd9b9-759b-40b4-8bde-f72537866629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733243166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1733243166
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4292726472
Short name T413
Test name
Test status
Simulation time 230460791 ps
CPU time 2.7 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:16:33 PM PDT 24
Peak memory 206560 kb
Host smart-475f5839-767e-49f4-9f66-506c78369bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292726472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4292726472
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3685863327
Short name T871
Test name
Test status
Simulation time 1984703630 ps
CPU time 27.27 seconds
Started Jul 22 07:17:53 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 215476 kb
Host smart-05a5bcfc-f1ad-4f03-bc2c-2d7edb4cae8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685863327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3685863327
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4223794971
Short name T459
Test name
Test status
Simulation time 246645175 ps
CPU time 5.3 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:27 PM PDT 24
Peak memory 208036 kb
Host smart-2b87375a-8909-47ba-8739-a0eb09383906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223794971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4223794971
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.759030734
Short name T401
Test name
Test status
Simulation time 38558883 ps
CPU time 2 seconds
Started Jul 22 07:17:43 PM PDT 24
Finished Jul 22 07:18:38 PM PDT 24
Peak memory 209580 kb
Host smart-72b8c4da-1d4b-449c-9980-58bc6a6678ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759030734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.759030734
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1868022426
Short name T637
Test name
Test status
Simulation time 14270678 ps
CPU time 0.73 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:37 PM PDT 24
Peak memory 205824 kb
Host smart-cb8dc63b-b556-4ae6-822e-65172ee7d21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868022426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1868022426
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1672156428
Short name T41
Test name
Test status
Simulation time 1188536703 ps
CPU time 10.74 seconds
Started Jul 22 07:19:09 PM PDT 24
Finished Jul 22 07:19:59 PM PDT 24
Peak memory 214080 kb
Host smart-36f3ab42-33c4-40a3-b97d-23a02b6fe7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672156428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1672156428
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3780596127
Short name T729
Test name
Test status
Simulation time 1791489827 ps
CPU time 12.65 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 210268 kb
Host smart-c70112f8-add1-4917-a6a3-f9b517b1e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780596127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3780596127
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.677140310
Short name T470
Test name
Test status
Simulation time 31126776 ps
CPU time 2.13 seconds
Started Jul 22 07:19:10 PM PDT 24
Finished Jul 22 07:19:51 PM PDT 24
Peak memory 213968 kb
Host smart-24086d9e-3476-4088-b68e-b67683640217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677140310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.677140310
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.900592014
Short name T650
Test name
Test status
Simulation time 696614657 ps
CPU time 2.43 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:28 PM PDT 24
Peak memory 213996 kb
Host smart-09858061-75da-4557-bd8e-9325b73568d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900592014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.900592014
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2973122709
Short name T243
Test name
Test status
Simulation time 540284577 ps
CPU time 5.46 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 210020 kb
Host smart-2893b5ce-e03d-4fdc-8187-1f261323a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973122709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2973122709
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.436399257
Short name T491
Test name
Test status
Simulation time 188262379 ps
CPU time 5.38 seconds
Started Jul 22 07:19:10 PM PDT 24
Finished Jul 22 07:19:54 PM PDT 24
Peak memory 207808 kb
Host smart-6baccc3b-d2ac-4812-8e6f-907648dffcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436399257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.436399257
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1622830134
Short name T613
Test name
Test status
Simulation time 55205727 ps
CPU time 1.81 seconds
Started Jul 22 07:15:40 PM PDT 24
Finished Jul 22 07:16:19 PM PDT 24
Peak memory 207952 kb
Host smart-1391e183-548a-4c43-aa5d-171dd6306805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622830134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1622830134
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2635117135
Short name T512
Test name
Test status
Simulation time 133606165 ps
CPU time 3.42 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 208272 kb
Host smart-22778338-e543-45a5-bfe5-4542d6696557
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635117135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2635117135
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3906383556
Short name T293
Test name
Test status
Simulation time 888890761 ps
CPU time 7.39 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:36 PM PDT 24
Peak memory 208456 kb
Host smart-1206c4df-d583-43d0-be76-e6105b368e0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906383556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3906383556
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3323447557
Short name T553
Test name
Test status
Simulation time 103368199 ps
CPU time 4.23 seconds
Started Jul 22 07:17:56 PM PDT 24
Finished Jul 22 07:18:50 PM PDT 24
Peak memory 208720 kb
Host smart-6be8dd69-3cc8-4f4e-a18e-92f710da0071
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323447557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3323447557
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.137686167
Short name T165
Test name
Test status
Simulation time 232616511 ps
CPU time 3.42 seconds
Started Jul 22 07:19:10 PM PDT 24
Finished Jul 22 07:19:52 PM PDT 24
Peak memory 214032 kb
Host smart-2d446552-8c41-4f91-8385-f5f9e6204b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137686167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.137686167
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3018318126
Short name T714
Test name
Test status
Simulation time 3870993386 ps
CPU time 21.31 seconds
Started Jul 22 07:17:56 PM PDT 24
Finished Jul 22 07:19:07 PM PDT 24
Peak memory 207932 kb
Host smart-c5010135-4e00-4f49-8641-feedb8aab271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018318126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3018318126
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.522440356
Short name T387
Test name
Test status
Simulation time 263059640 ps
CPU time 16.44 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:16:45 PM PDT 24
Peak memory 219892 kb
Host smart-e1c62dc8-1ff6-4d66-89f2-c63d9a005cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522440356 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.522440356
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1144704252
Short name T889
Test name
Test status
Simulation time 278443542 ps
CPU time 3.35 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 207816 kb
Host smart-d2044ab9-100a-4d2e-a94a-641d8fc4cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144704252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1144704252
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2499395136
Short name T539
Test name
Test status
Simulation time 122312886 ps
CPU time 1.93 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:57 PM PDT 24
Peak memory 209036 kb
Host smart-eacdc29c-40ff-4517-ad25-4695e1ae9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499395136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2499395136
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1006158687
Short name T446
Test name
Test status
Simulation time 53896182 ps
CPU time 0.88 seconds
Started Jul 22 07:15:47 PM PDT 24
Finished Jul 22 07:16:34 PM PDT 24
Peak memory 205920 kb
Host smart-3f70cd1b-6a5c-48f5-88e4-a3b5b4f5a9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006158687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1006158687
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2880176894
Short name T292
Test name
Test status
Simulation time 40185453 ps
CPU time 2.74 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:45 PM PDT 24
Peak memory 215208 kb
Host smart-d7396648-1ced-4b89-ab61-1825aafaca94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880176894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2880176894
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2983394244
Short name T617
Test name
Test status
Simulation time 177377895 ps
CPU time 2.37 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 221144 kb
Host smart-d5a7b432-9588-484d-851e-69775d5d36b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983394244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2983394244
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2986017607
Short name T737
Test name
Test status
Simulation time 31370265 ps
CPU time 2.01 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:45 PM PDT 24
Peak memory 214044 kb
Host smart-cbfec5e9-7a44-434c-b42c-62be203a9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986017607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2986017607
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4140167207
Short name T100
Test name
Test status
Simulation time 99798283 ps
CPU time 4.27 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:46 PM PDT 24
Peak memory 218900 kb
Host smart-1359c03e-ab66-44a6-a29d-fd4f7e7ee075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140167207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4140167207
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2653966437
Short name T303
Test name
Test status
Simulation time 41330060 ps
CPU time 2.13 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:45 PM PDT 24
Peak memory 214040 kb
Host smart-e70cf107-b03c-4792-9f1c-695a7b0c1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653966437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2653966437
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1803128508
Short name T571
Test name
Test status
Simulation time 168265664 ps
CPU time 1.74 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:27 PM PDT 24
Peak memory 205784 kb
Host smart-70557938-728b-4265-a91c-7c7026226f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803128508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1803128508
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.810979591
Short name T748
Test name
Test status
Simulation time 52560281 ps
CPU time 2.82 seconds
Started Jul 22 07:15:52 PM PDT 24
Finished Jul 22 07:16:44 PM PDT 24
Peak memory 208304 kb
Host smart-a3245eeb-ef33-49b6-b0fe-1490421d98ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810979591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.810979591
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.999427882
Short name T294
Test name
Test status
Simulation time 406588029 ps
CPU time 5.32 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:16:43 PM PDT 24
Peak memory 208240 kb
Host smart-d2b0e052-8ca9-4f30-9e39-b6b2a5d51e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999427882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.999427882
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2836712801
Short name T630
Test name
Test status
Simulation time 2779311196 ps
CPU time 19.53 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:16:57 PM PDT 24
Peak memory 208188 kb
Host smart-d99e700c-1604-4d9f-a18f-2cd1ec54b773
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836712801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2836712801
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2760783682
Short name T559
Test name
Test status
Simulation time 60989501 ps
CPU time 2.17 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:37 PM PDT 24
Peak memory 206496 kb
Host smart-bef68310-a7ff-4c0a-8431-6254794e0726
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760783682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2760783682
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2111631883
Short name T734
Test name
Test status
Simulation time 1144905795 ps
CPU time 7.4 seconds
Started Jul 22 07:15:51 PM PDT 24
Finished Jul 22 07:16:47 PM PDT 24
Peak memory 208612 kb
Host smart-d67cb7a0-c237-47e1-9930-d2a03ee2a9ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111631883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2111631883
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3292337599
Short name T894
Test name
Test status
Simulation time 1439021176 ps
CPU time 6.89 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:30 PM PDT 24
Peak memory 207944 kb
Host smart-99307b6a-1ac7-4f3e-bacc-956bd4ab57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292337599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3292337599
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2854908227
Short name T231
Test name
Test status
Simulation time 138539164 ps
CPU time 2.27 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:38 PM PDT 24
Peak memory 206644 kb
Host smart-58b74248-48c8-49c6-94d6-893e2957b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854908227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2854908227
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1992387473
Short name T704
Test name
Test status
Simulation time 14904814045 ps
CPU time 126.96 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:18:42 PM PDT 24
Peak memory 216016 kb
Host smart-644d3c3b-d4c8-41ce-8a4d-5ecb375aad2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992387473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1992387473
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.130912756
Short name T137
Test name
Test status
Simulation time 2006891955 ps
CPU time 24.84 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:35 PM PDT 24
Peak memory 222376 kb
Host smart-c18530df-d428-46dc-9cdf-ff01bc2021fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130912756 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.130912756
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2079996643
Short name T325
Test name
Test status
Simulation time 219693186 ps
CPU time 5.47 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:41 PM PDT 24
Peak memory 207976 kb
Host smart-95317029-a94d-4d81-abc4-6caf5b470022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079996643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2079996643
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.320727569
Short name T198
Test name
Test status
Simulation time 3753826991 ps
CPU time 16.05 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:44 PM PDT 24
Peak memory 211420 kb
Host smart-01a37a4c-cf9f-4a23-8971-70b0aaadf1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320727569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.320727569
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1481341778
Short name T472
Test name
Test status
Simulation time 8888403 ps
CPU time 0.71 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:16:32 PM PDT 24
Peak memory 205744 kb
Host smart-61c30b2d-8829-40a1-838e-385e881c2820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481341778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1481341778
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3643528099
Short name T269
Test name
Test status
Simulation time 31681339 ps
CPU time 2.47 seconds
Started Jul 22 07:18:16 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 214088 kb
Host smart-1bad2978-4bc0-43b5-88d5-9670a607cb36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643528099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3643528099
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2595477772
Short name T826
Test name
Test status
Simulation time 38937664 ps
CPU time 1.9 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:16:33 PM PDT 24
Peak memory 208852 kb
Host smart-3b3998de-0fe2-4ac0-8736-10e6358c80b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595477772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2595477772
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4043418456
Short name T628
Test name
Test status
Simulation time 65612376 ps
CPU time 2.47 seconds
Started Jul 22 07:16:18 PM PDT 24
Finished Jul 22 07:17:22 PM PDT 24
Peak memory 214076 kb
Host smart-8f51e8c4-567a-4fe5-b0cc-e5e149af7f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043418456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4043418456
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2541614285
Short name T658
Test name
Test status
Simulation time 112096714 ps
CPU time 2.23 seconds
Started Jul 22 07:15:42 PM PDT 24
Finished Jul 22 07:16:23 PM PDT 24
Peak memory 214116 kb
Host smart-a1c10f6d-5992-4d7f-9881-0db829520c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541614285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2541614285
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_random.484099254
Short name T876
Test name
Test status
Simulation time 153988517 ps
CPU time 5.26 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:16:44 PM PDT 24
Peak memory 214236 kb
Host smart-5574af5e-7f7a-4353-b11a-2137c31127c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484099254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.484099254
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3954222183
Short name T715
Test name
Test status
Simulation time 181995750 ps
CPU time 2.71 seconds
Started Jul 22 07:18:14 PM PDT 24
Finished Jul 22 07:19:10 PM PDT 24
Peak memory 207556 kb
Host smart-4bdc940a-045c-48e7-b8e9-ee1319cd764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954222183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3954222183
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3184022754
Short name T666
Test name
Test status
Simulation time 1026078487 ps
CPU time 35.45 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:17:13 PM PDT 24
Peak memory 208876 kb
Host smart-70daf1d5-9c12-4245-8982-c837f9f2495c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184022754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3184022754
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1989280074
Short name T915
Test name
Test status
Simulation time 1847428763 ps
CPU time 5.12 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:15 PM PDT 24
Peak memory 208408 kb
Host smart-bf6f93d0-5f83-4aff-afbd-ac4fa7154812
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989280074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1989280074
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.412413468
Short name T240
Test name
Test status
Simulation time 105101269 ps
CPU time 3.56 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 206668 kb
Host smart-64fe7216-4722-4e80-abb4-85a393a9fade
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412413468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.412413468
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3023773830
Short name T752
Test name
Test status
Simulation time 2995464752 ps
CPU time 25.8 seconds
Started Jul 22 07:16:18 PM PDT 24
Finished Jul 22 07:17:44 PM PDT 24
Peak memory 208484 kb
Host smart-1e768689-b019-4052-b882-8303d6fc4f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023773830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3023773830
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4034644088
Short name T217
Test name
Test status
Simulation time 223817797 ps
CPU time 5.1 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:42 PM PDT 24
Peak memory 208288 kb
Host smart-52f89ec8-ac98-4ddb-8602-45aefa43f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034644088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4034644088
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3215515938
Short name T76
Test name
Test status
Simulation time 5810792378 ps
CPU time 31.11 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:57 PM PDT 24
Peak memory 216472 kb
Host smart-c0bb0c36-6935-4e4d-8235-6e29e0364fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215515938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3215515938
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2967717379
Short name T54
Test name
Test status
Simulation time 201345389 ps
CPU time 11.45 seconds
Started Jul 22 07:15:44 PM PDT 24
Finished Jul 22 07:16:37 PM PDT 24
Peak memory 220960 kb
Host smart-87481be8-3891-419a-a6fd-5a8035b0a40e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967717379 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2967717379
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3093960504
Short name T67
Test name
Test status
Simulation time 130802195 ps
CPU time 2.88 seconds
Started Jul 22 07:17:58 PM PDT 24
Finished Jul 22 07:18:50 PM PDT 24
Peak memory 209912 kb
Host smart-f73f7650-041e-4fe8-b433-9f0e0f35a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093960504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3093960504
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.450284017
Short name T473
Test name
Test status
Simulation time 21786055 ps
CPU time 0.91 seconds
Started Jul 22 07:15:51 PM PDT 24
Finished Jul 22 07:16:40 PM PDT 24
Peak memory 205976 kb
Host smart-35915cac-23f4-4fef-8379-b60eeb810aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450284017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.450284017
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4064974016
Short name T778
Test name
Test status
Simulation time 445376837 ps
CPU time 4.08 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:59 PM PDT 24
Peak memory 214056 kb
Host smart-613b40a0-c487-4f49-930f-b5cf5fecdad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064974016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4064974016
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4008677253
Short name T481
Test name
Test status
Simulation time 226468889 ps
CPU time 4.52 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:28 PM PDT 24
Peak memory 207028 kb
Host smart-043ccf96-ee83-4220-a201-bc2e164b8b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008677253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4008677253
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1753866872
Short name T384
Test name
Test status
Simulation time 93221612 ps
CPU time 4.09 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:59 PM PDT 24
Peak memory 213460 kb
Host smart-2a11d327-2520-4177-8fa5-a3b62d94ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753866872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1753866872
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3017078808
Short name T816
Test name
Test status
Simulation time 102319061 ps
CPU time 2.49 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:37 PM PDT 24
Peak memory 214168 kb
Host smart-31c94d17-988b-4aa0-bb5e-c6c579cf0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017078808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3017078808
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4223422613
Short name T886
Test name
Test status
Simulation time 83635572 ps
CPU time 3.41 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:16:34 PM PDT 24
Peak memory 208396 kb
Host smart-187499f2-7d0a-43a8-bba4-344fcf9485cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223422613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4223422613
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2745780908
Short name T772
Test name
Test status
Simulation time 1143045055 ps
CPU time 24.75 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 209140 kb
Host smart-e9a7bbfb-5611-4234-9471-af9a1067df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745780908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2745780908
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.788103287
Short name T163
Test name
Test status
Simulation time 105781673 ps
CPU time 2.64 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 208388 kb
Host smart-46dbcd8a-fd78-4dce-bb86-f42ef27e71af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788103287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.788103287
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.740536226
Short name T497
Test name
Test status
Simulation time 205244892 ps
CPU time 2.48 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:57 PM PDT 24
Peak memory 206648 kb
Host smart-c2c23405-a93e-4137-945d-9c82d4b04db0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740536226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.740536226
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2314058514
Short name T806
Test name
Test status
Simulation time 3804906878 ps
CPU time 58.29 seconds
Started Jul 22 07:15:46 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 208404 kb
Host smart-3313471c-9631-48e3-bf7d-5c87ede8d159
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314058514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2314058514
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1124721576
Short name T453
Test name
Test status
Simulation time 283826790 ps
CPU time 3.53 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:59 PM PDT 24
Peak memory 208408 kb
Host smart-103eac5b-3eea-4325-9d5c-5cecab7f6254
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124721576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1124721576
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1085152922
Short name T919
Test name
Test status
Simulation time 100863528 ps
CPU time 1.77 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 215252 kb
Host smart-3cc4f499-bdcf-4db1-b2c9-3380b5c17cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085152922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1085152922
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2124938741
Short name T581
Test name
Test status
Simulation time 326578030 ps
CPU time 2.32 seconds
Started Jul 22 07:15:55 PM PDT 24
Finished Jul 22 07:16:50 PM PDT 24
Peak memory 207988 kb
Host smart-b4cebc3a-5793-492e-a185-87b2bd27ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124938741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2124938741
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.379961175
Short name T342
Test name
Test status
Simulation time 1664852132 ps
CPU time 24.63 seconds
Started Jul 22 07:15:50 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 222424 kb
Host smart-5c875124-d40e-4542-93ea-c5f75abb1377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379961175 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.379961175
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1985104815
Short name T500
Test name
Test status
Simulation time 710877407 ps
CPU time 16 seconds
Started Jul 22 07:19:10 PM PDT 24
Finished Jul 22 07:20:04 PM PDT 24
Peak memory 208128 kb
Host smart-24724843-0636-4c1c-abf9-633dc3ea6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985104815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1985104815
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2180028768
Short name T735
Test name
Test status
Simulation time 161572981 ps
CPU time 3.1 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 210340 kb
Host smart-6838cd9d-17a3-42d7-a064-eb8477ed911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180028768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2180028768
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1951220679
Short name T510
Test name
Test status
Simulation time 44340261 ps
CPU time 0.75 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 205872 kb
Host smart-c7dca920-9da6-45f2-90c2-320d6b2cc7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951220679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1951220679
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1520755129
Short name T799
Test name
Test status
Simulation time 107281864 ps
CPU time 3.69 seconds
Started Jul 22 07:18:16 PM PDT 24
Finished Jul 22 07:19:13 PM PDT 24
Peak memory 214364 kb
Host smart-e2bb6e83-958f-4591-8fc3-2b429f78dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520755129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1520755129
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3074321320
Short name T885
Test name
Test status
Simulation time 28845044 ps
CPU time 1.99 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 218156 kb
Host smart-8f32c155-c58b-438d-b820-a5da6ba8da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074321320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3074321320
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3016318633
Short name T300
Test name
Test status
Simulation time 60634663 ps
CPU time 2.26 seconds
Started Jul 22 07:18:15 PM PDT 24
Finished Jul 22 07:19:10 PM PDT 24
Peak memory 222296 kb
Host smart-9f71e585-cbec-4c96-b92c-1b5101c69d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016318633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3016318633
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2832462337
Short name T24
Test name
Test status
Simulation time 92561167 ps
CPU time 1.91 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:30 PM PDT 24
Peak memory 221080 kb
Host smart-1595c0c8-144c-432d-ab07-22ae35c4c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832462337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2832462337
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2501555573
Short name T716
Test name
Test status
Simulation time 252142740 ps
CPU time 2.34 seconds
Started Jul 22 07:15:45 PM PDT 24
Finished Jul 22 07:16:31 PM PDT 24
Peak memory 214196 kb
Host smart-1d73e3f7-f39f-4694-aedf-0352dc9150ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501555573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2501555573
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1066257519
Short name T686
Test name
Test status
Simulation time 783165068 ps
CPU time 5.68 seconds
Started Jul 22 07:15:43 PM PDT 24
Finished Jul 22 07:16:28 PM PDT 24
Peak memory 208644 kb
Host smart-9cd3fb6e-10ab-4f8c-a58e-33faf599448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066257519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1066257519
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1023049354
Short name T795
Test name
Test status
Simulation time 302343731 ps
CPU time 4.81 seconds
Started Jul 22 07:15:48 PM PDT 24
Finished Jul 22 07:16:40 PM PDT 24
Peak memory 208532 kb
Host smart-39e2b7b5-4ffe-4ff4-9df1-941a823a4257
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023049354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1023049354
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.989420327
Short name T149
Test name
Test status
Simulation time 851149598 ps
CPU time 2.77 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:45 PM PDT 24
Peak memory 206732 kb
Host smart-9585e303-02f5-46cb-843b-e56d71d729fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989420327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.989420327
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2473179235
Short name T837
Test name
Test status
Simulation time 30910055 ps
CPU time 1.85 seconds
Started Jul 22 07:15:49 PM PDT 24
Finished Jul 22 07:16:39 PM PDT 24
Peak memory 214164 kb
Host smart-0203df27-c3f2-49c7-8124-f831dcf46742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473179235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2473179235
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2051301695
Short name T784
Test name
Test status
Simulation time 70844185 ps
CPU time 2.32 seconds
Started Jul 22 07:15:53 PM PDT 24
Finished Jul 22 07:16:44 PM PDT 24
Peak memory 208124 kb
Host smart-1b6fc5d8-dae2-48dd-ad3f-ec10443f5690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051301695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2051301695
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1073002753
Short name T860
Test name
Test status
Simulation time 339049070 ps
CPU time 4.3 seconds
Started Jul 22 07:18:14 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 207556 kb
Host smart-3b09c70e-c77c-4038-a84d-e39e64e49d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073002753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1073002753
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.902078933
Short name T851
Test name
Test status
Simulation time 465712014 ps
CPU time 2.88 seconds
Started Jul 22 07:18:15 PM PDT 24
Finished Jul 22 07:19:11 PM PDT 24
Peak memory 210208 kb
Host smart-cec3a587-3687-4786-8a87-bae44a0dd331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902078933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.902078933
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1720881304
Short name T461
Test name
Test status
Simulation time 19957901 ps
CPU time 0.71 seconds
Started Jul 22 07:12:43 PM PDT 24
Finished Jul 22 07:13:31 PM PDT 24
Peak memory 205860 kb
Host smart-b79dbeb8-0037-49da-bb5a-10f91e5c7dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720881304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1720881304
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1708854383
Short name T631
Test name
Test status
Simulation time 557042897 ps
CPU time 11.47 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:44 PM PDT 24
Peak memory 207932 kb
Host smart-7c63e456-2663-4a01-8c0e-9192fb97b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708854383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1708854383
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1403648320
Short name T107
Test name
Test status
Simulation time 201480004 ps
CPU time 6.75 seconds
Started Jul 22 07:13:22 PM PDT 24
Finished Jul 22 07:14:19 PM PDT 24
Peak memory 222168 kb
Host smart-268955a6-d9b2-43a4-928a-2a9c6f8e1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403648320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1403648320
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1043457233
Short name T641
Test name
Test status
Simulation time 120574685 ps
CPU time 2.53 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 215040 kb
Host smart-46a4f852-883e-41f4-96e4-51c4ff6a2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043457233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1043457233
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3652316755
Short name T252
Test name
Test status
Simulation time 203193372 ps
CPU time 2.27 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:34 PM PDT 24
Peak memory 219900 kb
Host smart-a954da4f-2b1f-44db-b038-1c77ff89f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652316755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3652316755
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3626732760
Short name T817
Test name
Test status
Simulation time 81768736 ps
CPU time 3.89 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 209188 kb
Host smart-de14ea2d-fd03-43d1-8689-38b0417a7c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626732760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3626732760
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2588132355
Short name T14
Test name
Test status
Simulation time 2607111032 ps
CPU time 13.3 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:45 PM PDT 24
Peak memory 231060 kb
Host smart-982aac68-87f4-491c-b0d0-322073ac2b4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588132355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2588132355
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1793113191
Short name T350
Test name
Test status
Simulation time 38138748 ps
CPU time 1.66 seconds
Started Jul 22 07:12:48 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 206712 kb
Host smart-272739d9-d0a7-4d27-8d92-ff430734f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793113191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1793113191
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4236906162
Short name T732
Test name
Test status
Simulation time 75240772 ps
CPU time 2.56 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 208144 kb
Host smart-9e01c3d6-b6d4-4c34-9ff3-f9c42bca7e30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236906162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4236906162
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1472777862
Short name T910
Test name
Test status
Simulation time 63451519 ps
CPU time 2.95 seconds
Started Jul 22 07:12:46 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 208620 kb
Host smart-ac367960-8253-4e07-920e-fa97b41aaa04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472777862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1472777862
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.188769921
Short name T733
Test name
Test status
Simulation time 28952074 ps
CPU time 1.79 seconds
Started Jul 22 07:12:46 PM PDT 24
Finished Jul 22 07:13:35 PM PDT 24
Peak memory 206780 kb
Host smart-e1e45936-27ed-4ba0-8dbe-ef94e3cab384
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188769921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.188769921
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2315771062
Short name T521
Test name
Test status
Simulation time 67510693 ps
CPU time 2.39 seconds
Started Jul 22 07:12:44 PM PDT 24
Finished Jul 22 07:13:34 PM PDT 24
Peak memory 214200 kb
Host smart-e11d4f0a-1368-4910-a293-5c3b2101dec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315771062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2315771062
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3439202182
Short name T411
Test name
Test status
Simulation time 232156240 ps
CPU time 2.6 seconds
Started Jul 22 07:13:09 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 206536 kb
Host smart-6d2e28f0-7f12-4024-9673-811cb56f84d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439202182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3439202182
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.50254393
Short name T366
Test name
Test status
Simulation time 521561787 ps
CPU time 14.1 seconds
Started Jul 22 07:13:09 PM PDT 24
Finished Jul 22 07:14:13 PM PDT 24
Peak memory 221748 kb
Host smart-9f8cedf6-2f10-45e1-838b-bcc4e1870b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50254393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.50254393
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.180486593
Short name T348
Test name
Test status
Simulation time 1635422318 ps
CPU time 24.47 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:56 PM PDT 24
Peak memory 222420 kb
Host smart-86544d5b-cb88-44d8-8ecd-7edeb7a4395b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180486593 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.180486593
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4050455742
Short name T656
Test name
Test status
Simulation time 182298827 ps
CPU time 7.03 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:39 PM PDT 24
Peak memory 214012 kb
Host smart-bd0060fb-c045-4581-a9e0-f942c3fa0b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050455742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4050455742
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.266198163
Short name T745
Test name
Test status
Simulation time 28964266 ps
CPU time 1.65 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:33 PM PDT 24
Peak memory 209600 kb
Host smart-ca79225f-1aed-47d4-a949-fa3478b63072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266198163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.266198163
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2224792781
Short name T834
Test name
Test status
Simulation time 9014508 ps
CPU time 0.7 seconds
Started Jul 22 07:16:24 PM PDT 24
Finished Jul 22 07:17:28 PM PDT 24
Peak memory 205864 kb
Host smart-70d36548-0c0c-4a31-837c-64662a11fb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224792781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2224792781
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2072913967
Short name T238
Test name
Test status
Simulation time 281967755 ps
CPU time 2.34 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:01 PM PDT 24
Peak memory 214204 kb
Host smart-4b1aec24-fba1-4f1d-a590-c561545a94fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072913967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2072913967
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3564214526
Short name T290
Test name
Test status
Simulation time 312876138 ps
CPU time 4.93 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:06 PM PDT 24
Peak memory 214172 kb
Host smart-a02505c1-6190-4a51-baf5-63905e2b39b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564214526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3564214526
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3491607364
Short name T587
Test name
Test status
Simulation time 131183108 ps
CPU time 1.93 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:16:59 PM PDT 24
Peak memory 207392 kb
Host smart-2a684c2e-26bf-40d9-9f1b-1a712e620490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491607364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3491607364
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1942030619
Short name T804
Test name
Test status
Simulation time 632420521 ps
CPU time 4.07 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:05 PM PDT 24
Peak memory 209004 kb
Host smart-55333306-6a6a-4ed0-b858-df215de57649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942030619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1942030619
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1363609306
Short name T86
Test name
Test status
Simulation time 146499021 ps
CPU time 4.56 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:05 PM PDT 24
Peak memory 214068 kb
Host smart-d3baaf3e-e4c7-461f-92f9-91a62a4a16c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363609306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1363609306
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2092580665
Short name T669
Test name
Test status
Simulation time 236782952 ps
CPU time 8.34 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:48 PM PDT 24
Peak memory 209624 kb
Host smart-d928b024-9faa-41b6-9a7b-a1efd87a5e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092580665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2092580665
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1113998841
Short name T538
Test name
Test status
Simulation time 2794424414 ps
CPU time 32.19 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:33 PM PDT 24
Peak memory 208116 kb
Host smart-19476ea2-4748-46d1-b3ed-2849f53fb732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113998841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1113998841
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.754105059
Short name T880
Test name
Test status
Simulation time 336121128 ps
CPU time 3.65 seconds
Started Jul 22 07:15:59 PM PDT 24
Finished Jul 22 07:17:00 PM PDT 24
Peak memory 208576 kb
Host smart-8028f1e0-83e0-4b78-8258-984a1efb90f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754105059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.754105059
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.776605357
Short name T516
Test name
Test status
Simulation time 201367091 ps
CPU time 2.68 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 206564 kb
Host smart-ce26d793-7d7c-4e89-bb08-de752e270f40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776605357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.776605357
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2962156341
Short name T890
Test name
Test status
Simulation time 167345345 ps
CPU time 4.12 seconds
Started Jul 22 07:15:57 PM PDT 24
Finished Jul 22 07:16:55 PM PDT 24
Peak memory 208496 kb
Host smart-0f4f10d5-61df-43a0-bdd5-41aa0245c494
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962156341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2962156341
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1867363680
Short name T761
Test name
Test status
Simulation time 198037190 ps
CPU time 4.62 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 214056 kb
Host smart-ec2f71dc-5e1f-45cd-a953-3dfdd64a0a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867363680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1867363680
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2740022008
Short name T141
Test name
Test status
Simulation time 1070020369 ps
CPU time 5.82 seconds
Started Jul 22 07:15:59 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 206640 kb
Host smart-3ab4b607-4161-40ea-9099-d390b35f9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740022008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2740022008
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3040195217
Short name T728
Test name
Test status
Simulation time 3731138361 ps
CPU time 45.5 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:44 PM PDT 24
Peak memory 216672 kb
Host smart-ca0188ff-3f2e-416b-9591-6ba0a02aeb5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040195217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3040195217
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.388425013
Short name T263
Test name
Test status
Simulation time 7689556625 ps
CPU time 22.69 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:21 PM PDT 24
Peak memory 222476 kb
Host smart-c9c2537a-6010-43d7-b298-73cdb269a441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388425013 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.388425013
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4194823769
Short name T209
Test name
Test status
Simulation time 73919570 ps
CPU time 2.73 seconds
Started Jul 22 07:16:09 PM PDT 24
Finished Jul 22 07:17:11 PM PDT 24
Peak memory 218212 kb
Host smart-40a80591-0cfe-4519-af29-5f574f483617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194823769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4194823769
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.715402083
Short name T405
Test name
Test status
Simulation time 230616183 ps
CPU time 2.97 seconds
Started Jul 22 07:15:58 PM PDT 24
Finished Jul 22 07:16:55 PM PDT 24
Peak memory 210824 kb
Host smart-aee2b945-dc03-44b1-a25f-ad27796f088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715402083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.715402083
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3517013292
Short name T437
Test name
Test status
Simulation time 14734240 ps
CPU time 0.7 seconds
Started Jul 22 07:15:58 PM PDT 24
Finished Jul 22 07:16:54 PM PDT 24
Peak memory 205872 kb
Host smart-abea9eda-696a-4cbf-bbfa-55ff104c382e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517013292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3517013292
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2040313862
Short name T207
Test name
Test status
Simulation time 224040890 ps
CPU time 11.51 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:19:09 PM PDT 24
Peak memory 214308 kb
Host smart-e8679fbc-0b1a-4b69-a2dd-b7f32154ae3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040313862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2040313862
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.126306190
Short name T707
Test name
Test status
Simulation time 115066190 ps
CPU time 3.44 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:04 PM PDT 24
Peak memory 219416 kb
Host smart-1fd6b7d9-6de4-4ea5-b0a7-46915d2e1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126306190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.126306190
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2874791777
Short name T518
Test name
Test status
Simulation time 325385736 ps
CPU time 2.09 seconds
Started Jul 22 07:15:59 PM PDT 24
Finished Jul 22 07:16:57 PM PDT 24
Peak memory 208468 kb
Host smart-c0470647-c1d5-4784-9840-1cf5ed521061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874791777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2874791777
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1386359189
Short name T332
Test name
Test status
Simulation time 78654147 ps
CPU time 2.55 seconds
Started Jul 22 07:15:59 PM PDT 24
Finished Jul 22 07:16:57 PM PDT 24
Peak memory 205864 kb
Host smart-9d8b2728-9bb9-4cda-bfe2-1bc2af122f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386359189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1386359189
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1695188261
Short name T375
Test name
Test status
Simulation time 110094948 ps
CPU time 3.38 seconds
Started Jul 22 07:15:55 PM PDT 24
Finished Jul 22 07:16:51 PM PDT 24
Peak memory 213944 kb
Host smart-a76749f6-cf3a-439c-ae91-861d2b17bae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695188261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1695188261
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.775385075
Short name T699
Test name
Test status
Simulation time 106223436 ps
CPU time 2.95 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 217736 kb
Host smart-26281725-f98a-4d37-94ac-38155718fbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775385075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.775385075
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2993571668
Short name T275
Test name
Test status
Simulation time 506880516 ps
CPU time 5.17 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:06 PM PDT 24
Peak memory 207312 kb
Host smart-aa119a52-11e9-4eb9-a328-ba98d372dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993571668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2993571668
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1741738228
Short name T484
Test name
Test status
Simulation time 681211297 ps
CPU time 4.71 seconds
Started Jul 22 07:15:56 PM PDT 24
Finished Jul 22 07:16:54 PM PDT 24
Peak memory 208272 kb
Host smart-7e6e444a-9bff-4f1b-8f83-95991e3bbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741738228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1741738228
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.431299306
Short name T270
Test name
Test status
Simulation time 87449606 ps
CPU time 1.83 seconds
Started Jul 22 07:19:10 PM PDT 24
Finished Jul 22 07:19:50 PM PDT 24
Peak memory 206688 kb
Host smart-5f1444dd-f606-4d35-8a38-84f4a01319eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431299306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.431299306
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2947903525
Short name T635
Test name
Test status
Simulation time 1154405403 ps
CPU time 20.77 seconds
Started Jul 22 07:16:09 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 208284 kb
Host smart-7b146d75-a9a0-4de7-a034-eb9e2ff3da56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947903525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2947903525
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2722590185
Short name T457
Test name
Test status
Simulation time 1523913230 ps
CPU time 19.87 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:18 PM PDT 24
Peak memory 208012 kb
Host smart-6b805591-aeb3-447d-9945-f4fbf7eb8369
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722590185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2722590185
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2487454035
Short name T775
Test name
Test status
Simulation time 188224268 ps
CPU time 3.59 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:44 PM PDT 24
Peak memory 209568 kb
Host smart-e5ff0edc-4d04-4043-8721-593612aa14e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487454035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2487454035
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2920805892
Short name T495
Test name
Test status
Simulation time 55830950 ps
CPU time 2.17 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:00 PM PDT 24
Peak memory 208384 kb
Host smart-69224e47-facb-46ba-a1b7-16e75218eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920805892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2920805892
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3071596252
Short name T8
Test name
Test status
Simulation time 1060786869 ps
CPU time 18.04 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 215856 kb
Host smart-08db1ee4-c621-4965-b274-566adeaeeb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071596252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3071596252
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2751065669
Short name T201
Test name
Test status
Simulation time 948651319 ps
CPU time 9.01 seconds
Started Jul 22 07:16:03 PM PDT 24
Finished Jul 22 07:17:11 PM PDT 24
Peak memory 219388 kb
Host smart-c15d954a-83c5-44a1-a62f-d119c6aadef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751065669 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2751065669
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4139962480
Short name T600
Test name
Test status
Simulation time 562951761 ps
CPU time 5.82 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:04 PM PDT 24
Peak memory 208608 kb
Host smart-53076aab-2374-4fa0-bd2c-3500d62bf864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139962480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4139962480
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1066737363
Short name T465
Test name
Test status
Simulation time 240574260 ps
CPU time 2.48 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:00 PM PDT 24
Peak memory 210160 kb
Host smart-ee508849-bd9e-4ecc-b04e-2079734335d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066737363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1066737363
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2044774573
Short name T877
Test name
Test status
Simulation time 17341869 ps
CPU time 0.99 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:00 PM PDT 24
Peak memory 205896 kb
Host smart-fa58022d-a339-4942-ac97-78280cc2e1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044774573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2044774573
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2686907046
Short name T21
Test name
Test status
Simulation time 517340763 ps
CPU time 4.42 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 214332 kb
Host smart-4b245451-287c-46ce-8f9a-ce8cf027b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686907046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2686907046
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2825869722
Short name T780
Test name
Test status
Simulation time 595372891 ps
CPU time 2.61 seconds
Started Jul 22 07:17:45 PM PDT 24
Finished Jul 22 07:18:43 PM PDT 24
Peak memory 206944 kb
Host smart-60475525-79f3-42aa-ab38-3098c181caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825869722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2825869722
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3185462793
Short name T377
Test name
Test status
Simulation time 81607352 ps
CPU time 2.82 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 214084 kb
Host smart-b8c408a9-6d55-4543-b869-3664b709fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185462793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3185462793
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1669934648
Short name T351
Test name
Test status
Simulation time 40837223 ps
CPU time 2.53 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:01 PM PDT 24
Peak memory 222112 kb
Host smart-c5f04163-a86a-479d-b79d-48ae595fad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669934648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1669934648
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2024089884
Short name T722
Test name
Test status
Simulation time 135021279 ps
CPU time 4.48 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:04 PM PDT 24
Peak memory 210064 kb
Host smart-adbb723a-7e6b-4458-98fb-c482b7af2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024089884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2024089884
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3631621089
Short name T306
Test name
Test status
Simulation time 227154314 ps
CPU time 7.96 seconds
Started Jul 22 07:18:07 PM PDT 24
Finished Jul 22 07:19:05 PM PDT 24
Peak memory 214088 kb
Host smart-b88fb637-f5af-4362-bfa6-ad36eebaf23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631621089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3631621089
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3178156793
Short name T365
Test name
Test status
Simulation time 32198531 ps
CPU time 2.14 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:01 PM PDT 24
Peak memory 206588 kb
Host smart-01b90e9f-8159-4714-bf8e-db463f3fe531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178156793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3178156793
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1888107537
Short name T883
Test name
Test status
Simulation time 506392968 ps
CPU time 3.92 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:01 PM PDT 24
Peak memory 206468 kb
Host smart-7296e236-d562-4f80-bf44-07be33249041
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888107537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1888107537
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1577889265
Short name T709
Test name
Test status
Simulation time 510955458 ps
CPU time 6.09 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:07 PM PDT 24
Peak memory 208496 kb
Host smart-754051fc-1922-4488-b5cc-8e76bc94cfc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577889265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1577889265
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3254581771
Short name T651
Test name
Test status
Simulation time 169837667 ps
CPU time 5.77 seconds
Started Jul 22 07:16:03 PM PDT 24
Finished Jul 22 07:17:08 PM PDT 24
Peak memory 207748 kb
Host smart-46232b1e-e7df-4069-8902-44a23a48872b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254581771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3254581771
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3471423928
Short name T854
Test name
Test status
Simulation time 355651355 ps
CPU time 2.61 seconds
Started Jul 22 07:18:05 PM PDT 24
Finished Jul 22 07:18:58 PM PDT 24
Peak memory 209580 kb
Host smart-eaa2a456-5eb1-4844-9e07-dcab55aac278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471423928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3471423928
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3566630732
Short name T864
Test name
Test status
Simulation time 74949713 ps
CPU time 1.59 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 206680 kb
Host smart-f391ae0b-6935-4764-badb-52cced08001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566630732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3566630732
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1192301010
Short name T887
Test name
Test status
Simulation time 270189338 ps
CPU time 11.12 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:12 PM PDT 24
Peak memory 214848 kb
Host smart-97220eb8-d6ff-43e5-8e2f-f7a051dfbc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192301010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1192301010
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1605692076
Short name T362
Test name
Test status
Simulation time 227425299 ps
CPU time 6.71 seconds
Started Jul 22 07:16:03 PM PDT 24
Finished Jul 22 07:17:09 PM PDT 24
Peak memory 219768 kb
Host smart-fe140a6d-201f-4246-aeab-d37b1c3a2ae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605692076 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1605692076
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.228964773
Short name T503
Test name
Test status
Simulation time 532813524 ps
CPU time 4.76 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:05 PM PDT 24
Peak memory 207428 kb
Host smart-b72e453f-93fc-441c-8a2b-74b25f01f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228964773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.228964773
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3568310106
Short name T724
Test name
Test status
Simulation time 135026566 ps
CPU time 2.5 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 210220 kb
Host smart-780b05d9-ae78-4f82-95f4-235a81755af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568310106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3568310106
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2691627797
Short name T533
Test name
Test status
Simulation time 22967191 ps
CPU time 0.77 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:18:58 PM PDT 24
Peak memory 205812 kb
Host smart-21952c4f-0bc3-4a43-a460-af51d9d9c20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691627797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2691627797
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1900456118
Short name T427
Test name
Test status
Simulation time 780298998 ps
CPU time 6.77 seconds
Started Jul 22 07:16:24 PM PDT 24
Finished Jul 22 07:17:34 PM PDT 24
Peak memory 214720 kb
Host smart-d1407337-468e-4e2b-8c4f-2a9c33e5e8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900456118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1900456118
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1194944915
Short name T545
Test name
Test status
Simulation time 171446161 ps
CPU time 2.52 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 208388 kb
Host smart-21278b5f-5b61-45de-ab17-ada9a285d415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194944915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1194944915
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.4263013354
Short name T800
Test name
Test status
Simulation time 113780638 ps
CPU time 4.44 seconds
Started Jul 22 07:16:03 PM PDT 24
Finished Jul 22 07:17:07 PM PDT 24
Peak memory 220568 kb
Host smart-e2ed78a2-92ab-467d-9343-5bec15fa3328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263013354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4263013354
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3671823260
Short name T251
Test name
Test status
Simulation time 337835904 ps
CPU time 2.77 seconds
Started Jul 22 07:16:04 PM PDT 24
Finished Jul 22 07:17:06 PM PDT 24
Peak memory 214624 kb
Host smart-25155b3e-911f-4fad-ab4c-b074c6c771f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671823260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3671823260
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1326489351
Short name T88
Test name
Test status
Simulation time 177812011 ps
CPU time 6.9 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:19:02 PM PDT 24
Peak memory 219464 kb
Host smart-5aefb490-b232-4bbe-b619-6a5270a2ac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326489351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1326489351
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3710158458
Short name T229
Test name
Test status
Simulation time 308045338 ps
CPU time 4.13 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 206676 kb
Host smart-1b1fe59f-b095-46f8-b16c-b0b0ca245ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710158458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3710158458
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3443955541
Short name T468
Test name
Test status
Simulation time 188408076 ps
CPU time 5.74 seconds
Started Jul 22 07:16:04 PM PDT 24
Finished Jul 22 07:17:08 PM PDT 24
Peak memory 207856 kb
Host smart-f9953bc4-bdb8-4673-8b96-a26483fc76a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443955541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3443955541
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2350150618
Short name T487
Test name
Test status
Simulation time 54694708 ps
CPU time 2.77 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 206768 kb
Host smart-e5c87e5d-0a39-4a33-850d-899a4f8814d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350150618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2350150618
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3781296167
Short name T692
Test name
Test status
Simulation time 614384535 ps
CPU time 2.54 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 206668 kb
Host smart-e83770a2-e8e2-43a7-9e81-adc145471cc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781296167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3781296167
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2418622258
Short name T718
Test name
Test status
Simulation time 158826711 ps
CPU time 4.47 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:05 PM PDT 24
Peak memory 208828 kb
Host smart-b232f468-b72d-45ca-aafd-955817c7d411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418622258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2418622258
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.625373576
Short name T519
Test name
Test status
Simulation time 58652625 ps
CPU time 2.68 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 206544 kb
Host smart-aa9ef669-2cec-402f-b006-7bc6818f69b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625373576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.625373576
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1643643053
Short name T783
Test name
Test status
Simulation time 3716658363 ps
CPU time 52.11 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:19:49 PM PDT 24
Peak memory 222268 kb
Host smart-01cfa3dd-c0c8-45c9-9a13-75a816607b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643643053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1643643053
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1603737637
Short name T338
Test name
Test status
Simulation time 345677958 ps
CPU time 5.18 seconds
Started Jul 22 07:18:37 PM PDT 24
Finished Jul 22 07:19:31 PM PDT 24
Peak memory 218112 kb
Host smart-beff3a00-c26d-470c-95a2-257fe5d19d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603737637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1603737637
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3245120945
Short name T402
Test name
Test status
Simulation time 75305001 ps
CPU time 3.26 seconds
Started Jul 22 07:16:10 PM PDT 24
Finished Jul 22 07:17:13 PM PDT 24
Peak memory 209896 kb
Host smart-18907b85-841f-4739-8d03-7657188f0e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245120945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3245120945
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3489824194
Short name T904
Test name
Test status
Simulation time 15479911 ps
CPU time 0.91 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:17 PM PDT 24
Peak memory 205896 kb
Host smart-edfbd190-8f5e-46e6-b2b2-eacd9968990d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489824194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3489824194
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1495118054
Short name T155
Test name
Test status
Simulation time 57632019 ps
CPU time 4.13 seconds
Started Jul 22 07:18:37 PM PDT 24
Finished Jul 22 07:19:30 PM PDT 24
Peak memory 214064 kb
Host smart-1bdc0404-ae2d-47c2-b6e2-16cf4ac29833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495118054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1495118054
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3116571630
Short name T597
Test name
Test status
Simulation time 387976105 ps
CPU time 3.38 seconds
Started Jul 22 07:16:01 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 218432 kb
Host smart-867da989-10bf-4e0a-b566-b28cd0d5b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116571630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3116571630
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3912965890
Short name T445
Test name
Test status
Simulation time 69995587 ps
CPU time 2.44 seconds
Started Jul 22 07:16:12 PM PDT 24
Finished Jul 22 07:17:17 PM PDT 24
Peak memory 207996 kb
Host smart-f715e21e-7a5b-4d53-bb73-228c395aa49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912965890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3912965890
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.337664798
Short name T279
Test name
Test status
Simulation time 2275729354 ps
CPU time 5.41 seconds
Started Jul 22 07:18:37 PM PDT 24
Finished Jul 22 07:19:31 PM PDT 24
Peak memory 222276 kb
Host smart-03aabc08-f296-483f-ae49-80d2a18a202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337664798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.337664798
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.310748427
Short name T99
Test name
Test status
Simulation time 160913269 ps
CPU time 6.5 seconds
Started Jul 22 07:16:24 PM PDT 24
Finished Jul 22 07:17:33 PM PDT 24
Peak memory 221528 kb
Host smart-082199f4-df4d-417d-b53f-dda225a9560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310748427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.310748427
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2435156015
Short name T262
Test name
Test status
Simulation time 195058964 ps
CPU time 5.55 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:06 PM PDT 24
Peak memory 214048 kb
Host smart-55d3fb0c-5555-4974-920d-b5fe06d50ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435156015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2435156015
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.956825096
Short name T506
Test name
Test status
Simulation time 4487738559 ps
CPU time 45.14 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:55 PM PDT 24
Peak memory 214072 kb
Host smart-9c0ec6d9-64fd-434d-b76d-ebf7d3f7cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956825096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.956825096
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1374019650
Short name T562
Test name
Test status
Simulation time 230013446 ps
CPU time 2.98 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 208212 kb
Host smart-14d1fc4b-14b7-4072-9615-2626cc144f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374019650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1374019650
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1076244678
Short name T912
Test name
Test status
Simulation time 2596161962 ps
CPU time 10.24 seconds
Started Jul 22 07:16:10 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 208760 kb
Host smart-81147950-c19d-413d-b392-c2ac99daf92f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076244678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1076244678
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2477222831
Short name T619
Test name
Test status
Simulation time 231446733 ps
CPU time 2.96 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 206728 kb
Host smart-0230bbcd-4dc9-4035-8ceb-a85666f98b36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477222831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2477222831
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3317413795
Short name T599
Test name
Test status
Simulation time 112181005 ps
CPU time 4.46 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:21 PM PDT 24
Peak memory 208004 kb
Host smart-670026a8-1f17-4daf-ae84-3a1c801b5f5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317413795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3317413795
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2115763780
Short name T482
Test name
Test status
Simulation time 314715906 ps
CPU time 2.1 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:16:59 PM PDT 24
Peak memory 214032 kb
Host smart-dae6c8c9-b4d0-49e2-9612-397ab690cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115763780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2115763780
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1354616329
Short name T227
Test name
Test status
Simulation time 273364038 ps
CPU time 3.13 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:19:00 PM PDT 24
Peak memory 206504 kb
Host smart-d9c4b6e6-93ed-410b-be3c-79a61c48ac6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354616329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1354616329
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1159147046
Short name T120
Test name
Test status
Simulation time 1882631367 ps
CPU time 36.54 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:34 PM PDT 24
Peak memory 216844 kb
Host smart-cf479000-77fa-4849-a804-e2a6750fd68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159147046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1159147046
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.224577564
Short name T762
Test name
Test status
Simulation time 205358627 ps
CPU time 4.41 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 209036 kb
Host smart-1c8bca38-1b34-42cb-ad39-f26d687eb5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224577564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.224577564
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3103275537
Short name T192
Test name
Test status
Simulation time 357227812 ps
CPU time 8.26 seconds
Started Jul 22 07:18:37 PM PDT 24
Finished Jul 22 07:19:34 PM PDT 24
Peak memory 210752 kb
Host smart-8c304e19-1bb1-4100-99a3-ac353aec2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103275537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3103275537
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4057280655
Short name T452
Test name
Test status
Simulation time 152484091 ps
CPU time 1.01 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:11 PM PDT 24
Peak memory 205900 kb
Host smart-be89b7f0-a36e-4be5-942b-50a2111a6064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057280655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4057280655
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.367119442
Short name T129
Test name
Test status
Simulation time 585245597 ps
CPU time 9.35 seconds
Started Jul 22 07:16:11 PM PDT 24
Finished Jul 22 07:17:21 PM PDT 24
Peak memory 214064 kb
Host smart-223e8792-6563-4a63-bdb5-df7aaad6fa36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367119442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.367119442
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2031311216
Short name T30
Test name
Test status
Simulation time 87117898 ps
CPU time 2.41 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 214196 kb
Host smart-aed9c3a5-fce4-4260-aa4e-3781ec43f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031311216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2031311216
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2786679785
Short name T828
Test name
Test status
Simulation time 526549647 ps
CPU time 5.88 seconds
Started Jul 22 07:16:10 PM PDT 24
Finished Jul 22 07:17:16 PM PDT 24
Peak memory 218080 kb
Host smart-7899f93b-8786-49e8-ab95-b2fc19e9350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786679785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2786679785
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.528153257
Short name T109
Test name
Test status
Simulation time 172743495 ps
CPU time 3.12 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 208700 kb
Host smart-e0638191-f197-4cc4-bf05-cc9c95865d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528153257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.528153257
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1073056329
Short name T143
Test name
Test status
Simulation time 62582910 ps
CPU time 2.98 seconds
Started Jul 22 07:16:09 PM PDT 24
Finished Jul 22 07:17:11 PM PDT 24
Peak memory 214004 kb
Host smart-79c35691-466b-4599-8836-53715b319cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073056329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1073056329
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1084490158
Short name T773
Test name
Test status
Simulation time 38433885 ps
CPU time 2.15 seconds
Started Jul 22 07:16:11 PM PDT 24
Finished Jul 22 07:17:14 PM PDT 24
Peak memory 222256 kb
Host smart-e25b3190-5265-40e0-9b1f-5a505ad18ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084490158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1084490158
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2289377457
Short name T225
Test name
Test status
Simulation time 245096785 ps
CPU time 4.22 seconds
Started Jul 22 07:16:00 PM PDT 24
Finished Jul 22 07:17:02 PM PDT 24
Peak memory 219524 kb
Host smart-84c17712-0251-4d01-b885-4638349363ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289377457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2289377457
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2653732907
Short name T621
Test name
Test status
Simulation time 119979753 ps
CPU time 3.21 seconds
Started Jul 22 07:16:13 PM PDT 24
Finished Jul 22 07:17:18 PM PDT 24
Peak memory 208504 kb
Host smart-756a3a85-c640-4a1d-9a44-9576e9bea54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653732907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2653732907
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2714588701
Short name T314
Test name
Test status
Simulation time 198685944 ps
CPU time 6.72 seconds
Started Jul 22 07:18:06 PM PDT 24
Finished Jul 22 07:19:04 PM PDT 24
Peak memory 207800 kb
Host smart-94b4425a-4fe7-46ff-9b9d-42c8f15557be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714588701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2714588701
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3438949800
Short name T835
Test name
Test status
Simulation time 119822188 ps
CPU time 3.17 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 208584 kb
Host smart-be52a30a-87f7-4bf4-8597-bc831189792c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438949800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3438949800
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1891047228
Short name T547
Test name
Test status
Simulation time 255698880 ps
CPU time 2.85 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 208292 kb
Host smart-af6c9abb-af20-419a-8ec6-e477943055ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891047228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1891047228
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3445971533
Short name T661
Test name
Test status
Simulation time 49810690 ps
CPU time 2.55 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:19 PM PDT 24
Peak memory 209532 kb
Host smart-4a5c5ae5-32ee-4bfb-8784-3d182e27156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445971533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3445971533
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3554815899
Short name T434
Test name
Test status
Simulation time 204220321 ps
CPU time 4.48 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:05 PM PDT 24
Peak memory 206524 kb
Host smart-4ba35bdd-e830-4711-a9d4-2e88a937f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554815899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3554815899
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.525299265
Short name T790
Test name
Test status
Simulation time 231243079 ps
CPU time 3.89 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:14 PM PDT 24
Peak memory 207720 kb
Host smart-a3ca9f2a-6a13-437a-b1e9-db2c1ca07788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525299265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.525299265
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1902460053
Short name T224
Test name
Test status
Simulation time 136271750 ps
CPU time 3.5 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:14 PM PDT 24
Peak memory 214108 kb
Host smart-e849a71b-53bd-40cb-a9fb-bb08499da750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902460053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1902460053
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2763439093
Short name T407
Test name
Test status
Simulation time 102127160 ps
CPU time 1.63 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:12 PM PDT 24
Peak memory 208288 kb
Host smart-b916f06a-1fd5-4055-9bb6-060d44df3018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763439093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2763439093
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.996860947
Short name T588
Test name
Test status
Simulation time 18114455 ps
CPU time 0.93 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:27 PM PDT 24
Peak memory 205924 kb
Host smart-27022cbc-0d4b-47e2-a677-703d493ef62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996860947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.996860947
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3645034193
Short name T583
Test name
Test status
Simulation time 623456149 ps
CPU time 2.76 seconds
Started Jul 22 07:19:24 PM PDT 24
Finished Jul 22 07:19:56 PM PDT 24
Peak memory 207616 kb
Host smart-dc298fdd-124a-4865-9dae-5cfd00be3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645034193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3645034193
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.765846354
Short name T103
Test name
Test status
Simulation time 113938844 ps
CPU time 3.93 seconds
Started Jul 22 07:18:08 PM PDT 24
Finished Jul 22 07:19:03 PM PDT 24
Peak memory 222204 kb
Host smart-4382f022-40bf-4757-a880-4d6edde1f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765846354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.765846354
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.986263958
Short name T39
Test name
Test status
Simulation time 511414832 ps
CPU time 6.49 seconds
Started Jul 22 07:16:13 PM PDT 24
Finished Jul 22 07:17:21 PM PDT 24
Peak memory 214072 kb
Host smart-b308c8b5-c83d-4823-9ad3-d63ffaf8e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986263958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.986263958
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2959456163
Short name T246
Test name
Test status
Simulation time 60364559 ps
CPU time 3.55 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 210024 kb
Host smart-eabd3eea-1a1d-44bb-aeb2-0176d7371d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959456163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2959456163
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3801711787
Short name T347
Test name
Test status
Simulation time 1726612071 ps
CPU time 12.6 seconds
Started Jul 22 07:16:19 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 208500 kb
Host smart-f4b2e5f4-5bd3-48cb-9576-9b791a710d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801711787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3801711787
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4234883394
Short name T291
Test name
Test status
Simulation time 2844350864 ps
CPU time 18.24 seconds
Started Jul 22 07:16:06 PM PDT 24
Finished Jul 22 07:17:22 PM PDT 24
Peak memory 207960 kb
Host smart-c03fa32d-36df-46b4-a537-ed60212a81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234883394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4234883394
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2396156668
Short name T239
Test name
Test status
Simulation time 22003134 ps
CPU time 1.73 seconds
Started Jul 22 07:16:13 PM PDT 24
Finished Jul 22 07:17:17 PM PDT 24
Peak memory 206696 kb
Host smart-33bde713-0032-48d3-9647-7432a0825be7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396156668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2396156668
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2735937472
Short name T663
Test name
Test status
Simulation time 169762476 ps
CPU time 2.43 seconds
Started Jul 22 07:16:02 PM PDT 24
Finished Jul 22 07:17:03 PM PDT 24
Peak memory 206752 kb
Host smart-921661af-5c5b-46a2-844a-d51c94774f10
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735937472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2735937472
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3643094855
Short name T908
Test name
Test status
Simulation time 204128107 ps
CPU time 2.29 seconds
Started Jul 22 07:18:04 PM PDT 24
Finished Jul 22 07:18:58 PM PDT 24
Peak memory 206704 kb
Host smart-e1086cca-cb5e-4912-8bf5-5e04c82d3028
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643094855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3643094855
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4246953207
Short name T313
Test name
Test status
Simulation time 57100996 ps
CPU time 2.91 seconds
Started Jul 22 07:19:24 PM PDT 24
Finished Jul 22 07:19:56 PM PDT 24
Peak memory 208620 kb
Host smart-7827cafa-5929-4aff-99d9-6fdfbf223628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246953207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4246953207
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.541326269
Short name T743
Test name
Test status
Simulation time 107977176 ps
CPU time 2.56 seconds
Started Jul 22 07:18:17 PM PDT 24
Finished Jul 22 07:19:13 PM PDT 24
Peak memory 207724 kb
Host smart-351296fd-32ad-4e08-8d42-ca6957685df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541326269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.541326269
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3012588357
Short name T833
Test name
Test status
Simulation time 941199647 ps
CPU time 6.04 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 206644 kb
Host smart-77b700ab-a8c4-4ff9-9339-42714e8fbf73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012588357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3012588357
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2357240446
Short name T572
Test name
Test status
Simulation time 547430324 ps
CPU time 17.01 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:33 PM PDT 24
Peak memory 222412 kb
Host smart-80a6b1b4-490a-4226-85e2-bf069d74887c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357240446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2357240446
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4188329486
Short name T488
Test name
Test status
Simulation time 200257566 ps
CPU time 5.41 seconds
Started Jul 22 07:16:15 PM PDT 24
Finished Jul 22 07:17:22 PM PDT 24
Peak memory 207796 kb
Host smart-a211726f-cf09-45c8-aa15-ca6acac43215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188329486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4188329486
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2745488719
Short name T767
Test name
Test status
Simulation time 730287096 ps
CPU time 10.8 seconds
Started Jul 22 07:19:24 PM PDT 24
Finished Jul 22 07:20:04 PM PDT 24
Peak memory 210796 kb
Host smart-2b81aaee-53cf-4ed3-ad87-7dfda5cbd861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745488719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2745488719
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3048978498
Short name T665
Test name
Test status
Simulation time 10946643 ps
CPU time 0.71 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:36 PM PDT 24
Peak memory 205816 kb
Host smart-9003369f-5dbb-4fc6-99f3-1e203a54e6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048978498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3048978498
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3572728053
Short name T390
Test name
Test status
Simulation time 111972756 ps
CPU time 3.7 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:17:34 PM PDT 24
Peak memory 215152 kb
Host smart-ea1b7091-7517-41e6-962e-250691531a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572728053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3572728053
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2121498846
Short name T20
Test name
Test status
Simulation time 495407800 ps
CPU time 3.45 seconds
Started Jul 22 07:16:25 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 214436 kb
Host smart-f4fa5f63-dca9-43d5-a3ac-e12b4f494b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121498846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2121498846
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.4101671274
Short name T861
Test name
Test status
Simulation time 187241377 ps
CPU time 2.16 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 207344 kb
Host smart-8e770980-3139-4226-afbc-e19eb81b8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101671274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.4101671274
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3824695555
Short name T26
Test name
Test status
Simulation time 72559525 ps
CPU time 3.62 seconds
Started Jul 22 07:19:24 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 214048 kb
Host smart-34ff8a20-7fa5-4bdc-8270-f4b5f511fcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824695555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3824695555
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1877669105
Short name T525
Test name
Test status
Simulation time 121458494 ps
CPU time 4.22 seconds
Started Jul 22 07:19:25 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 217284 kb
Host smart-c203170c-12df-4a08-b6d7-0352c7a5561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877669105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1877669105
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3610660081
Short name T608
Test name
Test status
Simulation time 1657909097 ps
CPU time 7.13 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:23 PM PDT 24
Peak memory 214056 kb
Host smart-374b1ea7-344c-44d7-8b2c-e6531562bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610660081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3610660081
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1296564587
Short name T875
Test name
Test status
Simulation time 600589414 ps
CPU time 2.95 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:29 PM PDT 24
Peak memory 206628 kb
Host smart-1cf3341c-f761-43f3-a163-65e0ab469d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296564587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1296564587
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.790969916
Short name T118
Test name
Test status
Simulation time 607468525 ps
CPU time 3.8 seconds
Started Jul 22 07:19:23 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 208236 kb
Host smart-4f8fea83-756b-47a5-8dbc-5204b113d060
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790969916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.790969916
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2272806682
Short name T674
Test name
Test status
Simulation time 324950367 ps
CPU time 3.83 seconds
Started Jul 22 07:19:24 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 208348 kb
Host smart-f47b2a92-aced-4a4d-8c0a-365e79360963
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272806682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2272806682
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.390186325
Short name T801
Test name
Test status
Simulation time 62340017 ps
CPU time 3.06 seconds
Started Jul 22 07:19:23 PM PDT 24
Finished Jul 22 07:19:56 PM PDT 24
Peak memory 208388 kb
Host smart-a42e5ec6-c574-4d4d-97fa-2766625ee989
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390186325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.390186325
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1508033102
Short name T896
Test name
Test status
Simulation time 35389187 ps
CPU time 2.01 seconds
Started Jul 22 07:19:25 PM PDT 24
Finished Jul 22 07:19:55 PM PDT 24
Peak memory 207720 kb
Host smart-65d90077-5645-45fb-9e3f-f94890dd02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508033102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1508033102
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4220712724
Short name T451
Test name
Test status
Simulation time 253294549 ps
CPU time 2.81 seconds
Started Jul 22 07:16:13 PM PDT 24
Finished Jul 22 07:17:18 PM PDT 24
Peak memory 208456 kb
Host smart-e01ff397-f9f9-4062-96fa-ba8fa7ee1e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220712724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4220712724
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2810813069
Short name T354
Test name
Test status
Simulation time 647851903 ps
CPU time 19.39 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:56 PM PDT 24
Peak memory 214484 kb
Host smart-b7cb6aba-c5db-419d-9278-647f8bf59854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810813069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2810813069
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.797029405
Short name T358
Test name
Test status
Simulation time 371053607 ps
CPU time 6.6 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:42 PM PDT 24
Peak memory 222272 kb
Host smart-56431e15-bd51-4f57-88af-26217463c245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797029405 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.797029405
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1443746515
Short name T657
Test name
Test status
Simulation time 292981181 ps
CPU time 4.12 seconds
Started Jul 22 07:16:25 PM PDT 24
Finished Jul 22 07:17:33 PM PDT 24
Peak memory 207716 kb
Host smart-06aceca9-512b-4f65-9335-a91cec48b776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443746515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1443746515
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1365496528
Short name T776
Test name
Test status
Simulation time 543261224 ps
CPU time 2.12 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:37 PM PDT 24
Peak memory 209828 kb
Host smart-4022d92b-1258-4b07-abb0-466213a420f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365496528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1365496528
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.326000739
Short name T633
Test name
Test status
Simulation time 34927524 ps
CPU time 0.77 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 205752 kb
Host smart-18bbc352-74bc-4b35-83fd-853bc9b9d70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326000739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.326000739
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.138299643
Short name T813
Test name
Test status
Simulation time 55239330 ps
CPU time 3 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:40 PM PDT 24
Peak memory 214892 kb
Host smart-6e9ff831-376f-4f59-9586-572eb9057e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138299643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.138299643
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3850473885
Short name T653
Test name
Test status
Simulation time 118944786 ps
CPU time 4.84 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 222452 kb
Host smart-9dbf10c0-ea69-4919-8f26-d5daaefdec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850473885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3850473885
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4042315846
Short name T584
Test name
Test status
Simulation time 529476009 ps
CPU time 14.44 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:48 PM PDT 24
Peak memory 208504 kb
Host smart-79e80bba-5cc4-43da-a73e-b4e0546c33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042315846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4042315846
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3422793616
Short name T282
Test name
Test status
Simulation time 64735249 ps
CPU time 1.91 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:36 PM PDT 24
Peak memory 214148 kb
Host smart-d4ee28ff-06cf-49f5-9197-57fd0a786491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422793616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3422793616
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3234403751
Short name T271
Test name
Test status
Simulation time 182672375 ps
CPU time 2.56 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 220720 kb
Host smart-3262292a-7aa3-478d-ac34-c04efc601060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234403751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3234403751
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.418973188
Short name T47
Test name
Test status
Simulation time 97303364 ps
CPU time 2.86 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:37 PM PDT 24
Peak memory 209380 kb
Host smart-801449fc-796a-4eb4-9272-ea696cbd34c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418973188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.418973188
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1008189076
Short name T592
Test name
Test status
Simulation time 109751940 ps
CPU time 5.12 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 209168 kb
Host smart-a837b12f-842e-4e5a-a9cf-c8bbe9e559aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008189076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1008189076
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1016738666
Short name T378
Test name
Test status
Simulation time 85289689 ps
CPU time 3.79 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:41 PM PDT 24
Peak memory 208364 kb
Host smart-82fe50df-2ddc-4185-bdac-6b560cd4c637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016738666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1016738666
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3127503500
Short name T897
Test name
Test status
Simulation time 92404261 ps
CPU time 3.81 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 208344 kb
Host smart-059a3be4-6325-4f5b-af35-1b9629592169
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127503500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3127503500
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3074079893
Short name T723
Test name
Test status
Simulation time 103166261 ps
CPU time 4.15 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:41 PM PDT 24
Peak memory 208664 kb
Host smart-76fd1031-8a3c-46d0-ba78-522376106f78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074079893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3074079893
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1217609627
Short name T460
Test name
Test status
Simulation time 269270418 ps
CPU time 9.91 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:47 PM PDT 24
Peak memory 208784 kb
Host smart-b842011d-7857-4f8b-8ebb-0e85a510fa15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217609627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1217609627
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1414862864
Short name T639
Test name
Test status
Simulation time 198160398 ps
CPU time 3.79 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 209380 kb
Host smart-d58a8464-2ccb-45c8-a28b-eb9a56fd5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414862864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1414862864
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3667554547
Short name T438
Test name
Test status
Simulation time 76940657 ps
CPU time 1.68 seconds
Started Jul 22 07:16:20 PM PDT 24
Finished Jul 22 07:17:22 PM PDT 24
Peak memory 206744 kb
Host smart-13e00a07-5dcc-4614-9dd7-5813af613f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667554547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3667554547
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2390188431
Short name T212
Test name
Test status
Simulation time 13210433964 ps
CPU time 142.9 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:19:57 PM PDT 24
Peak memory 222356 kb
Host smart-c3213abf-3800-406e-9d1b-4a90076e04bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390188431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2390188431
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2497412904
Short name T324
Test name
Test status
Simulation time 324800336 ps
CPU time 4.22 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 218044 kb
Host smart-8102f3cd-441a-4683-a4af-cdac9675c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497412904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2497412904
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3138384465
Short name T622
Test name
Test status
Simulation time 447558597 ps
CPU time 3.21 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 210304 kb
Host smart-1b17d571-9bcb-46f6-b38b-b3bb70ea746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138384465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3138384465
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3316049218
Short name T3
Test name
Test status
Simulation time 119853700 ps
CPU time 0.77 seconds
Started Jul 22 07:16:22 PM PDT 24
Finished Jul 22 07:17:25 PM PDT 24
Peak memory 205856 kb
Host smart-61b646a2-926b-40cc-8d3c-8cc4782b968b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316049218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3316049218
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.814927948
Short name T49
Test name
Test status
Simulation time 36629588 ps
CPU time 2.08 seconds
Started Jul 22 07:16:16 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 207408 kb
Host smart-5e1598af-fb4c-4684-83c1-ec1d9f0d6992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814927948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.814927948
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4215853218
Short name T747
Test name
Test status
Simulation time 2240555077 ps
CPU time 13.97 seconds
Started Jul 22 07:16:23 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 219148 kb
Host smart-1d1a5f0f-e2ba-4c8f-a721-64c8902f5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215853218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4215853218
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.858407596
Short name T791
Test name
Test status
Simulation time 148772200 ps
CPU time 2.84 seconds
Started Jul 22 07:16:24 PM PDT 24
Finished Jul 22 07:17:30 PM PDT 24
Peak memory 220776 kb
Host smart-0f18349c-2ad9-4b69-8e23-f91c58ab6a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858407596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.858407596
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1849214628
Short name T394
Test name
Test status
Simulation time 877255343 ps
CPU time 5.97 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:43 PM PDT 24
Peak memory 220216 kb
Host smart-a688e04d-acb3-4089-8dcd-a1f2db2b7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849214628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1849214628
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3723284316
Short name T678
Test name
Test status
Simulation time 135901159 ps
CPU time 2.38 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 205804 kb
Host smart-16e3d2db-375f-4dbb-8b67-eb2223762cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723284316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3723284316
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.4167856464
Short name T444
Test name
Test status
Simulation time 99336979 ps
CPU time 2.61 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 206492 kb
Host smart-4bf11fc1-4c1d-462f-80a1-77c9791a5558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167856464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4167856464
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1522412008
Short name T632
Test name
Test status
Simulation time 32758077 ps
CPU time 2.18 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:39 PM PDT 24
Peak memory 208584 kb
Host smart-044bdd18-9cb8-4441-9c08-ba9ba927da3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522412008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1522412008
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.747293755
Short name T475
Test name
Test status
Simulation time 669488382 ps
CPU time 3.97 seconds
Started Jul 22 07:16:28 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 206704 kb
Host smart-b0d7521c-1579-44f5-9c82-f46742260af3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747293755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.747293755
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4271415088
Short name T763
Test name
Test status
Simulation time 104667986 ps
CPU time 1.89 seconds
Started Jul 22 07:16:17 PM PDT 24
Finished Jul 22 07:17:20 PM PDT 24
Peak memory 208680 kb
Host smart-1a189da8-0be9-4206-b477-093aeafc8f2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271415088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4271415088
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4263715469
Short name T594
Test name
Test status
Simulation time 68833697 ps
CPU time 1.84 seconds
Started Jul 22 07:16:26 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 208416 kb
Host smart-89472ffb-1e88-4757-9b08-8bb81731f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263715469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4263715469
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2708482960
Short name T441
Test name
Test status
Simulation time 401569316 ps
CPU time 4.18 seconds
Started Jul 22 07:16:29 PM PDT 24
Finished Jul 22 07:17:38 PM PDT 24
Peak memory 206588 kb
Host smart-aa377e39-998f-4c34-aa6a-f737fccb6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708482960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2708482960
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.553671740
Short name T260
Test name
Test status
Simulation time 98261908 ps
CPU time 6.98 seconds
Started Jul 22 07:16:14 PM PDT 24
Finished Jul 22 07:17:23 PM PDT 24
Peak memory 222388 kb
Host smart-03bb64b5-f5fd-4f85-98ba-949b6fb6fb7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553671740 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.553671740
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.103937055
Short name T856
Test name
Test status
Simulation time 205788780 ps
CPU time 3.41 seconds
Started Jul 22 07:16:30 PM PDT 24
Finished Jul 22 07:17:40 PM PDT 24
Peak memory 209688 kb
Host smart-2ad3fdc1-1769-4ea1-b4b0-97b2219abc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103937055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.103937055
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2121039073
Short name T738
Test name
Test status
Simulation time 1886357165 ps
CPU time 3.06 seconds
Started Jul 22 07:16:25 PM PDT 24
Finished Jul 22 07:17:32 PM PDT 24
Peak memory 210928 kb
Host smart-46f53544-529d-4cf7-8989-c463458fefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121039073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2121039073
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.285803411
Short name T681
Test name
Test status
Simulation time 16653329 ps
CPU time 0.72 seconds
Started Jul 22 07:12:58 PM PDT 24
Finished Jul 22 07:13:47 PM PDT 24
Peak memory 205804 kb
Host smart-1a80e918-8790-4dab-998e-964d61eed7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285803411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.285803411
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3741741308
Short name T424
Test name
Test status
Simulation time 74015000 ps
CPU time 2.84 seconds
Started Jul 22 07:13:22 PM PDT 24
Finished Jul 22 07:14:16 PM PDT 24
Peak memory 214232 kb
Host smart-188311b6-427f-4362-b918-2de09d1bfeb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741741308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3741741308
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3788758550
Short name T42
Test name
Test status
Simulation time 220150415 ps
CPU time 6.02 seconds
Started Jul 22 07:13:01 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 210160 kb
Host smart-bc093cb8-b5db-4d7f-907b-f925287b36a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788758550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3788758550
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.653562052
Short name T543
Test name
Test status
Simulation time 114592005 ps
CPU time 3.33 seconds
Started Jul 22 07:13:05 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 214136 kb
Host smart-757e9751-c305-49d1-9ed7-06ba173830e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653562052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.653562052
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2846925516
Short name T577
Test name
Test status
Simulation time 76585994 ps
CPU time 3.72 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 213952 kb
Host smart-b283b316-f0a2-4813-81cb-0b741e321381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846925516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2846925516
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.639605485
Short name T857
Test name
Test status
Simulation time 35902716 ps
CPU time 1.7 seconds
Started Jul 22 07:12:59 PM PDT 24
Finished Jul 22 07:13:49 PM PDT 24
Peak memory 214016 kb
Host smart-5af85098-de53-4b43-ac6f-7a8293b8c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639605485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.639605485
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.240043256
Short name T218
Test name
Test status
Simulation time 140973056 ps
CPU time 2.87 seconds
Started Jul 22 07:13:04 PM PDT 24
Finished Jul 22 07:13:54 PM PDT 24
Peak memory 209144 kb
Host smart-16a422eb-803c-42c9-a428-c8e35c05f696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240043256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.240043256
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3380778161
Short name T564
Test name
Test status
Simulation time 76488295 ps
CPU time 3.59 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:38 PM PDT 24
Peak memory 207208 kb
Host smart-7e5261e5-5e7d-4bd4-a8a2-465b03aa8765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380778161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3380778161
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1989475434
Short name T560
Test name
Test status
Simulation time 26625914306 ps
CPU time 50.63 seconds
Started Jul 22 07:13:02 PM PDT 24
Finished Jul 22 07:14:40 PM PDT 24
Peak memory 208408 kb
Host smart-9ea3636e-49ba-4c2e-9947-65dfd8f703ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989475434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1989475434
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2406468368
Short name T298
Test name
Test status
Simulation time 1663786656 ps
CPU time 40.13 seconds
Started Jul 22 07:13:21 PM PDT 24
Finished Jul 22 07:14:51 PM PDT 24
Peak memory 207640 kb
Host smart-1a9633e7-d3e4-4a19-9850-fad45e5420ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406468368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2406468368
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.8257157
Short name T84
Test name
Test status
Simulation time 62601206 ps
CPU time 2.34 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:36 PM PDT 24
Peak memory 207332 kb
Host smart-6e3b95f3-bc1e-4514-8ea9-00b5e45123b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8257157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.8257157
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3041560998
Short name T705
Test name
Test status
Simulation time 63402678 ps
CPU time 3.04 seconds
Started Jul 22 07:12:47 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 208784 kb
Host smart-ac2a1dd1-9400-4c88-9eb4-4333c5a38bb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041560998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3041560998
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3496532897
Short name T232
Test name
Test status
Simulation time 74610934 ps
CPU time 3.22 seconds
Started Jul 22 07:13:00 PM PDT 24
Finished Jul 22 07:13:51 PM PDT 24
Peak memory 218108 kb
Host smart-abb1748d-d33a-4a39-b709-76d683e3581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496532897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3496532897
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2603967256
Short name T670
Test name
Test status
Simulation time 499196349 ps
CPU time 2.89 seconds
Started Jul 22 07:12:45 PM PDT 24
Finished Jul 22 07:13:34 PM PDT 24
Peak memory 208296 kb
Host smart-b81382b8-5c61-439e-a5be-010bca5f500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603967256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2603967256
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.792004931
Short name T340
Test name
Test status
Simulation time 413754859 ps
CPU time 14.56 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:14:00 PM PDT 24
Peak memory 222296 kb
Host smart-bea8ea76-29f8-4143-aef3-3181cd64db09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792004931 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.792004931
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.700088287
Short name T423
Test name
Test status
Simulation time 4163643908 ps
CPU time 56.44 seconds
Started Jul 22 07:13:08 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 208876 kb
Host smart-a6aa1340-8fff-4551-9f7e-a72cb7e5c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700088287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.700088287
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.75503195
Short name T449
Test name
Test status
Simulation time 10779128 ps
CPU time 0.86 seconds
Started Jul 22 07:13:00 PM PDT 24
Finished Jul 22 07:13:48 PM PDT 24
Peak memory 205840 kb
Host smart-39b76e82-ca4b-4326-b5f4-d1ef1c369b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75503195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.75503195
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3530834458
Short name T11
Test name
Test status
Simulation time 594228840 ps
CPU time 3.87 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 208452 kb
Host smart-b8372127-c04a-4dc5-9327-53aa7dc6cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530834458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3530834458
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3229740607
Short name T827
Test name
Test status
Simulation time 225152601 ps
CPU time 2.74 seconds
Started Jul 22 07:13:01 PM PDT 24
Finished Jul 22 07:13:52 PM PDT 24
Peak memory 207008 kb
Host smart-189951c6-5c18-4f65-9a27-4f3df76952bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229740607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3229740607
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1309169429
Short name T318
Test name
Test status
Simulation time 57123600 ps
CPU time 2.84 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:13:49 PM PDT 24
Peak memory 214052 kb
Host smart-e9e42c23-e1a3-4e94-bfbc-05b8b1759ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309169429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1309169429
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.392953745
Short name T374
Test name
Test status
Simulation time 94515215 ps
CPU time 1.99 seconds
Started Jul 22 07:14:04 PM PDT 24
Finished Jul 22 07:14:52 PM PDT 24
Peak memory 213928 kb
Host smart-b9fd6c39-86bf-43fc-b692-044276671213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392953745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.392953745
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3213222989
Short name T469
Test name
Test status
Simulation time 79301078 ps
CPU time 4.04 seconds
Started Jul 22 07:13:04 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 218108 kb
Host smart-0832a949-4ef7-4cfd-b386-bfecbbc06fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213222989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3213222989
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1661003483
Short name T85
Test name
Test status
Simulation time 1014602086 ps
CPU time 3.23 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:13:49 PM PDT 24
Peak memory 208780 kb
Host smart-4f8e9d7d-3029-485c-97ff-bd2bc8006838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661003483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1661003483
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2197194346
Short name T369
Test name
Test status
Simulation time 382986666 ps
CPU time 3.14 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:07 PM PDT 24
Peak memory 208272 kb
Host smart-11b9748e-7bc7-4639-9d77-ecae8d371c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197194346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2197194346
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.970978090
Short name T552
Test name
Test status
Simulation time 6575183463 ps
CPU time 22.26 seconds
Started Jul 22 07:12:59 PM PDT 24
Finished Jul 22 07:14:09 PM PDT 24
Peak memory 208808 kb
Host smart-82c6332d-98c3-4156-aef3-ad5ba63758d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970978090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.970978090
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1097090269
Short name T825
Test name
Test status
Simulation time 378670812 ps
CPU time 9.3 seconds
Started Jul 22 07:13:09 PM PDT 24
Finished Jul 22 07:14:08 PM PDT 24
Peak memory 208128 kb
Host smart-c3564731-a059-4e71-8879-6f6e327d451a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097090269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1097090269
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2959246210
Short name T905
Test name
Test status
Simulation time 106366292 ps
CPU time 4.04 seconds
Started Jul 22 07:12:58 PM PDT 24
Finished Jul 22 07:13:50 PM PDT 24
Peak memory 207924 kb
Host smart-09c3107b-ddea-4922-a4dd-332cc536e3da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959246210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2959246210
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2306703101
Short name T867
Test name
Test status
Simulation time 284855420 ps
CPU time 3.41 seconds
Started Jul 22 07:12:59 PM PDT 24
Finished Jul 22 07:13:51 PM PDT 24
Peak memory 207928 kb
Host smart-3d62046d-229e-420f-95da-44fb1dac154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306703101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2306703101
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1554043208
Short name T34
Test name
Test status
Simulation time 398810613 ps
CPU time 2.93 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:13:49 PM PDT 24
Peak memory 208336 kb
Host smart-d969fb92-6845-426c-aa51-0d879654d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554043208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1554043208
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3652535419
Short name T496
Test name
Test status
Simulation time 136738086 ps
CPU time 4.81 seconds
Started Jul 22 07:13:04 PM PDT 24
Finished Jul 22 07:13:56 PM PDT 24
Peak memory 207272 kb
Host smart-d7fdc07d-0bbe-4aa8-816c-1a5addcaf545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652535419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3652535419
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2598596345
Short name T838
Test name
Test status
Simulation time 362165599 ps
CPU time 8.42 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:13:54 PM PDT 24
Peak memory 210776 kb
Host smart-fcba3c60-2635-47da-b60a-4bdc9d7bc31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598596345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2598596345
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1343397073
Short name T822
Test name
Test status
Simulation time 29110727 ps
CPU time 0.76 seconds
Started Jul 22 07:13:03 PM PDT 24
Finished Jul 22 07:13:52 PM PDT 24
Peak memory 205832 kb
Host smart-d04163f3-03f7-4b50-b1ec-5fc0abe093ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343397073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1343397073
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.528591634
Short name T418
Test name
Test status
Simulation time 101160038 ps
CPU time 5.23 seconds
Started Jul 22 07:13:45 PM PDT 24
Finished Jul 22 07:14:43 PM PDT 24
Peak memory 214548 kb
Host smart-f8ccd404-21af-4736-afc9-406d4f0a15a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528591634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.528591634
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1142384515
Short name T719
Test name
Test status
Simulation time 196497186 ps
CPU time 2.14 seconds
Started Jul 22 07:13:01 PM PDT 24
Finished Jul 22 07:13:51 PM PDT 24
Peak memory 207224 kb
Host smart-e9934afb-5caf-49eb-81c3-db9ecdd9018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142384515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1142384515
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3101709123
Short name T708
Test name
Test status
Simulation time 71649262 ps
CPU time 2.94 seconds
Started Jul 22 07:13:07 PM PDT 24
Finished Jul 22 07:14:00 PM PDT 24
Peak memory 222304 kb
Host smart-022a155a-ebd0-4146-aced-80f343b09209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101709123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3101709123
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.90276503
Short name T2
Test name
Test status
Simulation time 368188397 ps
CPU time 4.28 seconds
Started Jul 22 07:13:46 PM PDT 24
Finished Jul 22 07:14:42 PM PDT 24
Peak memory 219500 kb
Host smart-8a547b38-b581-4ca0-b212-9a48dce19377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90276503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.90276503
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.279121357
Short name T808
Test name
Test status
Simulation time 311520348 ps
CPU time 5.35 seconds
Started Jul 22 07:12:59 PM PDT 24
Finished Jul 22 07:13:52 PM PDT 24
Peak memory 208548 kb
Host smart-baaf4551-ecf6-452c-a966-77a9bc9791e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279121357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.279121357
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2588229042
Short name T601
Test name
Test status
Simulation time 36621230 ps
CPU time 2.22 seconds
Started Jul 22 07:13:04 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 206408 kb
Host smart-8caa06b6-1c37-4c5a-bc71-2d23e6e0b4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588229042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2588229042
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1287094056
Short name T288
Test name
Test status
Simulation time 1107928988 ps
CPU time 4.03 seconds
Started Jul 22 07:14:27 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 208604 kb
Host smart-bd1d9dc0-c650-4a2a-a701-92600973906d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287094056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1287094056
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1033186375
Short name T863
Test name
Test status
Simulation time 120881201 ps
CPU time 4.52 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:13:50 PM PDT 24
Peak memory 206696 kb
Host smart-ace43abf-afe7-4185-a17b-4c2328dfd774
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033186375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1033186375
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4222428662
Short name T739
Test name
Test status
Simulation time 54941973 ps
CPU time 2.93 seconds
Started Jul 22 07:13:00 PM PDT 24
Finished Jul 22 07:13:50 PM PDT 24
Peak memory 208420 kb
Host smart-ddce9ddd-3787-4dd9-b986-f6961dc3192e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222428662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4222428662
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1325626694
Short name T272
Test name
Test status
Simulation time 270556072 ps
CPU time 3.37 seconds
Started Jul 22 07:13:01 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 207988 kb
Host smart-c91bb126-6a3b-4a9b-9c0f-d4b6fc634d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325626694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1325626694
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2494071092
Short name T456
Test name
Test status
Simulation time 202617304 ps
CPU time 2.59 seconds
Started Jul 22 07:13:08 PM PDT 24
Finished Jul 22 07:14:00 PM PDT 24
Peak memory 208652 kb
Host smart-0e022960-9a56-4455-afaf-224442af1433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494071092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2494071092
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1108648769
Short name T296
Test name
Test status
Simulation time 723619596 ps
CPU time 4.61 seconds
Started Jul 22 07:14:03 PM PDT 24
Finished Jul 22 07:14:54 PM PDT 24
Peak memory 207120 kb
Host smart-76ceeab9-59f8-4ade-b9f2-9b2d6e3fc403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108648769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1108648769
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.142360920
Short name T794
Test name
Test status
Simulation time 2684862465 ps
CPU time 12.21 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:15 PM PDT 24
Peak memory 210716 kb
Host smart-b3f38bc4-31c3-431e-9e2e-ee172baebf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142360920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.142360920
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.971870690
Short name T742
Test name
Test status
Simulation time 62059431 ps
CPU time 0.8 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 205852 kb
Host smart-e756be4b-70b4-443a-bf42-8c4eced0d967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971870690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.971870690
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3980305064
Short name T421
Test name
Test status
Simulation time 3899245810 ps
CPU time 45.63 seconds
Started Jul 22 07:14:03 PM PDT 24
Finished Jul 22 07:15:35 PM PDT 24
Peak memory 214400 kb
Host smart-4719e4a2-9415-487f-b854-33e230faee2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980305064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3980305064
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.348674615
Short name T901
Test name
Test status
Simulation time 184344032 ps
CPU time 1.67 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:02 PM PDT 24
Peak memory 209668 kb
Host smart-613409a7-a7cf-4b65-a673-787cec03c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348674615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.348674615
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2267071556
Short name T680
Test name
Test status
Simulation time 569226987 ps
CPU time 5.76 seconds
Started Jul 22 07:13:50 PM PDT 24
Finished Jul 22 07:14:47 PM PDT 24
Peak memory 209744 kb
Host smart-d935d387-1b76-4520-b3d5-c96d0062033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267071556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2267071556
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4241542409
Short name T356
Test name
Test status
Simulation time 469683109 ps
CPU time 5.51 seconds
Started Jul 22 07:13:11 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 209252 kb
Host smart-16758de3-7dcf-4287-b3f7-3c1ce96209b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241542409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4241542409
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4209346160
Short name T805
Test name
Test status
Simulation time 32521166 ps
CPU time 2.03 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 208916 kb
Host smart-db6ebcfc-d1ca-40db-9cfe-9fe6fd4b10b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209346160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4209346160
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4165832323
Short name T873
Test name
Test status
Simulation time 5912231382 ps
CPU time 52.81 seconds
Started Jul 22 07:14:28 PM PDT 24
Finished Jul 22 07:15:57 PM PDT 24
Peak memory 214008 kb
Host smart-71575adf-129a-4ed1-8804-583f1fc4c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165832323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4165832323
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2791571792
Short name T164
Test name
Test status
Simulation time 94917459 ps
CPU time 2.46 seconds
Started Jul 22 07:13:03 PM PDT 24
Finished Jul 22 07:13:53 PM PDT 24
Peak memory 208108 kb
Host smart-b9fa6130-29a3-4eb1-a26c-184d42aed283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791571792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2791571792
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.173052116
Short name T448
Test name
Test status
Simulation time 111184748 ps
CPU time 1.9 seconds
Started Jul 22 07:12:58 PM PDT 24
Finished Jul 22 07:13:48 PM PDT 24
Peak memory 207096 kb
Host smart-61bad7d5-b2fe-404a-b060-2a2edc422603
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173052116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.173052116
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3318225105
Short name T713
Test name
Test status
Simulation time 203176553 ps
CPU time 2.96 seconds
Started Jul 22 07:13:08 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 208260 kb
Host smart-ab89f651-7769-4a14-b219-039692e6d7e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318225105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3318225105
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2288811212
Short name T814
Test name
Test status
Simulation time 162867621 ps
CPU time 4.6 seconds
Started Jul 22 07:13:07 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 208696 kb
Host smart-bbaa0e7c-6294-4502-a616-7af14496f9d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288811212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2288811212
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4152638569
Short name T289
Test name
Test status
Simulation time 111923306 ps
CPU time 1.68 seconds
Started Jul 22 07:13:15 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 207628 kb
Host smart-4e9e55ed-ad16-4231-bd3a-2e76e8744749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152638569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4152638569
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.750855677
Short name T436
Test name
Test status
Simulation time 45873589 ps
CPU time 2.4 seconds
Started Jul 22 07:14:25 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 207716 kb
Host smart-adf28bdc-abf9-46cb-99e8-99ee077c21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750855677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.750855677
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2136005937
Short name T395
Test name
Test status
Simulation time 1620899678 ps
CPU time 26.93 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:28 PM PDT 24
Peak memory 207836 kb
Host smart-70603506-c6cd-4841-a969-cd1f41dcb734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136005937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2136005937
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.526165503
Short name T868
Test name
Test status
Simulation time 2308852898 ps
CPU time 53.43 seconds
Started Jul 22 07:12:57 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 209632 kb
Host smart-e6abe6b2-02a5-4fde-8403-a1711d9c4f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526165503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.526165503
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1448913288
Short name T879
Test name
Test status
Simulation time 71760165 ps
CPU time 2.27 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:04 PM PDT 24
Peak memory 210176 kb
Host smart-1cc20581-ba6e-4705-9902-be4cf5f3800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448913288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1448913288
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3271386701
Short name T695
Test name
Test status
Simulation time 80513373 ps
CPU time 0.72 seconds
Started Jul 22 07:13:15 PM PDT 24
Finished Jul 22 07:14:05 PM PDT 24
Peak memory 205860 kb
Host smart-e4a6633d-f609-4396-bdb9-e165c40a99fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271386701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3271386701
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1020260658
Short name T429
Test name
Test status
Simulation time 113796625 ps
CPU time 6.01 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:08 PM PDT 24
Peak memory 214788 kb
Host smart-4e369d67-3a6c-4d39-a5cd-a96ec11b7b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020260658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1020260658
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1779292535
Short name T498
Test name
Test status
Simulation time 48992884 ps
CPU time 2.88 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 218008 kb
Host smart-7b1d657d-8ec1-4965-b7da-07afa6ca592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779292535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1779292535
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2121116991
Short name T55
Test name
Test status
Simulation time 151831909 ps
CPU time 3.41 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:04 PM PDT 24
Peak memory 209072 kb
Host smart-88f6327d-3b55-4543-a39c-f5a3926ba2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121116991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2121116991
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.344006294
Short name T537
Test name
Test status
Simulation time 87333225 ps
CPU time 2.78 seconds
Started Jul 22 07:13:11 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 221956 kb
Host smart-321d031f-590d-4149-b731-0ff33a8aed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344006294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.344006294
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4258072676
Short name T297
Test name
Test status
Simulation time 158051577 ps
CPU time 6.32 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:07 PM PDT 24
Peak memory 214012 kb
Host smart-5afdd820-9cdd-457a-b225-ac02563a3114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258072676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4258072676
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1235940736
Short name T872
Test name
Test status
Simulation time 106065388 ps
CPU time 3.34 seconds
Started Jul 22 07:14:04 PM PDT 24
Finished Jul 22 07:14:53 PM PDT 24
Peak memory 220348 kb
Host smart-72d6ce10-dae7-4dff-b41a-37bc5e7a41ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235940736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1235940736
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2924185463
Short name T895
Test name
Test status
Simulation time 168244905 ps
CPU time 2.96 seconds
Started Jul 22 07:13:15 PM PDT 24
Finished Jul 22 07:14:07 PM PDT 24
Peak memory 218128 kb
Host smart-4bc71732-f64c-4589-8100-4b6ed13d1dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924185463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2924185463
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1865221685
Short name T569
Test name
Test status
Simulation time 81377621 ps
CPU time 2.6 seconds
Started Jul 22 07:13:15 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 206596 kb
Host smart-790e4eb5-594b-4924-9cca-c86230a77a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865221685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1865221685
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3920113904
Short name T907
Test name
Test status
Simulation time 79794336 ps
CPU time 3.03 seconds
Started Jul 22 07:13:12 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 207280 kb
Host smart-2a5c65b9-f3c5-476c-9a81-16d3e45d3def
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920113904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3920113904
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1472252571
Short name T843
Test name
Test status
Simulation time 536103513 ps
CPU time 3.19 seconds
Started Jul 22 07:13:11 PM PDT 24
Finished Jul 22 07:14:03 PM PDT 24
Peak memory 206684 kb
Host smart-04ba4c25-a899-4d11-954e-d206348688d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472252571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1472252571
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1711075884
Short name T611
Test name
Test status
Simulation time 18652177 ps
CPU time 1.74 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:04 PM PDT 24
Peak memory 206472 kb
Host smart-f7f425cc-56fb-46f2-8c93-b10e1265f399
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711075884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1711075884
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3662381566
Short name T494
Test name
Test status
Simulation time 21788874 ps
CPU time 1.69 seconds
Started Jul 22 07:13:11 PM PDT 24
Finished Jul 22 07:14:02 PM PDT 24
Peak memory 207368 kb
Host smart-b189b563-e2cc-4959-b298-33e3a03b05d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662381566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3662381566
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.771679294
Short name T636
Test name
Test status
Simulation time 171331975 ps
CPU time 2.2 seconds
Started Jul 22 07:13:15 PM PDT 24
Finished Jul 22 07:14:07 PM PDT 24
Peak memory 206500 kb
Host smart-1b3b367c-74b6-4e44-9048-55d45bb90e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771679294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.771679294
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1873404565
Short name T853
Test name
Test status
Simulation time 888014433 ps
CPU time 26.64 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:29 PM PDT 24
Peak memory 209256 kb
Host smart-3ea1c403-81e3-4e43-a92e-370f81f602e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873404565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1873404565
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1875864550
Short name T549
Test name
Test status
Simulation time 146938488 ps
CPU time 3.7 seconds
Started Jul 22 07:13:14 PM PDT 24
Finished Jul 22 07:14:06 PM PDT 24
Peak memory 210176 kb
Host smart-8a7add90-349b-4170-894b-15fa917cd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875864550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1875864550
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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