Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	40	1			T9	1		T45	1		T46	1
auto[OpGenId]	11	1			T54	1		T55	1		T63	1
auto[OpGenSwOut]	18	1			T141	1		T82	1		T64	1
auto[OpGenHwOut]	27	1			T6	1		T7	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1586	1			T15	1		T27	1		T78	1
auto[StInit]	83	1			T27	1		T54	1		T19	1
auto[StCreatorRootKey]	55	1			T57	1		T115	1		T42	1
auto[StOwnerIntKey]	47	1			T34	1		T27	1		T9	1
auto[StOwnerKey]	38	1			T15	1		T65	1		T67	1
auto[StDisabled]	463	1			T15	3		T27	2		T6	1
auto[StInvalid]	50	1			T37	1		T51	1		T38	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3316

1

T1

1

T2

1

T3

1

auto[1]

96

1

T9

1

T54

1

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1580	1			T15	1		T27	1		T78	1
auto[StReset]	auto[1]	6	1			T80	1		T84	1		T52	1
auto[StInit]	auto[0]	38	1			T27	1		T19	1		T20	1
auto[StInit]	auto[1]	45	1			T54	1		T55	1		T7	1
auto[StCreatorRootKey]	auto[0]	35	1			T57	1		T115	1		T42	1
auto[StCreatorRootKey]	auto[1]	20	1			T45	1		T46	1		T58	1
auto[StOwnerIntKey]	auto[0]	36	1			T34	1		T27	1		T115	1
auto[StOwnerIntKey]	auto[1]	11	1			T9	1		T63	1		T220	1
auto[StOwnerKey]	auto[0]	32	1			T15	1		T65	1		T67	1
auto[StOwnerKey]	auto[1]	6	1			T48	1		T70	1		T221	1
auto[StDisabled]	auto[0]	455	1			T15	3		T27	2		T55	5
auto[StDisabled]	auto[1]	8	1			T6	1		T47	1		T222	1
auto[StInvalid]	auto[0]	50	1			T37	1		T51	1		T38	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T80	1		T84	1		T52	1
auto[StInit]	auto[OpAdvance]	17	1			T30	1		T223	1		T224	1
auto[StInit]	auto[OpGenId]	4	1			T54	1		T55	1		T31	1
auto[StInit]	auto[OpGenSwOut]	10	1			T82	1		T64	1		T41	1
auto[StInit]	auto[OpGenHwOut]	14	1			T7	1		T8	1		T21	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T45	1		T46	1		T58	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T225	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T141	1		T226	1		T227	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T228	1		T229	1		T230	1
auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T9	1		T231	1		-	-
auto[StOwnerIntKey]	auto[OpGenId]	4	1			T63	1		T220	1		T232	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T233	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	4	1			T234	1		T235	1		T236	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T237	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T10	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	4	1			T48	1		T70	1		T221	1
auto[StDisabled]	auto[OpAdvance]	3	1			T47	1		T238	1		T239	1
auto[StDisabled]	auto[OpGenId]	1	1			T191	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T222	1		T240	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T6	1		T241	1		-	-