Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11016

1

T1

15

T2

8

T4

6

auto[Attestation]

7716

1

T1

4

T2

11

T4

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2734	1			T1	3		T2	3		T15	11
auto[Aes]	3376	1			T1	2		T2	3		T5	1
auto[Kmac]	3329	1			T1	4		T2	1		T5	3
auto[Otbn]	3415	1			T2	5		T4	2		T5	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7647	1			T1	8		T2	8		T3	1
auto[OpGenId]	5878	1			T1	10		T2	7		T4	6
auto[OpGenSwOut]	5905	1			T1	7		T2	6		T4	2
auto[OpGenHwOut]	6949	1			T1	2		T2	6		T5	4
auto[OpDisable]	151	1			T27	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10749

1

T1

11

T2

15

T3

1

auto[OpDoneFail]

15781

1

T1

16

T2

12

T4

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6461	1			T1	4		T2	1		T3	1
auto[StInit]	3648	1			T1	3		T2	2		T4	2
auto[StCreatorRootKey]	3137	1			T1	2		T2	1		T4	2
auto[StOwnerIntKey]	2856	1			T1	3		T2	6		T4	2
auto[StOwnerKey]	2542	1			T1	4		T2	6		T4	2
auto[StDisabled]	7886	1			T1	11		T2	11		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	342	1			T1	1		T27	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T27	2		T37	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T34	1		T193	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T15	2		T139	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T194	1		T56	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	234	1			T15	1		T99	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T27	2		T197	2		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	88	1			T34	1		T65	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T56	2		T186	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T2	2		T27	2		T65	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T57	1		T200	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	202	1			T1	1		T26	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	324	1			T1	1		T15	1		T9	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T2	1		T27	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T34	1		T198	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T1	1		T15	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T1	1		T5	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	209	1			T202	1		T203	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	341	1			T15	1		T27	1		T9	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T57	1		T115	1		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T15	1		T204	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T57	1		T55	1		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T5	1		T6	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	212	1			T2	2		T4	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	83	1			T27	1		T56	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T15	2		T55	2		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T98	1		T57	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	91	1			T26	1		T65	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T140	1		T56	3		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T27	1		T46	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T15	1		T26	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T15	1		T26	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	82	1			T26	1		T206	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T15	1		T196	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	209	1			T1	1		T139	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T27	1		T56	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	105	1			T54	1		T208	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T15	1		T26	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T27	1		T65	1		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T57	1		T56	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	226	1			T98	1		T99	2		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T56	1		T46	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	91	1			T5	1		T34	1		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T196	1		T211	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T148	2		T61	1		T210	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T4	1		T27	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	219	1			T26	1		T98	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	281	1			T27	3		T198	1		T204	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	75	1			T15	2		T42	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T194	1		T212	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T57	1		T206	1		T194	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T26	1		T203	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	479	1			T15	1		T198	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T208	1		T199	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	98	1			T5	1		T26	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	102	1			T213	1		T199	1		T193	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	99	1			T15	2		T26	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	307	1			T26	1		T27	1		T214	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	407	1			T16	4		T27	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	130	1			T15	1		T16	1		T9	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	120	1			T15	1		T16	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T16	1		T208	1		T55	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	79	1			T5	1		T35	1		T56	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	275	1			T1	1		T26	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	491	1			T65	1		T197	2		T215	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T15	1		T49	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T216	1		T217	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T26	1		T216	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T5	1		T215	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T35	2		T204	1		T216	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T46	2		T134	1		T77	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T65	1		T139	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	81	1			T27	1		T197	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	76	1			T15	1		T6	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T57	1		T139	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	148	1			T2	1		T15	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T46	1		T134	2		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T15	1		T214	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	100	1			T15	1		T211	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T35	1		T214	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T2	1		T15	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	258	1			T26	2		T35	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T46	3		T134	2		T47	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	101	1			T26	1		T27	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T9	1		T199	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T194	1		T208	1		T193	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T16	1		T201	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	300	1			T16	4		T26	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	69	1			T46	1		T47	3		T136	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T15	1		T27	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T34	1		T27	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	114	1			T2	1		T215	1		T199	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T2	1		T5	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	268	1			T2	1		T197	1		T216	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T15	2		T34	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	678	1			T1	1		T15	1		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	222	1			T2	2		T27	1		T65	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	615	1			T1	1		T34	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T1	2		T5	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	650	1			T1	1		T2	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T5	1		T204	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	667	1			T2	2		T4	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	208	1			T26	1		T98	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	400	1			T1	1		T2	1		T15	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	215	1			T15	1		T196	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	404	1			T1	1		T15	2		T26	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	213	1			T15	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	422	1			T27	1		T98	1		T99	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	211	1			T4	1		T27	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	399	1			T5	1		T34	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	190	1			T26	1		T57	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	541	1			T1	1		T2	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	277	1			T5	1		T15	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	928	1			T15	2		T26	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T5	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	828	1			T1	1		T15	1		T16	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T5	1		T26	1		T216	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	908	1			T15	1		T35	2		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	188	1			T15	1		T27	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	325	1			T2	1		T15	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	247	1			T2	1		T15	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	468	1			T15	2		T26	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T16	1		T9	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	478	1			T16	4		T26	2		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	299	1			T2	2		T5	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	468	1			T2	1		T15	1		T27	1