Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32734

1

T1

33

T2

31

T3

28

auto[1]

285

1

T1

8

T2

2

T35

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32740	1			T1	33		T2	32		T3	28
auto[134217728:268435455]	9	1			T139	1		T390	1		T371	2
auto[268435456:402653183]	15	1			T1	1		T259	1		T280	1
auto[402653184:536870911]	16	1			T1	3		T139	1		T262	2
auto[536870912:671088639]	7	1			T1	1		T262	1		T275	1
auto[671088640:805306367]	13	1			T397	1		T275	1		T319	1
auto[805306368:939524095]	10	1			T259	1		T262	1		T248	1
auto[939524096:1073741823]	9	1			T259	1		T248	1		T390	1
auto[1073741824:1207959551]	10	1			T259	2		T345	1		T365	1
auto[1207959552:1342177279]	6	1			T1	1		T345	1		T432	1
auto[1342177280:1476395007]	8	1			T139	1		T371	2		T297	1
auto[1476395008:1610612735]	8	1			T148	1		T275	1		T390	1
auto[1610612736:1744830463]	12	1			T139	1		T275	1		T432	2
auto[1744830464:1879048191]	4	1			T262	1		T433	1		T345	1
auto[1879048192:2013265919]	10	1			T139	1		T148	1		T390	1
auto[2013265920:2147483647]	10	1			T2	1		T35	2		T365	1
auto[2147483648:2281701375]	6	1			T139	1		T319	1		T300	1
auto[2281701376:2415919103]	3	1			T139	1		T297	1		T434	1
auto[2415919104:2550136831]	13	1			T397	1		T319	2		T253	1
auto[2550136832:2684354559]	3	1			T282	1		T243	1		T435	1
auto[2684354560:2818572287]	6	1			T35	1		T259	1		T253	1
auto[2818572288:2952790015]	10	1			T139	1		T268	1		T390	1
auto[2952790016:3087007743]	6	1			T265	1		T253	1		T279	1
auto[3087007744:3221225471]	10	1			T285	1		T319	2		T248	1
auto[3221225472:3355443199]	11	1			T268	1		T285	1		T275	1
auto[3355443200:3489660927]	5	1			T300	1		T265	1		T436	1
auto[3489660928:3623878655]	13	1			T1	1		T35	1		T139	1
auto[3623878656:3758096383]	11	1			T1	1		T436	1		T432	1
auto[3758096384:3892314111]	12	1			T259	1		T262	2		T319	1
auto[3892314112:4026531839]	7	1			T259	1		T436	1		T432	1
auto[4026531840:4160749567]	7	1			T275	1		T432	1		T371	1
auto[4160749568:4294967295]	9	1			T275	1		T265	1		T390	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32734	1			T1	33		T2	31		T3	28
auto[0:134217727]	auto[1]	6	1			T2	1		T139	1		T319	2
auto[134217728:268435455]	auto[1]	9	1			T139	1		T390	1		T371	2
auto[268435456:402653183]	auto[1]	15	1			T1	1		T259	1		T280	1
auto[402653184:536870911]	auto[1]	16	1			T1	3		T139	1		T262	2
auto[536870912:671088639]	auto[1]	7	1			T1	1		T262	1		T275	1
auto[671088640:805306367]	auto[1]	13	1			T397	1		T275	1		T319	1
auto[805306368:939524095]	auto[1]	10	1			T259	1		T262	1		T248	1
auto[939524096:1073741823]	auto[1]	9	1			T259	1		T248	1		T390	1
auto[1073741824:1207959551]	auto[1]	10	1			T259	2		T345	1		T365	1
auto[1207959552:1342177279]	auto[1]	6	1			T1	1		T345	1		T432	1
auto[1342177280:1476395007]	auto[1]	8	1			T139	1		T371	2		T297	1
auto[1476395008:1610612735]	auto[1]	8	1			T148	1		T275	1		T390	1
auto[1610612736:1744830463]	auto[1]	12	1			T139	1		T275	1		T432	2
auto[1744830464:1879048191]	auto[1]	4	1			T262	1		T433	1		T345	1
auto[1879048192:2013265919]	auto[1]	10	1			T139	1		T148	1		T390	1
auto[2013265920:2147483647]	auto[1]	10	1			T2	1		T35	2		T365	1
auto[2147483648:2281701375]	auto[1]	6	1			T139	1		T319	1		T300	1
auto[2281701376:2415919103]	auto[1]	3	1			T139	1		T297	1		T434	1
auto[2415919104:2550136831]	auto[1]	13	1			T397	1		T319	2		T253	1
auto[2550136832:2684354559]	auto[1]	3	1			T282	1		T243	1		T435	1
auto[2684354560:2818572287]	auto[1]	6	1			T35	1		T259	1		T253	1
auto[2818572288:2952790015]	auto[1]	10	1			T139	1		T268	1		T390	1
auto[2952790016:3087007743]	auto[1]	6	1			T265	1		T253	1		T279	1
auto[3087007744:3221225471]	auto[1]	10	1			T285	1		T319	2		T248	1
auto[3221225472:3355443199]	auto[1]	11	1			T268	1		T285	1		T275	1
auto[3355443200:3489660927]	auto[1]	5	1			T300	1		T265	1		T436	1
auto[3489660928:3623878655]	auto[1]	13	1			T1	1		T35	1		T139	1
auto[3623878656:3758096383]	auto[1]	11	1			T1	1		T436	1		T432	1
auto[3758096384:3892314111]	auto[1]	12	1			T259	1		T262	2		T319	1
auto[3892314112:4026531839]	auto[1]	7	1			T259	1		T436	1		T432	1
auto[4026531840:4160749567]	auto[1]	7	1			T275	1		T432	1		T371	1
auto[4160749568:4294967295]	auto[1]	9	1			T275	1		T265	1		T390	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565

1

T1

6

T3

3

T15

1

auto[1]

1774

1

T1

1

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T2	1		T26	1		T35	1
auto[134217728:268435455]	109	1			T15	1		T26	1		T27	1
auto[268435456:402653183]	111	1			T65	1		T6	1		T56	1
auto[402653184:536870911]	103	1			T1	1		T54	1		T65	1
auto[536870912:671088639]	109	1			T2	1		T9	1		T6	1
auto[671088640:805306367]	105	1			T54	1		T57	1		T148	1
auto[805306368:939524095]	94	1			T9	1		T148	1		T6	1
auto[939524096:1073741823]	107	1			T1	1		T194	1		T61	1
auto[1073741824:1207959551]	98	1			T36	1		T37	1		T193	1
auto[1207959552:1342177279]	96	1			T65	1		T208	1		T55	1
auto[1342177280:1476395007]	83	1			T1	1		T3	1		T5	1
auto[1476395008:1610612735]	121	1			T206	1		T194	1		T38	1
auto[1610612736:1744830463]	108	1			T2	1		T6	1		T37	1
auto[1744830464:1879048191]	116	1			T1	1		T27	1		T9	1
auto[1879048192:2013265919]	111	1			T35	1		T27	1		T37	1
auto[2013265920:2147483647]	94	1			T65	1		T36	1		T139	1
auto[2147483648:2281701375]	96	1			T1	1		T35	1		T54	1
auto[2281701376:2415919103]	107	1			T27	1		T148	1		T55	1
auto[2415919104:2550136831]	103	1			T26	1		T27	1		T36	1
auto[2550136832:2684354559]	97	1			T1	1		T5	1		T15	1
auto[2684354560:2818572287]	114	1			T194	1		T37	1		T56	1
auto[2818572288:2952790015]	94	1			T3	2		T54	1		T36	1
auto[2952790016:3087007743]	114	1			T27	1		T36	1		T194	2
auto[3087007744:3221225471]	113	1			T49	1		T56	3		T72	2
auto[3221225472:3355443199]	109	1			T27	1		T57	2		T140	1
auto[3355443200:3489660927]	108	1			T3	1		T15	1		T27	1
auto[3489660928:3623878655]	103	1			T35	1		T65	1		T57	1
auto[3623878656:3758096383]	111	1			T65	1		T193	2		T55	1
auto[3758096384:3892314111]	110	1			T57	1		T49	1		T148	1
auto[3892314112:4026531839]	91	1			T1	1		T206	1		T55	2
auto[4026531840:4160749567]	98	1			T36	1		T60	1		T55	1
auto[4160749568:4294967295]	105	1			T27	1		T206	1		T140	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T26	1		T270	1		T246	1
auto[0:134217727]	auto[1]	60	1			T2	1		T35	1		T201	1
auto[134217728:268435455]	auto[0]	54	1			T15	1		T27	1		T57	1
auto[134217728:268435455]	auto[1]	55	1			T26	1		T194	1		T20	1
auto[268435456:402653183]	auto[0]	39	1			T65	1		T56	1		T271	1
auto[268435456:402653183]	auto[1]	72	1			T6	1		T116	1		T66	1
auto[402653184:536870911]	auto[0]	56	1			T1	1		T54	1		T65	1
auto[402653184:536870911]	auto[1]	47	1			T55	2		T56	1		T71	1
auto[536870912:671088639]	auto[0]	59	1			T6	1		T50	1		T56	1
auto[536870912:671088639]	auto[1]	50	1			T2	1		T9	1		T56	1
auto[671088640:805306367]	auto[0]	49	1			T54	1		T57	1		T194	1
auto[671088640:805306367]	auto[1]	56	1			T148	1		T55	1		T56	2
auto[805306368:939524095]	auto[0]	41	1			T56	1		T45	1		T46	1
auto[805306368:939524095]	auto[1]	53	1			T9	1		T148	1		T6	1
auto[939524096:1073741823]	auto[0]	54	1			T61	1		T55	1		T171	1
auto[939524096:1073741823]	auto[1]	53	1			T1	1		T194	1		T56	1
auto[1073741824:1207959551]	auto[0]	55	1			T37	1		T193	1		T38	1
auto[1073741824:1207959551]	auto[1]	43	1			T36	1		T56	1		T46	1
auto[1207959552:1342177279]	auto[0]	43	1			T56	1		T351	1		T355	1
auto[1207959552:1342177279]	auto[1]	53	1			T65	1		T208	1		T55	1
auto[1342177280:1476395007]	auto[0]	36	1			T1	1		T54	1		T6	1
auto[1342177280:1476395007]	auto[1]	47	1			T3	1		T5	1		T49	1
auto[1476395008:1610612735]	auto[0]	58	1			T38	1		T56	1		T106	1
auto[1476395008:1610612735]	auto[1]	63	1			T206	1		T194	1		T55	1
auto[1610612736:1744830463]	auto[0]	52	1			T37	1		T56	2		T171	1
auto[1610612736:1744830463]	auto[1]	56	1			T2	1		T6	1		T38	1
auto[1744830464:1879048191]	auto[0]	48	1			T1	1		T27	1		T140	1
auto[1744830464:1879048191]	auto[1]	68	1			T9	1		T115	2		T56	2
auto[1879048192:2013265919]	auto[0]	51	1			T56	1		T270	1		T252	1
auto[1879048192:2013265919]	auto[1]	60	1			T35	1		T27	1		T37	1
auto[2013265920:2147483647]	auto[0]	51	1			T65	1		T36	1		T139	1
auto[2013265920:2147483647]	auto[1]	43	1			T140	1		T75	1		T102	1
auto[2147483648:2281701375]	auto[0]	44	1			T1	1		T54	1		T50	1
auto[2147483648:2281701375]	auto[1]	52	1			T35	1		T65	1		T78	1
auto[2281701376:2415919103]	auto[0]	44	1			T56	1		T218	1		T246	1
auto[2281701376:2415919103]	auto[1]	63	1			T27	1		T148	1		T55	1
auto[2415919104:2550136831]	auto[0]	51	1			T27	1		T36	1		T50	1
auto[2415919104:2550136831]	auto[1]	52	1			T26	1		T37	1		T75	1
auto[2550136832:2684354559]	auto[0]	48	1			T1	1		T27	1		T55	1
auto[2550136832:2684354559]	auto[1]	49	1			T5	1		T15	1		T60	1
auto[2684354560:2818572287]	auto[0]	47	1			T351	2		T247	1		T288	1
auto[2684354560:2818572287]	auto[1]	67	1			T194	1		T37	1		T56	1
auto[2818572288:2952790015]	auto[0]	48	1			T3	2		T54	1		T36	1
auto[2818572288:2952790015]	auto[1]	46	1			T139	1		T51	1		T55	1
auto[2952790016:3087007743]	auto[0]	48	1			T27	1		T36	1		T194	1
auto[2952790016:3087007743]	auto[1]	66	1			T194	1		T55	1		T218	1
auto[3087007744:3221225471]	auto[0]	60	1			T49	1		T56	2		T288	2
auto[3087007744:3221225471]	auto[1]	53	1			T56	1		T72	2		T138	2
auto[3221225472:3355443199]	auto[0]	46	1			T27	1		T57	1		T55	1
auto[3221225472:3355443199]	auto[1]	63	1			T57	1		T140	1		T38	1
auto[3355443200:3489660927]	auto[0]	54	1			T3	1		T27	1		T51	1
auto[3355443200:3489660927]	auto[1]	54	1			T15	1		T54	1		T139	1
auto[3489660928:3623878655]	auto[0]	50	1			T35	1		T37	1		T56	2
auto[3489660928:3623878655]	auto[1]	53	1			T65	1		T57	1		T37	1
auto[3623878656:3758096383]	auto[0]	60	1			T193	1		T55	1		T105	2
auto[3623878656:3758096383]	auto[1]	51	1			T65	1		T193	1		T56	1
auto[3758096384:3892314111]	auto[0]	42	1			T148	1		T193	1		T116	1
auto[3758096384:3892314111]	auto[1]	68	1			T57	1		T49	1		T55	1
auto[3892314112:4026531839]	auto[0]	41	1			T1	1		T105	1		T218	1
auto[3892314112:4026531839]	auto[1]	50	1			T206	1		T55	2		T186	1
auto[4026531840:4160749567]	auto[0]	47	1			T36	1		T60	1		T56	1
auto[4026531840:4160749567]	auto[1]	51	1			T55	1		T246	1		T134	1
auto[4160749568:4294967295]	auto[0]	48	1			T27	1		T38	1		T55	1
auto[4160749568:4294967295]	auto[1]	57	1			T206	1		T140	1		T37	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1566

1

T1

5

T3

4

T26

2

auto[1]

1775

1

T1

2

T2

3

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T65	1		T57	1		T206	1
auto[134217728:268435455]	111	1			T15	1		T65	1		T6	1
auto[268435456:402653183]	108	1			T9	1		T49	1		T139	1
auto[402653184:536870911]	102	1			T57	1		T194	1		T37	1
auto[536870912:671088639]	103	1			T27	1		T37	1		T201	1
auto[671088640:805306367]	103	1			T27	1		T54	1		T36	1
auto[805306368:939524095]	106	1			T1	2		T27	1		T9	1
auto[939524096:1073741823]	87	1			T35	1		T201	1		T55	2
auto[1073741824:1207959551]	111	1			T54	1		T194	2		T38	1
auto[1207959552:1342177279]	101	1			T57	1		T38	1		T55	1
auto[1342177280:1476395007]	101	1			T55	1		T56	1		T117	1
auto[1476395008:1610612735]	94	1			T57	2		T38	1		T61	1
auto[1610612736:1744830463]	123	1			T3	1		T27	1		T194	1
auto[1744830464:1879048191]	109	1			T15	1		T26	1		T50	1
auto[1879048192:2013265919]	92	1			T26	1		T27	1		T65	1
auto[2013265920:2147483647]	84	1			T1	1		T27	1		T139	1
auto[2147483648:2281701375]	110	1			T3	1		T26	1		T65	1
auto[2281701376:2415919103]	99	1			T3	1		T27	1		T65	1
auto[2415919104:2550136831]	125	1			T2	1		T35	1		T193	1
auto[2550136832:2684354559]	111	1			T140	1		T51	1		T55	1
auto[2684354560:2818572287]	106	1			T148	1		T6	1		T194	1
auto[2818572288:2952790015]	98	1			T5	1		T65	1		T140	1
auto[2952790016:3087007743]	117	1			T1	1		T35	1		T9	1
auto[3087007744:3221225471]	103	1			T1	1		T54	1		T139	1
auto[3221225472:3355443199]	104	1			T15	1		T27	1		T54	2
auto[3355443200:3489660927]	103	1			T65	1		T36	1		T38	1
auto[3489660928:3623878655]	93	1			T1	1		T2	1		T206	1
auto[3623878656:3758096383]	100	1			T27	1		T36	1		T56	3
auto[3758096384:3892314111]	99	1			T49	1		T148	1		T194	1
auto[3892314112:4026531839]	104	1			T1	1		T5	1		T27	1
auto[4026531840:4160749567]	124	1			T2	1		T3	1		T49	1
auto[4160749568:4294967295]	111	1			T35	1		T54	1		T36	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T140	1		T56	1		T105	1
auto[0:134217727]	auto[1]	51	1			T65	1		T57	1		T206	1
auto[134217728:268435455]	auto[0]	45	1			T65	1		T50	1		T55	1
auto[134217728:268435455]	auto[1]	66	1			T15	1		T6	1		T55	2
auto[268435456:402653183]	auto[0]	44	1			T105	1		T218	1		T274	1
auto[268435456:402653183]	auto[1]	64	1			T9	1		T49	1		T139	1
auto[402653184:536870911]	auto[0]	43	1			T194	1		T38	1		T117	2
auto[402653184:536870911]	auto[1]	59	1			T57	1		T37	1		T38	1
auto[536870912:671088639]	auto[0]	46	1			T27	1		T56	2		T271	1
auto[536870912:671088639]	auto[1]	57	1			T37	1		T201	1		T55	1
auto[671088640:805306367]	auto[0]	50	1			T27	1		T36	1		T50	1
auto[671088640:805306367]	auto[1]	53	1			T54	1		T46	1		T77	2
auto[805306368:939524095]	auto[0]	53	1			T1	1		T78	1		T56	3
auto[805306368:939524095]	auto[1]	53	1			T1	1		T27	1		T9	1
auto[939524096:1073741823]	auto[0]	44	1			T56	1		T116	1		T105	1
auto[939524096:1073741823]	auto[1]	43	1			T35	1		T201	1		T55	2
auto[1073741824:1207959551]	auto[0]	52	1			T54	1		T194	1		T60	1
auto[1073741824:1207959551]	auto[1]	59	1			T194	1		T38	1		T115	1
auto[1207959552:1342177279]	auto[0]	44	1			T57	1		T38	1		T56	1
auto[1207959552:1342177279]	auto[1]	57	1			T55	1		T56	1		T7	1
auto[1342177280:1476395007]	auto[0]	54	1			T55	1		T56	1		T117	1
auto[1342177280:1476395007]	auto[1]	47	1			T209	1		T218	1		T245	1
auto[1476395008:1610612735]	auto[0]	51	1			T57	1		T38	1		T55	1
auto[1476395008:1610612735]	auto[1]	43	1			T57	1		T61	1		T56	2
auto[1610612736:1744830463]	auto[0]	69	1			T3	1		T27	1		T37	1
auto[1610612736:1744830463]	auto[1]	54	1			T194	1		T51	1		T38	1
auto[1744830464:1879048191]	auto[0]	54	1			T26	1		T50	1		T38	1
auto[1744830464:1879048191]	auto[1]	55	1			T15	1		T193	1		T55	1
auto[1879048192:2013265919]	auto[0]	51	1			T65	1		T36	1		T37	1
auto[1879048192:2013265919]	auto[1]	41	1			T26	1		T27	1		T148	1
auto[2013265920:2147483647]	auto[0]	34	1			T1	1		T116	1		T117	1
auto[2013265920:2147483647]	auto[1]	50	1			T27	1		T139	1		T6	1
auto[2147483648:2281701375]	auto[0]	38	1			T3	1		T26	1		T55	1
auto[2147483648:2281701375]	auto[1]	72	1			T65	1		T55	1		T115	1
auto[2281701376:2415919103]	auto[0]	48	1			T3	1		T27	1		T65	1
auto[2281701376:2415919103]	auto[1]	51	1			T56	1		T116	1		T134	1
auto[2415919104:2550136831]	auto[0]	58	1			T35	1		T193	1		T55	1
auto[2415919104:2550136831]	auto[1]	67	1			T2	1		T56	2		T116	1
auto[2550136832:2684354559]	auto[0]	46	1			T56	1		T117	1		T252	2
auto[2550136832:2684354559]	auto[1]	65	1			T140	1		T51	1		T55	1
auto[2684354560:2818572287]	auto[0]	45	1			T148	1		T6	1		T60	1
auto[2684354560:2818572287]	auto[1]	61	1			T194	1		T186	1		T66	2
auto[2818572288:2952790015]	auto[0]	51	1			T65	1		T56	1		T104	1
auto[2818572288:2952790015]	auto[1]	47	1			T5	1		T140	1		T37	1
auto[2952790016:3087007743]	auto[0]	57	1			T57	1		T36	1		T55	3
auto[2952790016:3087007743]	auto[1]	60	1			T1	1		T35	1		T9	1
auto[3087007744:3221225471]	auto[0]	47	1			T1	1		T54	1		T56	1
auto[3087007744:3221225471]	auto[1]	56	1			T139	1		T6	1		T51	1
auto[3221225472:3355443199]	auto[0]	41	1			T27	1		T54	2		T37	1
auto[3221225472:3355443199]	auto[1]	63	1			T15	1		T20	1		T55	1
auto[3355443200:3489660927]	auto[0]	55	1			T65	1		T38	1		T56	3
auto[3355443200:3489660927]	auto[1]	48	1			T36	1		T56	2		T205	1
auto[3489660928:3623878655]	auto[0]	43	1			T1	1		T51	1		T56	1
auto[3489660928:3623878655]	auto[1]	50	1			T2	1		T206	1		T51	1
auto[3623878656:3758096383]	auto[0]	47	1			T27	1		T36	1		T56	1
auto[3623878656:3758096383]	auto[1]	53	1			T56	2		T23	1		T392	1
auto[3758096384:3892314111]	auto[0]	49	1			T56	1		T271	1		T288	1
auto[3758096384:3892314111]	auto[1]	50	1			T49	1		T148	1		T194	1
auto[3892314112:4026531839]	auto[0]	45	1			T1	1		T27	1		T36	1
auto[3892314112:4026531839]	auto[1]	59	1			T5	1		T55	1		T115	1
auto[4026531840:4160749567]	auto[0]	60	1			T3	1		T49	1		T206	1
auto[4026531840:4160749567]	auto[1]	64	1			T2	1		T56	4		T244	2
auto[4160749568:4294967295]	auto[0]	54	1			T54	1		T36	1		T56	1
auto[4160749568:4294967295]	auto[1]	57	1			T35	1		T45	1		T210	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1576

1

T1

5

T2

1

T3

3

auto[1]

1762

1

T1

2

T2

2

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T54	1		T194	1		T37	1
auto[134217728:268435455]	91	1			T15	1		T49	1		T37	1
auto[268435456:402653183]	100	1			T3	1		T36	1		T148	1
auto[402653184:536870911]	85	1			T3	1		T208	1		T51	1
auto[536870912:671088639]	118	1			T15	1		T27	1		T9	1
auto[671088640:805306367]	104	1			T140	1		T20	1		T193	1
auto[805306368:939524095]	100	1			T27	3		T193	1		T51	1
auto[939524096:1073741823]	100	1			T2	1		T35	1		T50	1
auto[1073741824:1207959551]	88	1			T27	1		T78	1		T194	1
auto[1207959552:1342177279]	110	1			T26	1		T65	1		T148	1
auto[1342177280:1476395007]	99	1			T36	1		T6	1		T60	1
auto[1476395008:1610612735]	92	1			T27	1		T65	1		T51	1
auto[1610612736:1744830463]	111	1			T65	1		T36	1		T6	1
auto[1744830464:1879048191]	94	1			T5	1		T55	2		T115	1
auto[1879048192:2013265919]	114	1			T1	1		T2	1		T38	1
auto[2013265920:2147483647]	114	1			T1	1		T36	1		T115	1
auto[2147483648:2281701375]	104	1			T5	1		T35	1		T54	1
auto[2281701376:2415919103]	100	1			T1	1		T9	1		T36	1
auto[2415919104:2550136831]	114	1			T206	1		T55	2		T116	1
auto[2550136832:2684354559]	110	1			T3	1		T35	1		T54	1
auto[2684354560:2818572287]	101	1			T65	2		T57	2		T36	1
auto[2818572288:2952790015]	128	1			T27	2		T54	1		T57	1
auto[2952790016:3087007743]	121	1			T1	2		T57	1		T37	1
auto[3087007744:3221225471]	88	1			T9	1		T51	1		T55	1
auto[3221225472:3355443199]	108	1			T2	1		T26	1		T6	1
auto[3355443200:3489660927]	105	1			T1	1		T3	1		T15	1
auto[3489660928:3623878655]	99	1			T206	1		T61	1		T56	2
auto[3623878656:3758096383]	115	1			T65	1		T148	1		T206	1
auto[3758096384:3892314111]	96	1			T27	1		T54	1		T36	1
auto[3892314112:4026531839]	105	1			T35	1		T37	1		T38	1
auto[4026531840:4160749567]	122	1			T1	1		T27	1		T65	1
auto[4160749568:4294967295]	98	1			T26	1		T148	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T54	1		T37	1		T50	1
auto[0:134217727]	auto[1]	49	1			T194	1		T56	1		T245	1
auto[134217728:268435455]	auto[0]	42	1			T37	1		T55	1		T56	2
auto[134217728:268435455]	auto[1]	49	1			T15	1		T49	1		T38	1
auto[268435456:402653183]	auto[0]	43	1			T3	1		T36	1		T194	1
auto[268435456:402653183]	auto[1]	57	1			T148	1		T37	1		T51	1
auto[402653184:536870911]	auto[0]	40	1			T51	1		T245	1		T104	1
auto[402653184:536870911]	auto[1]	45	1			T3	1		T208	1		T252	1
auto[536870912:671088639]	auto[0]	49	1			T27	1		T54	1		T57	1
auto[536870912:671088639]	auto[1]	69	1			T15	1		T9	1		T49	1
auto[671088640:805306367]	auto[0]	47	1			T193	1		T55	1		T355	1
auto[671088640:805306367]	auto[1]	57	1			T140	1		T20	1		T66	1
auto[805306368:939524095]	auto[0]	48	1			T27	2		T193	1		T51	1
auto[805306368:939524095]	auto[1]	52	1			T27	1		T38	1		T60	1
auto[939524096:1073741823]	auto[0]	43	1			T35	1		T38	1		T351	1
auto[939524096:1073741823]	auto[1]	57	1			T2	1		T50	1		T56	4
auto[1073741824:1207959551]	auto[0]	42	1			T27	1		T271	1		T274	1
auto[1073741824:1207959551]	auto[1]	46	1			T78	1		T194	1		T244	1
auto[1207959552:1342177279]	auto[0]	46	1			T38	1		T56	2		T270	1
auto[1207959552:1342177279]	auto[1]	64	1			T26	1		T65	1		T148	1
auto[1342177280:1476395007]	auto[0]	52	1			T36	1		T60	1		T116	1
auto[1342177280:1476395007]	auto[1]	47	1			T6	1		T55	1		T56	1
auto[1476395008:1610612735]	auto[0]	42	1			T38	1		T56	1		T218	1
auto[1476395008:1610612735]	auto[1]	50	1			T27	1		T65	1		T51	1
auto[1610612736:1744830463]	auto[0]	57	1			T36	1		T56	1		T103	1
auto[1610612736:1744830463]	auto[1]	54	1			T65	1		T6	1		T194	1
auto[1744830464:1879048191]	auto[0]	43	1			T55	1		T56	1		T45	1
auto[1744830464:1879048191]	auto[1]	51	1			T5	1		T55	1		T115	1
auto[1879048192:2013265919]	auto[0]	49	1			T1	1		T2	1		T56	1
auto[1879048192:2013265919]	auto[1]	65	1			T38	1		T71	1		T46	1
auto[2013265920:2147483647]	auto[0]	53	1			T1	1		T36	1		T56	1
auto[2013265920:2147483647]	auto[1]	61	1			T115	1		T209	1		T246	1
auto[2147483648:2281701375]	auto[0]	49	1			T54	1		T55	2		T56	1
auto[2147483648:2281701375]	auto[1]	55	1			T5	1		T35	1		T55	1
auto[2281701376:2415919103]	auto[0]	46	1			T36	1		T56	1		T104	1
auto[2281701376:2415919103]	auto[1]	54	1			T1	1		T9	1		T139	1
auto[2415919104:2550136831]	auto[0]	51	1			T116	1		T171	1		T105	1
auto[2415919104:2550136831]	auto[1]	63	1			T206	1		T55	2		T76	1
auto[2550136832:2684354559]	auto[0]	59	1			T3	1		T57	1		T193	1
auto[2550136832:2684354559]	auto[1]	51	1			T35	1		T54	1		T139	1
auto[2684354560:2818572287]	auto[0]	54	1			T65	1		T57	1		T36	1
auto[2684354560:2818572287]	auto[1]	47	1			T65	1		T57	1		T55	1
auto[2818572288:2952790015]	auto[0]	64	1			T27	1		T54	1		T50	1
auto[2818572288:2952790015]	auto[1]	64	1			T27	1		T57	1		T55	1
auto[2952790016:3087007743]	auto[0]	56	1			T1	2		T218	1		T46	1
auto[2952790016:3087007743]	auto[1]	65	1			T57	1		T37	1		T55	1
auto[3087007744:3221225471]	auto[0]	40	1			T55	1		T351	1		T24	2
auto[3087007744:3221225471]	auto[1]	48	1			T9	1		T51	1		T218	1
auto[3221225472:3355443199]	auto[0]	52	1			T6	1		T56	1		T116	1
auto[3221225472:3355443199]	auto[1]	56	1			T2	1		T26	1		T60	1
auto[3355443200:3489660927]	auto[0]	51	1			T1	1		T3	1		T37	1
auto[3355443200:3489660927]	auto[1]	54	1			T15	1		T6	1		T56	2
auto[3489660928:3623878655]	auto[0]	54	1			T206	1		T61	1		T56	1
auto[3489660928:3623878655]	auto[1]	45	1			T56	1		T79	1		T75	1
auto[3623878656:3758096383]	auto[0]	59	1			T65	1		T148	1		T194	1
auto[3623878656:3758096383]	auto[1]	56	1			T206	1		T140	1		T201	1
auto[3758096384:3892314111]	auto[0]	43	1			T27	1		T54	1		T36	1
auto[3758096384:3892314111]	auto[1]	53	1			T37	1		T55	1		T56	1
auto[3892314112:4026531839]	auto[0]	46	1			T37	1		T38	1		T105	1
auto[3892314112:4026531839]	auto[1]	59	1			T35	1		T56	1		T116	1
auto[4026531840:4160749567]	auto[0]	58	1			T65	1		T56	1		T117	1
auto[4026531840:4160749567]	auto[1]	64	1			T1	1		T27	1		T139	1
auto[4160749568:4294967295]	auto[0]	43	1			T26	1		T56	1		T117	1
auto[4160749568:4294967295]	auto[1]	55	1			T148	1		T6	1		T55	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1539

1

T1

6

T3

3

T26

2

auto[1]

1800

1

T1

1

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T35	1		T9	1		T54	1
auto[134217728:268435455]	104	1			T3	1		T54	1		T65	1
auto[268435456:402653183]	93	1			T5	1		T27	1		T57	1
auto[402653184:536870911]	118	1			T194	1		T37	1		T55	1
auto[536870912:671088639]	102	1			T1	1		T2	1		T65	1
auto[671088640:805306367]	98	1			T57	1		T6	1		T140	1
auto[805306368:939524095]	95	1			T1	1		T35	1		T27	1
auto[939524096:1073741823]	109	1			T27	1		T9	1		T65	1
auto[1073741824:1207959551]	105	1			T140	1		T51	1		T38	1
auto[1207959552:1342177279]	102	1			T15	1		T116	1		T117	2
auto[1342177280:1476395007]	111	1			T1	1		T27	1		T49	1
auto[1476395008:1610612735]	105	1			T1	1		T15	1		T65	1
auto[1610612736:1744830463]	107	1			T27	1		T65	1		T36	1
auto[1744830464:1879048191]	107	1			T35	1		T54	1		T57	1
auto[1879048192:2013265919]	93	1			T1	3		T15	1		T26	1
auto[2013265920:2147483647]	117	1			T27	1		T20	1		T117	1
auto[2147483648:2281701375]	108	1			T26	1		T54	1		T50	1
auto[2281701376:2415919103]	107	1			T3	1		T57	1		T37	1
auto[2415919104:2550136831]	96	1			T38	1		T55	1		T56	1
auto[2550136832:2684354559]	106	1			T55	2		T56	3		T270	1
auto[2684354560:2818572287]	127	1			T2	1		T3	1		T27	1
auto[2818572288:2952790015]	107	1			T5	1		T27	1		T54	1
auto[2952790016:3087007743]	100	1			T3	1		T54	1		T55	3
auto[3087007744:3221225471]	108	1			T9	1		T57	1		T36	1
auto[3221225472:3355443199]	109	1			T65	1		T49	1		T139	1
auto[3355443200:3489660927]	120	1			T2	1		T35	1		T194	2
auto[3489660928:3623878655]	84	1			T56	1		T116	1		T74	1
auto[3623878656:3758096383]	102	1			T208	1		T37	1		T38	1
auto[3758096384:3892314111]	100	1			T36	1		T37	1		T60	1
auto[3892314112:4026531839]	110	1			T26	1		T6	1		T140	1
auto[4026531840:4160749567]	106	1			T27	1		T148	1		T55	1
auto[4160749568:4294967295]	95	1			T78	1		T37	1		T50	1