Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964

1

T1

7

T2

3

T3

4

auto[1]

295

1

T1

6

T2

4

T35

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T1	2		T2	1		T27	1
auto[134217728:268435455]	110	1			T36	1		T193	1		T55	1
auto[268435456:402653183]	105	1			T1	1		T3	1		T35	1
auto[402653184:536870911]	113	1			T35	1		T27	1		T148	1
auto[536870912:671088639]	107	1			T27	1		T49	2		T37	1
auto[671088640:805306367]	97	1			T139	1		T51	1		T38	1
auto[805306368:939524095]	109	1			T26	1		T35	1		T57	1
auto[939524096:1073741823]	109	1			T54	1		T36	1		T49	1
auto[1073741824:1207959551]	111	1			T1	2		T27	1		T57	1
auto[1207959552:1342177279]	95	1			T9	1		T57	1		T60	1
auto[1342177280:1476395007]	89	1			T1	2		T2	1		T139	1
auto[1476395008:1610612735]	101	1			T56	1		T209	1		T71	1
auto[1610612736:1744830463]	95	1			T2	2		T36	2		T139	1
auto[1744830464:1879048191]	106	1			T26	1		T65	1		T50	2
auto[1879048192:2013265919]	109	1			T2	2		T206	1		T38	1
auto[2013265920:2147483647]	83	1			T1	1		T5	1		T35	1
auto[2147483648:2281701375]	101	1			T37	1		T38	1		T271	1
auto[2281701376:2415919103]	115	1			T5	1		T139	1		T194	1
auto[2415919104:2550136831]	101	1			T1	1		T2	1		T15	1
auto[2550136832:2684354559]	104	1			T15	1		T65	1		T194	1
auto[2684354560:2818572287]	87	1			T65	1		T139	1		T38	2
auto[2818572288:2952790015]	97	1			T139	1		T37	1		T201	1
auto[2952790016:3087007743]	96	1			T1	1		T35	1		T54	1
auto[3087007744:3221225471]	93	1			T1	2		T35	1		T194	1
auto[3221225472:3355443199]	99	1			T115	1		T56	2		T274	1
auto[3355443200:3489660927]	105	1			T148	1		T55	2		T56	2
auto[3489660928:3623878655]	107	1			T3	1		T35	1		T27	1
auto[3623878656:3758096383]	96	1			T3	1		T35	1		T27	2
auto[3758096384:3892314111]	102	1			T3	1		T194	1		T56	1
auto[3892314112:4026531839]	109	1			T139	1		T56	2		T117	1
auto[4026531840:4160749567]	93	1			T1	1		T15	1		T26	1
auto[4160749568:4294967295]	108	1			T65	1		T139	2		T206	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T2	1		T27	1		T194	1
auto[0:134217727]	auto[1]	12	1			T1	2		T259	2		T433	1
auto[134217728:268435455]	auto[0]	99	1			T36	1		T193	1		T55	1
auto[134217728:268435455]	auto[1]	11	1			T248	1		T345	2		T253	1
auto[268435456:402653183]	auto[0]	92	1			T1	1		T3	1		T27	2
auto[268435456:402653183]	auto[1]	13	1			T35	1		T259	1		T262	1
auto[402653184:536870911]	auto[0]	102	1			T27	1		T148	1		T60	1
auto[402653184:536870911]	auto[1]	11	1			T35	1		T319	1		T371	1
auto[536870912:671088639]	auto[0]	97	1			T27	1		T49	2		T37	1
auto[536870912:671088639]	auto[1]	10	1			T259	1		T390	1		T436	1
auto[671088640:805306367]	auto[0]	89	1			T139	1		T51	1		T38	1
auto[671088640:805306367]	auto[1]	8	1			T259	1		T319	1		T390	1
auto[805306368:939524095]	auto[0]	95	1			T26	1		T35	1		T57	1
auto[805306368:939524095]	auto[1]	14	1			T140	1		T319	1		T365	1
auto[939524096:1073741823]	auto[0]	105	1			T54	1		T36	1		T49	1
auto[939524096:1073741823]	auto[1]	4	1			T352	1		T317	1		T443	1
auto[1073741824:1207959551]	auto[0]	104	1			T1	2		T27	1		T57	1
auto[1073741824:1207959551]	auto[1]	7	1			T262	1		T248	1		T265	1
auto[1207959552:1342177279]	auto[0]	89	1			T9	1		T57	1		T60	1
auto[1207959552:1342177279]	auto[1]	6	1			T275	1		T317	1		T279	1
auto[1342177280:1476395007]	auto[0]	81	1			T55	2		T56	2		T244	1
auto[1342177280:1476395007]	auto[1]	8	1			T1	2		T2	1		T139	1
auto[1476395008:1610612735]	auto[0]	92	1			T56	1		T209	1		T71	1
auto[1476395008:1610612735]	auto[1]	9	1			T397	1		T390	1		T433	1
auto[1610612736:1744830463]	auto[0]	86	1			T36	2		T56	1		T45	1
auto[1610612736:1744830463]	auto[1]	9	1			T2	2		T139	1		T259	1
auto[1744830464:1879048191]	auto[0]	99	1			T26	1		T65	1		T50	2
auto[1744830464:1879048191]	auto[1]	7	1			T259	1		T265	1		T253	1
auto[1879048192:2013265919]	auto[0]	99	1			T2	2		T206	1		T38	1
auto[1879048192:2013265919]	auto[1]	10	1			T259	1		T319	1		T390	1
auto[2013265920:2147483647]	auto[0]	79	1			T1	1		T5	1		T27	1
auto[2013265920:2147483647]	auto[1]	4	1			T35	1		T275	1		T243	1
auto[2147483648:2281701375]	auto[0]	88	1			T37	1		T38	1		T271	1
auto[2147483648:2281701375]	auto[1]	13	1			T275	1		T300	1		T436	2
auto[2281701376:2415919103]	auto[0]	100	1			T5	1		T194	1		T201	1
auto[2281701376:2415919103]	auto[1]	15	1			T139	1		T259	1		T275	1
auto[2415919104:2550136831]	auto[0]	90	1			T1	1		T15	1		T9	1
auto[2415919104:2550136831]	auto[1]	11	1			T2	1		T397	1		T259	1
auto[2550136832:2684354559]	auto[0]	91	1			T15	1		T65	1		T194	1
auto[2550136832:2684354559]	auto[1]	13	1			T259	1		T319	1		T371	1
auto[2684354560:2818572287]	auto[0]	80	1			T65	1		T38	2		T115	1
auto[2684354560:2818572287]	auto[1]	7	1			T139	1		T262	1		T265	1
auto[2818572288:2952790015]	auto[0]	86	1			T37	1		T201	1		T56	1
auto[2818572288:2952790015]	auto[1]	11	1			T139	1		T319	2		T432	1
auto[2952790016:3087007743]	auto[0]	90	1			T1	1		T35	1		T54	1
auto[2952790016:3087007743]	auto[1]	6	1			T262	1		T345	1		T243	1
auto[3087007744:3221225471]	auto[0]	84	1			T194	1		T193	1		T115	2
auto[3087007744:3221225471]	auto[1]	9	1			T1	2		T35	1		T319	2
auto[3221225472:3355443199]	auto[0]	93	1			T115	1		T56	2		T274	1
auto[3221225472:3355443199]	auto[1]	6	1			T319	1		T436	1		T253	1
auto[3355443200:3489660927]	auto[0]	96	1			T148	1		T55	2		T56	2
auto[3355443200:3489660927]	auto[1]	9	1			T259	2		T275	1		T248	1
auto[3489660928:3623878655]	auto[0]	100	1			T3	1		T35	1		T27	1
auto[3489660928:3623878655]	auto[1]	7	1			T259	1		T262	1		T436	1
auto[3623878656:3758096383]	auto[0]	88	1			T3	1		T35	1		T27	2
auto[3623878656:3758096383]	auto[1]	8	1			T275	1		T242	1		T440	3
auto[3758096384:3892314111]	auto[0]	97	1			T3	1		T194	1		T56	1
auto[3758096384:3892314111]	auto[1]	5	1			T319	1		T253	1		T255	1
auto[3892314112:4026531839]	auto[0]	101	1			T56	2		T117	1		T45	1
auto[3892314112:4026531839]	auto[1]	8	1			T139	1		T262	1		T345	1
auto[4026531840:4160749567]	auto[0]	85	1			T1	1		T15	1		T26	1
auto[4026531840:4160749567]	auto[1]	8	1			T285	1		T262	1		T390	1
auto[4160749568:4294967295]	auto[0]	92	1			T65	1		T206	1		T6	1
auto[4160749568:4294967295]	auto[1]	16	1			T139	2		T397	1		T259	1