Unified Coverage Report :: Group Instance : sealing_sw_binding_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1592

1

T1

6

T3

4

T26

2

auto[1]

1747

1

T1

1

T2

3

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T1	2		T57	1		T206	1
auto[134217728:268435455]	90	1			T1	1		T27	1		T49	1
auto[268435456:402653183]	101	1			T15	1		T26	1		T37	1
auto[402653184:536870911]	105	1			T1	1		T65	1		T57	1
auto[536870912:671088639]	100	1			T55	1		T56	3		T117	1
auto[671088640:805306367]	98	1			T27	1		T194	1		T50	1
auto[805306368:939524095]	128	1			T27	1		T54	1		T65	1
auto[939524096:1073741823]	95	1			T54	1		T36	1		T38	1
auto[1073741824:1207959551]	103	1			T49	1		T6	1		T55	1
auto[1207959552:1342177279]	112	1			T57	1		T37	1		T55	1
auto[1342177280:1476395007]	98	1			T35	1		T78	1		T148	1
auto[1476395008:1610612735]	109	1			T27	1		T9	1		T54	1
auto[1610612736:1744830463]	101	1			T57	1		T193	1		T38	1
auto[1744830464:1879048191]	108	1			T2	1		T3	1		T26	1
auto[1879048192:2013265919]	97	1			T36	1		T194	1		T37	1
auto[2013265920:2147483647]	108	1			T54	1		T37	1		T38	1
auto[2147483648:2281701375]	97	1			T27	1		T36	1		T139	1
auto[2281701376:2415919103]	107	1			T3	1		T15	1		T35	1
auto[2415919104:2550136831]	88	1			T5	1		T27	1		T65	1
auto[2550136832:2684354559]	99	1			T65	1		T61	1		T115	1
auto[2684354560:2818572287]	124	1			T3	1		T54	1		T6	1
auto[2818572288:2952790015]	97	1			T1	1		T5	1		T27	1
auto[2952790016:3087007743]	97	1			T38	1		T55	1		T116	1
auto[3087007744:3221225471]	113	1			T27	1		T54	1		T139	1
auto[3221225472:3355443199]	110	1			T1	1		T140	1		T37	1
auto[3355443200:3489660927]	97	1			T1	1		T26	1		T9	1
auto[3489660928:3623878655]	120	1			T27	1		T194	2		T208	1
auto[3623878656:3758096383]	104	1			T36	1		T49	1		T50	1
auto[3758096384:3892314111]	121	1			T2	1		T3	1		T15	1
auto[3892314112:4026531839]	94	1			T35	1		T65	1		T57	2
auto[4026531840:4160749567]	119	1			T2	1		T148	1		T201	1
auto[4160749568:4294967295]	103	1			T35	1		T65	1		T36	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T1	1		T56	2		T117	1
auto[0:134217727]	auto[1]	54	1			T1	1		T57	1		T206	1
auto[134217728:268435455]	auto[0]	44	1			T1	1		T27	1		T55	2
auto[134217728:268435455]	auto[1]	46	1			T49	1		T55	1		T115	1
auto[268435456:402653183]	auto[0]	47	1			T26	1		T56	2		T351	1
auto[268435456:402653183]	auto[1]	54	1			T15	1		T37	1		T46	1
auto[402653184:536870911]	auto[0]	52	1			T1	1		T65	1		T36	1
auto[402653184:536870911]	auto[1]	53	1			T57	1		T56	1		T209	1
auto[536870912:671088639]	auto[0]	51	1			T56	2		T117	1		T105	1
auto[536870912:671088639]	auto[1]	49	1			T55	1		T56	1		T205	1
auto[671088640:805306367]	auto[0]	41	1			T27	1		T50	1		T56	2
auto[671088640:805306367]	auto[1]	57	1			T194	1		T51	1		T116	1
auto[805306368:939524095]	auto[0]	64	1			T27	1		T65	1		T193	1
auto[805306368:939524095]	auto[1]	64	1			T54	1		T56	1		T117	1
auto[939524096:1073741823]	auto[0]	47	1			T54	1		T36	1		T38	1
auto[939524096:1073741823]	auto[1]	48	1			T115	1		T56	1		T76	1
auto[1073741824:1207959551]	auto[0]	46	1			T49	1		T56	2		T124	1
auto[1073741824:1207959551]	auto[1]	57	1			T6	1		T55	1		T56	2
auto[1207959552:1342177279]	auto[0]	45	1			T57	1		T56	2		T134	1
auto[1207959552:1342177279]	auto[1]	67	1			T37	1		T55	1		T56	1
auto[1342177280:1476395007]	auto[0]	40	1			T148	1		T206	1		T37	1
auto[1342177280:1476395007]	auto[1]	58	1			T35	1		T78	1		T38	1
auto[1476395008:1610612735]	auto[0]	58	1			T27	1		T54	1		T6	1
auto[1476395008:1610612735]	auto[1]	51	1			T9	1		T37	1		T55	1
auto[1610612736:1744830463]	auto[0]	51	1			T38	1		T56	2		T270	1
auto[1610612736:1744830463]	auto[1]	50	1			T57	1		T193	1		T55	1
auto[1744830464:1879048191]	auto[0]	59	1			T3	1		T27	1		T56	2
auto[1744830464:1879048191]	auto[1]	49	1			T2	1		T26	1		T6	1
auto[1879048192:2013265919]	auto[0]	52	1			T36	1		T201	1		T56	1
auto[1879048192:2013265919]	auto[1]	45	1			T194	1		T37	1		T56	2
auto[2013265920:2147483647]	auto[0]	46	1			T54	1		T37	1		T38	1
auto[2013265920:2147483647]	auto[1]	62	1			T55	1		T56	1		T45	1
auto[2147483648:2281701375]	auto[0]	44	1			T27	1		T36	1		T51	1
auto[2147483648:2281701375]	auto[1]	53	1			T139	1		T20	1		T116	1
auto[2281701376:2415919103]	auto[0]	53	1			T3	1		T35	1		T45	1
auto[2281701376:2415919103]	auto[1]	54	1			T15	1		T148	1		T140	1
auto[2415919104:2550136831]	auto[0]	37	1			T171	1		T252	1		T247	1
auto[2415919104:2550136831]	auto[1]	51	1			T5	1		T27	1		T65	1
auto[2550136832:2684354559]	auto[0]	48	1			T61	1		T56	1		T270	1
auto[2550136832:2684354559]	auto[1]	51	1			T65	1		T115	1		T56	1
auto[2684354560:2818572287]	auto[0]	60	1			T3	1		T54	1		T115	1
auto[2684354560:2818572287]	auto[1]	64	1			T6	1		T51	1		T56	2
auto[2818572288:2952790015]	auto[0]	51	1			T1	1		T65	1		T50	1
auto[2818572288:2952790015]	auto[1]	46	1			T5	1		T27	1		T9	1
auto[2952790016:3087007743]	auto[0]	41	1			T116	1		T218	1		T351	1
auto[2952790016:3087007743]	auto[1]	56	1			T38	1		T55	1		T218	1
auto[3087007744:3221225471]	auto[0]	53	1			T27	1		T54	1		T6	1
auto[3087007744:3221225471]	auto[1]	60	1			T139	1		T288	1		T305	1
auto[3221225472:3355443199]	auto[0]	63	1			T1	1		T37	1		T60	1
auto[3221225472:3355443199]	auto[1]	47	1			T140	1		T55	1		T56	2
auto[3355443200:3489660927]	auto[0]	54	1			T1	1		T26	1		T37	1
auto[3355443200:3489660927]	auto[1]	43	1			T9	1		T206	1		T55	1
auto[3489660928:3623878655]	auto[0]	47	1			T194	1		T38	1		T116	1
auto[3489660928:3623878655]	auto[1]	73	1			T27	1		T194	1		T208	1
auto[3623878656:3758096383]	auto[0]	52	1			T36	1		T49	1		T50	1
auto[3623878656:3758096383]	auto[1]	52	1			T56	2		T351	1		T23	1
auto[3758096384:3892314111]	auto[0]	58	1			T3	1		T140	1		T55	1
auto[3758096384:3892314111]	auto[1]	63	1			T2	1		T15	1		T140	1
auto[3892314112:4026531839]	auto[0]	46	1			T65	1		T57	2		T36	1
auto[3892314112:4026531839]	auto[1]	48	1			T35	1		T38	1		T56	1
auto[4026531840:4160749567]	auto[0]	58	1			T193	1		T56	2		T117	1
auto[4026531840:4160749567]	auto[1]	61	1			T2	1		T148	1		T201	1
auto[4160749568:4294967295]	auto[0]	42	1			T36	1		T193	1		T55	2
auto[4160749568:4294967295]	auto[1]	61	1			T35	1		T65	1		T139	1