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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4556 1 T1 8 T2 6 T3 6
auto[1] 2122 1 T1 6 T3 2 T15 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 208 1 T148 2 T37 2 T61 2
auto[134217728:268435455] 200 1 T1 2 T38 2 T56 2
auto[268435456:402653183] 206 1 T1 2 T3 4 T194 2
auto[402653184:536870911] 220 1 T35 2 T54 2 T139 2
auto[536870912:671088639] 192 1 T26 2 T36 2 T148 2
auto[671088640:805306367] 206 1 T2 2 T27 2 T78 2
auto[805306368:939524095] 208 1 T3 2 T27 2 T54 2
auto[939524096:1073741823] 212 1 T15 2 T35 2 T9 2
auto[1073741824:1207959551] 202 1 T35 2 T54 2 T6 2
auto[1207959552:1342177279] 216 1 T54 2 T6 2 T37 2
auto[1342177280:1476395007] 222 1 T15 2 T65 2 T37 2
auto[1476395008:1610612735] 210 1 T54 2 T206 2 T60 2
auto[1610612736:1744830463] 214 1 T65 2 T36 2 T194 2
auto[1744830464:1879048191] 184 1 T65 2 T57 2 T51 2
auto[1879048192:2013265919] 174 1 T57 2 T49 2 T193 2
auto[2013265920:2147483647] 218 1 T2 2 T27 2 T65 2
auto[2147483648:2281701375] 196 1 T65 2 T56 4 T186 2
auto[2281701376:2415919103] 214 1 T26 2 T36 2 T140 2
auto[2415919104:2550136831] 234 1 T35 2 T27 4 T36 2
auto[2550136832:2684354559] 176 1 T27 2 T206 2 T140 2
auto[2684354560:2818572287] 202 1 T49 2 T194 2 T201 2
auto[2818572288:2952790015] 208 1 T51 2 T55 4 T56 4
auto[2952790016:3087007743] 234 1 T1 4 T15 2 T65 2
auto[3087007744:3221225471] 218 1 T27 2 T194 2 T37 2
auto[3221225472:3355443199] 198 1 T1 2 T2 2 T3 2
auto[3355443200:3489660927] 220 1 T1 2 T26 2 T27 2
auto[3489660928:3623878655] 192 1 T49 2 T206 2 T55 2
auto[3623878656:3758096383] 220 1 T193 2 T56 8 T171 2
auto[3758096384:3892314111] 206 1 T1 2 T5 2 T6 2
auto[3892314112:4026531839] 236 1 T27 2 T9 2 T54 2
auto[4026531840:4160749567] 192 1 T5 2 T27 2 T36 2
auto[4160749568:4294967295] 240 1 T36 2 T139 2 T37 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 148 1 T37 2 T56 2 T116 2
auto[0:134217727] auto[1] 60 1 T148 2 T61 2 T439 2
auto[134217728:268435455] auto[0] 128 1 T1 2 T38 2 T56 2
auto[134217728:268435455] auto[1] 72 1 T271 2 T71 2 T72 2
auto[268435456:402653183] auto[0] 136 1 T1 2 T3 4 T201 2
auto[268435456:402653183] auto[1] 70 1 T194 2 T134 2 T267 2
auto[402653184:536870911] auto[0] 156 1 T35 2 T54 2 T139 2
auto[402653184:536870911] auto[1] 64 1 T6 2 T38 2 T246 2
auto[536870912:671088639] auto[0] 126 1 T26 2 T36 2 T194 2
auto[536870912:671088639] auto[1] 66 1 T148 2 T56 8 T271 2
auto[671088640:805306367] auto[0] 136 1 T2 2 T193 2 T56 2
auto[671088640:805306367] auto[1] 70 1 T27 2 T78 2 T55 2
auto[805306368:939524095] auto[0] 154 1 T3 2 T27 2 T54 2
auto[805306368:939524095] auto[1] 54 1 T56 4 T209 2 T124 2
auto[939524096:1073741823] auto[0] 128 1 T15 2 T35 2 T208 2
auto[939524096:1073741823] auto[1] 84 1 T9 2 T37 2 T50 2
auto[1073741824:1207959551] auto[0] 138 1 T35 2 T54 2 T194 2
auto[1073741824:1207959551] auto[1] 64 1 T6 2 T20 2 T56 2
auto[1207959552:1342177279] auto[0] 160 1 T54 2 T6 2 T37 2
auto[1207959552:1342177279] auto[1] 56 1 T7 2 T47 2 T135 2
auto[1342177280:1476395007] auto[0] 160 1 T15 2 T65 2 T37 2
auto[1342177280:1476395007] auto[1] 62 1 T50 2 T56 2 T218 2
auto[1476395008:1610612735] auto[0] 138 1 T206 2 T60 2 T55 4
auto[1476395008:1610612735] auto[1] 72 1 T54 2 T115 2 T48 4
auto[1610612736:1744830463] auto[0] 152 1 T65 2 T36 2 T194 2
auto[1610612736:1744830463] auto[1] 62 1 T351 2 T252 2 T100 2
auto[1744830464:1879048191] auto[0] 126 1 T65 2 T51 2 T56 4
auto[1744830464:1879048191] auto[1] 58 1 T57 2 T55 2 T56 4
auto[1879048192:2013265919] auto[0] 112 1 T57 2 T38 2 T56 2
auto[1879048192:2013265919] auto[1] 62 1 T49 2 T193 2 T271 2
auto[2013265920:2147483647] auto[0] 146 1 T2 2 T27 2 T65 2
auto[2013265920:2147483647] auto[1] 72 1 T56 2 T171 2 T72 2
auto[2147483648:2281701375] auto[0] 150 1 T65 2 T56 4 T186 2
auto[2147483648:2281701375] auto[1] 46 1 T45 2 T274 2 T252 2
auto[2281701376:2415919103] auto[0] 144 1 T140 2 T55 4 T117 2
auto[2281701376:2415919103] auto[1] 70 1 T26 2 T36 2 T105 2
auto[2415919104:2550136831] auto[0] 170 1 T27 2 T36 2 T139 2
auto[2415919104:2550136831] auto[1] 64 1 T35 2 T27 2 T55 2
auto[2550136832:2684354559] auto[0] 124 1 T206 2 T117 2 T46 2
auto[2550136832:2684354559] auto[1] 52 1 T27 2 T140 2 T55 2
auto[2684354560:2818572287] auto[0] 132 1 T49 2 T194 2 T201 2
auto[2684354560:2818572287] auto[1] 70 1 T56 2 T75 2 T347 2
auto[2818572288:2952790015] auto[0] 116 1 T51 2 T55 4 T56 2
auto[2818572288:2952790015] auto[1] 92 1 T56 2 T103 2 T24 4
auto[2952790016:3087007743] auto[0] 154 1 T115 2 T116 2 T117 2
auto[2952790016:3087007743] auto[1] 80 1 T1 4 T15 2 T65 2
auto[3087007744:3221225471] auto[0] 134 1 T194 2 T37 2 T56 6
auto[3087007744:3221225471] auto[1] 84 1 T27 2 T51 2 T115 2
auto[3221225472:3355443199] auto[0] 128 1 T1 2 T2 2 T6 2
auto[3221225472:3355443199] auto[1] 70 1 T3 2 T9 2 T270 2
auto[3355443200:3489660927] auto[0] 148 1 T27 2 T57 4 T55 4
auto[3355443200:3489660927] auto[1] 72 1 T1 2 T26 2 T57 2
auto[3489660928:3623878655] auto[0] 138 1 T49 2 T206 2 T56 2
auto[3489660928:3623878655] auto[1] 54 1 T55 2 T209 2 T46 2
auto[3623878656:3758096383] auto[0] 150 1 T193 2 T56 8 T171 2
auto[3623878656:3758096383] auto[1] 70 1 T252 2 T75 2 T134 2
auto[3758096384:3892314111] auto[0] 152 1 T1 2 T5 2 T6 2
auto[3758096384:3892314111] auto[1] 54 1 T55 2 T210 2 T205 2
auto[3892314112:4026531839] auto[0] 152 1 T27 2 T9 2 T54 2
auto[3892314112:4026531839] auto[1] 84 1 T65 2 T55 4 T56 2
auto[4026531840:4160749567] auto[0] 146 1 T5 2 T27 2 T36 2
auto[4026531840:4160749567] auto[1] 46 1 T56 2 T79 2 T428 2
auto[4160749568:4294967295] auto[0] 174 1 T36 2 T38 2 T56 2
auto[4160749568:4294967295] auto[1] 66 1 T139 2 T37 2 T72 2

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