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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 97.99 98.34 100.00 99.02 98.41 91.17


Total test records in report: 1090
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T156 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2663955123 Jul 23 06:30:09 PM PDT 24 Jul 23 06:30:27 PM PDT 24 210944691 ps
T1006 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1330039926 Jul 23 06:30:13 PM PDT 24 Jul 23 06:30:24 PM PDT 24 8549698 ps
T1007 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.761401427 Jul 23 06:30:22 PM PDT 24 Jul 23 06:30:32 PM PDT 24 25344794 ps
T1008 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2441225920 Jul 23 06:30:01 PM PDT 24 Jul 23 06:30:04 PM PDT 24 351737474 ps
T1009 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.97440028 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:11 PM PDT 24 15926615 ps
T1010 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3957365292 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:27 PM PDT 24 623102181 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4095740651 Jul 23 06:30:13 PM PDT 24 Jul 23 06:30:24 PM PDT 24 90222429 ps
T1012 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2933196140 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:11 PM PDT 24 54921558 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2071851161 Jul 23 06:30:19 PM PDT 24 Jul 23 06:30:29 PM PDT 24 24564782 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3424281025 Jul 23 06:30:03 PM PDT 24 Jul 23 06:30:13 PM PDT 24 194877173 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1212517852 Jul 23 06:30:01 PM PDT 24 Jul 23 06:30:04 PM PDT 24 283456310 ps
T1016 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.959738964 Jul 23 06:30:22 PM PDT 24 Jul 23 06:30:32 PM PDT 24 28162095 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3898722159 Jul 23 06:30:03 PM PDT 24 Jul 23 06:30:08 PM PDT 24 111517059 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2054064112 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:23 PM PDT 24 15089286 ps
T1019 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1505366225 Jul 23 06:30:26 PM PDT 24 Jul 23 06:30:34 PM PDT 24 9825630 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2912658699 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 144951188 ps
T158 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3264437083 Jul 23 06:30:08 PM PDT 24 Jul 23 06:30:22 PM PDT 24 103316309 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2826680520 Jul 23 06:30:03 PM PDT 24 Jul 23 06:30:10 PM PDT 24 504325648 ps
T1022 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4160020176 Jul 23 06:30:23 PM PDT 24 Jul 23 06:30:33 PM PDT 24 12459570 ps
T1023 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1303849832 Jul 23 06:30:05 PM PDT 24 Jul 23 06:30:15 PM PDT 24 163747179 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3622690871 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:22 PM PDT 24 187381144 ps
T1025 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.342888980 Jul 23 06:30:19 PM PDT 24 Jul 23 06:30:29 PM PDT 24 34619097 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2786723414 Jul 23 06:30:11 PM PDT 24 Jul 23 06:30:21 PM PDT 24 19194691 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1788320803 Jul 23 06:30:02 PM PDT 24 Jul 23 06:30:07 PM PDT 24 999449070 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1164502717 Jul 23 06:30:18 PM PDT 24 Jul 23 06:30:29 PM PDT 24 28137999 ps
T1029 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2599974685 Jul 23 06:30:18 PM PDT 24 Jul 23 06:30:28 PM PDT 24 13843314 ps
T1030 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3642690982 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:10 PM PDT 24 21295443 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3634864681 Jul 23 06:30:14 PM PDT 24 Jul 23 06:30:25 PM PDT 24 187225009 ps
T1032 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2695391880 Jul 23 06:30:09 PM PDT 24 Jul 23 06:30:19 PM PDT 24 93513354 ps
T1033 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1791764896 Jul 23 06:30:16 PM PDT 24 Jul 23 06:30:26 PM PDT 24 12344144 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3681119149 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:24 PM PDT 24 62203772 ps
T1035 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.916686105 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:23 PM PDT 24 209092281 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4094194993 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:11 PM PDT 24 26266045 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3913377843 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:11 PM PDT 24 98576309 ps
T1038 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1764782739 Jul 23 06:30:18 PM PDT 24 Jul 23 06:30:28 PM PDT 24 9833792 ps
T1039 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1712630992 Jul 23 06:30:23 PM PDT 24 Jul 23 06:30:32 PM PDT 24 46008514 ps
T1040 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.829891051 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 191858863 ps
T1041 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2293469927 Jul 23 06:30:03 PM PDT 24 Jul 23 06:30:09 PM PDT 24 75545466 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1260635570 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:22 PM PDT 24 1552458771 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.820885149 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:13 PM PDT 24 112420600 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3435591471 Jul 23 06:29:58 PM PDT 24 Jul 23 06:30:01 PM PDT 24 56330789 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3439541442 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:12 PM PDT 24 531597596 ps
T1046 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3431413617 Jul 23 06:30:18 PM PDT 24 Jul 23 06:30:28 PM PDT 24 35948358 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.213252516 Jul 23 06:30:00 PM PDT 24 Jul 23 06:30:10 PM PDT 24 314710371 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.465415976 Jul 23 06:30:05 PM PDT 24 Jul 23 06:30:14 PM PDT 24 59671852 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1310424885 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:22 PM PDT 24 29714194 ps
T1050 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1472217677 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:12 PM PDT 24 138775376 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3720044303 Jul 23 06:29:59 PM PDT 24 Jul 23 06:30:01 PM PDT 24 30006813 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2845184295 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:22 PM PDT 24 48642954 ps
T1053 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2895026070 Jul 23 06:30:14 PM PDT 24 Jul 23 06:30:25 PM PDT 24 79287741 ps
T1054 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1097122150 Jul 23 06:30:02 PM PDT 24 Jul 23 06:30:06 PM PDT 24 25768411 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.717700030 Jul 23 06:30:05 PM PDT 24 Jul 23 06:30:14 PM PDT 24 25034626 ps
T167 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3605785152 Jul 23 06:29:58 PM PDT 24 Jul 23 06:30:03 PM PDT 24 349062769 ps
T1056 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.570787880 Jul 23 06:30:18 PM PDT 24 Jul 23 06:30:29 PM PDT 24 22331073 ps
T1057 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3102787010 Jul 23 06:30:09 PM PDT 24 Jul 23 06:30:20 PM PDT 24 65344138 ps
T1058 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1738405594 Jul 23 06:30:20 PM PDT 24 Jul 23 06:30:30 PM PDT 24 176621944 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1717690351 Jul 23 06:30:14 PM PDT 24 Jul 23 06:30:26 PM PDT 24 111894415 ps
T1060 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3838028454 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:24 PM PDT 24 323134273 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.175092798 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 17118067 ps
T1062 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2357536463 Jul 23 06:30:19 PM PDT 24 Jul 23 06:30:30 PM PDT 24 26608057 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3299245554 Jul 23 06:30:20 PM PDT 24 Jul 23 06:30:34 PM PDT 24 363958784 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1836503971 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:27 PM PDT 24 3237823004 ps
T1065 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2732805556 Jul 23 06:30:11 PM PDT 24 Jul 23 06:30:22 PM PDT 24 119078925 ps
T1066 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3222285296 Jul 23 06:30:15 PM PDT 24 Jul 23 06:30:27 PM PDT 24 136624764 ps
T159 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2765234014 Jul 23 06:30:08 PM PDT 24 Jul 23 06:30:21 PM PDT 24 390480999 ps
T1067 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3387240615 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:13 PM PDT 24 171322315 ps
T1068 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4114973362 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:18 PM PDT 24 193610296 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1892664196 Jul 23 06:30:08 PM PDT 24 Jul 23 06:30:19 PM PDT 24 261700549 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3153774437 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 154479192 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1839868415 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 81039714 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.446891837 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:18 PM PDT 24 365796360 ps
T168 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3529903188 Jul 23 06:30:16 PM PDT 24 Jul 23 06:30:32 PM PDT 24 405991932 ps
T1073 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.760669681 Jul 23 06:30:06 PM PDT 24 Jul 23 06:30:14 PM PDT 24 61606612 ps
T1074 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3764926147 Jul 23 06:30:12 PM PDT 24 Jul 23 06:30:23 PM PDT 24 160283728 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.311009847 Jul 23 06:30:06 PM PDT 24 Jul 23 06:30:15 PM PDT 24 24718026 ps
T1076 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2525867659 Jul 23 06:29:59 PM PDT 24 Jul 23 06:30:10 PM PDT 24 367437247 ps
T1077 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3489717968 Jul 23 06:30:06 PM PDT 24 Jul 23 06:30:37 PM PDT 24 894208172 ps
T1078 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1124294373 Jul 23 06:30:08 PM PDT 24 Jul 23 06:30:20 PM PDT 24 322907551 ps
T1079 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.637450106 Jul 23 06:30:00 PM PDT 24 Jul 23 06:30:05 PM PDT 24 2337718434 ps
T1080 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2896935596 Jul 23 06:30:24 PM PDT 24 Jul 23 06:30:33 PM PDT 24 12417637 ps
T1081 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1960989413 Jul 23 06:30:11 PM PDT 24 Jul 23 06:30:25 PM PDT 24 517167523 ps
T1082 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1610721204 Jul 23 06:30:06 PM PDT 24 Jul 23 06:30:25 PM PDT 24 1499769095 ps
T1083 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.294981048 Jul 23 06:30:13 PM PDT 24 Jul 23 06:30:23 PM PDT 24 54880558 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3011289545 Jul 23 06:30:01 PM PDT 24 Jul 23 06:30:03 PM PDT 24 47467990 ps
T1085 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4124356460 Jul 23 06:30:19 PM PDT 24 Jul 23 06:30:30 PM PDT 24 13935247 ps
T1086 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.6936727 Jul 23 06:30:04 PM PDT 24 Jul 23 06:30:42 PM PDT 24 5357776038 ps
T1087 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2129126875 Jul 23 06:30:17 PM PDT 24 Jul 23 06:30:30 PM PDT 24 113646951 ps
T1088 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2021731257 Jul 23 06:30:09 PM PDT 24 Jul 23 06:30:26 PM PDT 24 1254977036 ps
T1089 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.348148373 Jul 23 06:30:07 PM PDT 24 Jul 23 06:30:16 PM PDT 24 93672649 ps
T1090 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.478547630 Jul 23 06:29:58 PM PDT 24 Jul 23 06:30:03 PM PDT 24 91056465 ps

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.511311042
Short name T15
Test name
Test status
Simulation time 137215391 ps
CPU time 8.73 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:57 PM PDT 24
Peak memory 222348 kb
Host smart-d07d9f31-9cff-4abf-a586-8913adebcb94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511311042 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.511311042
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3555165010
Short name T56
Test name
Test status
Simulation time 2843957186 ps
CPU time 53.02 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 215508 kb
Host smart-6dab071e-88a1-4cb6-b699-d903aedc5754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555165010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3555165010
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3915607353
Short name T9
Test name
Test status
Simulation time 246606143 ps
CPU time 3.53 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 220424 kb
Host smart-433e5953-3bc1-4a3d-8d61-7061f1785ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915607353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3915607353
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3302975547
Short name T82
Test name
Test status
Simulation time 13012235984 ps
CPU time 242.67 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:49:05 PM PDT 24
Peak memory 222332 kb
Host smart-bf34e9c0-9584-45a1-8e60-a42632bdee71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302975547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3302975547
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.562670246
Short name T11
Test name
Test status
Simulation time 1128180930 ps
CPU time 12.39 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:46 PM PDT 24
Peak memory 230716 kb
Host smart-ba73fa88-7712-4437-aa17-5231f4814dbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562670246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.562670246
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2885154006
Short name T46
Test name
Test status
Simulation time 1331091140 ps
CPU time 15.76 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:59 PM PDT 24
Peak memory 222332 kb
Host smart-36ff3854-d237-4455-a05f-6d416c29e85d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885154006 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2885154006
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3536425934
Short name T55
Test name
Test status
Simulation time 649223919 ps
CPU time 24.13 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 222212 kb
Host smart-9ad12942-be4c-4aed-923c-c423f46a912a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536425934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3536425934
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.733546808
Short name T48
Test name
Test status
Simulation time 5030903983 ps
CPU time 37.91 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 216224 kb
Host smart-01ae9641-2d64-4a82-8303-6cfd481287e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733546808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.733546808
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4133804315
Short name T3
Test name
Test status
Simulation time 50360534 ps
CPU time 2.83 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 214124 kb
Host smart-7749e3f8-cf45-4087-b533-29685f5134f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133804315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4133804315
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.449940887
Short name T259
Test name
Test status
Simulation time 812385906 ps
CPU time 8.89 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 214068 kb
Host smart-39839e67-3da5-4fa0-b910-1308787627dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449940887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.449940887
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.582964194
Short name T126
Test name
Test status
Simulation time 474624206 ps
CPU time 4.55 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 214688 kb
Host smart-852e5a1c-1953-49f5-b224-e46fba4b0a3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582964194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.582964194
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.521151334
Short name T27
Test name
Test status
Simulation time 194797837 ps
CPU time 11.01 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:28 PM PDT 24
Peak memory 222212 kb
Host smart-e72549b0-aa0f-4f79-9621-0044aa83a80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521151334 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.521151334
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1482776560
Short name T253
Test name
Test status
Simulation time 2049334271 ps
CPU time 105.7 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:46:33 PM PDT 24
Peak memory 214772 kb
Host smart-4d6c0519-7819-4197-9cde-8e39943e9315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482776560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1482776560
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1399327465
Short name T24
Test name
Test status
Simulation time 5229387079 ps
CPU time 63.12 seconds
Started Jul 23 05:45:06 PM PDT 24
Finished Jul 23 05:46:10 PM PDT 24
Peak memory 222352 kb
Host smart-78d0931c-e417-43df-91dc-e2d7f7c961f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399327465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1399327465
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2506051276
Short name T139
Test name
Test status
Simulation time 1846703443 ps
CPU time 46.86 seconds
Started Jul 23 05:46:59 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 222224 kb
Host smart-35008a8a-0cfc-430e-9729-d1b3e1f8be12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506051276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2506051276
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3526540982
Short name T319
Test name
Test status
Simulation time 325202284 ps
CPU time 15.76 seconds
Started Jul 23 05:45:24 PM PDT 24
Finished Jul 23 05:45:41 PM PDT 24
Peak memory 215224 kb
Host smart-87e2fc4d-7215-4dd8-975a-b879f1ffe98b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526540982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3526540982
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3211706529
Short name T34
Test name
Test status
Simulation time 199634656 ps
CPU time 2.4 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 209800 kb
Host smart-ce23abe4-6f87-4a10-8a2b-4477ff839c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211706529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3211706529
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.513578101
Short name T1
Test name
Test status
Simulation time 275224599 ps
CPU time 13.68 seconds
Started Jul 23 05:46:31 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 214828 kb
Host smart-2cff8f00-fe0c-4523-b549-48437cde1a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513578101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.513578101
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.674783046
Short name T938
Test name
Test status
Simulation time 957516953 ps
CPU time 4.51 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 214688 kb
Host smart-f0d70962-5b34-414a-97a2-a0ff82ed4a3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674783046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.674783046
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.541120495
Short name T275
Test name
Test status
Simulation time 140742448 ps
CPU time 7.67 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 222180 kb
Host smart-7ae05017-a1b4-4634-bb35-2b94039f188d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541120495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.541120495
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2464820798
Short name T154
Test name
Test status
Simulation time 288975943 ps
CPU time 3.24 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214432 kb
Host smart-e4cac230-5c9d-4a3a-a6b9-3de7da5a52a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464820798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2464820798
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3997405077
Short name T134
Test name
Test status
Simulation time 841989337 ps
CPU time 17.03 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:19 PM PDT 24
Peak memory 222352 kb
Host smart-53e5402b-343e-48ec-afef-70d2944e8ab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997405077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3997405077
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1472212328
Short name T171
Test name
Test status
Simulation time 669939881 ps
CPU time 3.86 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:30 PM PDT 24
Peak memory 217896 kb
Host smart-f8d35420-e8e5-4fbf-979b-5d6fb0549dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472212328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1472212328
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.270215920
Short name T21
Test name
Test status
Simulation time 96012480 ps
CPU time 1.63 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 217080 kb
Host smart-5e974a04-1ca2-4505-ab63-5a697376801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270215920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.270215920
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.682711251
Short name T365
Test name
Test status
Simulation time 1123078727 ps
CPU time 14.83 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 215408 kb
Host smart-6714cdd6-bab1-4e68-b160-cf63385b1089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682711251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.682711251
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1540218143
Short name T223
Test name
Test status
Simulation time 864170145 ps
CPU time 9.16 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 209472 kb
Host smart-40cddaff-005c-45b8-ae46-f9b7446eb3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540218143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1540218143
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.236345288
Short name T501
Test name
Test status
Simulation time 230451790 ps
CPU time 4 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:46 PM PDT 24
Peak memory 222088 kb
Host smart-3c5a5ed8-5282-45f9-848c-64150815d436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236345288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.236345288
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4282135583
Short name T36
Test name
Test status
Simulation time 266535095 ps
CPU time 6.1 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:07 PM PDT 24
Peak memory 215176 kb
Host smart-35c1b358-cff2-49bd-93ae-3376bfd9519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282135583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4282135583
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3481577933
Short name T84
Test name
Test status
Simulation time 1024695262 ps
CPU time 38.39 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 215488 kb
Host smart-f8e8e3ad-2eec-4d5c-8ea7-51d6bd7aa211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481577933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3481577933
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3143110956
Short name T402
Test name
Test status
Simulation time 683516597 ps
CPU time 7.83 seconds
Started Jul 23 05:44:34 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 214108 kb
Host smart-bbc27f6a-d24e-44be-88f5-74bd90742a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143110956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3143110956
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1544868279
Short name T262
Test name
Test status
Simulation time 127042905 ps
CPU time 7.05 seconds
Started Jul 23 05:45:15 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 214156 kb
Host smart-aede20c9-7773-4af7-b29e-c9024aa27b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544868279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1544868279
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2201580115
Short name T105
Test name
Test status
Simulation time 196226554 ps
CPU time 3.33 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 214084 kb
Host smart-9a898ded-a953-476b-af35-ff2b7e92a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201580115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2201580115
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3246417459
Short name T248
Test name
Test status
Simulation time 83486847 ps
CPU time 4.88 seconds
Started Jul 23 05:44:55 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 214876 kb
Host smart-8d102df1-3fb1-4a13-a669-e83e18b2752f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246417459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3246417459
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.282477554
Short name T23
Test name
Test status
Simulation time 120766197 ps
CPU time 4.06 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 220892 kb
Host smart-3e76a367-6a12-4185-8d13-75c67e3e387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282477554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.282477554
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4058358652
Short name T233
Test name
Test status
Simulation time 9481273329 ps
CPU time 59.32 seconds
Started Jul 23 05:46:36 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 216072 kb
Host smart-cc5d0d42-e5b8-4768-89db-8a3e752b27a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058358652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4058358652
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1893774533
Short name T445
Test name
Test status
Simulation time 15867947 ps
CPU time 0.81 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:19 PM PDT 24
Peak memory 205788 kb
Host smart-e029c0e9-552b-4bc5-9fa3-5da4e2a117cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893774533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1893774533
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1095436672
Short name T288
Test name
Test status
Simulation time 242900090 ps
CPU time 3.06 seconds
Started Jul 23 05:46:18 PM PDT 24
Finished Jul 23 05:46:22 PM PDT 24
Peak memory 219500 kb
Host smart-a83bf99b-0058-43f4-913e-0da3ed011e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095436672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1095436672
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1658540732
Short name T254
Test name
Test status
Simulation time 185604343 ps
CPU time 9.36 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 214612 kb
Host smart-a964fbd2-e2ce-4e6c-aa0f-d8bc17508b01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658540732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1658540732
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3109130112
Short name T140
Test name
Test status
Simulation time 32123861 ps
CPU time 2.67 seconds
Started Jul 23 05:47:33 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 214808 kb
Host smart-322a0674-d517-43d7-83aa-5559a38e3d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109130112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3109130112
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1864223841
Short name T47
Test name
Test status
Simulation time 1041777420 ps
CPU time 17.45 seconds
Started Jul 23 05:47:41 PM PDT 24
Finished Jul 23 05:48:04 PM PDT 24
Peak memory 221152 kb
Host smart-d1a0903b-a1f6-493c-bb0b-99a18f31616e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864223841 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1864223841
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1010020375
Short name T52
Test name
Test status
Simulation time 656262610 ps
CPU time 25.23 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 222336 kb
Host smart-a3059bba-df35-40ec-a648-d4d96bf6b490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010020375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1010020375
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2693240651
Short name T357
Test name
Test status
Simulation time 148303982 ps
CPU time 4.06 seconds
Started Jul 23 05:45:01 PM PDT 24
Finished Jul 23 05:45:07 PM PDT 24
Peak memory 213996 kb
Host smart-29c899d1-612b-47f1-8d3f-1e8a393b84b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693240651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2693240651
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3264437083
Short name T158
Test name
Test status
Simulation time 103316309 ps
CPU time 4.7 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 214420 kb
Host smart-53e13b0c-af7a-4287-8252-6409b7830011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264437083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3264437083
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3529903188
Short name T168
Test name
Test status
Simulation time 405991932 ps
CPU time 5.99 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 214540 kb
Host smart-f456cae6-7a75-46bf-b38b-f7ef3a9e9f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529903188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3529903188
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1348637106
Short name T79
Test name
Test status
Simulation time 327186406 ps
CPU time 3.01 seconds
Started Jul 23 05:45:42 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 217104 kb
Host smart-526adb3e-d149-4569-b8cd-a6c17634ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348637106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1348637106
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1052490181
Short name T228
Test name
Test status
Simulation time 41088155479 ps
CPU time 107.46 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 222324 kb
Host smart-801bb034-f14a-4dbb-8e3d-6aaa7f891b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052490181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1052490181
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3741960573
Short name T106
Test name
Test status
Simulation time 60092800 ps
CPU time 2.27 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 220888 kb
Host smart-9a9ea105-c389-4094-a521-0d2d18ced814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741960573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3741960573
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1979023819
Short name T117
Test name
Test status
Simulation time 127915387 ps
CPU time 3.22 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 214136 kb
Host smart-23692090-ace1-4e50-8b70-e8553c577183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979023819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1979023819
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3862530090
Short name T390
Test name
Test status
Simulation time 289163729 ps
CPU time 9.34 seconds
Started Jul 23 05:45:05 PM PDT 24
Finished Jul 23 05:45:15 PM PDT 24
Peak memory 215304 kb
Host smart-fea03dc8-4993-43f7-b19e-166c4934f6d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862530090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3862530090
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2255337245
Short name T243
Test name
Test status
Simulation time 95153985 ps
CPU time 5.31 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:22 PM PDT 24
Peak memory 214040 kb
Host smart-dcf83894-9471-43c7-91b3-73557e275411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255337245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2255337245
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2472728964
Short name T312
Test name
Test status
Simulation time 254429430 ps
CPU time 5.19 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 220468 kb
Host smart-14a5af7e-ea21-479d-8189-1879f86ca027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472728964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2472728964
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.269772992
Short name T64
Test name
Test status
Simulation time 2443670972 ps
CPU time 35.29 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 214700 kb
Host smart-52af3fe1-185f-45a9-822b-a3ac91a435f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269772992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.269772992
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.579893017
Short name T317
Test name
Test status
Simulation time 481847445 ps
CPU time 7.24 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:26 PM PDT 24
Peak memory 215284 kb
Host smart-5c077934-e353-4203-848e-4be50af3e812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579893017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.579893017
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2987191125
Short name T404
Test name
Test status
Simulation time 216545842 ps
CPU time 5.88 seconds
Started Jul 23 05:48:24 PM PDT 24
Finished Jul 23 05:48:33 PM PDT 24
Peak memory 214068 kb
Host smart-4b17a409-c33e-4ecc-9b70-82721c05b8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987191125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2987191125
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1700497441
Short name T19
Test name
Test status
Simulation time 119148483 ps
CPU time 2.57 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:37 PM PDT 24
Peak memory 216236 kb
Host smart-0d06f8d0-bd14-48cd-92e4-645035e721d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700497441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1700497441
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.105658492
Short name T42
Test name
Test status
Simulation time 61748409 ps
CPU time 1.93 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 209844 kb
Host smart-e728c762-109a-44e5-a409-e876591816c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105658492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.105658492
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3605785152
Short name T167
Test name
Test status
Simulation time 349062769 ps
CPU time 4.16 seconds
Started Jul 23 06:29:58 PM PDT 24
Finished Jul 23 06:30:03 PM PDT 24
Peak memory 214312 kb
Host smart-cb098d04-b343-421e-96b5-518742b33718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605785152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3605785152
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2765234014
Short name T159
Test name
Test status
Simulation time 390480999 ps
CPU time 5.26 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 206244 kb
Host smart-d34a3772-56d2-45a2-9c0b-a59ccfcd5e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765234014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2765234014
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2407859101
Short name T58
Test name
Test status
Simulation time 135133098 ps
CPU time 4.27 seconds
Started Jul 23 05:48:30 PM PDT 24
Finished Jul 23 05:48:39 PM PDT 24
Peak memory 217588 kb
Host smart-387d27b8-5f65-4d62-be07-d6b61987c6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407859101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2407859101
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4271504874
Short name T222
Test name
Test status
Simulation time 663629601 ps
CPU time 33.18 seconds
Started Jul 23 05:45:06 PM PDT 24
Finished Jul 23 05:45:41 PM PDT 24
Peak memory 215520 kb
Host smart-c13c5e91-a18c-47bf-9e57-477598e6b952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271504874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4271504874
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3227387845
Short name T176
Test name
Test status
Simulation time 1595327511 ps
CPU time 21.79 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 222352 kb
Host smart-599d9e71-a8c1-470d-82dc-9bc03b06431f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227387845 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3227387845
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4246181539
Short name T107
Test name
Test status
Simulation time 115703585 ps
CPU time 5.08 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 214232 kb
Host smart-905549fa-679c-496b-aa6a-9055d3ebf474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246181539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4246181539
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.286499506
Short name T213
Test name
Test status
Simulation time 178342839 ps
CPU time 3.67 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 208288 kb
Host smart-848749b2-1ca6-472b-b41e-38af19363df0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286499506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.286499506
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2249766577
Short name T87
Test name
Test status
Simulation time 5983246563 ps
CPU time 53.8 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 216916 kb
Host smart-3916bb24-2418-4c06-8a69-aeb786ab17db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249766577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2249766577
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.579752284
Short name T151
Test name
Test status
Simulation time 61558749 ps
CPU time 2.72 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214464 kb
Host smart-4a5c8754-c238-4cf5-ae6e-f2d912be6c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579752284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.579752284
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2978169208
Short name T78
Test name
Test status
Simulation time 68828205 ps
CPU time 2.92 seconds
Started Jul 23 05:45:04 PM PDT 24
Finished Jul 23 05:45:07 PM PDT 24
Peak memory 217204 kb
Host smart-ebf69bfc-a7e8-40b1-8a08-0a29b414d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978169208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2978169208
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.339442650
Short name T173
Test name
Test status
Simulation time 92869051 ps
CPU time 4.55 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 217332 kb
Host smart-404b5c1e-cdac-4f1e-b941-d6d2e38d9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339442650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.339442650
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.564002806
Short name T35
Test name
Test status
Simulation time 1043144465 ps
CPU time 4.77 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:32 PM PDT 24
Peak memory 214032 kb
Host smart-7f0f528f-6025-4f0b-9387-4bfc6258682d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564002806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.564002806
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1471693980
Short name T591
Test name
Test status
Simulation time 323851908 ps
CPU time 3.56 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:04 PM PDT 24
Peak memory 210752 kb
Host smart-01ed1d9e-27e2-40bc-981a-a81238073094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471693980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1471693980
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1970032077
Short name T72
Test name
Test status
Simulation time 120107521 ps
CPU time 5.01 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:21 PM PDT 24
Peak memory 214040 kb
Host smart-c176f2df-853c-46a8-927a-ab499a06532c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970032077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1970032077
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.981334985
Short name T240
Test name
Test status
Simulation time 495095539 ps
CPU time 21.11 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 221188 kb
Host smart-345eb260-d632-43cf-8e85-8cda575c950d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981334985 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.981334985
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2154258100
Short name T297
Test name
Test status
Simulation time 581972554 ps
CPU time 16.43 seconds
Started Jul 23 05:46:24 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 214812 kb
Host smart-125faa1a-6e75-433c-9b7e-16e293160322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154258100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2154258100
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1214303953
Short name T285
Test name
Test status
Simulation time 595321134 ps
CPU time 4.6 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 215192 kb
Host smart-1bc23a3c-b6f0-4110-ab26-a0599fc9763b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214303953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1214303953
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2694658996
Short name T360
Test name
Test status
Simulation time 90850285 ps
CPU time 3.9 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 222136 kb
Host smart-dffd144d-f4e9-47f5-b823-2d0eafadc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694658996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2694658996
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3817305122
Short name T290
Test name
Test status
Simulation time 53035783 ps
CPU time 2.25 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:41 PM PDT 24
Peak memory 214016 kb
Host smart-edb18d92-54b4-4709-9728-27025f2c00a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817305122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3817305122
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3774295878
Short name T149
Test name
Test status
Simulation time 403790196 ps
CPU time 7.15 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:08 PM PDT 24
Peak memory 214428 kb
Host smart-7701a20c-d73f-46d1-acb9-cc8eb8684001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774295878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3774295878
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2004096267
Short name T157
Test name
Test status
Simulation time 186627894 ps
CPU time 4.25 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 206632 kb
Host smart-85a9303c-3acf-4536-9173-f19316d2579c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004096267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2004096267
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3981317923
Short name T12
Test name
Test status
Simulation time 477728332 ps
CPU time 6.77 seconds
Started Jul 23 05:44:14 PM PDT 24
Finished Jul 23 05:44:22 PM PDT 24
Peak memory 236956 kb
Host smart-9afab521-755a-49fc-af99-c2e1a2adeae0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981317923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3981317923
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1649878592
Short name T174
Test name
Test status
Simulation time 385046943 ps
CPU time 3.92 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 215296 kb
Host smart-c3d4268d-691b-4afc-9c23-3ec4c373a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649878592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1649878592
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1014192536
Short name T172
Test name
Test status
Simulation time 63052338 ps
CPU time 2.89 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 212976 kb
Host smart-7136403a-71fc-4821-a02c-4c64561a0745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014192536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1014192536
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3701645590
Short name T186
Test name
Test status
Simulation time 400571157 ps
CPU time 5.79 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 218012 kb
Host smart-137697bb-348e-4137-9b5f-1728c4c5cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701645590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3701645590
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4212131396
Short name T295
Test name
Test status
Simulation time 375576936 ps
CPU time 4.08 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 208308 kb
Host smart-dbffdcdc-d6a5-4b90-8a3a-1cf62df03c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212131396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4212131396
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1195743095
Short name T368
Test name
Test status
Simulation time 192782033 ps
CPU time 5.45 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 208348 kb
Host smart-4fc5a5e0-f2ca-46fa-8796-8db71b98a443
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195743095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1195743095
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2556972167
Short name T232
Test name
Test status
Simulation time 79522266 ps
CPU time 3.16 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 222228 kb
Host smart-8daf3f0a-40dd-40cc-8a4b-0cd4373c6faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556972167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2556972167
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4208329042
Short name T49
Test name
Test status
Simulation time 385667089 ps
CPU time 3.11 seconds
Started Jul 23 05:45:06 PM PDT 24
Finished Jul 23 05:45:11 PM PDT 24
Peak memory 209180 kb
Host smart-40eda87a-1d0c-475a-b8a6-35ae5a6f6edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208329042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4208329042
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.405426106
Short name T330
Test name
Test status
Simulation time 1714756123 ps
CPU time 16.01 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 222376 kb
Host smart-24a418c0-861a-439c-98c9-c75120b9b445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405426106 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.405426106
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_random.376794633
Short name T367
Test name
Test status
Simulation time 386890455 ps
CPU time 6.56 seconds
Started Jul 23 05:45:22 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 218176 kb
Host smart-bc5072e1-ea7c-4d44-aecd-493a0b3e3bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376794633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.376794633
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3330744061
Short name T797
Test name
Test status
Simulation time 28543460 ps
CPU time 2.18 seconds
Started Jul 23 05:45:21 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 214056 kb
Host smart-df22e4e7-d308-4446-9c42-c4c11178ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330744061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3330744061
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3855858734
Short name T191
Test name
Test status
Simulation time 1336132550 ps
CPU time 45.86 seconds
Started Jul 23 05:45:25 PM PDT 24
Finished Jul 23 05:46:12 PM PDT 24
Peak memory 222328 kb
Host smart-5077afff-5921-4c7c-ae5c-2c184cfe544d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855858734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3855858734
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.717119304
Short name T85
Test name
Test status
Simulation time 1263102317 ps
CPU time 29.26 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 219400 kb
Host smart-d0cb9df5-aaea-4f2a-8671-e749a5457b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717119304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.717119304
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.352127923
Short name T273
Test name
Test status
Simulation time 113863905 ps
CPU time 6.56 seconds
Started Jul 23 05:44:29 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 215444 kb
Host smart-441457d2-46a7-40b1-b5dd-09f4ee5f1e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352127923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.352127923
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_random.4076305917
Short name T346
Test name
Test status
Simulation time 205987821 ps
CPU time 3.34 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 218056 kb
Host smart-be28a4db-b442-4ea8-84fe-30847c21a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076305917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4076305917
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1504558246
Short name T197
Test name
Test status
Simulation time 84290986 ps
CPU time 3.58 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 208648 kb
Host smart-fb565d5c-1f70-4af1-8f49-d1845ea7f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504558246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1504558246
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3041141389
Short name T241
Test name
Test status
Simulation time 4271423909 ps
CPU time 35.91 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 208544 kb
Host smart-692c7bb7-5a5f-443f-b80d-cf8bd139f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041141389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3041141389
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3527559662
Short name T234
Test name
Test status
Simulation time 535317425 ps
CPU time 5.86 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:17 PM PDT 24
Peak memory 210364 kb
Host smart-e3bb301d-3892-4293-abff-f2da002ce195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527559662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3527559662
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2522574074
Short name T237
Test name
Test status
Simulation time 41294168 ps
CPU time 2.86 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:29 PM PDT 24
Peak memory 219664 kb
Host smart-73231666-5621-43a4-9de1-ea7bce95ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522574074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2522574074
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1110553901
Short name T306
Test name
Test status
Simulation time 214361224 ps
CPU time 7.68 seconds
Started Jul 23 05:46:33 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 208436 kb
Host smart-4767cdf7-9aff-4a3f-8795-f880ed240876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110553901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1110553901
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2442443465
Short name T225
Test name
Test status
Simulation time 179940790 ps
CPU time 3.31 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 207476 kb
Host smart-e52bb895-5bed-4d11-a3e7-5f1752f4f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442443465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2442443465
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2475295952
Short name T141
Test name
Test status
Simulation time 221948065 ps
CPU time 6.57 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 220376 kb
Host smart-3f22934b-ea53-4687-a4f9-1cefc18d3949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475295952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2475295952
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1899279102
Short name T401
Test name
Test status
Simulation time 218390285 ps
CPU time 15.52 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 220892 kb
Host smart-6e3cac44-ebf9-4216-88e8-0c0905c90725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899279102 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1899279102
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1670874635
Short name T25
Test name
Test status
Simulation time 359818927 ps
CPU time 4.1 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:55 PM PDT 24
Peak memory 220772 kb
Host smart-7a261ba2-703b-4411-a517-a89c45b9fdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670874635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1670874635
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1917222491
Short name T10
Test name
Test status
Simulation time 218034891 ps
CPU time 2.68 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 209740 kb
Host smart-c81b2839-f89e-4d6e-b3e5-000793b3b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917222491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1917222491
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3153120947
Short name T989
Test name
Test status
Simulation time 384801195 ps
CPU time 7.93 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 206064 kb
Host smart-a7bcee12-13f2-415f-b74e-a8903ee39014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153120947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
153120947
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.6936727
Short name T1086
Test name
Test status
Simulation time 5357776038 ps
CPU time 32.31 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:42 PM PDT 24
Peak memory 206332 kb
Host smart-5f5c3912-d5e8-4e5a-9d50-6e61b6dfd624
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6936727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.6936727
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3523859638
Short name T929
Test name
Test status
Simulation time 107495093 ps
CPU time 1.14 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 206340 kb
Host smart-1fadfd95-80ef-44ac-80fc-bed8dcdb9967
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523859638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
523859638
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3913377843
Short name T1037
Test name
Test status
Simulation time 98576309 ps
CPU time 1.59 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 214500 kb
Host smart-c44bd112-5949-4f74-95f9-145bdfba5bc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913377843 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3913377843
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1212517852
Short name T1015
Test name
Test status
Simulation time 283456310 ps
CPU time 1.33 seconds
Started Jul 23 06:30:01 PM PDT 24
Finished Jul 23 06:30:04 PM PDT 24
Peak memory 206148 kb
Host smart-45380a43-5c2a-4d7e-ba1b-de3914b307cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212517852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1212517852
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1746383840
Short name T980
Test name
Test status
Simulation time 46953207 ps
CPU time 0.78 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 206024 kb
Host smart-8c22d490-700b-4aaf-9574-65c126d78ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746383840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1746383840
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2554101567
Short name T964
Test name
Test status
Simulation time 141928660 ps
CPU time 2.42 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 206180 kb
Host smart-2aeea34d-3592-4a7b-98da-63801e6a17a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554101567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2554101567
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1049911675
Short name T972
Test name
Test status
Simulation time 527672512 ps
CPU time 4.04 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 214704 kb
Host smart-02ce0eea-cbb5-412c-8dc3-429d9c240a27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049911675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1049911675
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1098825467
Short name T987
Test name
Test status
Simulation time 511974420 ps
CPU time 6.64 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 214680 kb
Host smart-39809d3d-6f97-46da-9435-9d73c4ff8733
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098825467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1098825467
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.478547630
Short name T1090
Test name
Test status
Simulation time 91056465 ps
CPU time 3.69 seconds
Started Jul 23 06:29:58 PM PDT 24
Finished Jul 23 06:30:03 PM PDT 24
Peak memory 222428 kb
Host smart-27fcd287-4817-45a8-8a98-12477277dac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478547630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.478547630
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1171585789
Short name T146
Test name
Test status
Simulation time 501936543 ps
CPU time 7.26 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 206204 kb
Host smart-14f8aebc-28dd-4b66-82c8-d68901055d47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171585789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
171585789
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3489717968
Short name T1077
Test name
Test status
Simulation time 894208172 ps
CPU time 24.1 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 205996 kb
Host smart-4e586844-0ced-4a2e-b00d-a9b1d7b82a2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489717968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
489717968
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3011289545
Short name T1084
Test name
Test status
Simulation time 47467990 ps
CPU time 0.88 seconds
Started Jul 23 06:30:01 PM PDT 24
Finished Jul 23 06:30:03 PM PDT 24
Peak memory 206088 kb
Host smart-0b0bc016-ac09-4478-9e9f-cb39f8f606ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011289545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
011289545
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2623867683
Short name T926
Test name
Test status
Simulation time 171633368 ps
CPU time 2.02 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 206528 kb
Host smart-f4cda060-1cb5-4058-a8c5-e5d12de66393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623867683 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2623867683
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3349837577
Short name T189
Test name
Test status
Simulation time 39322072 ps
CPU time 1.15 seconds
Started Jul 23 06:29:59 PM PDT 24
Finished Jul 23 06:30:01 PM PDT 24
Peak memory 206160 kb
Host smart-1b52d441-e8e6-4d67-aadf-c10dfba92030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349837577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3349837577
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.152476029
Short name T927
Test name
Test status
Simulation time 19531857 ps
CPU time 0.97 seconds
Started Jul 23 06:29:58 PM PDT 24
Finished Jul 23 06:30:00 PM PDT 24
Peak memory 206092 kb
Host smart-3f8be8cf-dadb-4914-9521-973d33cb03be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152476029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.152476029
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.820885149
Short name T1043
Test name
Test status
Simulation time 112420600 ps
CPU time 2.47 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 206248 kb
Host smart-f80ddda3-6c31-4272-8163-9de622675c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820885149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.820885149
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3439541442
Short name T1045
Test name
Test status
Simulation time 531597596 ps
CPU time 2 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 214888 kb
Host smart-d26bfb8d-bf4a-4070-8016-d73b0af9f71e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439541442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3439541442
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1788320803
Short name T1027
Test name
Test status
Simulation time 999449070 ps
CPU time 3.47 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:07 PM PDT 24
Peak memory 216612 kb
Host smart-fc5cf690-615b-4a14-80c6-3d094ca37ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788320803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1788320803
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.213252516
Short name T1047
Test name
Test status
Simulation time 314710371 ps
CPU time 9.3 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 214316 kb
Host smart-2a716afd-0a2e-4c1f-a0b6-c6a9b8114704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213252516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
213252516
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4034976034
Short name T188
Test name
Test status
Simulation time 448102696 ps
CPU time 1.59 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:17 PM PDT 24
Peak memory 214516 kb
Host smart-f000b891-e93b-4b73-b48f-22f94f9f6776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034976034 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4034976034
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4228207774
Short name T959
Test name
Test status
Simulation time 255973781 ps
CPU time 1.46 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:17 PM PDT 24
Peak memory 206252 kb
Host smart-1002b1e1-36ea-4cc4-9d55-c81905d398de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228207774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4228207774
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1330039926
Short name T1006
Test name
Test status
Simulation time 8549698 ps
CPU time 0.8 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 206028 kb
Host smart-e353aa73-8059-47e0-9edc-7b04b0e8b93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330039926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1330039926
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2732805556
Short name T1065
Test name
Test status
Simulation time 119078925 ps
CPU time 1.94 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 206240 kb
Host smart-16149c98-45c8-47c7-b33c-0e9038956dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732805556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2732805556
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1892664196
Short name T1069
Test name
Test status
Simulation time 261700549 ps
CPU time 3.1 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 214664 kb
Host smart-e71c5395-e747-4caa-946e-18b841f93dc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892664196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1892664196
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.384735726
Short name T975
Test name
Test status
Simulation time 591852509 ps
CPU time 8.03 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 214644 kb
Host smart-852e5d0f-8e2b-4fd0-835f-563f29e7f4de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384735726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.384735726
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2368838758
Short name T965
Test name
Test status
Simulation time 351415761 ps
CPU time 2.33 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 217628 kb
Host smart-463fdb13-4e29-4618-8063-586438926c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368838758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2368838758
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2427390530
Short name T986
Test name
Test status
Simulation time 85494312 ps
CPU time 1.5 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:18 PM PDT 24
Peak memory 214500 kb
Host smart-7a8e8fc0-4529-4802-bcbb-0f8674b4eac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427390530 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2427390530
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1310424885
Short name T1049
Test name
Test status
Simulation time 29714194 ps
CPU time 1.32 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 206128 kb
Host smart-1657c5c4-ef82-4ca7-8296-2a3a363d2aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310424885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1310424885
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4003830079
Short name T977
Test name
Test status
Simulation time 83805264 ps
CPU time 0.69 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 205956 kb
Host smart-6728883e-371f-4c06-b1a4-5d0d65a5d080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003830079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4003830079
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.829891051
Short name T1040
Test name
Test status
Simulation time 191858863 ps
CPU time 1.78 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 206324 kb
Host smart-1f5eb22e-06b4-41fa-b3f3-36505b9e6542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829891051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.829891051
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3622690871
Short name T1024
Test name
Test status
Simulation time 187381144 ps
CPU time 7.48 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 214700 kb
Host smart-228a04c9-ee5c-4076-bf41-434c4a3e0f84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622690871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3622690871
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3764926147
Short name T1074
Test name
Test status
Simulation time 160283728 ps
CPU time 1.97 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 216476 kb
Host smart-fd9b1043-c1f5-441b-bcb8-df34c2aa838b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764926147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3764926147
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1960989413
Short name T1081
Test name
Test status
Simulation time 517167523 ps
CPU time 5.53 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214440 kb
Host smart-0f3bde96-2fb2-4763-b66f-b45645a92ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960989413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1960989413
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2695391880
Short name T1032
Test name
Test status
Simulation time 93513354 ps
CPU time 1.59 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 214508 kb
Host smart-2216713b-5455-458c-93ff-daa44f9d1f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695391880 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2695391880
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1909959071
Short name T951
Test name
Test status
Simulation time 76883083 ps
CPU time 0.9 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 205956 kb
Host smart-3dcca1c1-5cb7-4ff5-a282-d3ad1083cff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909959071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1909959071
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1839868415
Short name T1071
Test name
Test status
Simulation time 81039714 ps
CPU time 0.76 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 205956 kb
Host smart-312b9570-bec7-4fea-b853-6a42e25ded41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839868415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1839868415
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2843644474
Short name T991
Test name
Test status
Simulation time 69031879 ps
CPU time 1.51 seconds
Started Jul 23 06:30:10 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 206268 kb
Host smart-400eba55-c4cc-4f1b-aea6-a81b42d4c4b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843644474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2843644474
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4005054819
Short name T995
Test name
Test status
Simulation time 73287443 ps
CPU time 1.36 seconds
Started Jul 23 06:30:10 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 214652 kb
Host smart-03fde14e-ae23-4afb-9c03-6d92a0d7273b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005054819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4005054819
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4209166294
Short name T125
Test name
Test status
Simulation time 2093289173 ps
CPU time 11.79 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 214732 kb
Host smart-8db3b403-6c68-4284-93df-690a3c2f7e3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209166294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4209166294
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3445348481
Short name T937
Test name
Test status
Simulation time 170064226 ps
CPU time 2.77 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 214452 kb
Host smart-7721023d-8da0-47d9-9b4c-4948bf14d29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445348481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3445348481
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3443677558
Short name T974
Test name
Test status
Simulation time 16362320 ps
CPU time 1.17 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 206392 kb
Host smart-5f031e3e-5b62-4374-85ca-040330e41517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443677558 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3443677558
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3270101723
Short name T939
Test name
Test status
Simulation time 13628577 ps
CPU time 0.94 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 205964 kb
Host smart-00d9ae12-7972-429c-a119-bdfc0a0a6849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270101723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3270101723
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2520237475
Short name T985
Test name
Test status
Simulation time 17396643 ps
CPU time 0.83 seconds
Started Jul 23 06:30:10 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 206028 kb
Host smart-f4095ef0-b065-46c7-afb6-c3a349616a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520237475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2520237475
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1124294373
Short name T1078
Test name
Test status
Simulation time 322907551 ps
CPU time 2.46 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 206228 kb
Host smart-9c2701df-906c-4557-909d-e4bb759e036c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124294373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1124294373
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4125098725
Short name T953
Test name
Test status
Simulation time 209014315 ps
CPU time 3.05 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 214892 kb
Host smart-9564029d-55c7-4285-87bb-8b1358452b04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125098725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4125098725
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2021731257
Short name T1088
Test name
Test status
Simulation time 1254977036 ps
CPU time 8.08 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:26 PM PDT 24
Peak memory 214660 kb
Host smart-67c646eb-afa8-4a6b-8a64-684f2e19abe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021731257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2021731257
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3838028454
Short name T1060
Test name
Test status
Simulation time 323134273 ps
CPU time 2.29 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 222480 kb
Host smart-c5dd68e9-fe41-4db4-9df9-2d3901520050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838028454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3838028454
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2663955123
Short name T156
Test name
Test status
Simulation time 210944691 ps
CPU time 8.29 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206400 kb
Host smart-345adc28-8576-4785-8382-44c9a9f73571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663955123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2663955123
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3634864681
Short name T1031
Test name
Test status
Simulation time 187225009 ps
CPU time 1.54 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214508 kb
Host smart-550c8aa7-006e-4829-9543-6cdc01524b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634864681 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3634864681
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3439571331
Short name T940
Test name
Test status
Simulation time 19746466 ps
CPU time 1.21 seconds
Started Jul 23 06:30:15 PM PDT 24
Finished Jul 23 06:30:26 PM PDT 24
Peak memory 206180 kb
Host smart-7d8d9898-3895-43db-a83b-2848f5d13108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439571331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3439571331
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2054064112
Short name T1018
Test name
Test status
Simulation time 15089286 ps
CPU time 0.82 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 205948 kb
Host smart-0ba7d414-0d98-44be-9d36-980c2a1d2bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054064112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2054064112
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.916686105
Short name T1035
Test name
Test status
Simulation time 209092281 ps
CPU time 2.81 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 206136 kb
Host smart-b8d14211-52d8-4b55-abf8-b36a2cd71d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916686105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.916686105
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3957365292
Short name T1010
Test name
Test status
Simulation time 623102181 ps
CPU time 5.28 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 214612 kb
Host smart-9346208b-072b-41f7-942c-1b63341c5633
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957365292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3957365292
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3628882762
Short name T130
Test name
Test status
Simulation time 1640439664 ps
CPU time 8.92 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 214624 kb
Host smart-647a0208-dbc6-4a76-a621-b697b38977a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628882762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3628882762
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.465415976
Short name T1048
Test name
Test status
Simulation time 59671852 ps
CPU time 1.81 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:14 PM PDT 24
Peak memory 216492 kb
Host smart-7c7d45d6-965d-4692-bcdb-ad7551939cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465415976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.465415976
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3246272352
Short name T1001
Test name
Test status
Simulation time 66698748 ps
CPU time 2.99 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 214808 kb
Host smart-fac7e446-c1ca-4a1f-910d-713e5dfa065e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246272352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3246272352
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4095740651
Short name T1011
Test name
Test status
Simulation time 90222429 ps
CPU time 1.61 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 214476 kb
Host smart-ec312b0a-dd7f-45d6-90d0-c3ff160cc7bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095740651 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4095740651
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1164502717
Short name T1028
Test name
Test status
Simulation time 28137999 ps
CPU time 1.27 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 206204 kb
Host smart-b3c11b5f-9a60-4846-96ac-4eb0d523dcaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164502717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1164502717
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1791764896
Short name T1033
Test name
Test status
Simulation time 12344144 ps
CPU time 0.75 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:26 PM PDT 24
Peak memory 205896 kb
Host smart-ac902e80-3973-4f4f-b039-71ab4df5e6b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791764896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1791764896
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3505263693
Short name T142
Test name
Test status
Simulation time 144455355 ps
CPU time 2.72 seconds
Started Jul 23 06:30:15 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206288 kb
Host smart-e0bd181a-c112-49a8-87f3-2fe7e3ef23b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505263693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3505263693
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3179434669
Short name T129
Test name
Test status
Simulation time 355818969 ps
CPU time 2.04 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214696 kb
Host smart-6a79030d-750f-4b15-a762-c023585042a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179434669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3179434669
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.146126821
Short name T971
Test name
Test status
Simulation time 800405578 ps
CPU time 13.74 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 214644 kb
Host smart-4948d84e-be83-4d04-ac33-65ec5012965c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146126821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.146126821
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4176871050
Short name T1002
Test name
Test status
Simulation time 160889070 ps
CPU time 3.05 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214352 kb
Host smart-bec707b5-cdcc-4590-a426-e61ac010316d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176871050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4176871050
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2895026070
Short name T1053
Test name
Test status
Simulation time 79287741 ps
CPU time 1.83 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214356 kb
Host smart-08d06be6-669f-44cb-bb0a-a726c490859e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895026070 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2895026070
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.570787880
Short name T1056
Test name
Test status
Simulation time 22331073 ps
CPU time 1.03 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 206220 kb
Host smart-fbea1df7-58c6-485b-a5b9-93d72b436849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570787880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.570787880
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2656293233
Short name T982
Test name
Test status
Simulation time 43523188 ps
CPU time 0.73 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:26 PM PDT 24
Peak memory 205892 kb
Host smart-aef65998-bce9-417b-881b-77ccdf63043e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656293233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2656293233
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3222285296
Short name T1066
Test name
Test status
Simulation time 136624764 ps
CPU time 2.31 seconds
Started Jul 23 06:30:15 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206248 kb
Host smart-70bc4499-c7e9-496b-af3f-b9827edf895e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222285296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3222285296
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1717690351
Short name T1059
Test name
Test status
Simulation time 111894415 ps
CPU time 2.54 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:26 PM PDT 24
Peak memory 214872 kb
Host smart-95f19a41-42f9-46e1-a3e6-4b8e80e0cea3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717690351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1717690351
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2817623151
Short name T994
Test name
Test status
Simulation time 341197845 ps
CPU time 6.71 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 220736 kb
Host smart-fb8fac9c-e410-4e03-abb8-903183d84dcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817623151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2817623151
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1575926178
Short name T966
Test name
Test status
Simulation time 1153293397 ps
CPU time 2.02 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 214340 kb
Host smart-3584dab4-e657-4542-9d43-4050dec85c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575926178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1575926178
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3299245554
Short name T1063
Test name
Test status
Simulation time 363958784 ps
CPU time 4.5 seconds
Started Jul 23 06:30:20 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 215400 kb
Host smart-e6fb0fe9-ad27-4ec9-8451-5912da54223e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299245554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3299245554
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1734425460
Short name T152
Test name
Test status
Simulation time 30616510 ps
CPU time 1.45 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 214452 kb
Host smart-737eb73f-114c-4b54-b789-8088a4656536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734425460 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1734425460
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2402499052
Short name T934
Test name
Test status
Simulation time 17913620 ps
CPU time 0.98 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 206088 kb
Host smart-0063bc60-18bc-44f2-b0fd-4aeb564910d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402499052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2402499052
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2782728071
Short name T922
Test name
Test status
Simulation time 17226024 ps
CPU time 0.7 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 206024 kb
Host smart-8ad845c9-323b-4485-b2ba-542e9f2a6b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782728071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2782728071
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3148885967
Short name T145
Test name
Test status
Simulation time 130466457 ps
CPU time 1.81 seconds
Started Jul 23 06:30:15 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206140 kb
Host smart-cc36c4fb-8367-44e3-a765-ae6a9e17b2b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148885967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3148885967
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1225422088
Short name T133
Test name
Test status
Simulation time 287766927 ps
CPU time 2.44 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 214660 kb
Host smart-645ed8f4-6a95-4168-a0de-42330dd6ac19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225422088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1225422088
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2682691032
Short name T988
Test name
Test status
Simulation time 610225249 ps
CPU time 3.44 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 214600 kb
Host smart-0ca13f5a-8a40-4380-952d-6caa57f8b36a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682691032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2682691032
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1754765579
Short name T946
Test name
Test status
Simulation time 152754564 ps
CPU time 2.91 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214476 kb
Host smart-a9950c0b-933b-4548-9255-79f2959433f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754765579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1754765579
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3104180502
Short name T1004
Test name
Test status
Simulation time 13138613 ps
CPU time 1.2 seconds
Started Jul 23 06:30:22 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 214492 kb
Host smart-6c0e6b9e-94df-485e-998f-97f01ef7d8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104180502 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3104180502
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2071851161
Short name T1013
Test name
Test status
Simulation time 24564782 ps
CPU time 1.1 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 206124 kb
Host smart-8a040ef2-3148-4bcd-a5f5-d2a8f248ad0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071851161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2071851161
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.966174314
Short name T930
Test name
Test status
Simulation time 46891676 ps
CPU time 0.81 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 205940 kb
Host smart-470917b6-5fa6-4c17-8da8-b2b758e3dab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966174314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.966174314
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3039468505
Short name T984
Test name
Test status
Simulation time 347837213 ps
CPU time 3.56 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 206028 kb
Host smart-d26aa69c-ab6a-45af-9167-3add1a8b72dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039468505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3039468505
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.522261364
Short name T127
Test name
Test status
Simulation time 50066308 ps
CPU time 1.65 seconds
Started Jul 23 06:30:14 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214600 kb
Host smart-81c8e407-be9b-4ab9-bf04-3bfecd9a875f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522261364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.522261364
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2129126875
Short name T1087
Test name
Test status
Simulation time 113646951 ps
CPU time 3.99 seconds
Started Jul 23 06:30:17 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 214684 kb
Host smart-70eac9f8-9685-449b-922a-53a9cfad00f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129126875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2129126875
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2074458588
Short name T1005
Test name
Test status
Simulation time 110143508 ps
CPU time 2.97 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 216748 kb
Host smart-d1e72467-ec18-4d04-98fe-4171a8044985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074458588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2074458588
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2780584257
Short name T163
Test name
Test status
Simulation time 502974231 ps
CPU time 5.09 seconds
Started Jul 23 06:30:21 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 214332 kb
Host smart-b98423d2-a036-47ad-9da1-7284fb840077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780584257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2780584257
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1659680511
Short name T973
Test name
Test status
Simulation time 127134597 ps
CPU time 1.16 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 214552 kb
Host smart-64fca69e-39d9-45fc-ab06-92f82e2dce3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659680511 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1659680511
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2394426579
Short name T955
Test name
Test status
Simulation time 25612219 ps
CPU time 1.09 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206064 kb
Host smart-a95fb380-1f2e-425a-a826-3fde1ca0088e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394426579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2394426579
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3431413617
Short name T1046
Test name
Test status
Simulation time 35948358 ps
CPU time 0.71 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 205896 kb
Host smart-9cdcabce-955c-44ec-ba12-e7971dcfe48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431413617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3431413617
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2427924056
Short name T147
Test name
Test status
Simulation time 2005394340 ps
CPU time 4.19 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206116 kb
Host smart-2a9683ed-7dff-4856-aa7d-c5a8df356657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427924056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2427924056
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3118408600
Short name T976
Test name
Test status
Simulation time 109696813 ps
CPU time 1.8 seconds
Started Jul 23 06:30:16 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 214644 kb
Host smart-27c2f271-0772-4d67-b2da-5dfe5c57b2d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118408600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3118408600
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3729969663
Short name T1003
Test name
Test status
Simulation time 400952208 ps
CPU time 9.46 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 220804 kb
Host smart-739840a1-87af-43ff-a4a7-ae40e104de05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729969663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3729969663
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1231820514
Short name T924
Test name
Test status
Simulation time 832541595 ps
CPU time 2.91 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:31 PM PDT 24
Peak memory 214348 kb
Host smart-d5b7ce6d-59de-42e5-ad00-1cd7de98afc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231820514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1231820514
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1129803515
Short name T170
Test name
Test status
Simulation time 431146140 ps
CPU time 5.24 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206224 kb
Host smart-d74eca41-5d57-4f90-9f49-d3f644bf2c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129803515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1129803515
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2525867659
Short name T1076
Test name
Test status
Simulation time 367437247 ps
CPU time 10.17 seconds
Started Jul 23 06:29:59 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 205576 kb
Host smart-63f859ab-a202-4a2f-8603-7e16136cca76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525867659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
525867659
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2261926602
Short name T979
Test name
Test status
Simulation time 323555831 ps
CPU time 14.95 seconds
Started Jul 23 06:29:59 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 205756 kb
Host smart-569a2fbe-f106-44ac-9f47-e3696ec7596b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261926602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
261926602
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2933196140
Short name T1012
Test name
Test status
Simulation time 54921558 ps
CPU time 1.26 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 206416 kb
Host smart-ec459d57-a026-4cfa-a231-653570d5c57f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933196140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
933196140
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2441225920
Short name T1008
Test name
Test status
Simulation time 351737474 ps
CPU time 2.06 seconds
Started Jul 23 06:30:01 PM PDT 24
Finished Jul 23 06:30:04 PM PDT 24
Peak memory 214416 kb
Host smart-9f33cbc5-b7b3-4e54-ad37-144cb207606f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441225920 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2441225920
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2275698953
Short name T962
Test name
Test status
Simulation time 14782602 ps
CPU time 0.93 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:07 PM PDT 24
Peak memory 206076 kb
Host smart-4e363751-a87c-4a37-8585-fdd6c5040cd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275698953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2275698953
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3435685619
Short name T1000
Test name
Test status
Simulation time 8524682 ps
CPU time 0.83 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 206024 kb
Host smart-22d446dc-8bd0-488f-891f-80ef00efdf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435685619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3435685619
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3979997166
Short name T960
Test name
Test status
Simulation time 448360862 ps
CPU time 2.67 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:07 PM PDT 24
Peak memory 206200 kb
Host smart-e1cf9838-88ab-43f9-9fd8-a6debcc1d473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979997166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3979997166
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.637450106
Short name T1079
Test name
Test status
Simulation time 2337718434 ps
CPU time 3.88 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:05 PM PDT 24
Peak memory 214680 kb
Host smart-f6031c0f-ba82-41c2-a532-c800a937d4ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637450106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.637450106
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3247168088
Short name T958
Test name
Test status
Simulation time 864251044 ps
CPU time 9.96 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:18 PM PDT 24
Peak memory 214648 kb
Host smart-64a9abfa-ee27-4bd2-8f6c-130add94bfb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247168088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3247168088
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2293469927
Short name T1041
Test name
Test status
Simulation time 75545466 ps
CPU time 2.34 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:09 PM PDT 24
Peak memory 214356 kb
Host smart-12698902-730f-428c-9cc6-6e8c2ca04ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293469927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2293469927
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2583228169
Short name T923
Test name
Test status
Simulation time 47994199 ps
CPU time 0.86 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 206012 kb
Host smart-510c4784-4c33-468a-a752-b2e816cce612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583228169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2583228169
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4124356460
Short name T1085
Test name
Test status
Simulation time 13935247 ps
CPU time 0.74 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 205952 kb
Host smart-2eb365e8-b689-4117-9060-cf94bf4d3a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124356460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4124356460
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2599974685
Short name T1029
Test name
Test status
Simulation time 13843314 ps
CPU time 0.9 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 206036 kb
Host smart-8ac1e6ac-2f0b-47e3-b7a1-38e8d6369d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599974685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2599974685
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1764782739
Short name T1038
Test name
Test status
Simulation time 9833792 ps
CPU time 0.77 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 205968 kb
Host smart-f1355edd-21f7-4a77-bd00-95b6aa09ddb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764782739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1764782739
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1943736080
Short name T950
Test name
Test status
Simulation time 145317727 ps
CPU time 0.72 seconds
Started Jul 23 06:30:18 PM PDT 24
Finished Jul 23 06:30:28 PM PDT 24
Peak memory 205940 kb
Host smart-cdcc58f1-6d63-4a4c-afa8-e6950aceeb8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943736080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1943736080
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4009668704
Short name T998
Test name
Test status
Simulation time 10120165 ps
CPU time 0.73 seconds
Started Jul 23 06:30:17 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206020 kb
Host smart-d18daa7a-be38-4c25-b842-d145f923416e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009668704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4009668704
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2357536463
Short name T1062
Test name
Test status
Simulation time 26608057 ps
CPU time 0.94 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 206036 kb
Host smart-59046c7b-7804-4fcf-86be-a67e453b6021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357536463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2357536463
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2454619908
Short name T945
Test name
Test status
Simulation time 14976160 ps
CPU time 0.86 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 206160 kb
Host smart-0a0398b8-9ec0-42bb-ba20-0fa5eb1939ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454619908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2454619908
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1738405594
Short name T1058
Test name
Test status
Simulation time 176621944 ps
CPU time 0.75 seconds
Started Jul 23 06:30:20 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 205924 kb
Host smart-d555ab69-ecc2-4008-a98f-4889b5353de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738405594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1738405594
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.342888980
Short name T1025
Test name
Test status
Simulation time 34619097 ps
CPU time 0.81 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 205984 kb
Host smart-425a406e-25c5-4852-97b8-069b36aab57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342888980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.342888980
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2338927574
Short name T957
Test name
Test status
Simulation time 726695442 ps
CPU time 7.41 seconds
Started Jul 23 06:29:59 PM PDT 24
Finished Jul 23 06:30:07 PM PDT 24
Peak memory 206284 kb
Host smart-7b00a09e-2a9f-4e85-8ba1-96f943601feb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338927574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
338927574
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3130904329
Short name T983
Test name
Test status
Simulation time 1041571353 ps
CPU time 14.56 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 206276 kb
Host smart-208df696-d273-4d1c-9929-d5b57b411bce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130904329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
130904329
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2029984647
Short name T996
Test name
Test status
Simulation time 106860285 ps
CPU time 1.38 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:02 PM PDT 24
Peak memory 206144 kb
Host smart-e1a0a04f-cf0a-4b5e-9165-84dbab96cc39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029984647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
029984647
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3435591471
Short name T1044
Test name
Test status
Simulation time 56330789 ps
CPU time 2.19 seconds
Started Jul 23 06:29:58 PM PDT 24
Finished Jul 23 06:30:01 PM PDT 24
Peak memory 214524 kb
Host smart-940888d4-67d5-4457-9520-000ed7d7531f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435591471 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3435591471
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.637064855
Short name T956
Test name
Test status
Simulation time 134661286 ps
CPU time 1.09 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 206092 kb
Host smart-39b2093c-cda3-4499-a75d-c1628c36a2b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637064855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.637064855
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1097122150
Short name T1054
Test name
Test status
Simulation time 25768411 ps
CPU time 0.92 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:06 PM PDT 24
Peak memory 206012 kb
Host smart-9d4e001b-79b1-4f9e-8576-fd1eabff4de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097122150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1097122150
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.328723291
Short name T943
Test name
Test status
Simulation time 45201440 ps
CPU time 1.84 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:06 PM PDT 24
Peak memory 206116 kb
Host smart-2f40b4b0-0a6e-41f0-9f1d-7a27f6e7118c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328723291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.328723291
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1855995454
Short name T128
Test name
Test status
Simulation time 411352150 ps
CPU time 3.35 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 214584 kb
Host smart-7631247f-9d75-4073-8ce5-0283229cbafc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855995454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1855995454
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1260635570
Short name T1042
Test name
Test status
Simulation time 1552458771 ps
CPU time 12.06 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 214584 kb
Host smart-5c5f2365-5b10-4f1c-aae6-d61ede4cb458
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260635570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1260635570
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.481294111
Short name T181
Test name
Test status
Simulation time 572501827 ps
CPU time 3.59 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:17 PM PDT 24
Peak memory 214416 kb
Host smart-ed7f197c-ad09-4ebd-98b7-d6136708a964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481294111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.481294111
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2110113060
Short name T932
Test name
Test status
Simulation time 12225350 ps
CPU time 0.74 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:30 PM PDT 24
Peak memory 206028 kb
Host smart-76495d98-1ffc-48d9-9e87-9940d1bfec38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110113060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2110113060
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3617713685
Short name T999
Test name
Test status
Simulation time 47881755 ps
CPU time 0.8 seconds
Started Jul 23 06:30:19 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 205964 kb
Host smart-d2997e51-1caf-4c16-b5aa-d6b24f427787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617713685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3617713685
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.761401427
Short name T1007
Test name
Test status
Simulation time 25344794 ps
CPU time 0.8 seconds
Started Jul 23 06:30:22 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206016 kb
Host smart-8a31a25c-c9a1-478e-a2a7-d05566a404ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761401427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.761401427
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3657637818
Short name T952
Test name
Test status
Simulation time 45108769 ps
CPU time 0.82 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 206028 kb
Host smart-82a02b4d-9442-43dd-82b2-57b624e25f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657637818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3657637818
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3925168051
Short name T925
Test name
Test status
Simulation time 12647733 ps
CPU time 0.74 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 206016 kb
Host smart-60b9e087-38f3-4c09-a917-355a7ed9331a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925168051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3925168051
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1505366225
Short name T1019
Test name
Test status
Simulation time 9825630 ps
CPU time 0.73 seconds
Started Jul 23 06:30:26 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 206008 kb
Host smart-1c951e95-25a8-45ee-acc9-43dc9ad1a2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505366225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1505366225
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1712630992
Short name T1039
Test name
Test status
Simulation time 46008514 ps
CPU time 0.82 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206020 kb
Host smart-bb74a71b-cc00-4e91-95e6-31293ea0aa89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712630992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1712630992
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2187334006
Short name T993
Test name
Test status
Simulation time 10816051 ps
CPU time 0.72 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 205948 kb
Host smart-a3c1bbad-69d0-417f-8f97-78ec61068d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187334006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2187334006
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.135835865
Short name T948
Test name
Test status
Simulation time 26712384 ps
CPU time 0.74 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 205932 kb
Host smart-c1189daa-b7ff-42bc-a6b7-d4f0aae52a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135835865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.135835865
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2730231567
Short name T992
Test name
Test status
Simulation time 17209181 ps
CPU time 0.81 seconds
Started Jul 23 06:30:24 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 205940 kb
Host smart-8cba9c13-2e1f-4dd3-a52f-e32d7174227f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730231567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2730231567
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3424281025
Short name T1014
Test name
Test status
Simulation time 194877173 ps
CPU time 4.89 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 206304 kb
Host smart-d138721e-ea87-4875-aa2d-0da43cda446a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424281025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
424281025
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1836503971
Short name T1064
Test name
Test status
Simulation time 3237823004 ps
CPU time 17.01 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:27 PM PDT 24
Peak memory 206240 kb
Host smart-961adb5a-4b86-4cfd-a416-572b5c096058
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836503971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
836503971
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2912658699
Short name T1020
Test name
Test status
Simulation time 144951188 ps
CPU time 1.06 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 206208 kb
Host smart-1a6a685d-6863-4b4d-a3a1-4333c10c6ec0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912658699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
912658699
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.311009847
Short name T1075
Test name
Test status
Simulation time 24718026 ps
CPU time 1.66 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 214488 kb
Host smart-61576340-56d0-4907-84a1-3cb43c19d421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311009847 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.311009847
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4094194993
Short name T1036
Test name
Test status
Simulation time 26266045 ps
CPU time 1.14 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 206200 kb
Host smart-1c43abfe-c620-4906-ab42-a5c5e55ce693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094194993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4094194993
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3720044303
Short name T1051
Test name
Test status
Simulation time 30006813 ps
CPU time 0.91 seconds
Started Jul 23 06:29:59 PM PDT 24
Finished Jul 23 06:30:01 PM PDT 24
Peak memory 206016 kb
Host smart-95a543f9-de8d-481f-8214-de45e4b4e67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720044303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3720044303
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2826680520
Short name T1021
Test name
Test status
Simulation time 504325648 ps
CPU time 1.65 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 206216 kb
Host smart-71390e00-092b-412e-a999-b50023bc48ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826680520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2826680520
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.868304892
Short name T132
Test name
Test status
Simulation time 300205817 ps
CPU time 1.86 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:03 PM PDT 24
Peak memory 214608 kb
Host smart-301730dc-d9e6-4e5d-b089-2ddfb8dddfdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868304892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.868304892
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1172662745
Short name T947
Test name
Test status
Simulation time 245907870 ps
CPU time 5.17 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 214680 kb
Host smart-8fe817a3-2886-46f9-a2d4-a98fe93a7780
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172662745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1172662745
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3898722159
Short name T1017
Test name
Test status
Simulation time 111517059 ps
CPU time 2.01 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:08 PM PDT 24
Peak memory 214476 kb
Host smart-9de5bb07-671a-4bba-82bd-15f6aed01e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898722159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3898722159
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3922648885
Short name T166
Test name
Test status
Simulation time 804193097 ps
CPU time 5.84 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 215660 kb
Host smart-947ccee1-5a63-470e-961a-dd408d223218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922648885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3922648885
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2968501269
Short name T954
Test name
Test status
Simulation time 10485831 ps
CPU time 0.76 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 205968 kb
Host smart-bb6ddc1b-ae89-4443-a1be-78c9923e2a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968501269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2968501269
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3472801022
Short name T963
Test name
Test status
Simulation time 13371619 ps
CPU time 0.84 seconds
Started Jul 23 06:30:22 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206160 kb
Host smart-45642561-f425-41e2-a4a8-6164d8864bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472801022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3472801022
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.619271804
Short name T970
Test name
Test status
Simulation time 24311214 ps
CPU time 0.82 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 205892 kb
Host smart-8a860bd6-68ac-4756-8c82-7c0e09d6d13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619271804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.619271804
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3727648789
Short name T942
Test name
Test status
Simulation time 9502105 ps
CPU time 0.77 seconds
Started Jul 23 06:30:26 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 205980 kb
Host smart-394c17c8-946d-407f-8dd0-918c28da477c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727648789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3727648789
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2840287999
Short name T944
Test name
Test status
Simulation time 66439225 ps
CPU time 0.76 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 205788 kb
Host smart-bb042e22-a77b-4e25-abb5-0067a87f13e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840287999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2840287999
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.959738964
Short name T1016
Test name
Test status
Simulation time 28162095 ps
CPU time 0.77 seconds
Started Jul 23 06:30:22 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 206032 kb
Host smart-f5ad7c21-5d22-4c62-a6ed-2140938da19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959738964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.959738964
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3186462859
Short name T921
Test name
Test status
Simulation time 14160135 ps
CPU time 0.84 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:32 PM PDT 24
Peak memory 205960 kb
Host smart-3cc10c7d-15ce-416c-8603-777181f51c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186462859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3186462859
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3555204977
Short name T990
Test name
Test status
Simulation time 224898173 ps
CPU time 0.76 seconds
Started Jul 23 06:30:24 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 205940 kb
Host smart-9da6dfa8-5d1c-4cd7-9fc4-8a00b63f9c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555204977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3555204977
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2896935596
Short name T1080
Test name
Test status
Simulation time 12417637 ps
CPU time 0.88 seconds
Started Jul 23 06:30:24 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 206016 kb
Host smart-33ded8aa-44c1-4035-a6ba-8b0628707b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896935596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2896935596
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4160020176
Short name T1022
Test name
Test status
Simulation time 12459570 ps
CPU time 0.86 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 206016 kb
Host smart-1e9beaa8-d5dc-44ac-badb-c94df08d632a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160020176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4160020176
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.348148373
Short name T1089
Test name
Test status
Simulation time 93672649 ps
CPU time 1.52 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 214396 kb
Host smart-0e26f62d-34fa-42b4-b115-030daea62455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348148373 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.348148373
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2585226219
Short name T143
Test name
Test status
Simulation time 35305015 ps
CPU time 0.9 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:09 PM PDT 24
Peak memory 205920 kb
Host smart-79e42010-75db-4d53-853e-70a3b3e8042b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585226219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2585226219
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3778449261
Short name T935
Test name
Test status
Simulation time 26396860 ps
CPU time 0.75 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:09 PM PDT 24
Peak memory 205952 kb
Host smart-1ca41195-efe8-4420-8ac5-86cd28ac63b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778449261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3778449261
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.188023931
Short name T144
Test name
Test status
Simulation time 356236003 ps
CPU time 2.6 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:14 PM PDT 24
Peak memory 206144 kb
Host smart-82a4d094-7302-4aff-87a2-c8c952472586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188023931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.188023931
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1741683444
Short name T949
Test name
Test status
Simulation time 585537402 ps
CPU time 2.64 seconds
Started Jul 23 06:30:02 PM PDT 24
Finished Jul 23 06:30:07 PM PDT 24
Peak memory 218716 kb
Host smart-5cad7d66-e82f-477b-a818-30d90482e852
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741683444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1741683444
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.621226496
Short name T941
Test name
Test status
Simulation time 403932877 ps
CPU time 8.81 seconds
Started Jul 23 06:30:00 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 220804 kb
Host smart-291a67a3-7234-424a-9bac-e7dca9ae9377
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621226496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.621226496
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3748566720
Short name T928
Test name
Test status
Simulation time 26038927 ps
CPU time 1.88 seconds
Started Jul 23 06:30:03 PM PDT 24
Finished Jul 23 06:30:09 PM PDT 24
Peak memory 214436 kb
Host smart-14d97922-e28a-4d13-aa2f-2f7be59cda5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748566720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3748566720
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2665675785
Short name T150
Test name
Test status
Simulation time 163713073 ps
CPU time 4.51 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:14 PM PDT 24
Peak memory 214496 kb
Host smart-29537b4e-d97a-49f9-8140-ea91f145df25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665675785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2665675785
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2852993052
Short name T961
Test name
Test status
Simulation time 63469099 ps
CPU time 1.26 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 214472 kb
Host smart-46812293-b578-412e-9d75-8396b71f70b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852993052 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2852993052
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3642690982
Short name T1030
Test name
Test status
Simulation time 21295443 ps
CPU time 0.92 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:10 PM PDT 24
Peak memory 206068 kb
Host smart-93845a22-396e-47eb-9fd6-5b06c4f467ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642690982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3642690982
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.97440028
Short name T1009
Test name
Test status
Simulation time 15926615 ps
CPU time 0.84 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:11 PM PDT 24
Peak memory 206024 kb
Host smart-01827a3e-3581-4235-b6a0-a5083623debe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97440028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.97440028
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3797436585
Short name T978
Test name
Test status
Simulation time 122024055 ps
CPU time 3.07 seconds
Started Jul 23 06:30:01 PM PDT 24
Finished Jul 23 06:30:05 PM PDT 24
Peak memory 206188 kb
Host smart-b0e250e0-a946-4a1d-942a-944e6421efd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797436585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3797436585
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3153774437
Short name T1070
Test name
Test status
Simulation time 154479192 ps
CPU time 1.58 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 214688 kb
Host smart-541d3423-8097-4c81-b832-40b8208c0f9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153774437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3153774437
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1610721204
Short name T1082
Test name
Test status
Simulation time 1499769095 ps
CPU time 12.51 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 220740 kb
Host smart-3e36bbe1-10d2-4937-bd54-2650729cd604
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610721204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1610721204
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3387240615
Short name T1067
Test name
Test status
Simulation time 171322315 ps
CPU time 3.44 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:13 PM PDT 24
Peak memory 214436 kb
Host smart-a32057cb-59a5-4ae4-9c0e-69dbf15ad781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387240615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3387240615
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3573252392
Short name T161
Test name
Test status
Simulation time 195180240 ps
CPU time 2.62 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 206240 kb
Host smart-095274dd-76e9-400a-97b2-501f963a570c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573252392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3573252392
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2069883951
Short name T936
Test name
Test status
Simulation time 31305549 ps
CPU time 1.12 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 206236 kb
Host smart-c235b27b-6d90-48b0-ac0c-695c10572655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069883951 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2069883951
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.760669681
Short name T1073
Test name
Test status
Simulation time 61606612 ps
CPU time 1.18 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:14 PM PDT 24
Peak memory 206116 kb
Host smart-4beb0bfb-0e58-4338-b3ef-438642de29e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760669681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.760669681
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3505220495
Short name T931
Test name
Test status
Simulation time 83391009 ps
CPU time 0.79 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 206028 kb
Host smart-fcc3fb1d-055c-4c97-87df-c26611946ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505220495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3505220495
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3681119149
Short name T1034
Test name
Test status
Simulation time 62203772 ps
CPU time 2.02 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 206172 kb
Host smart-33dceb72-cb45-48ad-8497-47a30eeaa60d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681119149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3681119149
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1472217677
Short name T1050
Test name
Test status
Simulation time 138775376 ps
CPU time 2.64 seconds
Started Jul 23 06:30:04 PM PDT 24
Finished Jul 23 06:30:12 PM PDT 24
Peak memory 214648 kb
Host smart-d25991ba-be31-41fb-97ed-307d0e05d67e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472217677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1472217677
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.903408151
Short name T969
Test name
Test status
Simulation time 1513332143 ps
CPU time 8.18 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 214608 kb
Host smart-ebd69b38-10dd-4349-9c08-9def48446683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903408151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.903408151
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3102787010
Short name T1057
Test name
Test status
Simulation time 65344138 ps
CPU time 1.99 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 217520 kb
Host smart-9357e3d0-d510-4168-90be-c17d2fe33536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102787010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3102787010
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2851697808
Short name T164
Test name
Test status
Simulation time 188368306 ps
CPU time 2.69 seconds
Started Jul 23 06:30:06 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 214380 kb
Host smart-ab619999-223b-4daf-8d6d-69130695400a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851697808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2851697808
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2786723414
Short name T1026
Test name
Test status
Simulation time 19194691 ps
CPU time 1.58 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 214472 kb
Host smart-524ec3a7-f6e8-4ae2-96ba-e435a0c7e6cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786723414 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2786723414
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.294981048
Short name T1083
Test name
Test status
Simulation time 54880558 ps
CPU time 1.15 seconds
Started Jul 23 06:30:13 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 206228 kb
Host smart-bbae296d-57e4-4220-9a5a-bbae2285a22a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294981048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.294981048
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2700083837
Short name T981
Test name
Test status
Simulation time 35659310 ps
CPU time 0.73 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:21 PM PDT 24
Peak memory 206040 kb
Host smart-f77d811f-3a69-49d1-8a3c-52f921acfc60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700083837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2700083837
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.644192172
Short name T968
Test name
Test status
Simulation time 64072179 ps
CPU time 2.11 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:18 PM PDT 24
Peak memory 206192 kb
Host smart-be599641-9160-4f93-812b-a2171e9dd19b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644192172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.644192172
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.446891837
Short name T1072
Test name
Test status
Simulation time 365796360 ps
CPU time 3.27 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:18 PM PDT 24
Peak memory 214668 kb
Host smart-ffdaf9ee-1870-4f58-bee8-ec2bade8c310
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446891837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.446891837
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.17160311
Short name T131
Test name
Test status
Simulation time 581501918 ps
CPU time 7.6 seconds
Started Jul 23 06:30:08 PM PDT 24
Finished Jul 23 06:30:24 PM PDT 24
Peak memory 214712 kb
Host smart-332ce151-c783-4a64-bcbf-d0265de9096d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17160311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.17160311
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.717700030
Short name T1055
Test name
Test status
Simulation time 25034626 ps
CPU time 1.76 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:14 PM PDT 24
Peak memory 216496 kb
Host smart-e784aae6-908b-42f4-bc64-4c1f2d4afb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717700030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.717700030
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.420697630
Short name T165
Test name
Test status
Simulation time 163563496 ps
CPU time 5.38 seconds
Started Jul 23 06:30:11 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 214424 kb
Host smart-cab69fe9-e291-41c6-be9e-083184c87d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420697630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
420697630
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2940282102
Short name T997
Test name
Test status
Simulation time 20247201 ps
CPU time 1.23 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:17 PM PDT 24
Peak memory 206272 kb
Host smart-88fb3b10-54ac-4cfe-bef7-d7cedfe2807e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940282102 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2940282102
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2845184295
Short name T1052
Test name
Test status
Simulation time 48642954 ps
CPU time 1 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:22 PM PDT 24
Peak memory 206224 kb
Host smart-fe4ccd62-446d-4f23-96fe-edbeb0cb2fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845184295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2845184295
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.175092798
Short name T1061
Test name
Test status
Simulation time 17118067 ps
CPU time 0.8 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:16 PM PDT 24
Peak memory 205976 kb
Host smart-352a3175-4141-403d-8f13-852fa63c8d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175092798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.175092798
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.473081525
Short name T967
Test name
Test status
Simulation time 85792528 ps
CPU time 2.35 seconds
Started Jul 23 06:30:12 PM PDT 24
Finished Jul 23 06:30:23 PM PDT 24
Peak memory 214420 kb
Host smart-f748602b-2195-4eb1-bad8-fd3329194206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473081525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.473081525
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4114973362
Short name T1068
Test name
Test status
Simulation time 193610296 ps
CPU time 3.31 seconds
Started Jul 23 06:30:07 PM PDT 24
Finished Jul 23 06:30:18 PM PDT 24
Peak memory 214656 kb
Host smart-4a64584a-5cf5-4abb-9fc6-deae65cfb0e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114973362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4114973362
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1303849832
Short name T1023
Test name
Test status
Simulation time 163747179 ps
CPU time 4.56 seconds
Started Jul 23 06:30:05 PM PDT 24
Finished Jul 23 06:30:15 PM PDT 24
Peak memory 214656 kb
Host smart-bead4917-934d-4a6b-92be-d495718e584f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303849832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1303849832
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4010854204
Short name T933
Test name
Test status
Simulation time 73672059 ps
CPU time 2 seconds
Started Jul 23 06:30:09 PM PDT 24
Finished Jul 23 06:30:20 PM PDT 24
Peak memory 214448 kb
Host smart-14e452af-21d5-449a-9285-8f06659d1a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010854204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4010854204
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2965534822
Short name T279
Test name
Test status
Simulation time 492826707 ps
CPU time 13.51 seconds
Started Jul 23 05:44:17 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 215616 kb
Host smart-c2eb7ee9-eb09-4392-a743-d478f6ed23e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965534822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2965534822
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3303733134
Short name T71
Test name
Test status
Simulation time 242947490 ps
CPU time 3.59 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:23 PM PDT 24
Peak memory 208620 kb
Host smart-58611bb9-1aaa-40e1-954e-c1817384542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303733134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3303733134
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.491045546
Short name T256
Test name
Test status
Simulation time 76061355 ps
CPU time 3.24 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:22 PM PDT 24
Peak memory 218036 kb
Host smart-248b27d5-98a3-486f-ba78-98efd0384526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491045546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.491045546
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3188239204
Short name T758
Test name
Test status
Simulation time 75627711 ps
CPU time 3.45 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:22 PM PDT 24
Peak memory 208324 kb
Host smart-55e953b7-ea5a-4f06-9071-fbdc9ff118c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188239204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3188239204
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.168335942
Short name T289
Test name
Test status
Simulation time 37799954 ps
CPU time 2.09 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:19 PM PDT 24
Peak memory 213940 kb
Host smart-a53f1d55-52ed-4107-84e1-41b7e899ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168335942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.168335942
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2773222366
Short name T671
Test name
Test status
Simulation time 179917714 ps
CPU time 5.25 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:25 PM PDT 24
Peak memory 215744 kb
Host smart-09f13dc0-ac64-48e2-b1bf-e4d89b243ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773222366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2773222366
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1600937095
Short name T91
Test name
Test status
Simulation time 784019176 ps
CPU time 19.25 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:36 PM PDT 24
Peak memory 208788 kb
Host smart-2f99804c-a2b5-4f74-b0b0-078d6085590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600937095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1600937095
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3902021220
Short name T309
Test name
Test status
Simulation time 526064961 ps
CPU time 10.65 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 207976 kb
Host smart-08b60b12-367a-4d6a-a4c9-bf9a230ddd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902021220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3902021220
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3220248265
Short name T522
Test name
Test status
Simulation time 74711496 ps
CPU time 1.92 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:18 PM PDT 24
Peak memory 206556 kb
Host smart-dfa826e2-2c98-40b0-b05c-e0d0d4cfad4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220248265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3220248265
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2389895966
Short name T320
Test name
Test status
Simulation time 336153885 ps
CPU time 3.07 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 208332 kb
Host smart-793370db-646b-4e8c-ad5b-a6266f61bd93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389895966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2389895966
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.993114146
Short name T836
Test name
Test status
Simulation time 165212471 ps
CPU time 2.63 seconds
Started Jul 23 05:44:19 PM PDT 24
Finished Jul 23 05:44:23 PM PDT 24
Peak memory 208524 kb
Host smart-366b110f-d8b3-4248-8af3-591b575ace68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993114146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.993114146
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3777965168
Short name T602
Test name
Test status
Simulation time 81601115 ps
CPU time 2.19 seconds
Started Jul 23 05:44:21 PM PDT 24
Finished Jul 23 05:44:23 PM PDT 24
Peak memory 208532 kb
Host smart-49c1c89e-0c68-4a85-bd3c-12ebd29bfe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777965168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3777965168
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3706234199
Short name T603
Test name
Test status
Simulation time 729370356 ps
CPU time 4.18 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:24 PM PDT 24
Peak memory 208452 kb
Host smart-eff0b61e-1192-4af9-ae81-150926cf1c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706234199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3706234199
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3927385662
Short name T328
Test name
Test status
Simulation time 3359057440 ps
CPU time 113.98 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 220608 kb
Host smart-f6c5a8b9-d3cf-4791-afc4-03b8bae387a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927385662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3927385662
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3052405147
Short name T210
Test name
Test status
Simulation time 200692942 ps
CPU time 3.41 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:22 PM PDT 24
Peak memory 207152 kb
Host smart-4873e9cf-7f9d-4b25-a775-ce6fddf1dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052405147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3052405147
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3773944764
Short name T192
Test name
Test status
Simulation time 90132955 ps
CPU time 2.37 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:18 PM PDT 24
Peak memory 209728 kb
Host smart-28d8f450-557f-4cd2-892b-44902dd12f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773944764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3773944764
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.645309191
Short name T476
Test name
Test status
Simulation time 54571385 ps
CPU time 0.81 seconds
Started Jul 23 05:44:35 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 205768 kb
Host smart-e1f4c06e-de72-4563-8f70-9552da261b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645309191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.645309191
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.87186266
Short name T873
Test name
Test status
Simulation time 450617887 ps
CPU time 3.76 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:44:33 PM PDT 24
Peak memory 222076 kb
Host smart-531a4de4-0f85-466b-8519-b0f45e84fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87186266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.87186266
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.293423998
Short name T358
Test name
Test status
Simulation time 221366769 ps
CPU time 3.42 seconds
Started Jul 23 05:44:27 PM PDT 24
Finished Jul 23 05:44:33 PM PDT 24
Peak memory 213948 kb
Host smart-4852c765-d3f2-4809-8266-103b2833fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293423998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.293423998
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2174622074
Short name T250
Test name
Test status
Simulation time 172542970 ps
CPU time 3.93 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 207496 kb
Host smart-2144c23a-6ed7-49de-b284-7defd73b5140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174622074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2174622074
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2077718030
Short name T510
Test name
Test status
Simulation time 640077833 ps
CPU time 4.53 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 207880 kb
Host smart-b0221aed-2ccc-4e6c-ac24-b28443f7b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077718030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2077718030
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2791565306
Short name T707
Test name
Test status
Simulation time 171922569 ps
CPU time 2.71 seconds
Started Jul 23 05:44:24 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 206548 kb
Host smart-d65f591a-1611-4c38-ab09-cb3a9a540793
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791565306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2791565306
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2104675790
Short name T375
Test name
Test status
Simulation time 3231177333 ps
CPU time 54.84 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 207924 kb
Host smart-c7116f06-d144-4d04-9f77-71b1e1f274d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104675790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2104675790
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1243531817
Short name T426
Test name
Test status
Simulation time 99315903 ps
CPU time 2.74 seconds
Started Jul 23 05:44:24 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 207984 kb
Host smart-4c9ee25c-4afa-4441-9f6c-a41e69909087
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243531817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1243531817
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2185709294
Short name T664
Test name
Test status
Simulation time 155854180 ps
CPU time 2.17 seconds
Started Jul 23 05:44:24 PM PDT 24
Finished Jul 23 05:44:30 PM PDT 24
Peak memory 208520 kb
Host smart-e14a39b3-39da-43a1-9892-c2b99578a6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185709294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2185709294
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.243924798
Short name T743
Test name
Test status
Simulation time 290403359 ps
CPU time 2.99 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:37 PM PDT 24
Peak memory 208008 kb
Host smart-2d277262-4212-46b6-8ba7-5acb6865af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243924798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.243924798
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2967626896
Short name T57
Test name
Test status
Simulation time 187054778 ps
CPU time 7.74 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:32 PM PDT 24
Peak memory 219396 kb
Host smart-ec0d766f-2879-43f8-8a4a-3e9c1c84904e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967626896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2967626896
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4052598220
Short name T692
Test name
Test status
Simulation time 141448783 ps
CPU time 6.56 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:44:36 PM PDT 24
Peak memory 207592 kb
Host smart-7503385b-6062-45af-9df6-dc2b70a986aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052598220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4052598220
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1039846215
Short name T581
Test name
Test status
Simulation time 154171419 ps
CPU time 1.62 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 209736 kb
Host smart-9e07b519-c772-422b-83df-8121b5302dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039846215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1039846215
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1868153570
Short name T453
Test name
Test status
Simulation time 14783679 ps
CPU time 0.72 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:44:55 PM PDT 24
Peak memory 205844 kb
Host smart-a75c073b-e0c8-45e9-b258-7bda323908b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868153570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1868153570
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3587766632
Short name T436
Test name
Test status
Simulation time 524379546 ps
CPU time 14.54 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:45:10 PM PDT 24
Peak memory 215524 kb
Host smart-7f17aa71-24b3-4e8e-9018-2ae256fbf1e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587766632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3587766632
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2670250517
Short name T22
Test name
Test status
Simulation time 973471104 ps
CPU time 4.96 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 222556 kb
Host smart-8d70faeb-eeca-4a58-a225-581d1a1e989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670250517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2670250517
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.735819015
Short name T83
Test name
Test status
Simulation time 39037992 ps
CPU time 2.3 seconds
Started Jul 23 05:44:49 PM PDT 24
Finished Jul 23 05:44:54 PM PDT 24
Peak memory 207140 kb
Host smart-aeea7358-1743-4b24-8c01-cb7784d22b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735819015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.735819015
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4220932070
Short name T870
Test name
Test status
Simulation time 262074094 ps
CPU time 4.12 seconds
Started Jul 23 05:44:53 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 208948 kb
Host smart-34219e32-802a-4b12-b96d-d62cda77eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220932070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4220932070
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.71519185
Short name T383
Test name
Test status
Simulation time 75947859 ps
CPU time 3.14 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:55 PM PDT 24
Peak memory 221364 kb
Host smart-7fad13e6-ddd2-41ff-adf9-d7c71e4798ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71519185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.71519185
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2309614805
Short name T224
Test name
Test status
Simulation time 343415495 ps
CPU time 4.19 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 210044 kb
Host smart-b1e57ed8-fbc6-4e05-96a4-bab5ac050c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309614805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2309614805
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3555471707
Short name T654
Test name
Test status
Simulation time 900402400 ps
CPU time 6.3 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 218224 kb
Host smart-f7b71ea4-6532-4c41-acbc-bab31b305565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555471707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3555471707
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3099796880
Short name T704
Test name
Test status
Simulation time 525076852 ps
CPU time 4.42 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:57 PM PDT 24
Peak memory 206600 kb
Host smart-37ca377c-d214-4908-ab70-55bdad49919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099796880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3099796880
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3597346325
Short name T374
Test name
Test status
Simulation time 34533269 ps
CPU time 2.38 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 206688 kb
Host smart-ed078e2d-fcb0-474e-bb04-146dd8e93755
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597346325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3597346325
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.162863196
Short name T489
Test name
Test status
Simulation time 592977290 ps
CPU time 4.03 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:57 PM PDT 24
Peak memory 206708 kb
Host smart-b2783936-9a33-4ca6-956e-55d09fe0521b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162863196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.162863196
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2356403101
Short name T830
Test name
Test status
Simulation time 41311133 ps
CPU time 1.98 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 215080 kb
Host smart-6feb05a0-b5fb-4143-8866-f8c0f1b1c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356403101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2356403101
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2138147676
Short name T629
Test name
Test status
Simulation time 72960773 ps
CPU time 2.15 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:55 PM PDT 24
Peak memory 206644 kb
Host smart-b899cd97-eab1-48f9-bbf7-b9ae61772b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138147676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2138147676
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1935923959
Short name T895
Test name
Test status
Simulation time 4870527062 ps
CPU time 35.47 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 208616 kb
Host smart-1cb1a898-92fd-4a8a-bb25-51edbfcc73a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935923959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1935923959
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.520312262
Short name T413
Test name
Test status
Simulation time 155799467 ps
CPU time 4.63 seconds
Started Jul 23 05:44:53 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 209828 kb
Host smart-49eb1c06-1bc7-46bc-9bff-3e2301a8286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520312262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.520312262
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.308055684
Short name T601
Test name
Test status
Simulation time 17843471 ps
CPU time 0.79 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:03 PM PDT 24
Peak memory 205868 kb
Host smart-f7ea49ec-7df3-4a42-b3d0-e16d42c5de6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308055684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.308055684
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.933473600
Short name T323
Test name
Test status
Simulation time 95944674 ps
CPU time 3.84 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:02 PM PDT 24
Peak memory 215308 kb
Host smart-8427f0c4-01b9-4003-99bc-68a1af015af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933473600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.933473600
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4205774430
Short name T20
Test name
Test status
Simulation time 393090377 ps
CPU time 4.73 seconds
Started Jul 23 05:45:00 PM PDT 24
Finished Jul 23 05:45:07 PM PDT 24
Peak memory 210984 kb
Host smart-a9446367-a06c-47d1-87cc-708bdea93817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205774430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4205774430
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4077788308
Short name T787
Test name
Test status
Simulation time 85312684 ps
CPU time 3.05 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 206892 kb
Host smart-1867538c-41e1-4362-b87d-1fdf448e0595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077788308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4077788308
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.387956934
Short name T794
Test name
Test status
Simulation time 207552520 ps
CPU time 5.5 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 222140 kb
Host smart-48d1b679-2665-41ba-ac27-f671dbfcc964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387956934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.387956934
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2161310099
Short name T415
Test name
Test status
Simulation time 764105908 ps
CPU time 3.59 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 207660 kb
Host smart-0a08575f-7bc3-4491-9ff8-71d136cc4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161310099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2161310099
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1604490198
Short name T887
Test name
Test status
Simulation time 6657981064 ps
CPU time 66.17 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 208924 kb
Host smart-a7347d20-5df8-4e95-9034-a2c71b6949cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604490198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1604490198
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1723807085
Short name T809
Test name
Test status
Simulation time 157170552 ps
CPU time 4.15 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 207836 kb
Host smart-8789baae-f197-4cdd-8d1a-77fc5c46c96a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723807085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1723807085
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1579449071
Short name T349
Test name
Test status
Simulation time 2027544754 ps
CPU time 39.06 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 208084 kb
Host smart-dd9f1d97-6170-4cd8-9fd4-6d36e2caa7be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579449071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1579449071
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1383887965
Short name T506
Test name
Test status
Simulation time 807962113 ps
CPU time 7.7 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 207952 kb
Host smart-69716a9b-24bd-43cc-bb06-2ea42816fabe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383887965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1383887965
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1258195074
Short name T686
Test name
Test status
Simulation time 108128468 ps
CPU time 2.07 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:02 PM PDT 24
Peak memory 217932 kb
Host smart-61324aa1-fd5e-4799-96db-7c501383288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258195074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1258195074
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2173228095
Short name T845
Test name
Test status
Simulation time 139441447 ps
CPU time 2.39 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 208432 kb
Host smart-e3d193f2-5f5f-4f27-a20f-04571ef9161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173228095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2173228095
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3598660686
Short name T909
Test name
Test status
Simulation time 251467582 ps
CPU time 4.22 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 207360 kb
Host smart-452532f0-53c3-438f-895d-d9c8de54934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598660686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3598660686
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1521594754
Short name T137
Test name
Test status
Simulation time 44029183 ps
CPU time 0.86 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 205804 kb
Host smart-f1039d42-bb16-48a5-913c-4b5e82caed48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521594754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1521594754
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1692844739
Short name T443
Test name
Test status
Simulation time 47522582 ps
CPU time 3.12 seconds
Started Jul 23 05:45:00 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 214120 kb
Host smart-6b415c1c-bc9a-41f7-9530-ab1a7ef51880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692844739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1692844739
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3551483975
Short name T737
Test name
Test status
Simulation time 513338899 ps
CPU time 6.98 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:08 PM PDT 24
Peak memory 209532 kb
Host smart-f2bd5910-b389-4b09-a28e-92fa99c43184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551483975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3551483975
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4154826586
Short name T548
Test name
Test status
Simulation time 22770103 ps
CPU time 1.41 seconds
Started Jul 23 05:44:56 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 207388 kb
Host smart-54b0ec8d-13b8-425f-ae89-b5a26cfdce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154826586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4154826586
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3047834952
Short name T648
Test name
Test status
Simulation time 80842042 ps
CPU time 2.84 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:03 PM PDT 24
Peak memory 214412 kb
Host smart-c25d138c-2a48-427d-80ef-43f191cc6580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047834952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3047834952
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2235941395
Short name T124
Test name
Test status
Simulation time 101469297 ps
CPU time 1.98 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:04 PM PDT 24
Peak memory 205868 kb
Host smart-3847db5e-6f3a-4917-bace-c128cb5863d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235941395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2235941395
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.572833174
Short name T257
Test name
Test status
Simulation time 1421150940 ps
CPU time 24.89 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 218340 kb
Host smart-b2b4023c-2464-4cf7-b030-2943f1b9b7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572833174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.572833174
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3758748626
Short name T264
Test name
Test status
Simulation time 71007978 ps
CPU time 3.2 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:04 PM PDT 24
Peak memory 208580 kb
Host smart-27ee3e77-a6af-4d81-af1b-c202ea1be988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758748626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3758748626
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.514960863
Short name T568
Test name
Test status
Simulation time 124242883 ps
CPU time 2.23 seconds
Started Jul 23 05:45:01 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 206628 kb
Host smart-d99174b9-7d89-4f9c-86b0-52effbf38906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514960863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.514960863
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3940994173
Short name T700
Test name
Test status
Simulation time 85801845 ps
CPU time 3.31 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:04 PM PDT 24
Peak memory 208176 kb
Host smart-934e4da0-6ff2-4fa5-a021-7d75fa07d321
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940994173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3940994173
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2948145509
Short name T219
Test name
Test status
Simulation time 144501126 ps
CPU time 2.45 seconds
Started Jul 23 05:45:00 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 206532 kb
Host smart-a77afc5b-a32b-4480-b3c3-ed196e8288c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948145509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2948145509
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.850691943
Short name T752
Test name
Test status
Simulation time 504654389 ps
CPU time 9.4 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:10 PM PDT 24
Peak memory 208320 kb
Host smart-185acf0b-64cc-40d3-8541-cef7ad1d3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850691943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.850691943
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2483306809
Short name T98
Test name
Test status
Simulation time 37057739 ps
CPU time 1.98 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:03 PM PDT 24
Peak memory 206408 kb
Host smart-4d7e2e93-470d-417c-9ac5-8550f0b4a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483306809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2483306809
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2256088354
Short name T315
Test name
Test status
Simulation time 9645962635 ps
CPU time 57.42 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:59 PM PDT 24
Peak memory 222372 kb
Host smart-f4395bef-eff0-4483-a4fe-0e64bbcce17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256088354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2256088354
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3637818378
Short name T414
Test name
Test status
Simulation time 823271705 ps
CPU time 16.11 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:17 PM PDT 24
Peak memory 222112 kb
Host smart-d80dc81d-3e76-41bf-b7e0-120810326995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637818378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3637818378
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.950267792
Short name T657
Test name
Test status
Simulation time 138264883 ps
CPU time 4.87 seconds
Started Jul 23 05:44:58 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 209372 kb
Host smart-26636939-2070-414b-960f-0efc2316a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950267792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.950267792
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.986161554
Short name T535
Test name
Test status
Simulation time 33901532 ps
CPU time 0.73 seconds
Started Jul 23 05:45:05 PM PDT 24
Finished Jul 23 05:45:06 PM PDT 24
Peak memory 205844 kb
Host smart-8f872f4f-7fe9-46e1-8d0e-8dedd3052fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986161554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.986161554
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2306042510
Short name T622
Test name
Test status
Simulation time 211610980 ps
CPU time 3.31 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:15 PM PDT 24
Peak memory 214000 kb
Host smart-c776eed3-c508-4ea4-bcd6-bb63f187f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306042510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2306042510
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2392050783
Short name T572
Test name
Test status
Simulation time 40616522 ps
CPU time 2.27 seconds
Started Jul 23 05:45:06 PM PDT 24
Finished Jul 23 05:45:10 PM PDT 24
Peak memory 214068 kb
Host smart-ad9f4a74-9f58-4512-b56a-d08c92345e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392050783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2392050783
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1756496809
Short name T613
Test name
Test status
Simulation time 47745940 ps
CPU time 2.89 seconds
Started Jul 23 05:45:05 PM PDT 24
Finished Jul 23 05:45:08 PM PDT 24
Peak memory 214040 kb
Host smart-fa2c36ff-6dbd-443b-94e3-04a54992111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756496809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1756496809
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1415826420
Short name T772
Test name
Test status
Simulation time 81526746 ps
CPU time 3.43 seconds
Started Jul 23 05:45:00 PM PDT 24
Finished Jul 23 05:45:06 PM PDT 24
Peak memory 208476 kb
Host smart-3d709808-ff2c-49c1-b461-e59123d21790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415826420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1415826420
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2514496297
Short name T370
Test name
Test status
Simulation time 583932553 ps
CPU time 2.6 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 208876 kb
Host smart-7f7f10e0-e3ee-4b13-a49b-254dd7dded0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514496297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2514496297
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1126501451
Short name T571
Test name
Test status
Simulation time 119235712 ps
CPU time 3.04 seconds
Started Jul 23 05:44:56 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 207004 kb
Host smart-8297fe43-d7cc-489d-83d8-6db99e0ff032
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126501451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1126501451
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2384770102
Short name T596
Test name
Test status
Simulation time 200772843 ps
CPU time 2.86 seconds
Started Jul 23 05:45:08 PM PDT 24
Finished Jul 23 05:45:12 PM PDT 24
Peak memory 208416 kb
Host smart-d8894d58-08df-47bd-8d9d-3388cd035e2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384770102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2384770102
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4250250103
Short name T322
Test name
Test status
Simulation time 254702446 ps
CPU time 3.24 seconds
Started Jul 23 05:45:07 PM PDT 24
Finished Jul 23 05:45:12 PM PDT 24
Peak memory 209592 kb
Host smart-179ef3da-67c8-4a4a-8042-0995e2402120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250250103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4250250103
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1647339331
Short name T626
Test name
Test status
Simulation time 625700009 ps
CPU time 10.67 seconds
Started Jul 23 05:44:59 PM PDT 24
Finished Jul 23 05:45:13 PM PDT 24
Peak memory 207928 kb
Host smart-c279c402-3ccb-477a-a2f5-33f7489b3070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647339331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1647339331
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4205482541
Short name T698
Test name
Test status
Simulation time 701304313 ps
CPU time 17.84 seconds
Started Jul 23 05:45:07 PM PDT 24
Finished Jul 23 05:45:26 PM PDT 24
Peak memory 222300 kb
Host smart-96237bce-c4c0-45c2-9dc7-85eb001e6d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205482541 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4205482541
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2433284125
Short name T26
Test name
Test status
Simulation time 111346883 ps
CPU time 4.61 seconds
Started Jul 23 05:45:07 PM PDT 24
Finished Jul 23 05:45:14 PM PDT 24
Peak memory 207164 kb
Host smart-62843f4c-e876-40fe-89f0-5a42ba674f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433284125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2433284125
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3427181330
Short name T187
Test name
Test status
Simulation time 122892085 ps
CPU time 2.06 seconds
Started Jul 23 05:45:05 PM PDT 24
Finished Jul 23 05:45:08 PM PDT 24
Peak memory 209832 kb
Host smart-aec909e0-e88e-480b-a264-d49f668b167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427181330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3427181330
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2225473410
Short name T477
Test name
Test status
Simulation time 11790064 ps
CPU time 0.83 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:14 PM PDT 24
Peak memory 205808 kb
Host smart-be8fdb76-bb20-43c0-892e-8e8c3e2748f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225473410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2225473410
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1139136989
Short name T30
Test name
Test status
Simulation time 228527572 ps
CPU time 6.17 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 214056 kb
Host smart-775ab438-a209-4734-ad3a-9db90b87e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139136989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1139136989
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3634701183
Short name T314
Test name
Test status
Simulation time 41173719 ps
CPU time 2.51 seconds
Started Jul 23 05:45:16 PM PDT 24
Finished Jul 23 05:45:20 PM PDT 24
Peak memory 214028 kb
Host smart-af0a059d-8ee5-462d-acb0-3bacdb6ed98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634701183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3634701183
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2635671331
Short name T272
Test name
Test status
Simulation time 59543858 ps
CPU time 2.9 seconds
Started Jul 23 05:45:13 PM PDT 24
Finished Jul 23 05:45:18 PM PDT 24
Peak memory 205792 kb
Host smart-7ff961ed-39e8-471f-91f6-f34d0d91d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635671331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2635671331
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.3134679948
Short name T429
Test name
Test status
Simulation time 801151822 ps
CPU time 6.33 seconds
Started Jul 23 05:45:02 PM PDT 24
Finished Jul 23 05:45:10 PM PDT 24
Peak memory 214100 kb
Host smart-40b4ab04-72c9-4d05-9dd9-06d6b47cae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134679948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3134679948
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.72484531
Short name T473
Test name
Test status
Simulation time 197731624 ps
CPU time 2.77 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:15 PM PDT 24
Peak memory 206552 kb
Host smart-404c8f55-6329-45f7-a6ee-7f9a8303500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72484531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.72484531
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3895259162
Short name T855
Test name
Test status
Simulation time 784677981 ps
CPU time 3.75 seconds
Started Jul 23 05:45:04 PM PDT 24
Finished Jul 23 05:45:08 PM PDT 24
Peak memory 208640 kb
Host smart-d57ef506-ae29-48e0-9e18-a7a3e31300ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895259162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3895259162
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2816871559
Short name T545
Test name
Test status
Simulation time 2291706083 ps
CPU time 39.36 seconds
Started Jul 23 05:45:06 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 208080 kb
Host smart-be2a2662-adba-4fbd-a0e2-37c8f7d20a3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816871559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2816871559
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4106363085
Short name T829
Test name
Test status
Simulation time 195279225 ps
CPU time 5.17 seconds
Started Jul 23 05:45:05 PM PDT 24
Finished Jul 23 05:45:12 PM PDT 24
Peak memory 208764 kb
Host smart-18d1eb2a-26c7-46a4-ae58-8a4d85fec447
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106363085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4106363085
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.753822057
Short name T294
Test name
Test status
Simulation time 368485433 ps
CPU time 3.1 seconds
Started Jul 23 05:45:15 PM PDT 24
Finished Jul 23 05:45:20 PM PDT 24
Peak memory 209576 kb
Host smart-bb8ac846-ce35-4a8f-b5de-6f357f3cef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753822057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.753822057
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.4271761500
Short name T579
Test name
Test status
Simulation time 800540830 ps
CPU time 16.82 seconds
Started Jul 23 05:45:07 PM PDT 24
Finished Jul 23 05:45:26 PM PDT 24
Peak memory 207876 kb
Host smart-43309f6a-f06d-4134-8589-ac0def800292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271761500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.4271761500
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.393472166
Short name T62
Test name
Test status
Simulation time 1150563817 ps
CPU time 9.08 seconds
Started Jul 23 05:45:08 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 220872 kb
Host smart-f24f3b51-f330-45f3-bd22-ff26ca41e046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393472166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.393472166
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1160182659
Short name T380
Test name
Test status
Simulation time 2509940403 ps
CPU time 17.79 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 209344 kb
Host smart-2c807a59-2f4b-45b1-8467-0281cca202c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160182659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1160182659
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2077034325
Short name T662
Test name
Test status
Simulation time 29183059 ps
CPU time 1.94 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:15 PM PDT 24
Peak memory 209660 kb
Host smart-e6d46327-10b4-400b-8efd-5ed44d25f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077034325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2077034325
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3846477314
Short name T555
Test name
Test status
Simulation time 45944493 ps
CPU time 0.84 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:13 PM PDT 24
Peak memory 205828 kb
Host smart-6f748951-5111-4e36-8ffc-6e0c52f9b2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846477314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3846477314
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1358049051
Short name T31
Test name
Test status
Simulation time 397847626 ps
CPU time 2.97 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 214148 kb
Host smart-ff595779-0558-444b-a2da-94080c927365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358049051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1358049051
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2211731570
Short name T719
Test name
Test status
Simulation time 71975008 ps
CPU time 1.38 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:17 PM PDT 24
Peak memory 206224 kb
Host smart-61a23fc1-e56e-4945-be26-b2f9869feaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211731570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2211731570
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3138159514
Short name T333
Test name
Test status
Simulation time 87281311 ps
CPU time 2.92 seconds
Started Jul 23 05:45:16 PM PDT 24
Finished Jul 23 05:45:20 PM PDT 24
Peak memory 214064 kb
Host smart-bdb96105-e5f8-46d6-b7ff-82890180b527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138159514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3138159514
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3562117536
Short name T51
Test name
Test status
Simulation time 120448409 ps
CPU time 2.03 seconds
Started Jul 23 05:45:15 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 205776 kb
Host smart-0ff5ccc7-a424-44e9-8489-0ba24755d6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562117536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3562117536
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3625301974
Short name T54
Test name
Test status
Simulation time 354026439 ps
CPU time 2.94 seconds
Started Jul 23 05:45:13 PM PDT 24
Finished Jul 23 05:45:18 PM PDT 24
Peak memory 219912 kb
Host smart-24bfb5df-356b-413d-bf69-8523e97473fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625301974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3625301974
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3535566810
Short name T917
Test name
Test status
Simulation time 365961398 ps
CPU time 11.89 seconds
Started Jul 23 05:45:15 PM PDT 24
Finished Jul 23 05:45:29 PM PDT 24
Peak memory 207664 kb
Host smart-e967d37c-c919-4842-8202-4d660c7c1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535566810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3535566810
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.312992584
Short name T563
Test name
Test status
Simulation time 62774964 ps
CPU time 3.22 seconds
Started Jul 23 05:45:16 PM PDT 24
Finished Jul 23 05:45:21 PM PDT 24
Peak memory 206612 kb
Host smart-7dd1b6ce-a061-43a3-8b70-844da6a2ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312992584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.312992584
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.769640980
Short name T778
Test name
Test status
Simulation time 977618944 ps
CPU time 12.66 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:33 PM PDT 24
Peak memory 208200 kb
Host smart-7a7ae76e-a600-4a01-ae7b-8debc440016d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769640980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.769640980
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1209112783
Short name T843
Test name
Test status
Simulation time 123764657 ps
CPU time 4.31 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:17 PM PDT 24
Peak memory 208296 kb
Host smart-5b35e9ae-3be5-4535-9b42-1f31bc85a7c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209112783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1209112783
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1919635989
Short name T729
Test name
Test status
Simulation time 1896867018 ps
CPU time 17.21 seconds
Started Jul 23 05:45:13 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 208024 kb
Host smart-8261c3b5-94d0-4b61-9b08-0219e7d1cccb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919635989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1919635989
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.372432442
Short name T120
Test name
Test status
Simulation time 61546677 ps
CPU time 2.24 seconds
Started Jul 23 05:45:15 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 214156 kb
Host smart-c0c113f7-667b-4dad-abe1-eb40dfbb4daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372432442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.372432442
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.640801070
Short name T709
Test name
Test status
Simulation time 439781543 ps
CPU time 2.9 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 205832 kb
Host smart-5df26f4b-ac32-4fd8-a2b4-a219e83d1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640801070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.640801070
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.538663660
Short name T386
Test name
Test status
Simulation time 338680095 ps
CPU time 21.02 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:34 PM PDT 24
Peak memory 222724 kb
Host smart-e6dd1883-d64c-498e-993a-b9bbee9e3100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538663660 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.538663660
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.135779262
Short name T768
Test name
Test status
Simulation time 33538666 ps
CPU time 2.43 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:14 PM PDT 24
Peak memory 207248 kb
Host smart-0d6d5d98-8160-4ca3-b12f-87fa9806b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135779262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.135779262
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1249287841
Short name T795
Test name
Test status
Simulation time 129044749 ps
CPU time 2.85 seconds
Started Jul 23 05:45:13 PM PDT 24
Finished Jul 23 05:45:17 PM PDT 24
Peak memory 209704 kb
Host smart-c60e0f65-e6c7-4f4c-bbfa-fb330bfcf1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249287841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1249287841
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3643585801
Short name T462
Test name
Test status
Simulation time 70975557 ps
CPU time 0.77 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 205816 kb
Host smart-42e1ad22-dd9e-491c-9af0-f005c4f7db96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643585801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3643585801
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2215787359
Short name T379
Test name
Test status
Simulation time 29376527 ps
CPU time 2.21 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:16 PM PDT 24
Peak memory 214044 kb
Host smart-d491f4bf-0c05-42f8-9922-d2ba225a074f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215787359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2215787359
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.746236199
Short name T76
Test name
Test status
Simulation time 40555213 ps
CPU time 1.52 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:15 PM PDT 24
Peak memory 214052 kb
Host smart-8062e687-ce36-4ef1-8606-d79380524107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746236199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.746236199
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.808976336
Short name T102
Test name
Test status
Simulation time 1244753508 ps
CPU time 7.07 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 222104 kb
Host smart-c56d00ff-9e88-44a2-b68c-951ead1f7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808976336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.808976336
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.133915806
Short name T270
Test name
Test status
Simulation time 100425836 ps
CPU time 3.43 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 222060 kb
Host smart-904da9a2-26be-47a4-863d-864f5f9b32df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133915806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.133915806
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3392180038
Short name T221
Test name
Test status
Simulation time 1042205651 ps
CPU time 14.34 seconds
Started Jul 23 05:45:18 PM PDT 24
Finished Jul 23 05:45:34 PM PDT 24
Peak memory 209132 kb
Host smart-73c8e71c-5096-4bac-bc85-86308ee38831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392180038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3392180038
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3490315288
Short name T913
Test name
Test status
Simulation time 238603193 ps
CPU time 4.15 seconds
Started Jul 23 05:45:11 PM PDT 24
Finished Jul 23 05:45:16 PM PDT 24
Peak memory 217640 kb
Host smart-d68cda06-7aa5-4c0a-88f6-03c7b709792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490315288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3490315288
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1429062853
Short name T550
Test name
Test status
Simulation time 110357662 ps
CPU time 4.16 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:18 PM PDT 24
Peak memory 206556 kb
Host smart-f55003f9-092f-48b7-b034-738f28ff9b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429062853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1429062853
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.654544478
Short name T341
Test name
Test status
Simulation time 1495081270 ps
CPU time 6.79 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 208824 kb
Host smart-1a177a50-e286-42de-98a7-6eac48e401ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654544478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.654544478
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3933135821
Short name T764
Test name
Test status
Simulation time 303454776 ps
CPU time 2.68 seconds
Started Jul 23 05:45:13 PM PDT 24
Finished Jul 23 05:45:18 PM PDT 24
Peak memory 208680 kb
Host smart-c9279623-d304-4e4a-8695-c0e74ddff23b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933135821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3933135821
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2429829672
Short name T633
Test name
Test status
Simulation time 173021332 ps
CPU time 3.87 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 208424 kb
Host smart-f9c44c1f-f135-40a7-9f7d-ecdeed51fe4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429829672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2429829672
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2802269454
Short name T738
Test name
Test status
Simulation time 87844050 ps
CPU time 2.6 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 207764 kb
Host smart-e1e96391-ec8b-4a54-87cf-eb875a69ed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802269454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2802269454
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.258195022
Short name T468
Test name
Test status
Simulation time 148484029 ps
CPU time 2.62 seconds
Started Jul 23 05:45:12 PM PDT 24
Finished Jul 23 05:45:17 PM PDT 24
Peak memory 206400 kb
Host smart-9a3962d4-bc6e-4f71-87c6-9f9a06944230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258195022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.258195022
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.501919811
Short name T732
Test name
Test status
Simulation time 1428769761 ps
CPU time 31.22 seconds
Started Jul 23 05:45:23 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 215416 kb
Host smart-fe88f479-320f-4204-9675-3776e07271d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501919811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.501919811
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1302244216
Short name T180
Test name
Test status
Simulation time 1350005528 ps
CPU time 12.64 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:34 PM PDT 24
Peak memory 218280 kb
Host smart-40ca1640-2506-4e06-b5a8-61d202a3655c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302244216 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1302244216
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1695902882
Short name T769
Test name
Test status
Simulation time 199892179 ps
CPU time 3.76 seconds
Started Jul 23 05:45:14 PM PDT 24
Finished Jul 23 05:45:20 PM PDT 24
Peak memory 207348 kb
Host smart-0eab462b-78e0-4fd4-bfa4-601a94b7c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695902882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1695902882
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1575304622
Short name T791
Test name
Test status
Simulation time 444681293 ps
CPU time 4.21 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:26 PM PDT 24
Peak memory 210688 kb
Host smart-95409df1-3b52-4068-bcf5-57a9195efc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575304622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1575304622
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3053996932
Short name T553
Test name
Test status
Simulation time 41518252 ps
CPU time 0.9 seconds
Started Jul 23 05:45:18 PM PDT 24
Finished Jul 23 05:45:19 PM PDT 24
Peak memory 205840 kb
Host smart-863f6076-3eb9-498b-8254-632125935ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053996932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3053996932
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2490196508
Short name T440
Test name
Test status
Simulation time 426651747 ps
CPU time 10.35 seconds
Started Jul 23 05:45:24 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 215592 kb
Host smart-f630d369-0017-49a8-b23a-b950d20ff1bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490196508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2490196508
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1885129898
Short name T911
Test name
Test status
Simulation time 211478836 ps
CPU time 6.01 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:27 PM PDT 24
Peak memory 222628 kb
Host smart-2b8cc3f6-223b-4a7f-9d99-c0452266dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885129898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1885129898
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.960136971
Short name T808
Test name
Test status
Simulation time 53883403 ps
CPU time 2.93 seconds
Started Jul 23 05:45:24 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 207372 kb
Host smart-c665c30d-5e28-44ad-a3dd-fea0d8d42db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960136971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.960136971
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.662202706
Short name T110
Test name
Test status
Simulation time 5823524947 ps
CPU time 40.45 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:46:01 PM PDT 24
Peak memory 222320 kb
Host smart-c73fa6ab-9b04-442b-8438-a81d9095551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662202706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.662202706
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.306915971
Short name T403
Test name
Test status
Simulation time 99553160 ps
CPU time 2.23 seconds
Started Jul 23 05:45:21 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 211484 kb
Host smart-67d9650b-0745-45f0-a8b8-f1642a51db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306915971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.306915971
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2173806462
Short name T239
Test name
Test status
Simulation time 203029388 ps
CPU time 5.17 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:27 PM PDT 24
Peak memory 222088 kb
Host smart-afc81344-22a7-4d81-b5e5-cb0d5ad082ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173806462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2173806462
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2401048548
Short name T395
Test name
Test status
Simulation time 974876821 ps
CPU time 2.84 seconds
Started Jul 23 05:45:24 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 206996 kb
Host smart-cbc4140f-765a-4e59-9c29-db3b2455b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401048548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2401048548
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3147235858
Short name T919
Test name
Test status
Simulation time 95262435 ps
CPU time 3.31 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 208516 kb
Host smart-bffb61d3-f03f-439d-9389-f9c1e56dfd66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147235858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3147235858
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3013511620
Short name T652
Test name
Test status
Simulation time 23068179 ps
CPU time 1.83 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 206672 kb
Host smart-8ee9a5c0-42ed-4bf1-b43e-440f008e474d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013511620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3013511620
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1168156361
Short name T422
Test name
Test status
Simulation time 3061809550 ps
CPU time 9.16 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 208732 kb
Host smart-b75a7100-d8ee-47be-81c2-5cae5fe7c535
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168156361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1168156361
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4173094742
Short name T681
Test name
Test status
Simulation time 6373265316 ps
CPU time 31.74 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:53 PM PDT 24
Peak memory 208308 kb
Host smart-e944e342-72b8-48c0-a400-b140e9e91138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173094742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4173094742
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2331819008
Short name T659
Test name
Test status
Simulation time 305031033 ps
CPU time 3.7 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 207524 kb
Host smart-65c1a731-968a-4d0f-8672-ce4a1017d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331819008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2331819008
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1667058511
Short name T153
Test name
Test status
Simulation time 40014359 ps
CPU time 2.18 seconds
Started Jul 23 05:45:23 PM PDT 24
Finished Jul 23 05:45:27 PM PDT 24
Peak memory 210000 kb
Host smart-d6a3b392-7053-4b74-a731-370ee007434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667058511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1667058511
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.844344694
Short name T514
Test name
Test status
Simulation time 10792434 ps
CPU time 0.7 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 205856 kb
Host smart-46e756f3-3407-49f7-a80a-602a89df82db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844344694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.844344694
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.161978752
Short name T220
Test name
Test status
Simulation time 135883212 ps
CPU time 6.19 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:39 PM PDT 24
Peak memory 222512 kb
Host smart-7901fad6-cb2e-447c-bdf4-da8a256128a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161978752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.161978752
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2212888939
Short name T60
Test name
Test status
Simulation time 121890407 ps
CPU time 3.06 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 208456 kb
Host smart-16a3297e-bc50-4a06-a6d6-c12a41297c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212888939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2212888939
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1765817265
Short name T335
Test name
Test status
Simulation time 317749380 ps
CPU time 1.89 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 214060 kb
Host smart-a0a2fa14-d577-4fc1-8ff9-564042b7db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765817265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1765817265
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3884705513
Short name T94
Test name
Test status
Simulation time 28642962 ps
CPU time 1.68 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 214000 kb
Host smart-8d83d1c2-754a-45b1-905f-0dad37e415ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884705513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3884705513
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2685128029
Short name T678
Test name
Test status
Simulation time 59855512 ps
CPU time 1.92 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 214356 kb
Host smart-efd6d393-165d-4f3f-9d44-e226163b36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685128029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2685128029
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.5555714
Short name T385
Test name
Test status
Simulation time 4187554845 ps
CPU time 27.08 seconds
Started Jul 23 05:45:22 PM PDT 24
Finished Jul 23 05:45:51 PM PDT 24
Peak memory 218132 kb
Host smart-b1d1d833-0bce-4b71-8470-68590c83ca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5555714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.5555714
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1965241794
Short name T841
Test name
Test status
Simulation time 108576546 ps
CPU time 3.8 seconds
Started Jul 23 05:45:22 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 206676 kb
Host smart-d1581288-4bc2-42da-a577-847451aced5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965241794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1965241794
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2169840396
Short name T631
Test name
Test status
Simulation time 115104223 ps
CPU time 2.32 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 206576 kb
Host smart-2bb218c6-5515-434d-98bf-68d1ccb8ec1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169840396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2169840396
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3436998533
Short name T530
Test name
Test status
Simulation time 29608171 ps
CPU time 2.19 seconds
Started Jul 23 05:45:19 PM PDT 24
Finished Jul 23 05:45:22 PM PDT 24
Peak memory 206580 kb
Host smart-e38b0f69-6cc6-43e3-9c51-abca6d836827
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436998533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3436998533
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1035353410
Short name T813
Test name
Test status
Simulation time 46812415 ps
CPU time 2.72 seconds
Started Jul 23 05:45:18 PM PDT 24
Finished Jul 23 05:45:22 PM PDT 24
Peak memory 208344 kb
Host smart-070eed6d-c605-4e2f-92e5-fb0fc975cdec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035353410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1035353410
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3258153915
Short name T303
Test name
Test status
Simulation time 97501884 ps
CPU time 4.15 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:37 PM PDT 24
Peak memory 217976 kb
Host smart-bbedeb9b-0c5d-438a-a00c-139cf01d1949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258153915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3258153915
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.71847344
Short name T521
Test name
Test status
Simulation time 1845881918 ps
CPU time 18.88 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 208116 kb
Host smart-63812e93-32a3-4e17-a262-3e17af480ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71847344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.71847344
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3656216862
Short name T278
Test name
Test status
Simulation time 1754292440 ps
CPU time 23.28 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 215692 kb
Host smart-6b0c4eb2-978e-4264-b51e-c5d67e8f0d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656216862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3656216862
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4187566385
Short name T471
Test name
Test status
Simulation time 1060081294 ps
CPU time 18.68 seconds
Started Jul 23 05:45:18 PM PDT 24
Finished Jul 23 05:45:38 PM PDT 24
Peak memory 208612 kb
Host smart-0a4f7f2d-e025-482d-b409-439acfedf131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187566385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4187566385
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.878391497
Short name T160
Test name
Test status
Simulation time 144749174 ps
CPU time 1.85 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 209620 kb
Host smart-c19e4692-3ae4-4b0c-9f5b-91a97fb3ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878391497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.878391497
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2254801494
Short name T835
Test name
Test status
Simulation time 9977107 ps
CPU time 0.83 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 205848 kb
Host smart-41868967-acba-4397-a956-2619ee989c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254801494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2254801494
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.154065940
Short name T397
Test name
Test status
Simulation time 180644002 ps
CPU time 3.58 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 214152 kb
Host smart-49083ebc-3924-405b-b0a6-e9a1335c18dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154065940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.154065940
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4283828607
Short name T543
Test name
Test status
Simulation time 2123031393 ps
CPU time 5.3 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 214356 kb
Host smart-36914d15-f472-463d-a996-aabf64633e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283828607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4283828607
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1183855953
Short name T421
Test name
Test status
Simulation time 247384902 ps
CPU time 3.59 seconds
Started Jul 23 05:45:32 PM PDT 24
Finished Jul 23 05:45:38 PM PDT 24
Peak memory 213956 kb
Host smart-aaf2069c-dad2-40e9-a8a7-e2cf3869fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183855953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1183855953
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3067640844
Short name T359
Test name
Test status
Simulation time 156162039 ps
CPU time 2.74 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 222144 kb
Host smart-fbd9efb8-63c5-4e6e-bd62-cdd6830ff39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067640844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3067640844
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.575353715
Short name T238
Test name
Test status
Simulation time 256496112 ps
CPU time 3.22 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 209016 kb
Host smart-f0a6cd3c-9360-41d6-a4e1-c8367e6c385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575353715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.575353715
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3147007037
Short name T590
Test name
Test status
Simulation time 1960567545 ps
CPU time 8.56 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:42 PM PDT 24
Peak memory 222292 kb
Host smart-7e689b2a-ae4c-4b9f-8bad-413a969eb804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147007037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3147007037
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2963664992
Short name T198
Test name
Test status
Simulation time 31469018 ps
CPU time 2.33 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 207028 kb
Host smart-ed7d0169-2389-4f87-b72f-f65137cc8aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963664992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2963664992
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1520439166
Short name T566
Test name
Test status
Simulation time 156574018 ps
CPU time 2.37 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 206720 kb
Host smart-e4d738b4-6605-49bc-bac5-a8bd68210170
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520439166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1520439166
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1834609095
Short name T594
Test name
Test status
Simulation time 320493578 ps
CPU time 3.46 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 208708 kb
Host smart-6ef95c6d-48e1-4137-ba5e-376f116c7eb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834609095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1834609095
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.495836135
Short name T717
Test name
Test status
Simulation time 519049452 ps
CPU time 3.04 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 206636 kb
Host smart-a857a7ef-1e89-43de-a1b9-83a12e6d96db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495836135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.495836135
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2856396675
Short name T774
Test name
Test status
Simulation time 89192355 ps
CPU time 1.95 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 207356 kb
Host smart-b4f60f4a-decc-423c-9139-0db61e530716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856396675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2856396675
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3771423393
Short name T817
Test name
Test status
Simulation time 180729941 ps
CPU time 3.02 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 206648 kb
Host smart-1eb340c8-c44a-49a8-9226-ae388e44098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771423393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3771423393
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.317861237
Short name T483
Test name
Test status
Simulation time 2164760963 ps
CPU time 60.49 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:46:33 PM PDT 24
Peak memory 208536 kb
Host smart-5d93985c-8f02-4c35-a945-48f9f2bc9df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317861237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.317861237
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.433649707
Short name T879
Test name
Test status
Simulation time 113341608 ps
CPU time 7.41 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:39 PM PDT 24
Peak memory 219940 kb
Host smart-863d1b44-4568-4eab-b045-c73426ba0c62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433649707 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.433649707
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3884336355
Short name T247
Test name
Test status
Simulation time 494881577 ps
CPU time 8.09 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:39 PM PDT 24
Peak memory 209516 kb
Host smart-d09c5833-24d6-4fbe-aaed-31d69000b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884336355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3884336355
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1371776728
Short name T798
Test name
Test status
Simulation time 150312819 ps
CPU time 2.69 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 210232 kb
Host smart-8b2de271-1a9b-40cb-9c16-f3bdc12e824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371776728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1371776728
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4140374247
Short name T884
Test name
Test status
Simulation time 33038682 ps
CPU time 0.71 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 205848 kb
Host smart-d6651806-3776-4bdb-9f6c-f70dbc3bf3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140374247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4140374247
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2157589324
Short name T424
Test name
Test status
Simulation time 53084509 ps
CPU time 2.19 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 208060 kb
Host smart-7e0b3453-7016-4c16-9d94-8da41ce8eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157589324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2157589324
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1789847481
Short name T766
Test name
Test status
Simulation time 401695699 ps
CPU time 3.69 seconds
Started Jul 23 05:44:27 PM PDT 24
Finished Jul 23 05:44:34 PM PDT 24
Peak memory 218480 kb
Host smart-4f5ce06b-c031-41a1-a3bd-8f828b53d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789847481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1789847481
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1805912117
Short name T281
Test name
Test status
Simulation time 225840095 ps
CPU time 3.87 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 208668 kb
Host smart-b0140aeb-583d-4a88-8a0c-4aa61bffd810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805912117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1805912117
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3108913491
Short name T13
Test name
Test status
Simulation time 438045759 ps
CPU time 9.89 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 230720 kb
Host smart-a1c21f75-5865-4d23-9288-6de312b513cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108913491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3108913491
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3566145556
Short name T609
Test name
Test status
Simulation time 433221150 ps
CPU time 3.24 seconds
Started Jul 23 05:44:23 PM PDT 24
Finished Jul 23 05:44:30 PM PDT 24
Peak memory 208380 kb
Host smart-efc26a0c-509f-4c59-acc9-cf7d39f6fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566145556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3566145556
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2404326776
Short name T810
Test name
Test status
Simulation time 127690127 ps
CPU time 3.73 seconds
Started Jul 23 05:44:22 PM PDT 24
Finished Jul 23 05:44:28 PM PDT 24
Peak memory 207564 kb
Host smart-ea665d82-9dc1-42dc-bdad-c0c198ef7013
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404326776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2404326776
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1942385391
Short name T716
Test name
Test status
Simulation time 150152686 ps
CPU time 2.96 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:44:32 PM PDT 24
Peak memory 206652 kb
Host smart-87d3a015-c101-45fa-a832-68d7448a715b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942385391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1942385391
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3185025630
Short name T119
Test name
Test status
Simulation time 229695928 ps
CPU time 3.39 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:44:32 PM PDT 24
Peak memory 206676 kb
Host smart-36032479-4015-4c5a-a81c-dd9c3e1192f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185025630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3185025630
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1233228824
Short name T416
Test name
Test status
Simulation time 149375466 ps
CPU time 2.02 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:37 PM PDT 24
Peak memory 208692 kb
Host smart-62028520-a492-49ce-bde9-8f3c7cc91e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233228824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1233228824
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.724465083
Short name T643
Test name
Test status
Simulation time 63306513 ps
CPU time 2.89 seconds
Started Jul 23 05:44:25 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 208404 kb
Host smart-43422dec-eb9e-4b6d-b6b9-aba438f36f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724465083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.724465083
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.285099458
Short name T420
Test name
Test status
Simulation time 210396333 ps
CPU time 8.5 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 215960 kb
Host smart-f51e5964-ec64-421b-a7f8-2084cedcc18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285099458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.285099458
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1956424301
Short name T97
Test name
Test status
Simulation time 525467619 ps
CPU time 8.35 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 222328 kb
Host smart-522ed43a-a62f-43a4-b852-773877106374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956424301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1956424301
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.518328362
Short name T646
Test name
Test status
Simulation time 41143010 ps
CPU time 2.68 seconds
Started Jul 23 05:44:24 PM PDT 24
Finished Jul 23 05:44:31 PM PDT 24
Peak memory 208044 kb
Host smart-a7503ce9-86d8-4e9e-a178-b5569afbf476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518328362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.518328362
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3038586630
Short name T59
Test name
Test status
Simulation time 262479475 ps
CPU time 2.92 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 210224 kb
Host smart-ea673767-d6b1-4c0f-8459-700db7e5ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038586630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3038586630
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3734067548
Short name T466
Test name
Test status
Simulation time 23699467 ps
CPU time 0.89 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 205828 kb
Host smart-38d7d729-883c-478e-9dd6-2153d83a1a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734067548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3734067548
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2340893263
Short name T268
Test name
Test status
Simulation time 171099261 ps
CPU time 1.86 seconds
Started Jul 23 05:45:39 PM PDT 24
Finished Jul 23 05:45:42 PM PDT 24
Peak memory 214424 kb
Host smart-c85db695-1e6d-4b79-ae99-45207df24dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340893263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2340893263
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1697614272
Short name T811
Test name
Test status
Simulation time 40342211 ps
CPU time 1.21 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 206332 kb
Host smart-3905aa3b-91ee-4101-b742-af2db789757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697614272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1697614272
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4168287539
Short name T611
Test name
Test status
Simulation time 96765314 ps
CPU time 2.87 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 214064 kb
Host smart-8a92fa99-f5fd-46dc-98bb-ada9e3b3627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168287539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4168287539
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.4232653102
Short name T597
Test name
Test status
Simulation time 229173308 ps
CPU time 2.16 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 214008 kb
Host smart-c8d2c330-0258-4ecd-ab2a-e491a0e170fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232653102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.4232653102
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2277433002
Short name T498
Test name
Test status
Simulation time 306694920 ps
CPU time 9.66 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:52 PM PDT 24
Peak memory 222332 kb
Host smart-8cace0e5-6ac1-4f2e-b490-17752d6b3ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277433002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2277433002
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1598320910
Short name T904
Test name
Test status
Simulation time 830952591 ps
CPU time 12.19 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 209304 kb
Host smart-04da51aa-99f0-480e-a6a9-13619af13d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598320910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1598320910
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3167142871
Short name T204
Test name
Test status
Simulation time 597956551 ps
CPU time 5.46 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:33 PM PDT 24
Peak memory 208232 kb
Host smart-42869304-526d-47db-b254-20f6adc4f468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167142871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3167142871
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1041636252
Short name T381
Test name
Test status
Simulation time 894604408 ps
CPU time 6.26 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:37 PM PDT 24
Peak memory 208280 kb
Host smart-12fc6b8d-0ac3-4098-9b02-3e1d14f80310
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041636252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1041636252
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1447001502
Short name T599
Test name
Test status
Simulation time 217835833 ps
CPU time 3.04 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:36 PM PDT 24
Peak memory 208356 kb
Host smart-a0d51064-ee97-4bf1-b53d-07a290f8fead
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447001502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1447001502
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1493316186
Short name T527
Test name
Test status
Simulation time 59433359 ps
CPU time 2.85 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:34 PM PDT 24
Peak memory 207660 kb
Host smart-d40eee35-dcc9-4d76-82cf-7ba49f9462a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493316186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1493316186
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3548662582
Short name T915
Test name
Test status
Simulation time 254902281 ps
CPU time 2.67 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 217968 kb
Host smart-7eef6cb3-7a66-43d4-8ed5-6a2905078927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548662582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3548662582
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1570993047
Short name T537
Test name
Test status
Simulation time 184780660 ps
CPU time 2.54 seconds
Started Jul 23 05:45:26 PM PDT 24
Finished Jul 23 05:45:29 PM PDT 24
Peak memory 206552 kb
Host smart-0f13e434-71ad-442f-a380-59b46d3339e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570993047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1570993047
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2620259347
Short name T277
Test name
Test status
Simulation time 504087218 ps
CPU time 22.21 seconds
Started Jul 23 05:45:42 PM PDT 24
Finished Jul 23 05:46:06 PM PDT 24
Peak memory 216212 kb
Host smart-69a3a196-31d9-47dd-be1c-07c28f3082c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620259347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2620259347
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3377287495
Short name T96
Test name
Test status
Simulation time 730309423 ps
CPU time 4.98 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:48 PM PDT 24
Peak memory 207064 kb
Host smart-f99b876a-172d-48f0-8817-21f7a2a3a228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377287495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3377287495
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3987822148
Short name T169
Test name
Test status
Simulation time 315910404 ps
CPU time 1.95 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 210004 kb
Host smart-95d842aa-74d0-4126-bc8e-0120afa3e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987822148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3987822148
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.629864746
Short name T783
Test name
Test status
Simulation time 42214978 ps
CPU time 0.86 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 205836 kb
Host smart-1e456073-49cb-4920-8fe5-313181f7eb11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629864746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.629864746
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3593503102
Short name T298
Test name
Test status
Simulation time 50987325 ps
CPU time 3.45 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 215024 kb
Host smart-9dfa4e2d-7116-40d1-8498-d127fb16549d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593503102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3593503102
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2367984283
Short name T802
Test name
Test status
Simulation time 120135136 ps
CPU time 2.22 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 218084 kb
Host smart-50f6174b-b763-43ec-b353-6464fb2d63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367984283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2367984283
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3676822453
Short name T683
Test name
Test status
Simulation time 95202394 ps
CPU time 3.93 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 209028 kb
Host smart-ddff4818-6b70-4232-901c-0557a1fdd579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676822453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3676822453
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3936224946
Short name T362
Test name
Test status
Simulation time 60059240 ps
CPU time 2.47 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:54 PM PDT 24
Peak memory 214088 kb
Host smart-984cbc94-ed8b-435e-87a0-7e0e62950966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936224946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3936224946
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1148303469
Short name T482
Test name
Test status
Simulation time 509040341 ps
CPU time 2.16 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 211024 kb
Host smart-213cf009-6dd4-416d-9459-a4207176cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148303469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1148303469
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2512520989
Short name T660
Test name
Test status
Simulation time 71532764 ps
CPU time 3.02 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 222140 kb
Host smart-044cafa5-a3b7-4765-8dcc-b2edae06cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512520989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2512520989
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.314358025
Short name T749
Test name
Test status
Simulation time 119525185 ps
CPU time 3.17 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 208716 kb
Host smart-1459cd30-2484-4abb-9b4f-7e599c9cf508
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314358025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.314358025
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.47790402
Short name T118
Test name
Test status
Simulation time 109462488 ps
CPU time 3.57 seconds
Started Jul 23 05:45:44 PM PDT 24
Finished Jul 23 05:45:49 PM PDT 24
Peak memory 206712 kb
Host smart-3e5398c5-256e-40fe-abd4-f67e8519c2b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47790402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.47790402
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3355267083
Short name T753
Test name
Test status
Simulation time 100490039 ps
CPU time 3.56 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 206668 kb
Host smart-552755fc-d49a-4435-a20d-4385508cdb2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355267083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3355267083
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4178336831
Short name T675
Test name
Test status
Simulation time 49920155 ps
CPU time 2.65 seconds
Started Jul 23 05:45:55 PM PDT 24
Finished Jul 23 05:46:01 PM PDT 24
Peak memory 208748 kb
Host smart-049ef374-c791-484c-941f-40cf038da6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178336831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4178336831
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.121566910
Short name T418
Test name
Test status
Simulation time 307008726 ps
CPU time 4.3 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 208108 kb
Host smart-06af72fe-cabc-438e-833c-6d6b436aa8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121566910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.121566910
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2433547302
Short name T715
Test name
Test status
Simulation time 27976175216 ps
CPU time 167.34 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:48:40 PM PDT 24
Peak memory 221240 kb
Host smart-60b54617-52b1-4052-ba75-39767435ee78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433547302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2433547302
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3653237741
Short name T344
Test name
Test status
Simulation time 190587278 ps
CPU time 4.95 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 218316 kb
Host smart-cf3db2ef-fccd-4f40-91cf-21fc36a04da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653237741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3653237741
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1129776692
Short name T162
Test name
Test status
Simulation time 40444017 ps
CPU time 1.56 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 209688 kb
Host smart-3e9cafe1-d8b9-4244-8372-6c801f3f1a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129776692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1129776692
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.812783171
Short name T491
Test name
Test status
Simulation time 13959565 ps
CPU time 0.76 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 205848 kb
Host smart-cbbf0a8d-05d9-46c2-bd02-bee2c1e9fdc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812783171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.812783171
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2921044614
Short name T40
Test name
Test status
Simulation time 646051076 ps
CPU time 1.85 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:54 PM PDT 24
Peak memory 217284 kb
Host smart-93055b9e-a4b4-4eb4-a625-30aee9fe6d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921044614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2921044614
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2920359379
Short name T329
Test name
Test status
Simulation time 52741641 ps
CPU time 2.78 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 209984 kb
Host smart-a437ca2b-879b-4151-90c3-e5c6418bd119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920359379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2920359379
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3601513242
Short name T685
Test name
Test status
Simulation time 141646318 ps
CPU time 4.68 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 214248 kb
Host smart-42f39d9e-1bd7-4c5f-aeeb-1b40f05cbe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601513242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3601513242
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.4189976569
Short name T900
Test name
Test status
Simulation time 128261797 ps
CPU time 2.87 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 220628 kb
Host smart-1038a836-b7c7-4e89-bdbf-1cb68e46b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189976569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.4189976569
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.960226403
Short name T230
Test name
Test status
Simulation time 266152150 ps
CPU time 2.66 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 208192 kb
Host smart-16f4d05b-2c3f-4882-a2ab-041a87291e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960226403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.960226403
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2373327675
Short name T751
Test name
Test status
Simulation time 134620268 ps
CPU time 4.1 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 207868 kb
Host smart-546906ae-4840-4004-8123-d9dc2ad7053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373327675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2373327675
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.724854536
Short name T95
Test name
Test status
Simulation time 132995552 ps
CPU time 4.93 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 206572 kb
Host smart-241f2338-2cdf-4518-8404-75696b4edd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724854536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.724854536
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2830408746
Short name T696
Test name
Test status
Simulation time 116105739 ps
CPU time 4.35 seconds
Started Jul 23 05:45:48 PM PDT 24
Finished Jul 23 05:45:53 PM PDT 24
Peak memory 206556 kb
Host smart-a4c58f11-0446-47e7-b88a-d35f917eecee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830408746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2830408746
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3076481600
Short name T16
Test name
Test status
Simulation time 404072380 ps
CPU time 5.09 seconds
Started Jul 23 05:45:56 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 208640 kb
Host smart-70874270-777f-46f0-9303-ee46abe32bb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076481600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3076481600
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3763449743
Short name T647
Test name
Test status
Simulation time 104890462 ps
CPU time 4.55 seconds
Started Jul 23 05:45:56 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 208600 kb
Host smart-bc94a2fa-314a-4123-ad69-97a09c499fd9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763449743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3763449743
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.620440160
Short name T734
Test name
Test status
Simulation time 182448158 ps
CPU time 2.59 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 208044 kb
Host smart-e0e65214-aece-42eb-aed4-a00201941a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620440160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.620440160
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2395448513
Short name T914
Test name
Test status
Simulation time 1190521530 ps
CPU time 3.53 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 207728 kb
Host smart-bfea87a2-2637-4645-baf9-e00ac4cbcd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395448513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2395448513
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1150942314
Short name T305
Test name
Test status
Simulation time 243730389 ps
CPU time 7.62 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 208456 kb
Host smart-843e49bb-294a-4f38-88d9-00a0442cdbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150942314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1150942314
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3921882585
Short name T695
Test name
Test status
Simulation time 107317699 ps
CPU time 3.18 seconds
Started Jul 23 05:45:49 PM PDT 24
Finished Jul 23 05:45:53 PM PDT 24
Peak memory 210376 kb
Host smart-70e03875-52ca-4373-b48b-93e6e73504e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921882585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3921882585
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3865112421
Short name T720
Test name
Test status
Simulation time 14875580 ps
CPU time 0.76 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 205840 kb
Host smart-dcb11ea0-d70d-4f99-88ab-c4d7f64e4b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865112421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3865112421
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2157507993
Short name T255
Test name
Test status
Simulation time 552604272 ps
CPU time 13.96 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:46:09 PM PDT 24
Peak memory 215260 kb
Host smart-d56b49de-6a8e-4939-84f9-cde8ea2789f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157507993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2157507993
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.126172729
Short name T875
Test name
Test status
Simulation time 157401418 ps
CPU time 5.34 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 214008 kb
Host smart-f1712436-f7c6-4edf-9c53-0c951ca0709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126172729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.126172729
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.305732354
Short name T529
Test name
Test status
Simulation time 1228218095 ps
CPU time 12.55 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 209376 kb
Host smart-b12e4771-b63d-4afc-bc06-25ab2d381bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305732354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.305732354
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2165220323
Short name T693
Test name
Test status
Simulation time 446796458 ps
CPU time 2.61 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:06 PM PDT 24
Peak memory 214160 kb
Host smart-8ecfd8e1-c1ff-4074-9f64-794e5dda1fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165220323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2165220323
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2442023620
Short name T910
Test name
Test status
Simulation time 341226017 ps
CPU time 4.52 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:06 PM PDT 24
Peak memory 213884 kb
Host smart-5826efef-6dd9-46fa-8934-f10d8022c476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442023620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2442023620
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2449002798
Short name T63
Test name
Test status
Simulation time 325285122 ps
CPU time 3.04 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 215724 kb
Host smart-0cfc32dd-abd8-4987-bff9-2a10f5eb4803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449002798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2449002798
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1846608803
Short name T321
Test name
Test status
Simulation time 563895612 ps
CPU time 10.54 seconds
Started Jul 23 05:45:56 PM PDT 24
Finished Jul 23 05:46:09 PM PDT 24
Peak memory 207540 kb
Host smart-2dcf6b7f-0d3f-4050-8b6c-a54ed817e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846608803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1846608803
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3241310159
Short name T576
Test name
Test status
Simulation time 122113995 ps
CPU time 2.28 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:54 PM PDT 24
Peak memory 206468 kb
Host smart-5393a6f9-a276-419d-9c5b-2b086b4bfbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241310159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3241310159
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2471707788
Short name T638
Test name
Test status
Simulation time 971428851 ps
CPU time 6.34 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 207860 kb
Host smart-0a89dfaa-c6a0-420e-892a-93cdf2b51434
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471707788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2471707788
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3637983538
Short name T639
Test name
Test status
Simulation time 173402473 ps
CPU time 6.05 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 207712 kb
Host smart-0e91df91-8f1e-490e-b99f-93bfb46dba62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637983538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3637983538
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.764569648
Short name T818
Test name
Test status
Simulation time 1227530453 ps
CPU time 5.47 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 208372 kb
Host smart-fc761166-05fa-4dc7-a10c-eb5324d82c08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764569648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.764569648
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.784195511
Short name T201
Test name
Test status
Simulation time 117527773 ps
CPU time 3.06 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:06 PM PDT 24
Peak memory 208940 kb
Host smart-510572ac-0289-447f-911c-b58ec46aacc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784195511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.784195511
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1541689973
Short name T461
Test name
Test status
Simulation time 18215438 ps
CPU time 1.52 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 206568 kb
Host smart-313fbe2b-3d34-4155-8208-82528438c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541689973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1541689973
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2633958044
Short name T81
Test name
Test status
Simulation time 1122436412 ps
CPU time 7.44 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 214012 kb
Host smart-e4da0379-8eed-4426-a0be-d96cf16216ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633958044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2633958044
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.293184658
Short name T759
Test name
Test status
Simulation time 97323968 ps
CPU time 4.22 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 208248 kb
Host smart-c3745733-78eb-4c6e-acfb-923e6f388957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293184658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.293184658
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.632270332
Short name T178
Test name
Test status
Simulation time 239818128 ps
CPU time 3.23 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 210028 kb
Host smart-5fd351da-5a68-410c-8f9d-fe937004de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632270332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.632270332
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1206982973
Short name T469
Test name
Test status
Simulation time 55219310 ps
CPU time 0.71 seconds
Started Jul 23 05:46:07 PM PDT 24
Finished Jul 23 05:46:09 PM PDT 24
Peak memory 205848 kb
Host smart-611c9b16-62c8-4256-9bd6-78ed64ccbe0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206982973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1206982973
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3753594770
Short name T432
Test name
Test status
Simulation time 121277646 ps
CPU time 4.28 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 214020 kb
Host smart-80a3217f-b2be-4328-b8b7-543c85aadc0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753594770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3753594770
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.358844307
Short name T32
Test name
Test status
Simulation time 589573941 ps
CPU time 6.1 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:09 PM PDT 24
Peak memory 214264 kb
Host smart-cfa1e434-d250-451b-b8c4-e698528d1c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358844307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.358844307
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2965260065
Short name T570
Test name
Test status
Simulation time 66143418 ps
CPU time 2.48 seconds
Started Jul 23 05:45:58 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 219400 kb
Host smart-584e6354-86f4-49c6-b032-6da620743494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965260065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2965260065
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.731597100
Short name T334
Test name
Test status
Simulation time 202113365 ps
CPU time 1.83 seconds
Started Jul 23 05:45:59 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 214028 kb
Host smart-15aa8662-d1d9-4cbc-8149-0aab9b193fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731597100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.731597100
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.2122301332
Short name T351
Test name
Test status
Simulation time 1160888368 ps
CPU time 6.7 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:10 PM PDT 24
Peak memory 218048 kb
Host smart-8e98295c-6444-4979-a32b-a352f8b555f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122301332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2122301332
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.620947382
Short name T628
Test name
Test status
Simulation time 2202868027 ps
CPU time 23.3 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 207680 kb
Host smart-ae60b492-479f-46db-9314-6cfcb789ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620947382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.620947382
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1295232023
Short name T488
Test name
Test status
Simulation time 231703951 ps
CPU time 3.76 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 207792 kb
Host smart-a29d490b-c0e1-48ad-9ea2-392872d24fde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295232023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1295232023
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4192432158
Short name T842
Test name
Test status
Simulation time 225423238 ps
CPU time 3.14 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:07 PM PDT 24
Peak memory 208208 kb
Host smart-dd0315fc-b2d4-44e5-91cf-1f8fdd6036e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192432158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4192432158
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.318254820
Short name T396
Test name
Test status
Simulation time 44719263 ps
CPU time 2.68 seconds
Started Jul 23 05:46:04 PM PDT 24
Finished Jul 23 05:46:07 PM PDT 24
Peak memory 207872 kb
Host smart-70baac33-a9fb-4f5e-833e-c5178f0da5e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318254820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.318254820
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.473260288
Short name T846
Test name
Test status
Simulation time 84641954 ps
CPU time 3.46 seconds
Started Jul 23 05:46:14 PM PDT 24
Finished Jul 23 05:46:19 PM PDT 24
Peak memory 209348 kb
Host smart-07d18548-84f5-4241-b455-96067b851f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473260288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.473260288
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2256800476
Short name T694
Test name
Test status
Simulation time 72206406 ps
CPU time 2.9 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:06 PM PDT 24
Peak memory 206456 kb
Host smart-95f5e60f-f7c6-4c85-9ec8-5fc2e48768a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256800476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2256800476
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3287081503
Short name T792
Test name
Test status
Simulation time 1636428168 ps
CPU time 23.16 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:33 PM PDT 24
Peak memory 221164 kb
Host smart-03b970cf-1a5d-49ee-b028-8200e7fd435a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287081503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3287081503
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2481108618
Short name T372
Test name
Test status
Simulation time 1068946577 ps
CPU time 6.56 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 207744 kb
Host smart-925da6b8-bba4-49a7-85af-a992786f0e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481108618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2481108618
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1603938069
Short name T411
Test name
Test status
Simulation time 97744033 ps
CPU time 2.43 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 209988 kb
Host smart-7b22bc89-0d93-4a78-923e-5f480230bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603938069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1603938069
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2481558482
Short name T459
Test name
Test status
Simulation time 24360658 ps
CPU time 0.89 seconds
Started Jul 23 05:46:13 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 205848 kb
Host smart-46a688e3-3bfb-42c4-8f85-ca397972871c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481558482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2481558482
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.813737833
Short name T799
Test name
Test status
Simulation time 79015410 ps
CPU time 2.74 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 214472 kb
Host smart-dd61c646-56fa-44a9-bfaa-be150222567a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813737833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.813737833
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2837155767
Short name T819
Test name
Test status
Simulation time 105226367 ps
CPU time 2.19 seconds
Started Jul 23 05:46:07 PM PDT 24
Finished Jul 23 05:46:10 PM PDT 24
Peak memory 214172 kb
Host smart-445cb09f-5df9-40cb-a91a-ca0761dec20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837155767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2837155767
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1666771848
Short name T382
Test name
Test status
Simulation time 281927008 ps
CPU time 2.92 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 214052 kb
Host smart-3ccac798-6dfa-43e5-a56f-aee332ca9f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666771848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1666771848
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.407136666
Short name T38
Test name
Test status
Simulation time 236231655 ps
CPU time 6.5 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 222152 kb
Host smart-098764de-a4b4-442e-9ada-199f16b36bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407136666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.407136666
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.1223668454
Short name T263
Test name
Test status
Simulation time 500762683 ps
CPU time 10.17 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 208064 kb
Host smart-53ff511c-23d1-4ec5-8a5f-066156c8d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223668454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1223668454
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3402228863
Short name T99
Test name
Test status
Simulation time 69838294 ps
CPU time 3.41 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 206216 kb
Host smart-e783aaab-ce88-4de4-ac53-f8281159b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402228863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3402228863
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4166152341
Short name T886
Test name
Test status
Simulation time 388146142 ps
CPU time 5.01 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:14 PM PDT 24
Peak memory 208516 kb
Host smart-b355fa74-7510-441a-9721-98b9932345ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166152341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4166152341
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1944266740
Short name T852
Test name
Test status
Simulation time 334054192 ps
CPU time 3.64 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 208324 kb
Host smart-5d193508-e2b6-4498-9f80-16d40b16cf2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944266740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1944266740
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1842076735
Short name T523
Test name
Test status
Simulation time 185822977 ps
CPU time 3.39 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 208748 kb
Host smart-526ad9db-5c1e-4ddd-a05a-52d9a2afbf59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842076735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1842076735
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.585504760
Short name T347
Test name
Test status
Simulation time 253330052 ps
CPU time 5.65 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 217924 kb
Host smart-545e6ede-d3af-4c6e-9966-b799bd8f928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585504760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.585504760
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3387770219
Short name T485
Test name
Test status
Simulation time 195336425 ps
CPU time 2.61 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 206464 kb
Host smart-340db91d-27de-4b79-b5af-5eeaa8ede966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387770219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3387770219
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2091587142
Short name T595
Test name
Test status
Simulation time 408135880 ps
CPU time 5.36 seconds
Started Jul 23 05:46:13 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 207524 kb
Host smart-b6b81a1f-cb2e-455f-83c9-0358c443884d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091587142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2091587142
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.495624391
Short name T77
Test name
Test status
Simulation time 377442936 ps
CPU time 17.67 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 222264 kb
Host smart-024d98e1-a5b6-4944-85ae-41769a7e85cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495624391 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.495624391
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3562062319
Short name T503
Test name
Test status
Simulation time 105620244 ps
CPU time 5 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:19 PM PDT 24
Peak memory 209052 kb
Host smart-bf2fddc0-2fac-4f93-b045-cce8d0ededdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562062319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3562062319
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1856586829
Short name T920
Test name
Test status
Simulation time 81820479 ps
CPU time 1.48 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 209596 kb
Host smart-9b8399a9-bf61-4493-bf45-cc0c0f396ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856586829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1856586829
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2631149943
Short name T898
Test name
Test status
Simulation time 52146525 ps
CPU time 0.74 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 205832 kb
Host smart-49035ef9-a39d-443c-b27d-dd21b9e7ab17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631149943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2631149943
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2176720181
Short name T615
Test name
Test status
Simulation time 195276917 ps
CPU time 4.87 seconds
Started Jul 23 05:46:18 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 221332 kb
Host smart-a0f22dca-7e96-428b-bc01-b24d3e138f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176720181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2176720181
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1588219947
Short name T815
Test name
Test status
Simulation time 111850842 ps
CPU time 2.85 seconds
Started Jul 23 05:46:17 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 208712 kb
Host smart-76233301-fd3b-4d69-836d-8be7e768e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588219947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1588219947
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3785783689
Short name T680
Test name
Test status
Simulation time 1596497732 ps
CPU time 4 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 208992 kb
Host smart-0d4aa82e-7170-4aa1-b9e4-012ad1da7a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785783689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3785783689
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3842567497
Short name T821
Test name
Test status
Simulation time 1343570795 ps
CPU time 2.82 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 205888 kb
Host smart-29f18b31-f000-4568-80ad-d1e95eecdcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842567497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3842567497
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1840401342
Short name T393
Test name
Test status
Simulation time 934247053 ps
CPU time 6.66 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:17 PM PDT 24
Peak memory 208504 kb
Host smart-cf153c52-9852-4067-bdb3-40a4b9d67726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840401342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1840401342
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3627464554
Short name T793
Test name
Test status
Simulation time 295411988 ps
CPU time 7.59 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 207840 kb
Host smart-9fd565a7-9955-4ed0-9c38-373684740aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627464554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3627464554
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2153002894
Short name T885
Test name
Test status
Simulation time 359325601 ps
CPU time 3.16 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:18 PM PDT 24
Peak memory 207676 kb
Host smart-d823045d-c6db-4429-9423-3099d7df16ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153002894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2153002894
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1805019859
Short name T587
Test name
Test status
Simulation time 963799395 ps
CPU time 30.04 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 207732 kb
Host smart-45eac1a0-9abb-49f9-b51f-2a33f43a748b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805019859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1805019859
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1864239492
Short name T524
Test name
Test status
Simulation time 2115051518 ps
CPU time 14.95 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 207748 kb
Host smart-c246d037-d857-4d6c-a4aa-19ce421be34e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864239492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1864239492
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1190181288
Short name T703
Test name
Test status
Simulation time 144919599 ps
CPU time 2.17 seconds
Started Jul 23 05:46:17 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 208048 kb
Host smart-4079cc62-2ad1-4a85-82ab-7ec9a88b2352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190181288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1190181288
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3071425797
Short name T450
Test name
Test status
Simulation time 210182938 ps
CPU time 2.38 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:12 PM PDT 24
Peak memory 206688 kb
Host smart-242fffdd-b06a-4152-98e4-36defb973824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071425797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3071425797
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2561397941
Short name T593
Test name
Test status
Simulation time 681125339 ps
CPU time 18.14 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 214904 kb
Host smart-0de88758-0475-4315-b437-13623688a9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561397941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2561397941
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2787104996
Short name T363
Test name
Test status
Simulation time 995539824 ps
CPU time 7.78 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:32 PM PDT 24
Peak memory 222340 kb
Host smart-6a370c89-a427-4bde-9dd0-38a1f8ab5a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787104996 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2787104996
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2435119845
Short name T540
Test name
Test status
Simulation time 1515339540 ps
CPU time 19.13 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 219460 kb
Host smart-5dc61ae1-e24f-4213-b707-1fb6d79dbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435119845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2435119845
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.722021875
Short name T500
Test name
Test status
Simulation time 26007560 ps
CPU time 0.81 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:22 PM PDT 24
Peak memory 205812 kb
Host smart-d1820249-e373-4b13-aa36-e7920fa578f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722021875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.722021875
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3183801985
Short name T242
Test name
Test status
Simulation time 1790675844 ps
CPU time 47.4 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:47:13 PM PDT 24
Peak memory 215588 kb
Host smart-3c4f9619-006f-4270-8dc8-46605bed63ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183801985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3183801985
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2172706915
Short name T28
Test name
Test status
Simulation time 244830249 ps
CPU time 4.38 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 210592 kb
Host smart-2334dd54-5d61-481d-8918-acd9164e55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172706915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2172706915
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4039605914
Short name T75
Test name
Test status
Simulation time 2993492481 ps
CPU time 6.6 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 218472 kb
Host smart-e1d3ea39-1c3c-497c-8652-5015f32c4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039605914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4039605914
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.8752672
Short name T899
Test name
Test status
Simulation time 41336379 ps
CPU time 1.71 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 214052 kb
Host smart-854b6e5e-9338-484a-a7f0-9abdacd53aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8752672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.8752672
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4071668957
Short name T103
Test name
Test status
Simulation time 114885210 ps
CPU time 2.5 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 220568 kb
Host smart-eca0bc68-77c1-491a-896a-a7e793056cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071668957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4071668957
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.389979672
Short name T209
Test name
Test status
Simulation time 45049042 ps
CPU time 2.83 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 213972 kb
Host smart-30ab4310-049b-4d0c-b4b5-fda62a3f8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389979672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.389979672
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4126796448
Short name T348
Test name
Test status
Simulation time 115428215 ps
CPU time 3.11 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 208472 kb
Host smart-f2ae3e43-f393-48f4-84cb-2872895ef442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126796448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4126796448
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1831220011
Short name T763
Test name
Test status
Simulation time 89789748 ps
CPU time 2.1 seconds
Started Jul 23 05:46:18 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 208584 kb
Host smart-661d3ada-c1e7-44de-975f-5d321a8051a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831220011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1831220011
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2346681619
Short name T525
Test name
Test status
Simulation time 408904213 ps
CPU time 8.49 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 208500 kb
Host smart-e556c470-72c6-4b27-b4e9-d242e1c2daa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346681619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2346681619
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1730296585
Short name T541
Test name
Test status
Simulation time 143076694 ps
CPU time 5.31 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 208396 kb
Host smart-55b3ce71-5d0b-4f77-80dc-66b604018362
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730296585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1730296585
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1079290859
Short name T502
Test name
Test status
Simulation time 113829932 ps
CPU time 4 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 208052 kb
Host smart-7ebdff46-99b2-47e9-9d2b-589b54bddc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079290859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1079290859
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2639663162
Short name T452
Test name
Test status
Simulation time 37041551 ps
CPU time 2.17 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 206596 kb
Host smart-56631b85-bed5-4086-9512-a7f34cb48385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639663162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2639663162
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3178943534
Short name T331
Test name
Test status
Simulation time 1948432530 ps
CPU time 40.7 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 220764 kb
Host smart-e94abc76-8a04-4142-8eba-9146d7064cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178943534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3178943534
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1915620496
Short name T325
Test name
Test status
Simulation time 96959971 ps
CPU time 3.96 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 208380 kb
Host smart-8c304a70-c59a-412d-b464-8f219ca8d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915620496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1915620496
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3411386466
Short name T412
Test name
Test status
Simulation time 136274001 ps
CPU time 1.67 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 209528 kb
Host smart-4228f8f0-df84-4d06-9098-1b32e0204d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411386466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3411386466
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3402213719
Short name T860
Test name
Test status
Simulation time 83616379 ps
CPU time 0.76 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 205784 kb
Host smart-d20c3b8b-233a-42d0-b891-6c42218b5e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402213719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3402213719
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2596254111
Short name T723
Test name
Test status
Simulation time 437457704 ps
CPU time 8.77 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 221452 kb
Host smart-8c9e7c0a-7604-4aaa-9b76-1c5795b1dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596254111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2596254111
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1327062763
Short name T417
Test name
Test status
Simulation time 70960192 ps
CPU time 1.98 seconds
Started Jul 23 05:46:31 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 209016 kb
Host smart-938f241a-71db-4060-8438-87c2546e675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327062763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1327062763
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3522197634
Short name T761
Test name
Test status
Simulation time 2568357198 ps
CPU time 14.25 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 209236 kb
Host smart-68d54cb8-0247-4880-8df4-5b927ce4d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522197634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3522197634
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1394381864
Short name T37
Test name
Test status
Simulation time 1534157136 ps
CPU time 4.83 seconds
Started Jul 23 05:46:30 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 222144 kb
Host smart-93d5f3a3-95ea-4d2b-834f-9a3274a6f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394381864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1394381864
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4188746347
Short name T6
Test name
Test status
Simulation time 1735826919 ps
CPU time 6.65 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 209768 kb
Host smart-47760286-323a-463e-bef0-52e2f27cec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188746347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4188746347
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1435399252
Short name T726
Test name
Test status
Simulation time 51488017 ps
CPU time 2.98 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 214044 kb
Host smart-aa391ca6-73d7-4287-8e0a-f2f8faa03d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435399252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1435399252
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1386485063
Short name T203
Test name
Test status
Simulation time 763184839 ps
CPU time 4.45 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 206516 kb
Host smart-b69d58f3-5e0f-4cf6-a6af-cb2af7807050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386485063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1386485063
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.423227860
Short name T711
Test name
Test status
Simulation time 366736497 ps
CPU time 2.98 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 208064 kb
Host smart-59b1024a-e308-41d5-b888-7323a7928e96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423227860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.423227860
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1738830696
Short name T881
Test name
Test status
Simulation time 469860045 ps
CPU time 4.14 seconds
Started Jul 23 05:46:31 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 208048 kb
Host smart-3d5162f7-e5d5-4d3d-8133-dd700344e82d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738830696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1738830696
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.798925170
Short name T588
Test name
Test status
Simulation time 115569377 ps
CPU time 4.23 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 207772 kb
Host smart-7ebf2c6c-cf1b-46d2-8522-6e111d1f0f8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798925170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.798925170
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.191883073
Short name T199
Test name
Test status
Simulation time 3115774979 ps
CPU time 12.91 seconds
Started Jul 23 05:46:34 PM PDT 24
Finished Jul 23 05:46:48 PM PDT 24
Peak memory 208932 kb
Host smart-a598c42c-64f5-422d-ae04-4f6f9393bad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191883073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.191883073
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.82544872
Short name T642
Test name
Test status
Simulation time 53236292 ps
CPU time 2.56 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 207884 kb
Host smart-a203e78f-9171-4752-9259-0aaae6c2c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82544872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.82544872
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1332043313
Short name T276
Test name
Test status
Simulation time 1723575312 ps
CPU time 18.02 seconds
Started Jul 23 05:46:31 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 222368 kb
Host smart-5ceb934a-2375-47e1-8aad-b86987a11659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332043313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1332043313
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.992556614
Short name T194
Test name
Test status
Simulation time 565485275 ps
CPU time 6.48 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:37 PM PDT 24
Peak memory 218396 kb
Host smart-c770d7e5-d6b9-4e46-b7b9-ef2dca92ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992556614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.992556614
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1557977256
Short name T812
Test name
Test status
Simulation time 329674820 ps
CPU time 6.6 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 210880 kb
Host smart-b74ecfcc-1882-4a82-bab1-78285d2c7c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557977256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1557977256
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1724416590
Short name T517
Test name
Test status
Simulation time 22861232 ps
CPU time 0.91 seconds
Started Jul 23 05:46:42 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 205872 kb
Host smart-c5aba733-fc6a-496f-96fc-3db656e6909e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724416590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1724416590
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.409678475
Short name T433
Test name
Test status
Simulation time 59451202 ps
CPU time 4.17 seconds
Started Jul 23 05:46:28 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 215004 kb
Host smart-4a5a2a9d-acac-4dd1-9cdd-7e6456af1a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409678475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.409678475
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3504992409
Short name T425
Test name
Test status
Simulation time 615790497 ps
CPU time 2.75 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 221608 kb
Host smart-81af6199-525e-4785-ab67-a7d670c3b6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504992409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3504992409
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3484918
Short name T299
Test name
Test status
Simulation time 531098932 ps
CPU time 4.11 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 214536 kb
Host smart-f7e38fd3-e88d-4b3b-8d23-2828da9ef5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3484918
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.939284667
Short name T439
Test name
Test status
Simulation time 574112916 ps
CPU time 6.06 seconds
Started Jul 23 05:46:36 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 222316 kb
Host smart-18fbf63f-3b4d-4009-8ab9-b2551b20651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939284667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.939284667
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2849701146
Short name T765
Test name
Test status
Simulation time 399149380 ps
CPU time 4.92 seconds
Started Jul 23 05:46:28 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 208556 kb
Host smart-563562b7-7201-4e1a-9813-d0892ef893bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849701146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2849701146
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2659320408
Short name T736
Test name
Test status
Simulation time 257971673 ps
CPU time 3.11 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:39 PM PDT 24
Peak memory 206748 kb
Host smart-cb590639-3491-44fc-9ab1-32fa49579a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659320408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2659320408
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.589099697
Short name T650
Test name
Test status
Simulation time 23917856 ps
CPU time 1.97 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:33 PM PDT 24
Peak memory 208084 kb
Host smart-6336d790-737c-40b6-8d2d-89c1130f97b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589099697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.589099697
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3137279037
Short name T731
Test name
Test status
Simulation time 81390883 ps
CPU time 1.77 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:38 PM PDT 24
Peak memory 207280 kb
Host smart-102ed04e-994f-409c-be39-ac3153dadddd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137279037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3137279037
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3460720459
Short name T536
Test name
Test status
Simulation time 78159059 ps
CPU time 3.63 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:37 PM PDT 24
Peak memory 208300 kb
Host smart-7ac4fce6-3425-4389-a7e3-7786b2517a35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460720459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3460720459
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3946445881
Short name T518
Test name
Test status
Simulation time 183739307 ps
CPU time 2.14 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 208328 kb
Host smart-9f658970-812b-420f-9db5-e3f3899dbe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946445881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3946445881
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.489350111
Short name T896
Test name
Test status
Simulation time 75146291 ps
CPU time 2.94 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 208248 kb
Host smart-3f75ff49-11d2-4390-b64f-111159d0ccf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489350111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.489350111
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1162071875
Short name T624
Test name
Test status
Simulation time 177016267 ps
CPU time 4.18 seconds
Started Jul 23 05:46:36 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 210192 kb
Host smart-0d2d7bbb-e2c3-44f4-be9c-e867c8a4d159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162071875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1162071875
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1376989838
Short name T155
Test name
Test status
Simulation time 104305983 ps
CPU time 1.84 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 210032 kb
Host smart-a2dc2d0f-591d-4828-aeda-a18745880ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376989838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1376989838
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.477767871
Short name T679
Test name
Test status
Simulation time 89253342 ps
CPU time 0.78 seconds
Started Jul 23 05:44:35 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 205828 kb
Host smart-7c987e9b-dcee-44e5-b0d0-4e11e2ebffc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477767871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.477767871
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2695476135
Short name T435
Test name
Test status
Simulation time 311901156 ps
CPU time 16.68 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 215676 kb
Host smart-5a6c4a5d-697a-4fb5-ad85-e0ff61ac9ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695476135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2695476135
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.641422338
Short name T577
Test name
Test status
Simulation time 752925380 ps
CPU time 4.75 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 214056 kb
Host smart-aed2656d-8bea-4677-81ec-c7dae79d3eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641422338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.641422338
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2339804135
Short name T773
Test name
Test status
Simulation time 322146814 ps
CPU time 4.24 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 208400 kb
Host smart-34324314-0b43-4da3-829b-5c2b1242545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339804135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2339804135
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.369765320
Short name T384
Test name
Test status
Simulation time 54996507 ps
CPU time 2.36 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:37 PM PDT 24
Peak memory 211020 kb
Host smart-ec2ec70a-82a5-4783-9d39-e1d39a3f48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369765320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.369765320
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.3735079077
Short name T556
Test name
Test status
Simulation time 69150513 ps
CPU time 3.35 seconds
Started Jul 23 05:44:27 PM PDT 24
Finished Jul 23 05:44:34 PM PDT 24
Peak memory 207404 kb
Host smart-8d1127d7-4b91-4ed5-bf13-a5c03d602279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735079077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3735079077
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1923171304
Short name T43
Test name
Test status
Simulation time 377900598 ps
CPU time 10.04 seconds
Started Jul 23 05:44:34 PM PDT 24
Finished Jul 23 05:44:47 PM PDT 24
Peak memory 231344 kb
Host smart-e1a0a17a-9763-47e8-bbe0-330272539733
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923171304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1923171304
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3148058152
Short name T207
Test name
Test status
Simulation time 44247355 ps
CPU time 1.89 seconds
Started Jul 23 05:44:28 PM PDT 24
Finished Jul 23 05:44:33 PM PDT 24
Peak memory 206460 kb
Host smart-6d4d2245-7576-4200-beff-a8171dca97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148058152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3148058152
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.859295505
Short name T708
Test name
Test status
Simulation time 1385984251 ps
CPU time 9.47 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:47 PM PDT 24
Peak memory 207036 kb
Host smart-2ed8dd4c-ef60-4dde-a70c-f109b5f97e88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859295505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.859295505
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2919975402
Short name T667
Test name
Test status
Simulation time 601363530 ps
CPU time 15.46 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:53 PM PDT 24
Peak memory 206712 kb
Host smart-f40a6123-84b2-4610-a52b-9b3c90fbdd07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919975402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2919975402
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1503170863
Short name T848
Test name
Test status
Simulation time 405724839 ps
CPU time 3 seconds
Started Jul 23 05:44:29 PM PDT 24
Finished Jul 23 05:44:35 PM PDT 24
Peak memory 206700 kb
Host smart-3aee88ae-6bc8-4875-b93f-bf52134742a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503170863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1503170863
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4167987373
Short name T494
Test name
Test status
Simulation time 337047627 ps
CPU time 3.02 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 214068 kb
Host smart-044db10f-8f74-40e0-9ad4-562bd1256fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167987373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4167987373
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1111835761
Short name T448
Test name
Test status
Simulation time 50564106 ps
CPU time 2.49 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 208420 kb
Host smart-4087ea3f-af83-4687-8c3b-1e77cb1e4b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111835761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1111835761
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4107732638
Short name T88
Test name
Test status
Simulation time 126839198 ps
CPU time 3.46 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 219712 kb
Host smart-fbfd477a-a7f1-476e-81bb-c4cc771310cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107732638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4107732638
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2373883423
Short name T179
Test name
Test status
Simulation time 915311293 ps
CPU time 16.34 seconds
Started Jul 23 05:44:30 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 222472 kb
Host smart-1bc9186d-53c4-4e38-bee2-efd7647dac0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373883423 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2373883423
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2701321656
Short name T699
Test name
Test status
Simulation time 131163380 ps
CPU time 6.09 seconds
Started Jul 23 05:44:29 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 209772 kb
Host smart-ac10d20b-7d15-4047-a6d8-4a2f729d04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701321656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2701321656
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1583915137
Short name T68
Test name
Test status
Simulation time 88136028 ps
CPU time 2.26 seconds
Started Jul 23 05:44:28 PM PDT 24
Finished Jul 23 05:44:34 PM PDT 24
Peak memory 209920 kb
Host smart-037472a5-2e9c-4950-b9f7-4c517d473fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583915137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1583915137
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1437379758
Short name T827
Test name
Test status
Simulation time 15018237 ps
CPU time 0.92 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 205904 kb
Host smart-a43ff013-3c38-4d39-8fe3-b35b8e66e914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437379758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1437379758
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.485430619
Short name T442
Test name
Test status
Simulation time 44877886 ps
CPU time 3.48 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 214640 kb
Host smart-adc12abe-ca58-42a8-9a52-500d8397e674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485430619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.485430619
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1507905827
Short name T389
Test name
Test status
Simulation time 177241650 ps
CPU time 5.91 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:47 PM PDT 24
Peak memory 221564 kb
Host smart-39c7f4a9-c708-4bf2-9872-5b3d2af9b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507905827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1507905827
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1306304135
Short name T806
Test name
Test status
Simulation time 135375787 ps
CPU time 3.26 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 218220 kb
Host smart-3f4dc282-1c31-480b-8c84-0923119024a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306304135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1306304135
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.818802416
Short name T735
Test name
Test status
Simulation time 158393006 ps
CPU time 2.64 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 214068 kb
Host smart-995829f8-05b9-4864-aab9-3f8612dd052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818802416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.818802416
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2907189233
Short name T398
Test name
Test status
Simulation time 178545018 ps
CPU time 1.24 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 214000 kb
Host smart-067bceef-f9c1-4407-976e-fb7a55a2b27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907189233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2907189233
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.793100188
Short name T644
Test name
Test status
Simulation time 112650053 ps
CPU time 2.38 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 214068 kb
Host smart-ea148649-62d4-41e8-9013-0fe2b3dce252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793100188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.793100188
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4256438609
Short name T832
Test name
Test status
Simulation time 1246466858 ps
CPU time 19.74 seconds
Started Jul 23 05:46:36 PM PDT 24
Finished Jul 23 05:46:57 PM PDT 24
Peak memory 209212 kb
Host smart-7a59c13b-43d3-4147-b09b-dc3050896c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256438609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4256438609
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3254954461
Short name T822
Test name
Test status
Simulation time 265643330 ps
CPU time 3.31 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:46:47 PM PDT 24
Peak memory 208404 kb
Host smart-1580853f-939a-4199-93b2-f890776365d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254954461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3254954461
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1690756068
Short name T121
Test name
Test status
Simulation time 169815514 ps
CPU time 5.79 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 207888 kb
Host smart-0bfa3b44-8936-4594-bd92-2bab1e727d5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690756068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1690756068
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.723443520
Short name T677
Test name
Test status
Simulation time 683540805 ps
CPU time 16.51 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 207708 kb
Host smart-17d5f12e-69d1-46dd-8cbc-75357c88c3e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723443520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.723443520
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3037501981
Short name T338
Test name
Test status
Simulation time 74953276 ps
CPU time 3.13 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 208168 kb
Host smart-d2e993fc-9629-44c1-9134-720019b9be67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037501981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3037501981
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3130832268
Short name T211
Test name
Test status
Simulation time 230056123 ps
CPU time 2.51 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 207664 kb
Host smart-926e6521-94e4-42ec-b730-e0a8ce1d15de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130832268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3130832268
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3398894230
Short name T504
Test name
Test status
Simulation time 158358402 ps
CPU time 4.05 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:47 PM PDT 24
Peak memory 207880 kb
Host smart-d31c74a6-f9dc-41cf-889a-f95d083ff7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398894230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3398894230
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3644955076
Short name T236
Test name
Test status
Simulation time 1026863941 ps
CPU time 10.22 seconds
Started Jul 23 05:46:42 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 218572 kb
Host smart-bee94e00-a71f-4272-9218-7ce50b31c123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644955076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3644955076
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1977155739
Short name T515
Test name
Test status
Simulation time 103839176 ps
CPU time 5.62 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 222356 kb
Host smart-13a0bad5-2c62-4ac2-a782-ef485eaa4e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977155739 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1977155739
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1261688150
Short name T400
Test name
Test status
Simulation time 214240492 ps
CPU time 4.38 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 218140 kb
Host smart-c9d3976d-75e7-4a8c-b1d0-71567fcb91b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261688150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1261688150
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3033782256
Short name T775
Test name
Test status
Simulation time 301929454 ps
CPU time 5 seconds
Started Jul 23 05:46:41 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 210192 kb
Host smart-07a18994-7977-4e92-9ec2-d0b8650e0569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033782256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3033782256
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1218511877
Short name T674
Test name
Test status
Simulation time 32240932 ps
CPU time 0.74 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 205804 kb
Host smart-76d57cdb-f967-44d8-a5c8-704666fe9b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218511877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1218511877
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.201209598
Short name T871
Test name
Test status
Simulation time 402999757 ps
CPU time 4.04 seconds
Started Jul 23 05:46:50 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 214360 kb
Host smart-af41ba77-a5c5-4e89-9c77-0c37d4bdb246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201209598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.201209598
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.346269273
Short name T874
Test name
Test status
Simulation time 34591096 ps
CPU time 2.02 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 214076 kb
Host smart-2a5fce4b-6c2f-45bf-9761-d0885e22c496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346269273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.346269273
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.135958884
Short name T690
Test name
Test status
Simulation time 41580913 ps
CPU time 2.63 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 214052 kb
Host smart-ef665dde-db7a-4e03-aad5-6200109340f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135958884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.135958884
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2891435732
Short name T361
Test name
Test status
Simulation time 207140726 ps
CPU time 2.71 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 213968 kb
Host smart-c605c099-2218-4d4a-a81c-6ed80e08fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891435732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2891435732
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.2892358340
Short name T828
Test name
Test status
Simulation time 454495901 ps
CPU time 4.99 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 214148 kb
Host smart-09d7f9b9-b60b-4a78-b087-3784dc60a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892358340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2892358340
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4150132371
Short name T122
Test name
Test status
Simulation time 43373551 ps
CPU time 2.24 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 206580 kb
Host smart-6210c07e-c1e0-494b-ae71-379310814451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150132371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4150132371
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.24063462
Short name T784
Test name
Test status
Simulation time 107858313 ps
CPU time 2.72 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 206560 kb
Host smart-e99e18fb-c135-4b5f-8f16-cc4c1b76e12e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.24063462
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3751180556
Short name T427
Test name
Test status
Simulation time 5456224325 ps
CPU time 30.86 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 208924 kb
Host smart-1a572a6a-ed26-4fa0-a9e3-ca33082c8a9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751180556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3751180556
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1812218102
Short name T216
Test name
Test status
Simulation time 756602208 ps
CPU time 20.91 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 208348 kb
Host smart-3bf4ce41-27bd-40b5-a5d1-a026aa8cddb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812218102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1812218102
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2378505217
Short name T464
Test name
Test status
Simulation time 464236475 ps
CPU time 5.41 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 207360 kb
Host smart-53c5eb29-731c-422b-ae0e-c0ed0a514063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378505217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2378505217
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.878179591
Short name T460
Test name
Test status
Simulation time 30546414 ps
CPU time 1.9 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 206620 kb
Host smart-6de9fef4-e757-4c40-bae7-7ecc06b4b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878179591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.878179591
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1730581721
Short name T350
Test name
Test status
Simulation time 3994198700 ps
CPU time 39.23 seconds
Started Jul 23 05:46:49 PM PDT 24
Finished Jul 23 05:47:32 PM PDT 24
Peak memory 222364 kb
Host smart-6c780858-ca44-4fbd-a08a-8d4e2de51793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730581721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1730581721
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3102881683
Short name T561
Test name
Test status
Simulation time 208875013 ps
CPU time 5.96 seconds
Started Jul 23 05:46:44 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 208984 kb
Host smart-66d1ad04-62d8-41f7-b323-e7b238f68fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102881683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3102881683
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1269712257
Short name T408
Test name
Test status
Simulation time 46961010 ps
CPU time 2.2 seconds
Started Jul 23 05:46:44 PM PDT 24
Finished Jul 23 05:46:48 PM PDT 24
Peak memory 209544 kb
Host smart-6bb8f14f-39c6-4ddc-9e88-8b09ba19b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269712257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1269712257
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3913548397
Short name T557
Test name
Test status
Simulation time 242139718 ps
CPU time 1 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 205840 kb
Host smart-0a1b708d-8d6d-4263-839b-fc6d17744270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913548397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3913548397
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3270781804
Short name T300
Test name
Test status
Simulation time 109942722 ps
CPU time 4.04 seconds
Started Jul 23 05:46:41 PM PDT 24
Finished Jul 23 05:46:48 PM PDT 24
Peak memory 214148 kb
Host smart-f0710ced-d835-4559-b8b2-9e57a9f19434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270781804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3270781804
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.351823004
Short name T7
Test name
Test status
Simulation time 251045072 ps
CPU time 3.88 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:11 PM PDT 24
Peak memory 214320 kb
Host smart-87486c93-3cb5-4b6d-ba87-a1f6bec861a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351823004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.351823004
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.203645282
Short name T74
Test name
Test status
Simulation time 1238648011 ps
CPU time 3.44 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 206940 kb
Host smart-7604b410-cf7e-45ad-a476-0154456cdd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203645282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.203645282
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.66459572
Short name T109
Test name
Test status
Simulation time 141322038 ps
CPU time 5.72 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 214060 kb
Host smart-186d8789-f4ce-48b1-a055-073a1550ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66459572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.66459572
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2742836018
Short name T682
Test name
Test status
Simulation time 619496753 ps
CPU time 2.76 seconds
Started Jul 23 05:47:00 PM PDT 24
Finished Jul 23 05:47:05 PM PDT 24
Peak memory 220016 kb
Host smart-71bf3392-c701-4ca7-97cb-56c9b1a618f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742836018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2742836018
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3126537427
Short name T670
Test name
Test status
Simulation time 355381346 ps
CPU time 4.77 seconds
Started Jul 23 05:46:44 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 208972 kb
Host smart-c3bf6556-2a68-4f8e-aef0-22011c19d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126537427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3126537427
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3892671355
Short name T586
Test name
Test status
Simulation time 393274834 ps
CPU time 2.98 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 208400 kb
Host smart-e6f16acd-eb7d-48bf-98b2-74aa727d67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892671355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3892671355
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2459730876
Short name T585
Test name
Test status
Simulation time 30289753 ps
CPU time 2.09 seconds
Started Jul 23 05:46:44 PM PDT 24
Finished Jul 23 05:46:48 PM PDT 24
Peak memory 206532 kb
Host smart-4a230241-ff33-4160-9b43-4fd59c0a332e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459730876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2459730876
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1445125637
Short name T908
Test name
Test status
Simulation time 4930275411 ps
CPU time 43.78 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 208800 kb
Host smart-7d043336-e63d-492a-ada2-0536d1bbdbae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445125637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1445125637
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2486098233
Short name T549
Test name
Test status
Simulation time 917753115 ps
CPU time 6.75 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 208288 kb
Host smart-512397db-454e-4218-bd55-45b9dc2d6bee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486098233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2486098233
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4234770834
Short name T470
Test name
Test status
Simulation time 918049395 ps
CPU time 3.49 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 206816 kb
Host smart-aa64f424-97dd-421e-bc7d-325f438c68ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234770834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4234770834
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2114781090
Short name T859
Test name
Test status
Simulation time 924453814 ps
CPU time 23.95 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 222248 kb
Host smart-4f29e7a2-92e0-4ef1-b7dc-bab83fff7875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114781090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2114781090
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3117633514
Short name T231
Test name
Test status
Simulation time 2072656195 ps
CPU time 26.91 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:24 PM PDT 24
Peak memory 222508 kb
Host smart-ad4700ed-c348-4546-b5d8-64b1a0e4d3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117633514 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3117633514
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1893141946
Short name T866
Test name
Test status
Simulation time 2281049133 ps
CPU time 8.32 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:47:05 PM PDT 24
Peak memory 219608 kb
Host smart-c92b07bf-52ce-4524-bcbd-208e142fa994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893141946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1893141946
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3241453278
Short name T853
Test name
Test status
Simulation time 162224507 ps
CPU time 4.86 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 210272 kb
Host smart-e7d80fb9-a67f-4284-9bfb-371cf3abb7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241453278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3241453278
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.907028861
Short name T496
Test name
Test status
Simulation time 40957534 ps
CPU time 0.84 seconds
Started Jul 23 05:47:05 PM PDT 24
Finished Jul 23 05:47:10 PM PDT 24
Peak memory 205872 kb
Host smart-a4445119-db69-4838-881d-bc3a06d47626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907028861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.907028861
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2675706833
Short name T645
Test name
Test status
Simulation time 2036305166 ps
CPU time 7.85 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:47:04 PM PDT 24
Peak memory 218124 kb
Host smart-d4512a70-a5c9-4f1e-ade9-2a45c562ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675706833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2675706833
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.917932622
Short name T342
Test name
Test status
Simulation time 2156849212 ps
CPU time 8.1 seconds
Started Jul 23 05:46:59 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 219520 kb
Host smart-96f868c7-c364-442f-8fd8-2985c7fc5163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917932622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.917932622
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1050769219
Short name T618
Test name
Test status
Simulation time 51686616 ps
CPU time 2.54 seconds
Started Jul 23 05:46:58 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 222096 kb
Host smart-f0393137-b0c9-4758-a6d8-ced80a7a1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050769219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1050769219
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.457569989
Short name T70
Test name
Test status
Simulation time 143868554 ps
CPU time 4.59 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:59 PM PDT 24
Peak memory 220176 kb
Host smart-5bdfd696-9fe9-46ed-9506-6dc27c17ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457569989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.457569989
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.129627314
Short name T558
Test name
Test status
Simulation time 126780262 ps
CPU time 3.91 seconds
Started Jul 23 05:46:58 PM PDT 24
Finished Jul 23 05:47:04 PM PDT 24
Peak memory 207904 kb
Host smart-5ca7e0a7-4e2b-4383-a20e-b8f0af9d950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129627314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.129627314
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1590665460
Short name T771
Test name
Test status
Simulation time 424731016 ps
CPU time 13.88 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 207904 kb
Host smart-b82e5c04-8ed1-4b9a-a086-96f4e551b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590665460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1590665460
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2461796062
Short name T458
Test name
Test status
Simulation time 98807986 ps
CPU time 4.08 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 208040 kb
Host smart-2690ed82-d01b-474f-9836-9e9841f5cbf2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461796062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2461796062
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.878769394
Short name T538
Test name
Test status
Simulation time 124289465 ps
CPU time 2.66 seconds
Started Jul 23 05:46:56 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 207100 kb
Host smart-1ad60e17-06e8-445b-a359-613629133230
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878769394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.878769394
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.75840577
Short name T728
Test name
Test status
Simulation time 679981317 ps
CPU time 5.21 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 207704 kb
Host smart-2f74b967-26aa-4470-8bd5-092000b89a6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75840577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.75840577
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3899345320
Short name T5
Test name
Test status
Simulation time 126463597 ps
CPU time 3.46 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 207848 kb
Host smart-bf5ac38f-05f8-497d-85f8-4d9bd01b1b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899345320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3899345320
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2130064280
Short name T196
Test name
Test status
Simulation time 133714857 ps
CPU time 2.94 seconds
Started Jul 23 05:47:00 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 208424 kb
Host smart-f6344e83-7dfb-4627-91cc-889260f942f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130064280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2130064280
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2843586810
Short name T339
Test name
Test status
Simulation time 2020506795 ps
CPU time 61.61 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:48:09 PM PDT 24
Peak memory 216152 kb
Host smart-41937f33-1d03-4d13-8221-73fdc2c4a35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843586810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2843586810
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2118813952
Short name T355
Test name
Test status
Simulation time 337839491 ps
CPU time 5.78 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:13 PM PDT 24
Peak memory 210020 kb
Host smart-d3f22f63-0297-4d53-9fcf-d32945f33cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118813952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2118813952
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1631704762
Short name T409
Test name
Test status
Simulation time 38418876 ps
CPU time 1.41 seconds
Started Jul 23 05:46:59 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 209448 kb
Host smart-89c2b0e6-0e6c-488e-b42c-48a7c7ccdf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631704762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1631704762
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3584513425
Short name T463
Test name
Test status
Simulation time 47231237 ps
CPU time 0.77 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 205832 kb
Host smart-f945188d-784f-4ad1-9ffc-c290857adf67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584513425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3584513425
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.488852891
Short name T148
Test name
Test status
Simulation time 172616290 ps
CPU time 3.67 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 214020 kb
Host smart-b46bc274-038e-4aba-851e-271636353f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488852891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.488852891
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1361324068
Short name T73
Test name
Test status
Simulation time 802090528 ps
CPU time 11.29 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 214368 kb
Host smart-35fe850e-cb8d-4951-b56b-cfd8daab69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361324068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1361324068
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.159237518
Short name T651
Test name
Test status
Simulation time 585474569 ps
CPU time 3.15 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 207048 kb
Host smart-a45289a7-9ffe-4848-9a83-d3694dd68c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159237518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.159237518
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1743685846
Short name T893
Test name
Test status
Simulation time 58841520 ps
CPU time 2.28 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:47:10 PM PDT 24
Peak memory 214064 kb
Host smart-73d2f122-2483-4f05-ad4d-16b761b12e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743685846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1743685846
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3127402026
Short name T311
Test name
Test status
Simulation time 1205411283 ps
CPU time 6.24 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:13 PM PDT 24
Peak memory 222172 kb
Host smart-a7892ecd-d18a-4324-bea9-c65a2723d90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127402026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3127402026
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2267902083
Short name T45
Test name
Test status
Simulation time 237736071 ps
CPU time 3.36 seconds
Started Jul 23 05:47:06 PM PDT 24
Finished Jul 23 05:47:13 PM PDT 24
Peak memory 215724 kb
Host smart-042ba84b-5e4f-4c81-83a9-6012506daa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267902083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2267902083
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3977362628
Short name T206
Test name
Test status
Simulation time 222828884 ps
CPU time 3.37 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 207968 kb
Host smart-143e20ab-17dc-4877-a88f-fe651d3f0ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977362628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3977362628
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3571724134
Short name T705
Test name
Test status
Simulation time 287329948 ps
CPU time 3.66 seconds
Started Jul 23 05:47:06 PM PDT 24
Finished Jul 23 05:47:14 PM PDT 24
Peak memory 208528 kb
Host smart-935fe07a-826c-4e12-a9a7-120ff23dc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571724134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3571724134
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3140128311
Short name T214
Test name
Test status
Simulation time 329491940 ps
CPU time 3.45 seconds
Started Jul 23 05:47:07 PM PDT 24
Finished Jul 23 05:47:14 PM PDT 24
Peak memory 207076 kb
Host smart-6e094384-6acb-40eb-91b9-d6d5728a370d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140128311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3140128311
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2539759621
Short name T526
Test name
Test status
Simulation time 71747164 ps
CPU time 2.71 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 208548 kb
Host smart-859dd40a-3241-4e96-aeeb-5864d91dab73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539759621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2539759621
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.846826072
Short name T554
Test name
Test status
Simulation time 202090172 ps
CPU time 5.68 seconds
Started Jul 23 05:47:05 PM PDT 24
Finished Jul 23 05:47:15 PM PDT 24
Peak memory 207736 kb
Host smart-78365cca-02d1-40d1-bd26-353023e926c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846826072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.846826072
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2933497919
Short name T892
Test name
Test status
Simulation time 136699477 ps
CPU time 3.31 seconds
Started Jul 23 05:47:05 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 218108 kb
Host smart-8f8b15a8-a3c0-4df8-8326-091214b88c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933497919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2933497919
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.778030019
Short name T649
Test name
Test status
Simulation time 2489094181 ps
CPU time 11.66 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 207608 kb
Host smart-7ab59fd4-0a07-4d27-ac1e-4adebad5c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778030019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.778030019
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.747417854
Short name T854
Test name
Test status
Simulation time 313556984 ps
CPU time 15.11 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 222304 kb
Host smart-34c60866-6549-42de-a4e1-0e650f9eceb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747417854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.747417854
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1312970663
Short name T138
Test name
Test status
Simulation time 2404739279 ps
CPU time 13.88 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:18 PM PDT 24
Peak memory 220548 kb
Host smart-8902aa64-dad2-4229-bee0-b559964e45b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312970663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1312970663
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3974645545
Short name T691
Test name
Test status
Simulation time 96157165 ps
CPU time 4.34 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 208508 kb
Host smart-42551459-1f64-409c-988b-c7ff7b9cde28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974645545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3974645545
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3695994931
Short name T406
Test name
Test status
Simulation time 210875761 ps
CPU time 2.95 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 209740 kb
Host smart-45ac2642-9587-41bb-a2b9-f726fce94985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695994931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3695994931
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1183879846
Short name T863
Test name
Test status
Simulation time 19809921 ps
CPU time 1.04 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:18 PM PDT 24
Peak memory 205900 kb
Host smart-4158966a-9205-475a-abee-13ef8b6d6f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183879846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1183879846
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3674806695
Short name T444
Test name
Test status
Simulation time 212028473 ps
CPU time 10.98 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:29 PM PDT 24
Peak memory 215084 kb
Host smart-ecb7bb56-fc52-4e33-934e-2293120564ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674806695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3674806695
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3968142079
Short name T391
Test name
Test status
Simulation time 28090559 ps
CPU time 1.94 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 216752 kb
Host smart-5e729d4a-9727-48ad-8269-3eb87165b617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968142079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3968142079
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3294172981
Short name T805
Test name
Test status
Simulation time 1234165467 ps
CPU time 4.07 seconds
Started Jul 23 05:47:09 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 214132 kb
Host smart-4e554ede-46ce-4fa4-8a86-b56609732ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294172981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3294172981
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3098991424
Short name T113
Test name
Test status
Simulation time 134214457 ps
CPU time 5.13 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 208816 kb
Host smart-e8466253-8254-4406-b3b0-8a53a5512808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098991424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3098991424
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2476831496
Short name T573
Test name
Test status
Simulation time 271707747 ps
CPU time 3.55 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 220704 kb
Host smart-7a276156-3806-4762-89fd-2f0d1746d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476831496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2476831496
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3451346271
Short name T532
Test name
Test status
Simulation time 93621196 ps
CPU time 3.58 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 208080 kb
Host smart-6c15201c-4c50-4683-9daa-f3d480dfe2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451346271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3451346271
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1717093271
Short name T492
Test name
Test status
Simulation time 630653447 ps
CPU time 19.58 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 208768 kb
Host smart-93cb29f0-6d40-4560-9725-5666939fb44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717093271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1717093271
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2111878138
Short name T534
Test name
Test status
Simulation time 214537734 ps
CPU time 6.08 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:11 PM PDT 24
Peak memory 207684 kb
Host smart-f6fd6c8a-e85b-46fa-b717-5af916a6a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111878138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2111878138
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1845183957
Short name T569
Test name
Test status
Simulation time 280394930 ps
CPU time 2.86 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 206540 kb
Host smart-d8588719-f6c7-460b-84a7-d1affa1d367e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845183957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1845183957
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1795011093
Short name T724
Test name
Test status
Simulation time 193863614 ps
CPU time 2.93 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 206592 kb
Host smart-626e165c-2e2c-4342-8077-6eb5efec893f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795011093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1795011093
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1261527433
Short name T559
Test name
Test status
Simulation time 1188012407 ps
CPU time 12.57 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 208080 kb
Host smart-d4ad8310-90e3-42f5-b1b9-821b5d452f2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261527433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1261527433
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2649873794
Short name T616
Test name
Test status
Simulation time 100577989 ps
CPU time 1.61 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 215048 kb
Host smart-fa38229c-f0b7-4910-a934-598c650ae797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649873794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2649873794
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.915651242
Short name T4
Test name
Test status
Simulation time 31868457 ps
CPU time 2.18 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 206548 kb
Host smart-f7a7af60-4950-4d03-a20a-073b6814a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915651242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.915651242
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1156570206
Short name T269
Test name
Test status
Simulation time 7007582379 ps
CPU time 36.25 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 216656 kb
Host smart-47dacad1-1e49-4881-bad8-21d02c0100ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156570206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1156570206
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3952465254
Short name T92
Test name
Test status
Simulation time 1231453148 ps
CPU time 8.82 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:26 PM PDT 24
Peak memory 208420 kb
Host smart-ac1a32e9-0acd-4502-9793-690ce0246f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952465254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3952465254
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2026356248
Short name T67
Test name
Test status
Simulation time 99352293 ps
CPU time 2.75 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 209972 kb
Host smart-e8eec585-1aa3-4b16-b7c1-6d2f51297a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026356248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2026356248
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4211551314
Short name T18
Test name
Test status
Simulation time 26740182 ps
CPU time 0.69 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 205832 kb
Host smart-0136d1bc-697c-49f1-afc9-f95fcdcf82d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211551314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4211551314
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1150388451
Short name T39
Test name
Test status
Simulation time 98629229 ps
CPU time 2.85 seconds
Started Jul 23 05:47:23 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 209004 kb
Host smart-e670598d-b0d7-4477-a5ab-a1f11e0c3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150388451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1150388451
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2022439930
Short name T50
Test name
Test status
Simulation time 602170572 ps
CPU time 2.87 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:18 PM PDT 24
Peak memory 214156 kb
Host smart-8e9224cf-cef5-48f3-a0f4-1bef340e45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022439930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2022439930
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2467350974
Short name T114
Test name
Test status
Simulation time 232436786 ps
CPU time 3.64 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 220476 kb
Host smart-12f443c3-a6f9-4ccb-9df7-8993a64926a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467350974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2467350974
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2114125968
Short name T356
Test name
Test status
Simulation time 43928869 ps
CPU time 2.59 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:26 PM PDT 24
Peak memory 214812 kb
Host smart-4070e9ac-606d-4242-be1e-c2126bb90c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114125968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2114125968
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.151244358
Short name T767
Test name
Test status
Simulation time 418232298 ps
CPU time 3.57 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 222288 kb
Host smart-0a9eccbe-25f0-4a59-b542-d2019d3db0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151244358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.151244358
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3304992582
Short name T840
Test name
Test status
Simulation time 439628217 ps
CPU time 5.75 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 214040 kb
Host smart-4fae4f54-affa-4026-9636-59eb2b409c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304992582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3304992582
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3298712118
Short name T533
Test name
Test status
Simulation time 82671854 ps
CPU time 3.88 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:27 PM PDT 24
Peak memory 208656 kb
Host smart-966244cc-acd5-4616-b45d-b564ad9d1c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298712118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3298712118
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1035937547
Short name T296
Test name
Test status
Simulation time 627622201 ps
CPU time 3.68 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 208420 kb
Host smart-d16563f0-3073-4900-9aeb-6422157b00db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035937547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1035937547
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.91106109
Short name T467
Test name
Test status
Simulation time 1770502759 ps
CPU time 23.23 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 208544 kb
Host smart-9878910b-6eca-4afe-a3b8-1d744b9cca13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91106109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.91106109
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1487645106
Short name T293
Test name
Test status
Simulation time 83966969 ps
CPU time 2.77 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 209684 kb
Host smart-854ffc97-c229-40dd-b36f-05ec20c20205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487645106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1487645106
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3339833973
Short name T481
Test name
Test status
Simulation time 117977987 ps
CPU time 4.34 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 207792 kb
Host smart-3d7e0b23-2d65-4437-9847-1380f4f1aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339833973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3339833973
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1098755193
Short name T742
Test name
Test status
Simulation time 214766131 ps
CPU time 7.48 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:32 PM PDT 24
Peak memory 218584 kb
Host smart-3d4c4e0d-77e3-4473-8a76-1386bda9cb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098755193 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1098755193
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2880446867
Short name T803
Test name
Test status
Simulation time 1220895398 ps
CPU time 5.15 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 207160 kb
Host smart-92ebc1df-f003-4944-9ad5-8658c5ad7e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880446867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2880446867
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.306698276
Short name T837
Test name
Test status
Simulation time 189722929 ps
CPU time 1.56 seconds
Started Jul 23 05:47:22 PM PDT 24
Finished Jul 23 05:47:30 PM PDT 24
Peak memory 209460 kb
Host smart-925307cd-f991-4bd5-bec8-5bd00ba2ac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306698276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.306698276
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3949870743
Short name T14
Test name
Test status
Simulation time 10874215 ps
CPU time 0.81 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 205848 kb
Host smart-a873dd56-3c62-4188-9c60-b02a186e6902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949870743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3949870743
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.511690698
Short name T229
Test name
Test status
Simulation time 89493888 ps
CPU time 3.36 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 207872 kb
Host smart-26c51140-67a0-43b9-9625-838209a9e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511690698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.511690698
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2241962642
Short name T684
Test name
Test status
Simulation time 150877788 ps
CPU time 4.57 seconds
Started Jul 23 05:47:16 PM PDT 24
Finished Jul 23 05:47:26 PM PDT 24
Peak memory 214040 kb
Host smart-62b44ad8-e292-4c9a-83e4-d0c4186aa069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241962642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2241962642
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3290427206
Short name T111
Test name
Test status
Simulation time 3808826177 ps
CPU time 10.58 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:35 PM PDT 24
Peak memory 220380 kb
Host smart-29b88140-bf51-4aea-b5c5-81a8da5f09c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290427206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3290427206
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2722667829
Short name T721
Test name
Test status
Simulation time 36003859 ps
CPU time 1.97 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 214032 kb
Host smart-c33533a9-169e-4f60-995e-16c63b95f648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722667829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2722667829
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3202202451
Short name T903
Test name
Test status
Simulation time 174451236 ps
CPU time 5.45 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 222256 kb
Host smart-1817f428-a41c-400f-b9b3-29576ff5f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202202451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3202202451
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1190495240
Short name T509
Test name
Test status
Simulation time 467654731 ps
CPU time 5.63 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:29 PM PDT 24
Peak memory 208928 kb
Host smart-30b3bdf8-83bb-47c2-947f-ba7b423b8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190495240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1190495240
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.171472487
Short name T619
Test name
Test status
Simulation time 130205479 ps
CPU time 2.45 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 206632 kb
Host smart-0b217f9b-44e8-4dcf-b465-b9939d079598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171472487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.171472487
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1343066769
Short name T614
Test name
Test status
Simulation time 68349517 ps
CPU time 3.32 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:29 PM PDT 24
Peak memory 208188 kb
Host smart-e19c0346-7830-4081-be44-f9388c476469
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343066769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1343066769
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3572143396
Short name T258
Test name
Test status
Simulation time 156053558 ps
CPU time 2.53 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:27 PM PDT 24
Peak memory 208168 kb
Host smart-20ac7bf1-13ca-458e-b51c-bbe6ef061f43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572143396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3572143396
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2473809767
Short name T562
Test name
Test status
Simulation time 383587370 ps
CPU time 3.84 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:30 PM PDT 24
Peak memory 208300 kb
Host smart-88247b70-a637-4732-8124-7b8a1f35c755
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473809767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2473809767
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1230099915
Short name T505
Test name
Test status
Simulation time 852101937 ps
CPU time 7.45 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:30 PM PDT 24
Peak memory 217956 kb
Host smart-4a56da10-75e4-417a-9b92-d28d369c872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230099915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1230099915
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1034989633
Short name T544
Test name
Test status
Simulation time 253859497 ps
CPU time 2.78 seconds
Started Jul 23 05:47:23 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 206608 kb
Host smart-ab1a577f-5db7-414f-989d-4ffc8ede0b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034989633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1034989633
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.161098018
Short name T226
Test name
Test status
Simulation time 893218281 ps
CPU time 9.64 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 220204 kb
Host smart-da0919c2-162a-4fd3-93b1-72ecab0f7a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161098018 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.161098018
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4049471426
Short name T304
Test name
Test status
Simulation time 140145884 ps
CPU time 2.82 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 218304 kb
Host smart-437301c6-8c7d-4b22-a96f-21b986ae066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049471426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4049471426
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.915091633
Short name T405
Test name
Test status
Simulation time 36487199 ps
CPU time 1.97 seconds
Started Jul 23 05:47:22 PM PDT 24
Finished Jul 23 05:47:30 PM PDT 24
Peak memory 209760 kb
Host smart-f0066c7d-4522-4474-841f-a30bfe8dba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915091633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.915091633
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2523197751
Short name T567
Test name
Test status
Simulation time 58385964 ps
CPU time 1 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 205884 kb
Host smart-cafd6e40-05a4-4525-8b94-65ec78ad919d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523197751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2523197751
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3251955951
Short name T280
Test name
Test status
Simulation time 269434376 ps
CPU time 2.64 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 214068 kb
Host smart-56c50c4e-1ecf-4e77-8422-cc537e39d329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251955951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3251955951
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1377247685
Short name T29
Test name
Test status
Simulation time 82151936 ps
CPU time 2.96 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 209104 kb
Host smart-ba88103f-c8e4-458b-8633-7b86dbdfd84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377247685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1377247685
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.637773112
Short name T86
Test name
Test status
Simulation time 169666431 ps
CPU time 2.08 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 217896 kb
Host smart-de2358ff-f4a6-48d5-b916-bf40c76e347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637773112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.637773112
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2211543879
Short name T575
Test name
Test status
Simulation time 194712547 ps
CPU time 3.49 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 209900 kb
Host smart-c53cc0b0-c87f-4668-99b4-92f544fa8b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211543879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2211543879
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1128379347
Short name T847
Test name
Test status
Simulation time 1216051677 ps
CPU time 6.32 seconds
Started Jul 23 05:47:27 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 214684 kb
Host smart-14528449-9db1-4968-acd1-c8ab4bd95b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128379347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1128379347
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1191448297
Short name T318
Test name
Test status
Simulation time 1740722516 ps
CPU time 3.53 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 214148 kb
Host smart-1635ec1c-ded1-4a0a-b2bc-1fa89e7ea534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191448297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1191448297
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3447771106
Short name T366
Test name
Test status
Simulation time 167521177 ps
CPU time 4.09 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 217804 kb
Host smart-fdc2bbf8-6be4-4f40-8bd4-f7fa2c34d117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447771106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3447771106
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4128550275
Short name T637
Test name
Test status
Simulation time 76116889 ps
CPU time 3.01 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 206460 kb
Host smart-cb61cdfe-77c6-4c18-90bf-6f7a11dcf8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128550275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4128550275
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3190373849
Short name T762
Test name
Test status
Simulation time 107161040 ps
CPU time 3.58 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 208276 kb
Host smart-027f65ad-71c8-4700-89c5-4c5481069dc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190373849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3190373849
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1660216675
Short name T373
Test name
Test status
Simulation time 50478125 ps
CPU time 2.63 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 207916 kb
Host smart-dea47a28-3ccf-40df-9378-b143cd444030
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660216675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1660216675
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2426445311
Short name T472
Test name
Test status
Simulation time 48051337 ps
CPU time 2.46 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 206900 kb
Host smart-f43017ac-f415-4d68-8ccb-506ac6fe4fc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426445311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2426445311
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2670713847
Short name T208
Test name
Test status
Simulation time 301578990 ps
CPU time 2.54 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 207804 kb
Host smart-d7391c93-6a91-4bbe-b92f-9dda88bcc7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670713847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2670713847
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1853306797
Short name T185
Test name
Test status
Simulation time 39260487 ps
CPU time 2.56 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 208356 kb
Host smart-5e0bccdf-81cd-4038-9a3a-93af9ef6464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853306797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1853306797
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3964593000
Short name T878
Test name
Test status
Simulation time 2570337827 ps
CPU time 18.26 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:54 PM PDT 24
Peak memory 215800 kb
Host smart-5926b9d2-281b-4803-85c0-f17abf4ef8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964593000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3964593000
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1773506027
Short name T136
Test name
Test status
Simulation time 264543119 ps
CPU time 10.34 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:55 PM PDT 24
Peak memory 218424 kb
Host smart-8db757f4-7f7c-4ad4-a9cb-d85744b3b664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773506027 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1773506027
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2745644339
Short name T777
Test name
Test status
Simulation time 108704032 ps
CPU time 2.26 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 217780 kb
Host smart-692377d0-1144-4646-b023-4c00fbd6e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745644339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2745644339
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1732382480
Short name T851
Test name
Test status
Simulation time 636896393 ps
CPU time 1.65 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 209684 kb
Host smart-dbfa586a-e456-4a0d-8dd1-e284120bfc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732382480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1732382480
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3538685034
Short name T451
Test name
Test status
Simulation time 12340770 ps
CPU time 0.71 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 205796 kb
Host smart-1f44b256-a673-4ade-9b51-5aa8120d5b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538685034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3538685034
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1422546490
Short name T606
Test name
Test status
Simulation time 85307712 ps
CPU time 2.87 seconds
Started Jul 23 05:47:33 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 209072 kb
Host smart-3bc55c9d-4e1e-4fa9-a64e-38f3771c875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422546490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1422546490
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1287940341
Short name T61
Test name
Test status
Simulation time 1761526699 ps
CPU time 3.66 seconds
Started Jul 23 05:47:23 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 207532 kb
Host smart-f06f40dc-9bb4-4677-93d9-038a2dcc9c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287940341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1287940341
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4134225625
Short name T108
Test name
Test status
Simulation time 254637719 ps
CPU time 3.64 seconds
Started Jul 23 05:47:27 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 214060 kb
Host smart-cf6f1733-9d45-4aad-af11-173dc743f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134225625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4134225625
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1530218055
Short name T513
Test name
Test status
Simulation time 69967131 ps
CPU time 2.41 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:35 PM PDT 24
Peak memory 216328 kb
Host smart-f0adcf3c-5253-46c2-946c-f00dadcd9a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530218055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1530218055
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2760726374
Short name T578
Test name
Test status
Simulation time 3539766634 ps
CPU time 8.75 seconds
Started Jul 23 05:47:27 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 218160 kb
Host smart-73dcbb31-8724-40b9-a1a7-e403c08472e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760726374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2760726374
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.829337649
Short name T394
Test name
Test status
Simulation time 227416220 ps
CPU time 6.41 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 207624 kb
Host smart-57fe4fdc-6b98-4746-bef5-ccf29e30bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829337649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.829337649
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.671452585
Short name T785
Test name
Test status
Simulation time 91433088 ps
CPU time 3.45 seconds
Started Jul 23 05:47:33 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 208592 kb
Host smart-c686756a-23f5-4478-9e44-2097cb4801fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671452585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.671452585
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1293977023
Short name T369
Test name
Test status
Simulation time 198569874 ps
CPU time 2.5 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 208504 kb
Host smart-0fbf2ea0-51e7-4688-a97a-2cd54168d162
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293977023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1293977023
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3957092738
Short name T387
Test name
Test status
Simulation time 39302159 ps
CPU time 2.69 seconds
Started Jul 23 05:47:23 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 208476 kb
Host smart-34f5b799-2734-4c15-98b7-b6be458230b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957092738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3957092738
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1461204083
Short name T656
Test name
Test status
Simulation time 188548524 ps
CPU time 2.7 seconds
Started Jul 23 05:47:27 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 214052 kb
Host smart-d6f7ba72-bb99-4e10-9cd0-7bfd5c882ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461204083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1461204083
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2163578071
Short name T814
Test name
Test status
Simulation time 34212217 ps
CPU time 2.44 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:47:40 PM PDT 24
Peak memory 208252 kb
Host smart-6ca0b447-8e8a-4e72-80d6-e00f26da9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163578071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2163578071
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1171924446
Short name T834
Test name
Test status
Simulation time 2200709351 ps
CPU time 38.49 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 216628 kb
Host smart-c1e0687f-f315-43c7-98d0-128a497111a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171924446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1171924446
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3817842994
Short name T53
Test name
Test status
Simulation time 550128965 ps
CPU time 16.84 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 222488 kb
Host smart-cb09626b-4a8d-4531-b792-d5a7400f6f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817842994 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3817842994
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2918498683
Short name T480
Test name
Test status
Simulation time 285183467 ps
CPU time 6.45 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 209984 kb
Host smart-b9525509-578f-420f-b79d-dce93d9641ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918498683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2918498683
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2734161712
Short name T410
Test name
Test status
Simulation time 98459481 ps
CPU time 2.17 seconds
Started Jul 23 05:47:30 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 209576 kb
Host smart-c404abb4-0a2d-4ecd-bb68-e55c77c50475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734161712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2734161712
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3972721914
Short name T17
Test name
Test status
Simulation time 19749264 ps
CPU time 0.74 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 205828 kb
Host smart-bc091543-229f-40a9-82ed-707953859f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972721914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3972721914
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1745627298
Short name T352
Test name
Test status
Simulation time 1234364785 ps
CPU time 65.4 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:45:41 PM PDT 24
Peak memory 214180 kb
Host smart-44ae0f5b-9a9c-40a4-baa5-4ad435a698df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1745627298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1745627298
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3793400405
Short name T725
Test name
Test status
Simulation time 442241173 ps
CPU time 5.2 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 209140 kb
Host smart-d5d7a69b-524f-44f6-85b7-4de4fe332084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793400405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3793400405
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2014317574
Short name T868
Test name
Test status
Simulation time 151457948 ps
CPU time 4.39 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:47 PM PDT 24
Peak memory 213952 kb
Host smart-7cd8ddfe-108c-48df-ac62-471492fb81c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014317574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2014317574
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2449677186
Short name T864
Test name
Test status
Simulation time 166193773 ps
CPU time 3.08 seconds
Started Jul 23 05:44:29 PM PDT 24
Finished Jul 23 05:44:36 PM PDT 24
Peak memory 209232 kb
Host smart-2d9f4bb2-4938-4553-a95f-c50941e01b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449677186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2449677186
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2554524299
Short name T218
Test name
Test status
Simulation time 103375241 ps
CPU time 4.45 seconds
Started Jul 23 05:44:31 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 214032 kb
Host smart-05f3b20c-7b96-4b5a-80e0-15fe37786f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554524299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2554524299
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3375397569
Short name T44
Test name
Test status
Simulation time 418559872 ps
CPU time 5.76 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 237240 kb
Host smart-a44597ed-d0f2-4610-b093-76e15a8dff90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375397569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3375397569
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3413810934
Short name T820
Test name
Test status
Simulation time 152727657 ps
CPU time 3.04 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:38 PM PDT 24
Peak memory 206592 kb
Host smart-e8d234af-f0cf-421e-91f9-e179646af28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413810934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3413810934
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.5370263
Short name T519
Test name
Test status
Simulation time 1143332394 ps
CPU time 6.18 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 208300 kb
Host smart-15b2d385-3d31-4985-a1e0-56430af758b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5370263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.5370263
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1706560272
Short name T364
Test name
Test status
Simulation time 56739507 ps
CPU time 2.87 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 208216 kb
Host smart-8a2815d9-60f5-44f1-94e3-7ef69b2a02be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706560272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1706560272
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3268516729
Short name T741
Test name
Test status
Simulation time 10881028149 ps
CPU time 29.26 seconds
Started Jul 23 05:44:32 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 208768 kb
Host smart-58e788a9-805e-471d-90d3-0cd395239251
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268516729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3268516729
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4024330038
Short name T744
Test name
Test status
Simulation time 45774645 ps
CPU time 2.06 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 207756 kb
Host smart-a1145c21-19ca-40c5-82fd-4965f345ab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024330038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4024330038
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4200654946
Short name T447
Test name
Test status
Simulation time 8463844658 ps
CPU time 27.83 seconds
Started Jul 23 05:44:35 PM PDT 24
Finished Jul 23 05:45:05 PM PDT 24
Peak memory 207944 kb
Host smart-bc8ee9a5-26e9-40f5-9c07-a376c9b11420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200654946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4200654946
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1036997479
Short name T894
Test name
Test status
Simulation time 319763223 ps
CPU time 3.52 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 206872 kb
Host smart-a437ceea-7865-47f8-8985-46877527ee18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036997479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1036997479
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1211505841
Short name T673
Test name
Test status
Simulation time 758484337 ps
CPU time 18.91 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 222124 kb
Host smart-bc956f50-010d-4b9c-ba3e-3a3fed2eaa2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211505841 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1211505841
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1787405478
Short name T600
Test name
Test status
Simulation time 400232107 ps
CPU time 7.54 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 208616 kb
Host smart-4f1865be-57e1-44a8-b868-d1a71fe5a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787405478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1787405478
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3039872788
Short name T190
Test name
Test status
Simulation time 146132533 ps
CPU time 1.39 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 209308 kb
Host smart-777ec4e1-d2ed-4349-bc6a-24b2e78ac027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039872788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3039872788
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2063905814
Short name T833
Test name
Test status
Simulation time 22681469 ps
CPU time 0.76 seconds
Started Jul 23 05:47:40 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 205812 kb
Host smart-a63a4910-f466-4d19-9672-4e33b8f6d06b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063905814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2063905814
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2467934598
Short name T780
Test name
Test status
Simulation time 184688888 ps
CPU time 2.65 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 217600 kb
Host smart-cfc917d8-66fe-4bec-b2a0-ffffface3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467934598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2467934598
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1569629762
Short name T564
Test name
Test status
Simulation time 361645650 ps
CPU time 4.34 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 209448 kb
Host smart-da2e2e3c-4ee3-4345-9008-38d44131b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569629762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1569629762
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3788051127
Short name T252
Test name
Test status
Simulation time 82181948 ps
CPU time 1.63 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:46 PM PDT 24
Peak memory 214040 kb
Host smart-dadaf584-1e16-4fb2-85a9-a6d5306b8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788051127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3788051127
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3090008675
Short name T676
Test name
Test status
Simulation time 610092975 ps
CPU time 3.05 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 214096 kb
Host smart-c6a075d2-94c4-4e98-bcb4-8b72f98e3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090008675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3090008675
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3715232670
Short name T552
Test name
Test status
Simulation time 58242987 ps
CPU time 3.28 seconds
Started Jul 23 05:47:40 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 208300 kb
Host smart-95fd5e31-5d52-4c0b-a7f4-cb1e168aa603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715232670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3715232670
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.4037176857
Short name T889
Test name
Test status
Simulation time 143063016 ps
CPU time 2.34 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 207208 kb
Host smart-0bf09ddf-18dd-42f2-a00e-89a258bbc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037176857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4037176857
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1088426757
Short name T786
Test name
Test status
Simulation time 137358870 ps
CPU time 3.21 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:46 PM PDT 24
Peak memory 208240 kb
Host smart-24c7d31a-92cb-4fb4-a6ec-5d0d7dee020b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088426757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1088426757
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1754894223
Short name T687
Test name
Test status
Simulation time 1106285447 ps
CPU time 6.26 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 208568 kb
Host smart-9851c2d3-6c56-4555-9ba2-95046d4f0509
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754894223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1754894223
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4041051553
Short name T353
Test name
Test status
Simulation time 36517637 ps
CPU time 2.38 seconds
Started Jul 23 05:47:32 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 206696 kb
Host smart-543984f7-981e-4612-948e-a92a1ddda6b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041051553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4041051553
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2379918639
Short name T605
Test name
Test status
Simulation time 50181302 ps
CPU time 2.57 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 207992 kb
Host smart-957ffb9c-cc6e-42c1-9cc6-5bb005d588a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379918639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2379918639
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2645868104
Short name T475
Test name
Test status
Simulation time 331198513 ps
CPU time 4.56 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 214048 kb
Host smart-0dd0b0d2-f197-46c8-8b61-4b57ec039cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645868104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2645868104
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1501153057
Short name T497
Test name
Test status
Simulation time 69952499 ps
CPU time 2.16 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 205864 kb
Host smart-ee1ac8c4-f59f-4fcb-8ae2-44429bc396a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501153057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1501153057
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3123012140
Short name T789
Test name
Test status
Simulation time 431239849 ps
CPU time 16.71 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 219436 kb
Host smart-59ae2d14-fdb1-4760-9dad-55c60db5a6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123012140 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3123012140
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3382687331
Short name T760
Test name
Test status
Simulation time 614237145 ps
CPU time 16.6 seconds
Started Jul 23 05:47:34 PM PDT 24
Finished Jul 23 05:47:57 PM PDT 24
Peak memory 209616 kb
Host smart-dbeedfc3-679c-48e2-a42c-747d9a46fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382687331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3382687331
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2492570362
Short name T755
Test name
Test status
Simulation time 100724985 ps
CPU time 2.14 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 209844 kb
Host smart-6fc67351-77f9-4de6-b9e0-50817642cb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492570362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2492570362
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.458558564
Short name T623
Test name
Test status
Simulation time 12954275 ps
CPU time 0.77 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 205836 kb
Host smart-c60bf550-924f-4944-b51f-e1d70181d190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458558564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.458558564
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.642379875
Short name T434
Test name
Test status
Simulation time 37790395 ps
CPU time 2.96 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 214232 kb
Host smart-1d9d5969-e830-43b6-9caf-e4c8e3747615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642379875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.642379875
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2780731423
Short name T33
Test name
Test status
Simulation time 269088054 ps
CPU time 3.19 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 214360 kb
Host smart-147fbc3f-4688-429e-bb96-c469a1362b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780731423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2780731423
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.63835572
Short name T598
Test name
Test status
Simulation time 97814478 ps
CPU time 1.59 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 208848 kb
Host smart-da665ffc-5ceb-40a6-a1e5-e17962f1bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63835572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.63835572
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.19131920
Short name T547
Test name
Test status
Simulation time 50471947 ps
CPU time 2.17 seconds
Started Jul 23 05:47:41 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 214100 kb
Host smart-240cbc90-ec63-412f-8bcd-bd40065e8287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19131920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.19131920
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1140731418
Short name T8
Test name
Test status
Simulation time 144463986 ps
CPU time 3.79 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 215196 kb
Host smart-502c4bcd-8b12-4eb5-8fc1-f800c6c0c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140731418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1140731418
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3941908925
Short name T291
Test name
Test status
Simulation time 93151861 ps
CPU time 2.85 seconds
Started Jul 23 05:47:32 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 214036 kb
Host smart-bfdc9af0-a94d-4c86-a572-28e39e2dd6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941908925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3941908925
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.913709812
Short name T583
Test name
Test status
Simulation time 493924341 ps
CPU time 4.66 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:46 PM PDT 24
Peak memory 208336 kb
Host smart-6c00274a-bee7-41ed-b99b-3e57c838a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913709812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.913709812
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1030925118
Short name T849
Test name
Test status
Simulation time 1562753120 ps
CPU time 4.51 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 206524 kb
Host smart-5b3ce80a-91b0-48e4-b092-78bbf8f8f072
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030925118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1030925118
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3834687646
Short name T902
Test name
Test status
Simulation time 243331338 ps
CPU time 2.8 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 206648 kb
Host smart-39c92bfd-6033-4c7d-bc1e-0317a1877e1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834687646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3834687646
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3027685644
Short name T542
Test name
Test status
Simulation time 466142969 ps
CPU time 5.01 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 208120 kb
Host smart-b96d8931-2a1f-4851-bbf1-026d1edce15a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027685644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3027685644
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.953559447
Short name T316
Test name
Test status
Simulation time 186597282 ps
CPU time 1.64 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 209052 kb
Host smart-b689f24a-66e7-41bc-9412-ec0ce62dbee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953559447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.953559447
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.926651905
Short name T454
Test name
Test status
Simulation time 907967655 ps
CPU time 3.35 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 208596 kb
Host smart-c1a61cac-84e4-4019-85ad-4bbc7db29715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926651905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.926651905
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2135222513
Short name T865
Test name
Test status
Simulation time 41858025 ps
CPU time 2.25 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 208100 kb
Host smart-9ccf5c9d-18a6-4980-ac0c-1f319273b8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135222513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2135222513
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3903918172
Short name T838
Test name
Test status
Simulation time 97749703 ps
CPU time 4.27 seconds
Started Jul 23 05:47:43 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 214056 kb
Host smart-1dded7b6-ada7-49d9-83a0-c4ad9b40a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903918172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3903918172
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3495601656
Short name T495
Test name
Test status
Simulation time 577964896 ps
CPU time 5.78 seconds
Started Jul 23 05:47:40 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 210340 kb
Host smart-f30b0ca3-3b8a-4717-bc4b-16901518de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495601656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3495601656
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2273489506
Short name T446
Test name
Test status
Simulation time 9379333 ps
CPU time 0.73 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 205828 kb
Host smart-6476c6df-befd-42b5-84de-20a2e96eac0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273489506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2273489506
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.756934990
Short name T906
Test name
Test status
Simulation time 1925541445 ps
CPU time 8.82 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 215024 kb
Host smart-e79fe3fd-cefe-4576-95db-2d6dc4f6c213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756934990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.756934990
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1301383924
Short name T582
Test name
Test status
Simulation time 558662474 ps
CPU time 4.89 seconds
Started Jul 23 05:47:53 PM PDT 24
Finished Jul 23 05:47:59 PM PDT 24
Peak memory 214060 kb
Host smart-be99f967-2013-4603-9517-a7b0f86546f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301383924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1301383924
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1401819350
Short name T499
Test name
Test status
Simulation time 374989436 ps
CPU time 3.33 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 207780 kb
Host smart-895b15d4-8a93-4d94-9084-efc272191b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401819350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1401819350
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1855398897
Short name T336
Test name
Test status
Simulation time 87203315 ps
CPU time 4.32 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:55 PM PDT 24
Peak memory 214060 kb
Host smart-83952d0e-a2e2-4133-b6d8-ccdd9bae41a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855398897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1855398897
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2734079856
Short name T781
Test name
Test status
Simulation time 383218716 ps
CPU time 3.24 seconds
Started Jul 23 05:47:49 PM PDT 24
Finished Jul 23 05:47:56 PM PDT 24
Peak memory 214020 kb
Host smart-a23755ce-55d6-4654-adf6-c8a66aa5d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734079856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2734079856
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2059595205
Short name T672
Test name
Test status
Simulation time 58243046 ps
CPU time 2.23 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 219928 kb
Host smart-e39adf21-91aa-4c9e-9b73-370cc6225e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059595205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2059595205
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3560195278
Short name T267
Test name
Test status
Simulation time 67923228 ps
CPU time 3.51 seconds
Started Jul 23 05:47:40 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 208792 kb
Host smart-3cd87d54-5f21-44dc-be6e-a203f19d3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560195278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3560195278
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4125004140
Short name T867
Test name
Test status
Simulation time 847796406 ps
CPU time 6.6 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 207772 kb
Host smart-03d700bc-1e18-4c5b-a070-1ed8eb6d6184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125004140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4125004140
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2369012253
Short name T580
Test name
Test status
Simulation time 94906979 ps
CPU time 3.4 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 206700 kb
Host smart-24829538-586f-47c7-8922-7be5a1ea47a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369012253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2369012253
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2651855715
Short name T712
Test name
Test status
Simulation time 121370650 ps
CPU time 3.63 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 208344 kb
Host smart-ef539c16-9678-487f-90f9-f423205477b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651855715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2651855715
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3336276940
Short name T634
Test name
Test status
Simulation time 100632614 ps
CPU time 2.68 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:54 PM PDT 24
Peak memory 206708 kb
Host smart-c792a8c1-e89b-4dc1-a17c-39019b787f84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336276940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3336276940
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3093633884
Short name T520
Test name
Test status
Simulation time 13145277768 ps
CPU time 43.09 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:48:32 PM PDT 24
Peak memory 214180 kb
Host smart-864d41c9-bd2f-4094-bc88-b5bb6efc2bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093633884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3093633884
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1486332456
Short name T627
Test name
Test status
Simulation time 149888863 ps
CPU time 5.39 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 208232 kb
Host smart-96ec751a-fa17-4bec-836d-9ced879f7298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486332456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1486332456
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2710754157
Short name T343
Test name
Test status
Simulation time 823501575 ps
CPU time 13.07 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 214840 kb
Host smart-d4575e25-62bd-4efe-b696-d162ee27ebfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710754157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2710754157
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2288871088
Short name T324
Test name
Test status
Simulation time 764468375 ps
CPU time 25.1 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 208072 kb
Host smart-1061b04b-ebcb-45f5-ae09-9a7b2c6acbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288871088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2288871088
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.488717731
Short name T546
Test name
Test status
Simulation time 18553769 ps
CPU time 0.85 seconds
Started Jul 23 05:48:03 PM PDT 24
Finished Jul 23 05:48:06 PM PDT 24
Peak memory 205832 kb
Host smart-b94b194b-23f9-4104-ace0-1fa1bc5efbfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488717731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.488717731
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1774356794
Short name T437
Test name
Test status
Simulation time 289399677 ps
CPU time 4.14 seconds
Started Jul 23 05:47:43 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 214056 kb
Host smart-9d94d9c8-d397-4508-8459-a3d4b49b7c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774356794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1774356794
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4128304726
Short name T916
Test name
Test status
Simulation time 186759828 ps
CPU time 5.73 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:55 PM PDT 24
Peak memory 208584 kb
Host smart-c1629bbb-a5e3-4e70-b618-ec80fd1a5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128304726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4128304726
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2559856205
Short name T66
Test name
Test status
Simulation time 2266090764 ps
CPU time 4.83 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 209008 kb
Host smart-b3b48b83-9084-4594-9ff1-ec74363a2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559856205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2559856205
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.705120326
Short name T100
Test name
Test status
Simulation time 52456601 ps
CPU time 2.08 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 213960 kb
Host smart-a58daa5f-0966-410d-901e-6caec2e022ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705120326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.705120326
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_random.3677899194
Short name T327
Test name
Test status
Simulation time 2399933516 ps
CPU time 40.82 seconds
Started Jul 23 05:47:48 PM PDT 24
Finished Jul 23 05:48:33 PM PDT 24
Peak memory 218280 kb
Host smart-9e054cb2-0001-4a0a-b028-ec18a7d6b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677899194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3677899194
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1708320677
Short name T861
Test name
Test status
Simulation time 51945478 ps
CPU time 2.56 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 206516 kb
Host smart-d1278291-89ad-4f5d-bac6-00170b0fdc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708320677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1708320677
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.525645451
Short name T308
Test name
Test status
Simulation time 274049001 ps
CPU time 3.03 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 206700 kb
Host smart-63838d30-5824-4e01-8a2b-6ba834b51eb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525645451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.525645451
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3989470104
Short name T90
Test name
Test status
Simulation time 774458724 ps
CPU time 6.15 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 207824 kb
Host smart-9e034c29-7c08-4d8a-b671-f1bd60a7063d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989470104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3989470104
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1383615224
Short name T872
Test name
Test status
Simulation time 918583563 ps
CPU time 7.27 seconds
Started Jul 23 05:47:49 PM PDT 24
Finished Jul 23 05:48:00 PM PDT 24
Peak memory 208444 kb
Host smart-691841a8-2cd0-456b-88fc-29da83dcec5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383615224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1383615224
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.675815207
Short name T636
Test name
Test status
Simulation time 796968091 ps
CPU time 7.36 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:04 PM PDT 24
Peak memory 208984 kb
Host smart-65690b9d-472d-4a47-88be-d0308683e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675815207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.675815207
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.801610608
Short name T776
Test name
Test status
Simulation time 206803815 ps
CPU time 6.28 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:54 PM PDT 24
Peak memory 208664 kb
Host smart-fecb786f-adbe-44dd-acd2-42c172ca8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801610608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.801610608
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2719658836
Short name T89
Test name
Test status
Simulation time 6089251875 ps
CPU time 33.09 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 221428 kb
Host smart-4c67d979-f228-48a4-9d49-4eeea2d58c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719658836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2719658836
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2083344160
Short name T376
Test name
Test status
Simulation time 99186713 ps
CPU time 3.39 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 207288 kb
Host smart-6bde9b64-c8c0-414d-83b7-7d4021bc296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083344160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2083344160
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1534880802
Short name T407
Test name
Test status
Simulation time 310525531 ps
CPU time 2.89 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:05 PM PDT 24
Peak memory 210108 kb
Host smart-77c296b1-a8e5-40d4-9fb0-7ee7d538a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534880802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1534880802
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2369329912
Short name T668
Test name
Test status
Simulation time 38914469 ps
CPU time 0.86 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:47:59 PM PDT 24
Peak memory 205832 kb
Host smart-bdc10827-06c4-4d99-bdc3-8015e938d554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369329912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2369329912
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1067736994
Short name T438
Test name
Test status
Simulation time 151317997 ps
CPU time 7.98 seconds
Started Jul 23 05:48:00 PM PDT 24
Finished Jul 23 05:48:11 PM PDT 24
Peak memory 215040 kb
Host smart-1392778d-e526-42e7-a52e-a002ae5cdd22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067736994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1067736994
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2049495877
Short name T831
Test name
Test status
Simulation time 38161785 ps
CPU time 2.55 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 217656 kb
Host smart-8aacdbfd-4ea6-4b6c-b1cf-1794c8e92653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049495877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2049495877
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3990066408
Short name T266
Test name
Test status
Simulation time 179333935 ps
CPU time 3.86 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:04 PM PDT 24
Peak memory 207184 kb
Host smart-9c828db8-b316-40de-9b89-097b6b23c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990066408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3990066408
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3380695866
Short name T655
Test name
Test status
Simulation time 271676706 ps
CPU time 6.67 seconds
Started Jul 23 05:48:00 PM PDT 24
Finished Jul 23 05:48:10 PM PDT 24
Peak memory 220736 kb
Host smart-f958370e-ef9b-4701-a96a-7af7da105abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380695866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3380695866
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2087148807
Short name T869
Test name
Test status
Simulation time 360635336 ps
CPU time 3.6 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:01 PM PDT 24
Peak memory 214080 kb
Host smart-3b2aa332-2d77-4b3e-ab9c-81185de2e5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087148807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2087148807
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.392351104
Short name T608
Test name
Test status
Simulation time 728640438 ps
CPU time 9.35 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:06 PM PDT 24
Peak memory 209568 kb
Host smart-a17814b6-ed8a-47a0-ab72-ad2f7fb77c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392351104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.392351104
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2403064118
Short name T718
Test name
Test status
Simulation time 584430329 ps
CPU time 7.02 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:06 PM PDT 24
Peak memory 217980 kb
Host smart-40392205-a793-4fa0-bb36-8ddf7e916856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403064118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2403064118
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1660734469
Short name T730
Test name
Test status
Simulation time 146259177 ps
CPU time 2.61 seconds
Started Jul 23 05:47:54 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 208352 kb
Host smart-abedc725-deb3-4970-ba38-07559e11d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660734469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1660734469
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4191619413
Short name T706
Test name
Test status
Simulation time 106845867 ps
CPU time 3.65 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:05 PM PDT 24
Peak memory 206572 kb
Host smart-a8369b2b-409c-435f-b68e-1a94eada9d94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191619413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4191619413
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1012185704
Short name T722
Test name
Test status
Simulation time 2466502972 ps
CPU time 4.78 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:06 PM PDT 24
Peak memory 206664 kb
Host smart-51d9a8db-4757-41f4-9610-8f7023747fa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012185704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1012185704
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2040906227
Short name T739
Test name
Test status
Simulation time 210143179 ps
CPU time 7.71 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:08 PM PDT 24
Peak memory 208592 kb
Host smart-e9592da9-4b0c-4f94-8dbe-af8695f2d4bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040906227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2040906227
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3486428629
Short name T193
Test name
Test status
Simulation time 2610720878 ps
CPU time 14.89 seconds
Started Jul 23 05:47:59 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 209428 kb
Host smart-aac35feb-68aa-4f4a-8fd8-df9c063fc660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486428629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3486428629
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2963500816
Short name T688
Test name
Test status
Simulation time 821510446 ps
CPU time 4.22 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 208372 kb
Host smart-e60a8d8f-2807-4b9f-ac15-041a53651a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963500816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2963500816
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1230358024
Short name T714
Test name
Test status
Simulation time 1977256483 ps
CPU time 46.51 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:48 PM PDT 24
Peak memory 216384 kb
Host smart-c27babc2-cd5d-4f57-8d4a-13601a4a6556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230358024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1230358024
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1046505025
Short name T589
Test name
Test status
Simulation time 795429907 ps
CPU time 7.68 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:08 PM PDT 24
Peak memory 222364 kb
Host smart-a6d5c9c4-5ab2-458f-8fcf-8b4b5bb96bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046505025 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1046505025
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.36991891
Short name T205
Test name
Test status
Simulation time 157786982 ps
CPU time 5.18 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:01 PM PDT 24
Peak memory 210004 kb
Host smart-1e6e7ca4-23c3-4763-95d0-046f16fdc2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36991891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.36991891
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3220446702
Short name T641
Test name
Test status
Simulation time 160400173 ps
CPU time 2.16 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 209820 kb
Host smart-86ad9ca6-daac-4fac-a4eb-1dc485e92746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220446702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3220446702
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3378612305
Short name T825
Test name
Test status
Simulation time 17308628 ps
CPU time 0.95 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:13 PM PDT 24
Peak memory 205868 kb
Host smart-0568d2eb-8ffa-4cb7-80b2-1a3132ef7eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378612305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3378612305
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1073895577
Short name T345
Test name
Test status
Simulation time 700728412 ps
CPU time 9.8 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 222212 kb
Host smart-a18dcb9d-5679-4428-ae87-e215eb0c95bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073895577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1073895577
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1826175521
Short name T747
Test name
Test status
Simulation time 221843965 ps
CPU time 3.02 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 217576 kb
Host smart-ec1b1807-5262-4758-84bf-1b860b7e0838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826175521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1826175521
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1447818344
Short name T891
Test name
Test status
Simulation time 662411952 ps
CPU time 7.08 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 208140 kb
Host smart-b66ccd0f-ee9d-436a-9750-60f3134ef9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447818344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1447818344
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3502675171
Short name T666
Test name
Test status
Simulation time 1131329777 ps
CPU time 8.85 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:26 PM PDT 24
Peak memory 208956 kb
Host smart-6c08a195-e8b6-476a-b9a5-68081853ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502675171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3502675171
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1760210129
Short name T310
Test name
Test status
Simulation time 272263899 ps
CPU time 2.9 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 213976 kb
Host smart-08fe06d3-39c8-4491-baa0-3d67f6baf020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760210129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1760210129
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3160815555
Short name T251
Test name
Test status
Simulation time 79801560 ps
CPU time 3.06 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 207368 kb
Host smart-e883ed2a-56a2-4f4b-8e29-27fcd54b40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160815555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3160815555
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.230654605
Short name T653
Test name
Test status
Simulation time 1993134622 ps
CPU time 4.71 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 214048 kb
Host smart-f16c5386-e737-4866-b081-1d06a448178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230654605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.230654605
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.659631294
Short name T195
Test name
Test status
Simulation time 52777969 ps
CPU time 2.81 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 208284 kb
Host smart-9dd9b990-a09a-44d1-811d-f867ef46ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659631294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.659631294
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2150534560
Short name T539
Test name
Test status
Simulation time 208290552 ps
CPU time 2.91 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:15 PM PDT 24
Peak memory 206900 kb
Host smart-418afa94-1d77-4edd-ac38-3313b148d98f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150534560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2150534560
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1484765498
Short name T478
Test name
Test status
Simulation time 347962102 ps
CPU time 3.28 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 208304 kb
Host smart-c17fc591-d5b3-49cf-bb74-2e0b584963ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484765498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1484765498
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2200000462
Short name T457
Test name
Test status
Simulation time 191895060 ps
CPU time 5.15 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 208492 kb
Host smart-ef4c452f-85e4-4ebb-979b-04ec17c4896e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200000462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2200000462
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2367971615
Short name T856
Test name
Test status
Simulation time 364676239 ps
CPU time 3.2 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 206688 kb
Host smart-6200ea08-eb44-4b99-87f5-efa7c8dd4c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367971615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2367971615
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.701742303
Short name T745
Test name
Test status
Simulation time 94078049 ps
CPU time 1.66 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:11 PM PDT 24
Peak memory 206656 kb
Host smart-976034a5-5152-40d9-b4b8-c9ed3c39db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701742303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.701742303
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.869034494
Short name T423
Test name
Test status
Simulation time 348979936 ps
CPU time 8.49 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 221304 kb
Host smart-6d0cd992-bb5c-4965-b43c-174e89fd1a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869034494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.869034494
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.359751049
Short name T782
Test name
Test status
Simulation time 569970445 ps
CPU time 6.59 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 208692 kb
Host smart-ee79156f-ac17-498a-b471-7104b3d11459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359751049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.359751049
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.988077218
Short name T890
Test name
Test status
Simulation time 134313724 ps
CPU time 1.77 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:15 PM PDT 24
Peak memory 209524 kb
Host smart-2e8afdca-4f3a-4cf7-af30-12098a594227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988077218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.988077218
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2900608842
Short name T740
Test name
Test status
Simulation time 31553056 ps
CPU time 0.95 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 205888 kb
Host smart-d854afec-db21-4291-9d5a-f36c8dec4ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900608842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2900608842
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3272464172
Short name T41
Test name
Test status
Simulation time 2007276756 ps
CPU time 56.35 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:49:15 PM PDT 24
Peak memory 219964 kb
Host smart-e7c20128-2723-4e31-8ea7-c674378fc197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272464172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3272464172
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.957147197
Short name T754
Test name
Test status
Simulation time 662257196 ps
CPU time 7.94 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 208384 kb
Host smart-91088f81-2b48-45d0-a09a-3e4c4e10725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957147197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.957147197
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2384911701
Short name T101
Test name
Test status
Simulation time 244972720 ps
CPU time 3.61 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 208744 kb
Host smart-b4538ade-3e1b-4194-9a90-d2f95f8f1dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384911701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2384911701
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1719839726
Short name T516
Test name
Test status
Simulation time 96795073 ps
CPU time 3.26 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 214444 kb
Host smart-2d6b8a00-38b8-4ae1-8e38-5c2753a87c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719839726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1719839726
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2235822455
Short name T65
Test name
Test status
Simulation time 400033665 ps
CPU time 4.1 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 209788 kb
Host smart-8e4fb38b-71d0-474f-be08-49e16e61dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235822455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2235822455
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.108839877
Short name T689
Test name
Test status
Simulation time 1357252058 ps
CPU time 12.27 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 218032 kb
Host smart-ee339ce7-94d7-40d6-920d-e393abdea903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108839877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.108839877
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1921382505
Short name T212
Test name
Test status
Simulation time 228551217 ps
CPU time 1.87 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 205948 kb
Host smart-f41c3aaa-d73a-41cf-a5ae-9ad1140c8a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921382505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1921382505
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1513670022
Short name T284
Test name
Test status
Simulation time 46377200 ps
CPU time 2.44 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 206488 kb
Host smart-1b9b0873-c329-43dc-9fc8-3c37ffddae8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513670022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1513670022
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1835258174
Short name T184
Test name
Test status
Simulation time 1821032830 ps
CPU time 19.15 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:28 PM PDT 24
Peak memory 208180 kb
Host smart-05fff9ea-5331-4cb5-9cee-62196ba71d2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835258174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1835258174
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1746228239
Short name T183
Test name
Test status
Simulation time 41418210 ps
CPU time 1.72 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 206728 kb
Host smart-001a5cf1-9e81-4a65-9d19-01364dd8188a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746228239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1746228239
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2178632787
Short name T883
Test name
Test status
Simulation time 53546815 ps
CPU time 2.53 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:15 PM PDT 24
Peak memory 208692 kb
Host smart-765a9649-fa3d-49b4-9fad-10b137079c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178632787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2178632787
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3043605656
Short name T897
Test name
Test status
Simulation time 1232930507 ps
CPU time 3.25 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 208684 kb
Host smart-f52df431-1bda-4b7c-b596-6983aa67a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043605656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3043605656
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2443464651
Short name T287
Test name
Test status
Simulation time 3664905107 ps
CPU time 65.84 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:49:19 PM PDT 24
Peak memory 222264 kb
Host smart-c3404f18-c3e9-4580-97fa-636f56c045f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443464651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2443464651
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1415535353
Short name T115
Test name
Test status
Simulation time 190104011 ps
CPU time 5.12 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 218812 kb
Host smart-97598dbb-4de5-4697-a77c-f4e84baee681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415535353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1415535353
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2311773528
Short name T560
Test name
Test status
Simulation time 31346179 ps
CPU time 2.45 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:15 PM PDT 24
Peak memory 207940 kb
Host smart-7f70b63d-3eab-46e5-8e77-8348e010a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311773528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2311773528
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3995706150
Short name T430
Test name
Test status
Simulation time 507533175 ps
CPU time 4.71 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 210344 kb
Host smart-a7611cf4-e9dd-4a89-a598-9ea802d0746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995706150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3995706150
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.613587244
Short name T779
Test name
Test status
Simulation time 59518139 ps
CPU time 0.78 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 205844 kb
Host smart-5def05c2-46fe-43f3-b464-0c213ee6e76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613587244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.613587244
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3631847992
Short name T823
Test name
Test status
Simulation time 149082937 ps
CPU time 2.6 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 208976 kb
Host smart-74583c2b-0db4-4fdd-bf89-1f6be3328d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631847992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3631847992
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2843496994
Short name T486
Test name
Test status
Simulation time 147326076 ps
CPU time 2.42 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 207360 kb
Host smart-9616b9da-d4a9-4a4e-99ae-32af550d3f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843496994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2843496994
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1035589446
Short name T332
Test name
Test status
Simulation time 108880928 ps
CPU time 3.16 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 206944 kb
Host smart-7658ef24-0d10-48b5-b168-864606307933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035589446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1035589446
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.930806644
Short name T658
Test name
Test status
Simulation time 138001087 ps
CPU time 3.19 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 222180 kb
Host smart-6da1421b-4b35-4258-a30e-021e2a827b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930806644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.930806644
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1500452648
Short name T661
Test name
Test status
Simulation time 90879550 ps
CPU time 4.06 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 208472 kb
Host smart-726e247a-ef3a-41e5-b8d2-d7910ddfa406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500452648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1500452648
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.165405659
Short name T877
Test name
Test status
Simulation time 974837472 ps
CPU time 2.71 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 206732 kb
Host smart-9542a2aa-28ea-4968-ba02-d593675e53c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165405659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.165405659
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.262259539
Short name T377
Test name
Test status
Simulation time 475812143 ps
CPU time 2.9 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 206696 kb
Host smart-01038b3c-864d-4f5d-91a8-f059e1e103cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262259539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.262259539
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.541719339
Short name T621
Test name
Test status
Simulation time 80122577 ps
CPU time 2.99 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 206756 kb
Host smart-17eb9f10-fdd3-414d-bc31-6f98bd5692af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541719339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.541719339
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1888390558
Short name T217
Test name
Test status
Simulation time 209058667 ps
CPU time 5.45 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 207636 kb
Host smart-b50cd575-9648-43c3-ba0e-57c89bf7bd7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888390558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1888390558
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1155728069
Short name T283
Test name
Test status
Simulation time 464332188 ps
CPU time 3.44 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 218060 kb
Host smart-a6e2abe5-772e-46a2-aa6f-0f9cfe7f08b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155728069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1155728069
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.899670706
Short name T200
Test name
Test status
Simulation time 209838071 ps
CPU time 2.63 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 206596 kb
Host smart-52c5b4bf-8fa7-47ac-a8e7-9db44ebde7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899670706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.899670706
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2856193775
Short name T713
Test name
Test status
Simulation time 2875930620 ps
CPU time 15.74 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:36 PM PDT 24
Peak memory 208712 kb
Host smart-40c21111-9c27-4980-8ed8-1d76cbb52b62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856193775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2856193775
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2165222338
Short name T326
Test name
Test status
Simulation time 60509021 ps
CPU time 3.85 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:26 PM PDT 24
Peak memory 207780 kb
Host smart-3d47691f-03c8-4e3f-af4d-b1eb91020ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165222338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2165222338
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1572178515
Short name T431
Test name
Test status
Simulation time 94329449 ps
CPU time 2.23 seconds
Started Jul 23 05:48:16 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 209984 kb
Host smart-1372cd8c-5743-4eb4-8332-1b780a3db3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572178515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1572178515
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.961699546
Short name T770
Test name
Test status
Simulation time 16095145 ps
CPU time 0.8 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 205816 kb
Host smart-0d03900c-987b-4747-8c29-8a10e82d3026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961699546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.961699546
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2252668095
Short name T441
Test name
Test status
Simulation time 2178789610 ps
CPU time 51.51 seconds
Started Jul 23 05:48:20 PM PDT 24
Finished Jul 23 05:49:15 PM PDT 24
Peak memory 214228 kb
Host smart-7b75bd9e-3dae-4ee8-bc33-9ed3502637de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252668095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2252668095
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.794344365
Short name T862
Test name
Test status
Simulation time 83432934 ps
CPU time 3.5 seconds
Started Jul 23 05:48:22 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 210324 kb
Host smart-10b7076a-6947-46fd-b87e-af06500cc59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794344365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.794344365
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1501808300
Short name T112
Test name
Test status
Simulation time 372665564 ps
CPU time 6.51 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 220572 kb
Host smart-d98d431e-4271-47d2-82bf-4c6f1c0a0d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501808300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1501808300
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1807865037
Short name T104
Test name
Test status
Simulation time 38937095 ps
CPU time 2.59 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 213976 kb
Host smart-08f86513-e2eb-4bca-b3e8-b977c47d0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807865037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1807865037
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2706977120
Short name T612
Test name
Test status
Simulation time 53751882 ps
CPU time 2.1 seconds
Started Jul 23 05:48:22 PM PDT 24
Finished Jul 23 05:48:27 PM PDT 24
Peak memory 214076 kb
Host smart-75c2c6ff-9bf2-44bf-961c-cdb38afce0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706977120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2706977120
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1240985935
Short name T260
Test name
Test status
Simulation time 5166205522 ps
CPU time 12.24 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:32 PM PDT 24
Peak memory 209244 kb
Host smart-30ec6f38-7d94-4563-aee3-98cb67e17834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240985935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1240985935
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.78108620
Short name T419
Test name
Test status
Simulation time 55421655 ps
CPU time 3.09 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 206632 kb
Host smart-f239f2d7-5185-43fc-b99a-5316902cba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78108620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.78108620
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1928991156
Short name T307
Test name
Test status
Simulation time 315122394 ps
CPU time 3.63 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 208224 kb
Host smart-71370efb-72bc-4256-856b-27ca21824b3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928991156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1928991156
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1191084931
Short name T528
Test name
Test status
Simulation time 202975212 ps
CPU time 3.27 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 206468 kb
Host smart-de9be6cd-f4e5-4541-bfec-b6388f9bf6a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191084931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1191084931
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3237003859
Short name T640
Test name
Test status
Simulation time 79076918 ps
CPU time 3.56 seconds
Started Jul 23 05:48:19 PM PDT 24
Finished Jul 23 05:48:26 PM PDT 24
Peak memory 207736 kb
Host smart-609ad72f-fed3-4f79-bb79-b3ee6cc85f27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237003859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3237003859
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1303867101
Short name T301
Test name
Test status
Simulation time 246798077 ps
CPU time 3.58 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 208408 kb
Host smart-148e9a2a-0834-4a72-b6fb-70669212e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303867101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1303867101
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1638913794
Short name T912
Test name
Test status
Simulation time 408365738 ps
CPU time 2.23 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 206772 kb
Host smart-29e708f9-79af-4299-95bf-fb35b9902fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638913794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1638913794
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3536868772
Short name T824
Test name
Test status
Simulation time 1492232209 ps
CPU time 26.22 seconds
Started Jul 23 05:48:27 PM PDT 24
Finished Jul 23 05:48:57 PM PDT 24
Peak memory 214920 kb
Host smart-c1f83b97-82e1-4d07-8916-505a778a65ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536868772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3536868772
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.242489691
Short name T907
Test name
Test status
Simulation time 130905799 ps
CPU time 4.62 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 207412 kb
Host smart-ae74c0f4-3eb1-42aa-963b-48a02f379a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242489691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.242489691
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1690180814
Short name T697
Test name
Test status
Simulation time 65496195 ps
CPU time 1.58 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 209616 kb
Host smart-f8c95a07-37bd-40b2-af0e-56d75d027f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690180814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1690180814
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1154106575
Short name T449
Test name
Test status
Simulation time 31048518 ps
CPU time 0.99 seconds
Started Jul 23 05:48:22 PM PDT 24
Finished Jul 23 05:48:26 PM PDT 24
Peak memory 206072 kb
Host smart-77dd1f0e-00a6-48ed-9af7-927d4b1a5fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154106575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1154106575
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.716419070
Short name T265
Test name
Test status
Simulation time 55156865 ps
CPU time 3.74 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 215008 kb
Host smart-f74f97f9-0f70-40e9-ba11-50b2e1fb7493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716419070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.716419070
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3257953952
Short name T531
Test name
Test status
Simulation time 608276286 ps
CPU time 2.44 seconds
Started Jul 23 05:48:14 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 218028 kb
Host smart-f3a1e3f6-c87f-42e1-8144-ea7191296107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257953952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3257953952
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1687835978
Short name T337
Test name
Test status
Simulation time 494151776 ps
CPU time 5.31 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:28 PM PDT 24
Peak memory 214380 kb
Host smart-3a8885ba-d3df-4423-929b-4dcf85726a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687835978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1687835978
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.612963210
Short name T399
Test name
Test status
Simulation time 81428573 ps
CPU time 1.5 seconds
Started Jul 23 05:48:26 PM PDT 24
Finished Jul 23 05:48:31 PM PDT 24
Peak memory 213996 kb
Host smart-7613f853-b898-4cc2-8e71-9a478d2dd0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612963210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.612963210
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.723757896
Short name T479
Test name
Test status
Simulation time 320789790 ps
CPU time 2.49 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 214652 kb
Host smart-ef40719f-19f5-4579-85e1-4eb9bad53adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723757896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.723757896
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.4110009691
Short name T757
Test name
Test status
Simulation time 456178545 ps
CPU time 15 seconds
Started Jul 23 05:48:19 PM PDT 24
Finished Jul 23 05:48:38 PM PDT 24
Peak memory 218116 kb
Host smart-d5a6c5cb-dff1-40e8-8028-1e2c70253cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110009691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4110009691
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3707841402
Short name T484
Test name
Test status
Simulation time 2124576653 ps
CPU time 12.65 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:48:30 PM PDT 24
Peak memory 207832 kb
Host smart-31aa4204-3bbb-4c3a-9a93-d17ecd27e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707841402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3707841402
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.816447157
Short name T487
Test name
Test status
Simulation time 229862219 ps
CPU time 5.36 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 206744 kb
Host smart-d5ece5d2-fca2-4784-83dc-0412dc315d14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816447157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.816447157
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1834806931
Short name T574
Test name
Test status
Simulation time 59689949 ps
CPU time 3.18 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 206816 kb
Host smart-c8545dd0-06cb-41fc-b313-c8a0fd2546a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834806931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1834806931
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3695461436
Short name T610
Test name
Test status
Simulation time 63334528 ps
CPU time 2.92 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 206708 kb
Host smart-9b177545-1068-44fa-862d-96b4eb113e76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695461436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3695461436
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.860814829
Short name T428
Test name
Test status
Simulation time 166658165 ps
CPU time 2.2 seconds
Started Jul 23 05:48:21 PM PDT 24
Finished Jul 23 05:48:27 PM PDT 24
Peak memory 208596 kb
Host smart-daea5691-fe96-4128-abed-b6a161c23c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860814829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.860814829
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2805023931
Short name T748
Test name
Test status
Simulation time 839558942 ps
CPU time 13.73 seconds
Started Jul 23 05:48:22 PM PDT 24
Finished Jul 23 05:48:39 PM PDT 24
Peak memory 208388 kb
Host smart-8b3768a5-ef09-4062-8983-8653df04c630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805023931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2805023931
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3318605668
Short name T807
Test name
Test status
Simulation time 45248460235 ps
CPU time 60.13 seconds
Started Jul 23 05:48:25 PM PDT 24
Finished Jul 23 05:49:28 PM PDT 24
Peak memory 216000 kb
Host smart-c895e098-e4fe-46be-b370-8d393e283a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318605668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3318605668
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2997676370
Short name T135
Test name
Test status
Simulation time 1000504731 ps
CPU time 11.04 seconds
Started Jul 23 05:48:32 PM PDT 24
Finished Jul 23 05:48:47 PM PDT 24
Peak memory 222368 kb
Host smart-2b310fa7-377a-468d-8b54-5e44c4376d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997676370 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2997676370
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1231562635
Short name T511
Test name
Test status
Simulation time 131626712 ps
CPU time 4.95 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 208916 kb
Host smart-21203d9e-912c-43e1-b1ed-5abd91576235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231562635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1231562635
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2493731399
Short name T607
Test name
Test status
Simulation time 101532022 ps
CPU time 2.48 seconds
Started Jul 23 05:48:19 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 210232 kb
Host smart-804e70d7-a9b1-4f6e-b041-0270f5e8a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493731399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2493731399
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3347305507
Short name T508
Test name
Test status
Simulation time 13618414 ps
CPU time 0.82 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 205828 kb
Host smart-7768e205-a61b-407a-bc9c-12b64d7559d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347305507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3347305507
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4069804844
Short name T2
Test name
Test status
Simulation time 364165948 ps
CPU time 3.72 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 222108 kb
Host smart-f154089a-6ada-4bee-a25b-5a4b69218399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069804844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4069804844
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3601674916
Short name T876
Test name
Test status
Simulation time 179757112 ps
CPU time 1.95 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:41 PM PDT 24
Peak memory 209372 kb
Host smart-0930e4a0-9e5e-4ea1-9fb9-61f540e76e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601674916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3601674916
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3695552351
Short name T756
Test name
Test status
Simulation time 104464403 ps
CPU time 2.9 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 207156 kb
Host smart-34848156-5227-404a-863b-d2deffa87aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695552351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3695552351
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.68696105
Short name T271
Test name
Test status
Simulation time 210403619 ps
CPU time 2.96 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 215460 kb
Host smart-beba8bb2-a737-46a3-8362-bf5404f0bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68696105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.68696105
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3390640076
Short name T804
Test name
Test status
Simulation time 107983876 ps
CPU time 2.64 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:42 PM PDT 24
Peak memory 220852 kb
Host smart-56d7794f-a10c-4b7c-8949-f5aed29c2454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390640076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3390640076
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3795168022
Short name T302
Test name
Test status
Simulation time 58227152 ps
CPU time 3.61 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 208136 kb
Host smart-ba3d99c2-c48b-4b62-8412-33127f21fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795168022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3795168022
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2650840038
Short name T592
Test name
Test status
Simulation time 509717597 ps
CPU time 6.58 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 208512 kb
Host smart-7cbe4c31-b7e9-47d4-add1-8c70631e51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650840038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2650840038
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.10994353
Short name T123
Test name
Test status
Simulation time 1813903823 ps
CPU time 19.15 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:45:06 PM PDT 24
Peak memory 207660 kb
Host smart-e46ec9e2-3ef9-4d5d-819a-92372d9c4bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10994353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.10994353
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1171707812
Short name T701
Test name
Test status
Simulation time 281543518 ps
CPU time 2.7 seconds
Started Jul 23 05:44:35 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 206712 kb
Host smart-823944d0-dd35-473d-b8bb-c2201b7f99bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171707812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1171707812
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1017436370
Short name T790
Test name
Test status
Simulation time 25404111 ps
CPU time 1.99 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 206784 kb
Host smart-4a57fa1a-1fb4-438e-a883-07e3a0778fe7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017436370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1017436370
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1632864
Short name T512
Test name
Test status
Simulation time 59833378 ps
CPU time 2.28 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 206720 kb
Host smart-4cd9d4aa-1e32-4028-9f15-4ba381c71584
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1632864
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2399041326
Short name T490
Test name
Test status
Simulation time 246930634 ps
CPU time 2.76 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 218156 kb
Host smart-0eb3a2e3-705f-4390-b177-e09769620895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399041326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2399041326
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3450704624
Short name T202
Test name
Test status
Simulation time 149087775 ps
CPU time 2.52 seconds
Started Jul 23 05:44:40 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 208548 kb
Host smart-75527776-3946-4039-8490-21dd191ba8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450704624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3450704624
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3606952966
Short name T249
Test name
Test status
Simulation time 4613773752 ps
CPU time 9.89 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 221628 kb
Host smart-38245e74-5bab-4786-9c04-0eb54d5912f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606952966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3606952966
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3246085225
Short name T244
Test name
Test status
Simulation time 145162043 ps
CPU time 2.85 seconds
Started Jul 23 05:44:36 PM PDT 24
Finished Jul 23 05:44:42 PM PDT 24
Peak memory 206748 kb
Host smart-62fa6336-c95f-427e-8538-6f62d74df41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246085225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3246085225
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3249305774
Short name T69
Test name
Test status
Simulation time 159779318 ps
CPU time 3.05 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 209488 kb
Host smart-a8813c9a-2a16-41cb-8701-f3449ca9a232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249305774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3249305774
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.811923212
Short name T456
Test name
Test status
Simulation time 10599815 ps
CPU time 0.84 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 205836 kb
Host smart-fd2e33d4-0eb7-4630-8775-5f99b97193f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811923212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.811923212
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1131359861
Short name T371
Test name
Test status
Simulation time 12410700438 ps
CPU time 107.92 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 214164 kb
Host smart-3e63fc21-b128-47b1-ba1c-4c8f8e325df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131359861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1131359861
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2317210337
Short name T286
Test name
Test status
Simulation time 113797362 ps
CPU time 3.78 seconds
Started Jul 23 05:44:35 PM PDT 24
Finished Jul 23 05:44:41 PM PDT 24
Peak memory 214072 kb
Host smart-e0755959-7dc0-440b-80b4-24665b9158a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317210337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2317210337
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3847288105
Short name T844
Test name
Test status
Simulation time 684422322 ps
CPU time 5.65 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:46 PM PDT 24
Peak memory 215464 kb
Host smart-50e8ce6e-868f-405e-9791-7767b2ab7592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847288105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3847288105
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3369471530
Short name T839
Test name
Test status
Simulation time 264349768 ps
CPU time 1.87 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 213944 kb
Host smart-33c1392a-fc71-4588-8034-d68c0580e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369471530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3369471530
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2660024872
Short name T235
Test name
Test status
Simulation time 248278435 ps
CPU time 6.02 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 222152 kb
Host smart-5030a057-b9a5-431b-80b7-375c5543fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660024872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2660024872
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.781716561
Short name T801
Test name
Test status
Simulation time 555851465 ps
CPU time 4.23 seconds
Started Jul 23 05:44:40 PM PDT 24
Finished Jul 23 05:44:47 PM PDT 24
Peak memory 207132 kb
Host smart-b9ebf99f-d971-4dc1-8971-73faca43a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781716561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.781716561
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1379349752
Short name T663
Test name
Test status
Simulation time 6783703296 ps
CPU time 49.56 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 208404 kb
Host smart-b115d435-119a-48d4-9b9d-7870b8df269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379349752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1379349752
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.605603050
Short name T261
Test name
Test status
Simulation time 99322590 ps
CPU time 4.23 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:46 PM PDT 24
Peak memory 209040 kb
Host smart-64c3f60b-6db5-405f-b84e-ef963bb2dc9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605603050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.605603050
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.770348862
Short name T93
Test name
Test status
Simulation time 7001399829 ps
CPU time 43 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 206900 kb
Host smart-888628d7-eb95-4b29-81ce-6db1c7ee81b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770348862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.770348862
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3034320613
Short name T182
Test name
Test status
Simulation time 117382024 ps
CPU time 2.99 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 208712 kb
Host smart-bbf2eb30-a871-40ff-a8d7-8689b8b6c135
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034320613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3034320613
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.507291488
Short name T274
Test name
Test status
Simulation time 52619354 ps
CPU time 2.88 seconds
Started Jul 23 05:44:39 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 209512 kb
Host smart-44939b2f-6527-4acb-a099-aae79d0bc49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507291488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.507291488
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2891121293
Short name T880
Test name
Test status
Simulation time 133394696 ps
CPU time 3.41 seconds
Started Jul 23 05:44:37 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 206348 kb
Host smart-7e16607f-3061-480e-b457-e8f9fbd23870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891121293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2891121293
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.4139124335
Short name T175
Test name
Test status
Simulation time 287678000 ps
CPU time 11.41 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 216124 kb
Host smart-b0eecb00-4429-4350-9553-f391fff5939b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139124335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.4139124335
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1169675859
Short name T901
Test name
Test status
Simulation time 36810663 ps
CPU time 2.63 seconds
Started Jul 23 05:44:38 PM PDT 24
Finished Jul 23 05:44:44 PM PDT 24
Peak memory 206820 kb
Host smart-27663350-9cb9-451c-943f-3643d673d682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169675859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1169675859
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3353273757
Short name T617
Test name
Test status
Simulation time 62441117 ps
CPU time 2.89 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 209828 kb
Host smart-7f605bff-8473-4d35-a891-03d59df71df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353273757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3353273757
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3043320813
Short name T551
Test name
Test status
Simulation time 36083997 ps
CPU time 0.73 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 205812 kb
Host smart-933f090e-63fc-4df3-9989-f67526eba012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043320813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3043320813
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3177191450
Short name T282
Test name
Test status
Simulation time 40378186 ps
CPU time 3.24 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 214020 kb
Host smart-ad302b51-75ab-42db-b462-5199241fb58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177191450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3177191450
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1612093852
Short name T292
Test name
Test status
Simulation time 64982152 ps
CPU time 2.24 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:49 PM PDT 24
Peak memory 205836 kb
Host smart-f2174439-aa23-479f-aa57-7c2401f5e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612093852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1612093852
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2995103580
Short name T750
Test name
Test status
Simulation time 492640451 ps
CPU time 6.72 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:55 PM PDT 24
Peak memory 217996 kb
Host smart-299e0228-b6cb-4492-b44f-253c79cc766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995103580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2995103580
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.267740858
Short name T857
Test name
Test status
Simulation time 129879671 ps
CPU time 2.41 seconds
Started Jul 23 05:44:47 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 214040 kb
Host smart-8baa13cb-ce46-4c51-b92a-af6fed8d1a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267740858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.267740858
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2570492818
Short name T632
Test name
Test status
Simulation time 70598270 ps
CPU time 3.46 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 214000 kb
Host smart-c8154613-9e53-4d32-8317-b3760487f27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570492818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2570492818
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2458584098
Short name T227
Test name
Test status
Simulation time 51370672 ps
CPU time 2.94 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 209692 kb
Host smart-736464b1-3ef0-4af5-bcd7-e317cc5b7925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458584098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2458584098
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3525918204
Short name T620
Test name
Test status
Simulation time 90550677 ps
CPU time 4.72 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:53 PM PDT 24
Peak memory 218272 kb
Host smart-2d7c90e0-3fb1-43f3-bb52-b3365d57d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525918204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3525918204
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3651942736
Short name T625
Test name
Test status
Simulation time 95740273 ps
CPU time 2.43 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 206492 kb
Host smart-1801747c-fc48-4e44-8eae-0b677c9cb44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651942736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3651942736
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.487641816
Short name T378
Test name
Test status
Simulation time 37543183 ps
CPU time 2.5 seconds
Started Jul 23 05:44:43 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 206724 kb
Host smart-bec6191c-3218-4905-8ceb-3738ec38cba2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487641816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.487641816
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3257440623
Short name T493
Test name
Test status
Simulation time 112604033 ps
CPU time 3.01 seconds
Started Jul 23 05:44:43 PM PDT 24
Finished Jul 23 05:44:49 PM PDT 24
Peak memory 206708 kb
Host smart-067aaf17-e143-4343-ac81-b921568ad1ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257440623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3257440623
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2102588230
Short name T215
Test name
Test status
Simulation time 9485128094 ps
CPU time 35.25 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:45:22 PM PDT 24
Peak memory 208416 kb
Host smart-f0989d96-3c9f-40aa-ad59-f61dadcfaa9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102588230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2102588230
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.627359515
Short name T392
Test name
Test status
Simulation time 341703520 ps
CPU time 3.32 seconds
Started Jul 23 05:44:46 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 207448 kb
Host smart-a0134a1f-4743-4c47-8f11-b26e72a45b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627359515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.627359515
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1435211872
Short name T584
Test name
Test status
Simulation time 177784782 ps
CPU time 2.61 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:49 PM PDT 24
Peak memory 206708 kb
Host smart-420d0bc6-8f53-4d48-8c8b-0fbb5404d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435211872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1435211872
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.89666879
Short name T80
Test name
Test status
Simulation time 1895086460 ps
CPU time 37.17 seconds
Started Jul 23 05:44:47 PM PDT 24
Finished Jul 23 05:45:26 PM PDT 24
Peak memory 216384 kb
Host smart-5b05f1fa-5bb1-43b5-9c21-bdbf5f49f766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89666879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.89666879
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2219186662
Short name T816
Test name
Test status
Simulation time 388865187 ps
CPU time 4.98 seconds
Started Jul 23 05:44:46 PM PDT 24
Finished Jul 23 05:44:54 PM PDT 24
Peak memory 209052 kb
Host smart-396043bc-4b16-49ae-a0f4-f97e528b9e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219186662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2219186662
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3507043757
Short name T850
Test name
Test status
Simulation time 3450675437 ps
CPU time 6.46 seconds
Started Jul 23 05:44:47 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 211296 kb
Host smart-2de3cd45-07a4-4fa2-bbc4-7e8f5068eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507043757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3507043757
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1962538606
Short name T710
Test name
Test status
Simulation time 18455091 ps
CPU time 0.73 seconds
Started Jul 23 05:44:47 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 205852 kb
Host smart-be17eb4d-f74b-4fd3-808c-1cf442a3d201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962538606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1962538606
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3535907451
Short name T665
Test name
Test status
Simulation time 991149869 ps
CPU time 19.17 seconds
Started Jul 23 05:44:49 PM PDT 24
Finished Jul 23 05:45:10 PM PDT 24
Peak memory 207540 kb
Host smart-ad0b8036-d1d4-4801-aa9d-9eaf7db45dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535907451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3535907451
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2928025774
Short name T313
Test name
Test status
Simulation time 88970382 ps
CPU time 3.1 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 214080 kb
Host smart-7c3f1e39-ec53-444c-9e7c-932923c11561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928025774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2928025774
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3922132773
Short name T116
Test name
Test status
Simulation time 151188420 ps
CPU time 4.5 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 221328 kb
Host smart-e210c1b3-3f1b-42eb-8dce-47b8d01483b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922132773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3922132773
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2657921046
Short name T354
Test name
Test status
Simulation time 194984383 ps
CPU time 3.69 seconds
Started Jul 23 05:44:43 PM PDT 24
Finished Jul 23 05:44:49 PM PDT 24
Peak memory 222104 kb
Host smart-1c094ec9-43e0-4358-a192-84a4a920f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657921046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2657921046
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2393006578
Short name T245
Test name
Test status
Simulation time 301449230 ps
CPU time 10.3 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 209764 kb
Host smart-16f98b3c-170a-42d0-bead-d56309754260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393006578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2393006578
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2925352019
Short name T746
Test name
Test status
Simulation time 38991230 ps
CPU time 2.37 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:50 PM PDT 24
Peak memory 206508 kb
Host smart-579ca036-1a78-424f-8b59-3b6501908827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925352019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2925352019
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1550439631
Short name T702
Test name
Test status
Simulation time 387854692 ps
CPU time 3.16 seconds
Started Jul 23 05:44:47 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 206672 kb
Host smart-c7103135-4e5b-4adb-a7f4-fbf493ed93b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550439631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1550439631
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2313933995
Short name T733
Test name
Test status
Simulation time 62071211 ps
CPU time 3.08 seconds
Started Jul 23 05:44:46 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 208364 kb
Host smart-46c34d65-db57-41f5-9001-01137d54d328
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313933995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2313933995
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3755984019
Short name T507
Test name
Test status
Simulation time 220214009 ps
CPU time 2.85 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 206688 kb
Host smart-8fcbee4d-48ce-4853-8c28-b22d8978a26b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755984019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3755984019
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1128378900
Short name T340
Test name
Test status
Simulation time 160459924 ps
CPU time 4.62 seconds
Started Jul 23 05:44:44 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 209836 kb
Host smart-b25e9927-3835-4da0-8908-b5210077f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128378900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1128378900
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.466149949
Short name T800
Test name
Test status
Simulation time 241840733 ps
CPU time 2.8 seconds
Started Jul 23 05:44:54 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 206584 kb
Host smart-e8112211-47d8-437b-8039-e8da63aa5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466149949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.466149949
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.948884803
Short name T788
Test name
Test status
Simulation time 357998492 ps
CPU time 4.36 seconds
Started Jul 23 05:44:45 PM PDT 24
Finished Jul 23 05:44:52 PM PDT 24
Peak memory 208596 kb
Host smart-e9b7ff18-f974-4565-98d6-fec337dc4731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948884803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.948884803
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.430715687
Short name T177
Test name
Test status
Simulation time 1796488263 ps
CPU time 12.71 seconds
Started Jul 23 05:44:46 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 218824 kb
Host smart-8300c3b9-11fd-40bd-8e6b-deb83af62121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430715687 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.430715687
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.143627903
Short name T388
Test name
Test status
Simulation time 128357183 ps
CPU time 5.8 seconds
Started Jul 23 05:44:43 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 209932 kb
Host smart-4167c2c8-db95-4fd9-89ed-daf607e1a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143627903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.143627903
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3572799815
Short name T918
Test name
Test status
Simulation time 118873772 ps
CPU time 2.19 seconds
Started Jul 23 05:44:46 PM PDT 24
Finished Jul 23 05:44:51 PM PDT 24
Peak memory 209940 kb
Host smart-3c075219-0ca0-4fb8-a788-dec969aef590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572799815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3572799815
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3799977536
Short name T465
Test name
Test status
Simulation time 78638241 ps
CPU time 0.94 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 205860 kb
Host smart-5a084a80-43fe-45ed-84a8-14524ecebe8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799977536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3799977536
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.510585302
Short name T796
Test name
Test status
Simulation time 561771699 ps
CPU time 4.81 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 208332 kb
Host smart-94f3ee77-12c7-461c-be6f-7503dc1497a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510585302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.510585302
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1823289168
Short name T669
Test name
Test status
Simulation time 1433955119 ps
CPU time 2.91 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 208932 kb
Host smart-be1edf54-4b75-4ae9-afbb-6fdae2f74a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823289168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1823289168
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2992473600
Short name T858
Test name
Test status
Simulation time 254616389 ps
CPU time 8.41 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:45:02 PM PDT 24
Peak memory 209364 kb
Host smart-6fdeea15-1b63-4cbe-b0f0-3983ffc756d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992473600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2992473600
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2947110644
Short name T905
Test name
Test status
Simulation time 234918132 ps
CPU time 2.47 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 220548 kb
Host smart-13b6f05f-29f1-42d3-98b8-a8d367fe3e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947110644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2947110644
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1631440369
Short name T635
Test name
Test status
Simulation time 94687715 ps
CPU time 3.37 seconds
Started Jul 23 05:44:49 PM PDT 24
Finished Jul 23 05:44:54 PM PDT 24
Peak memory 218256 kb
Host smart-3145f1c6-121e-497e-8c18-c5cc9bf3782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631440369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1631440369
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.240697421
Short name T246
Test name
Test status
Simulation time 166391412 ps
CPU time 4.12 seconds
Started Jul 23 05:44:52 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 208912 kb
Host smart-f2efa3a5-9c03-4f7a-957b-7f1ccc53f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240697421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.240697421
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2726777538
Short name T882
Test name
Test status
Simulation time 144260026 ps
CPU time 3.86 seconds
Started Jul 23 05:44:53 PM PDT 24
Finished Jul 23 05:44:59 PM PDT 24
Peak memory 207420 kb
Host smart-32b9627a-baf2-43c4-b45a-d1fc7d0526ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726777538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2726777538
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2066868605
Short name T727
Test name
Test status
Simulation time 64217816 ps
CPU time 3.39 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:01 PM PDT 24
Peak memory 208704 kb
Host smart-baf5e789-f67b-4ff3-9988-f14a8291295c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066868605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2066868605
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1888602652
Short name T826
Test name
Test status
Simulation time 42144027 ps
CPU time 1.96 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 206744 kb
Host smart-c195f3ad-5b75-4e74-8ce5-b5f25ab95bbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888602652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1888602652
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1514797970
Short name T474
Test name
Test status
Simulation time 1358981773 ps
CPU time 6.5 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 207680 kb
Host smart-1b7efbc3-1a99-4089-bf16-7e01335e5e18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514797970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1514797970
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3921649937
Short name T604
Test name
Test status
Simulation time 493740223 ps
CPU time 2.49 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:55 PM PDT 24
Peak memory 218072 kb
Host smart-331deeb9-01b9-4aa8-91e7-0fb1ad3230c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921649937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3921649937
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3671229510
Short name T455
Test name
Test status
Simulation time 1299024817 ps
CPU time 5.97 seconds
Started Jul 23 05:44:50 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 206532 kb
Host smart-151b5b6a-3a4f-4728-ae60-12715323b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671229510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3671229510
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.447949353
Short name T888
Test name
Test status
Simulation time 11017425945 ps
CPU time 132.92 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 222328 kb
Host smart-d5f0c982-d494-497a-8a44-ff4defe69302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447949353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.447949353
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3442006826
Short name T565
Test name
Test status
Simulation time 957578006 ps
CPU time 4.74 seconds
Started Jul 23 05:44:57 PM PDT 24
Finished Jul 23 05:45:03 PM PDT 24
Peak memory 214056 kb
Host smart-cd90442d-daf2-4077-b1bd-520e866fabe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442006826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3442006826
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3795657474
Short name T630
Test name
Test status
Simulation time 421986661 ps
CPU time 4.11 seconds
Started Jul 23 05:44:51 PM PDT 24
Finished Jul 23 05:44:58 PM PDT 24
Peak memory 210668 kb
Host smart-cbef0f70-61ee-4082-a78a-2a5755f4338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795657474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3795657474
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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