| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 87.50 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 1 | 7 | 87.50 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| auto[OtpRootKeyValidLow] | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[OtpRootKeyInvalid] | 1 | 1 | T375 | 1 | - | - | - | - | ||||
| auto[LcStateInvalid] | 156 | 1 | T22 | 24 | T98 | 24 | T365 | 84 | ||||
| auto[OtpDevIdInvalid] | 228 | 1 | T96 | 24 | T99 | 36 | T98 | 12 | ||||
| auto[RomDigestInvalid] | 120 | 1 | T99 | 12 | T100 | 36 | T258 | 12 | ||||
| auto[RomDigestValidLow] | 84 | 1 | T96 | 12 | T99 | 12 | T98 | 12 | ||||
| auto[FlashCreatorSeedInvalid] | 24 | 1 | T23 | 12 | T376 | 12 | - | - | ||||
| auto[FlashOwnerSeedInvalid] | 48 | 1 | T19 | 12 | T96 | 36 | - | - |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |