Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	36	1			T16	1		T48	1		T41	1
auto[OpGenId]	13	1			T17	1		T67	1		T6	1
auto[OpGenSwOut]	17	1			T49	1		T225	1		T165	1
auto[OpGenHwOut]	25	1			T5	1		T24	1		T105	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1607	1			T13	2		T15	3		T16	6
auto[StInit]	91	1			T5	1		T16	1		T32	1
auto[StCreatorRootKey]	59	1			T15	1		T49	1		T18	1
auto[StOwnerIntKey]	42	1			T13	3		T33	1		T57	1
auto[StOwnerKey]	25	1			T13	2		T15	1		T58	1
auto[StDisabled]	438	1			T13	3		T16	8		T88	4
auto[StInvalid]	49	1			T34	1		T52	1		T46	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3299

1

T1

1

T2

1

T3

1

auto[1]

91

1

T5

1

T16

1

T17

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1603	1			T13	2		T15	3		T16	6
auto[StReset]	auto[1]	4	1			T61	1		T47	1		T196	1
auto[StInit]	auto[0]	47	1			T32	1		T35	1		T118	1
auto[StInit]	auto[1]	44	1			T5	1		T16	1		T17	1
auto[StCreatorRootKey]	auto[0]	39	1			T15	1		T49	1		T18	1
auto[StCreatorRootKey]	auto[1]	20	1			T105	1		T226	1		T43	1
auto[StOwnerIntKey]	auto[0]	32	1			T13	3		T33	1		T57	1
auto[StOwnerIntKey]	auto[1]	10	1			T116	1		T6	1		T7	2
auto[StOwnerKey]	auto[0]	21	1			T13	2		T15	1		T58	1
auto[StOwnerKey]	auto[1]	4	1			T227	1		T228	1		T229	1
auto[StDisabled]	auto[0]	429	1			T13	3		T16	8		T88	4
auto[StDisabled]	auto[1]	9	1			T67	1		T68	1		T230	1
auto[StInvalid]	auto[0]	49	1			T34	1		T52	1		T46	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpAdvance] , auto[OpGenId]]	--	--	2
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenSwOut]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T61	1		T47	1		T196	1
auto[StInit]	auto[OpAdvance]	15	1			T16	1		T48	1		T41	1
auto[StInit]	auto[OpGenId]	7	1			T17	1		T167	1		T79	1
auto[StInit]	auto[OpGenSwOut]	11	1			T49	1		T225	1		T165	1
auto[StInit]	auto[OpGenHwOut]	11	1			T5	1		T24	1		T31	1
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T231	1		T232	1		T233	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T234	1		T210	1		T235	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T226	1		T236	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T105	1		T43	1		T38	1
auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T116	1		T164	1		-	-
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T6	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T237	1		T238	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T7	2		T79	1		T239	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T228	1		T229	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T227	1		T240	1		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T68	1		T230	1		T79	1
auto[StDisabled]	auto[OpGenId]	1	1			T67	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T241	1		-	-		-	-