Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.79	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	77	253	76.67

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	58	222	79.29	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4789

1

T1

8

T2

6

T3

2

auto[1]

522

1

T4

1

T16

7

T86

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4789

1

T1

8

T2

6

T3

2

auto[1]

522

1

T4

1

T16

7

T86

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4711

1

T1

3

T2

4

T3

2

auto[1]

600

1

T1

5

T2

2

T4

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4711

1

T1

3

T2

4

T3

2

auto[1]

600

1

T1

5

T2

2

T4

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	406	1			T13	2		T16	1		T133	1
auto[OpGenId]	1123	1			T2	2		T12	2		T13	3
auto[OpGenSwOut]	1126	1			T2	3		T3	2		T4	1
auto[OpGenHwOut]	2591	1			T1	8		T2	1		T4	2
auto[OpDisable]	65	1			T13	1		T59	1		T49	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	406	1			T13	2		T16	1		T133	1
auto[OpGenId]	1123	1			T2	2		T12	2		T13	3
auto[OpGenSwOut]	1126	1			T2	3		T3	2		T4	1
auto[OpGenHwOut]	2591	1			T1	8		T2	1		T4	2
auto[OpDisable]	65	1			T13	1		T59	1		T49	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T1

8

T2

6

T3

2

auto[1]

579

1

T14

2

T16

5

T88

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T1

8

T2

6

T3

2

auto[1]

579

1

T14

2

T16

5

T88

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4959

1

T1

8

T2

6

T3

2

auto[1]

352

1

T137

4

T142

10

T144

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1843	1			T1	2		T2	1		T3	1
auto[1]	665	1			T1	4		T2	2		T12	2
auto[2]	658	1			T12	1		T13	2		T14	1
auto[3]	691	1			T2	1		T14	1		T15	1
auto[4]	316	1			T2	2		T13	1		T14	1
auto[5]	404	1			T1	1		T13	1		T14	2
auto[6]	337	1			T1	1		T14	2		T16	1
auto[7]	397	1			T3	1		T12	1		T13	3

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1454	1			T1	2		T2	2		T3	1
clear_one[1]	665	1			T1	4		T2	2		T12	2
clear_one[2]	658	1			T12	1		T13	2		T14	1
clear_one[3]	691	1			T2	1		T14	1		T15	1
clear_none	1843	1			T1	2		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T3	1		T4	2		T12	4
auto[StInit]	669	1			T1	1		T2	1		T12	1
auto[StCreatorRootKey]	544	1			T1	1		T3	1		T12	1
auto[StOwnerIntKey]	497	1			T1	1		T2	1		T13	3
auto[StOwnerKey]	479	1			T1	1		T2	1		T13	2
auto[StDisabled]	1828	1			T1	4		T2	3		T4	1
auto[StInvalid]	282	1			T34	2		T44	6		T45	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T3	1		T4	2		T12	4
auto[StInit]	669	1			T1	1		T2	1		T12	1
auto[StCreatorRootKey]	544	1			T1	1		T3	1		T12	1
auto[StOwnerIntKey]	497	1			T1	1		T2	1		T13	3
auto[StOwnerKey]	479	1			T1	1		T2	1		T13	2
auto[StDisabled]	1828	1			T1	4		T2	3		T4	1
auto[StInvalid]	282	1			T34	2		T44	6		T45	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	58	222	79.29	58

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	6
[auto[0] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	6
[auto[0] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	24
[auto[0] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	6
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpGenId]	162	1			T12	1		T16	1		T48	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	138	1			T3	1		T15	1		T88	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	265	1			T4	2		T14	1		T15	2
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T133	1		T214	1		T216	1
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T13	1		T137	1		T141	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	86	1			T2	1		T16	1		T219	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	170	1			T1	1		T13	1		T16	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T34	1		T49	1		T137	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	44	1			T16	1		T106	2		T216	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T13	1		T16	1		T218	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	78	1			T12	1		T13	1		T16	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T13	1		T106	1		T80	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T217	1		T242	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T58	1		T146	1		T75	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	61	1			T16	1		T203	1		T243	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T131	1		T244	1		T245	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T49	2		T246	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	38	1			T13	1		T59	1		T138	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	54	1			T14	1		T212	1		T248	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	22	1			T212	1		T49	1		T242	1
auto[0]	auto[StDisabled]	auto[OpGenId]	61	1			T16	3		T106	1		T216	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	81	1			T4	1		T85	1		T212	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	179	1			T1	1		T86	1		T221	1
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T70	1		T53	1		T73	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T249	1		T250	2		T251	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T44	1		T252	1		T90	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T253	1		T254	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T45	1		T46	1		T256	1
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T12	1		T15	1		T50	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T12	1		T22	1		T107	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	46	1			T14	1		T88	1		T84	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T257	1		T99	1		T258	1
auto[1]	auto[StInit]	auto[OpGenId]	5	1			T144	1		T259	1		T260	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T144	1		T107	1		T261	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	20	1			T49	1		T242	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T263	1		T240	1		T264	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T147	1		T148	1		T207	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T144	1		T19	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T1	1		T87	1		T219	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T261	1		T207	1		T266	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T2	1		T107	1		T259	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T130	1		T43	1		T134	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T221	1		T248	1		T222	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T70	1		T147	1		T43	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T106	1		T49	1		T122	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T218	1		T144	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T221	1		T224	1		T220	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	19	1			T137	1		T141	1		T267	1
auto[1]	auto[StDisabled]	auto[OpGenId]	45	1			T2	1		T16	1		T88	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T88	1		T146	1		T70	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	170	1			T1	3		T16	3		T221	1
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T68	1		T53	1		T7	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T91	1		T268	1		T269	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T45	1		T90	1		T270	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T44	1		T271	1		T272	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T44	1		T270	1		T273	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T213	1		T274	1		T107	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T22	1		T96	1		T275	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	62	1			T12	1		T158	1		T143	1
auto[2]	auto[StInit]	auto[OpAdvance]	2	1			T231	1		T276	1		-	-
auto[2]	auto[StInit]	auto[OpGenId]	15	1			T88	1		T274	1		T7	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	8	1			T88	1		T23	1		T277	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	34	1			T248	1		T278	1		T223	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T13	1		T96	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T212	1		T259	1		T237	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T16	1		T60	1		T7	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T224	1		T223	1		T81	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T116	1		-	-		-	-
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T49	1		T280	1		T132	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T122	1		T70	1		T25	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T158	1		T204	1		T281	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T50	1		T282	1		T230	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T49	1		T283	3		T284	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T80	1		T58	1		T70	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T214	1		T106	1		T285	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T286	1		T247	1		T58	1
auto[2]	auto[StDisabled]	auto[OpGenId]	59	1			T13	1		T16	1		T49	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T220	1		T49	1		T159	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T14	1		T87	1		T287	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T55	1		T51	1		T63	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	8	1			T270	1		T253	1		T288	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T34	1		T252	2		T256	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T45	1		T289	1		T251	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T252	1		T249	1		T290	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T86	1		T259	1		T122	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T48	1		T88	1		T117	2
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T49	1		T158	1		T143	2
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T58	1		T147	1		T7	1
auto[3]	auto[StInit]	auto[OpGenId]	5	1			T58	1		T291	2		T209	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	19	1			T53	1		T279	1		T292	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	20	1			T14	1		T158	1		T293	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T70	1		T294	1		T295	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T88	1		T49	1		T58	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T15	1		T220	1		T296	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T221	1		T49	1		T158	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T122	1		T297	1		T207	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T49	1		T122	1		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T16	1		T50	2		T299	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T223	1		T143	1		T300	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T162	1		T301	1		T302	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T277	1		T208	1		T303	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T86	1		T88	1		T242	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T87	1		T278	1		T143	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T106	1		T304	1		T110	3
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T16	1		T139	1		T144	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T2	1		T49	1		T144	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	131	1			T16	2		T88	1		T224	2
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T59	1		T49	1		T122	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T46	1		T270	1		T305	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T90	1		T288	1		T306	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T46	1		T271	1		T111	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T44	1		T91	1		T307	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T274	1		T50	1		T267	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T60	1		T110	1		T308	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T204	1		T110	1		T262	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T110	1		T96	1		T309	1
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T132	1		T92	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T22	1		T110	1		T96	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T310	1		T64	1		T311	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T88	1		T231	1		T232	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T287	1		T110	1		T7	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T227	1		T312	1		T196	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T50	1		T313	1		T262	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T314	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T22	1		T208	1		T235	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T49	1		T315	1		T316	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T133	1		T88	1		T161	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T110	1		T317	1		T316	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T67	1		T310	1		T318	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T2	1		T304	1		T319	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T101	1		T320	1		T321	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	7	1			T322	1		T43	1		T314	1
auto[4]	auto[StDisabled]	auto[OpGenId]	16	1			T219	1		T71	1		T323	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T106	1		T122	1		T324	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T2	1		T14	1		T221	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T13	1		T325	1		T237	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T34	1		T111	1		T270	1
auto[4]	auto[StInvalid]	auto[OpGenId]	9	1			T253	1		T254	1		T326	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T327	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T328	2		T254	1		T305	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T58	1		T227	1		T329	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T283	1		T227	1		T208	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T248	1		T330	1		T262	1
auto[5]	auto[StInit]	auto[OpAdvance]	9	1			T142	3		T331	1		T332	1
auto[5]	auto[StInit]	auto[OpGenId]	9	1			T107	1		T42	1		T331	2
auto[5]	auto[StInit]	auto[OpGenSwOut]	9	1			T16	1		T331	2		T237	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T204	1		T333	1		T334	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T245	1		T335	1		T336	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T96	1		T337	1		T338	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T142	1		T52	1		T210	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T14	1		T222	1		T141	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T49	1		T332	1		T237	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T7	1		T77	1		T308	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T218	1		T63	1		T339	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T87	1		T88	1		T287	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T137	1		T70	1		T340	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T298	1		T146	1		T302	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T22	1		T50	1		T146	2
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T1	1		T82	1		T341	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T144	2		T50	1		T283	2
auto[5]	auto[StDisabled]	auto[OpGenId]	37	1			T49	1		T137	1		T141	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T13	1		T16	1		T49	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	63	1			T14	1		T222	1		T223	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T50	1		T196	1		T342	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T343	1		T268	1		T344	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T52	1		T289	1		T260	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T345	1		T273	1		T346	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T44	2		T90	1		T251	1
auto[6]	auto[StReset]	auto[OpGenId]	8	1			T72	1		T117	1		T310	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T97	1		T64	1		T254	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T278	1		T223	1		T50	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T347	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T98	1		T232	1		T348	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T49	1		T22	1		T349	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T321	1		T350	1		T65	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T351	1		T352	1		T347	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T113	1		T237	1		T353	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T107	1		T354	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T50	1		T84	1		T201	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T122	1		T207	1		T356	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T19	1		T58	1		T227	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T1	1		T14	1		T219	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T97	1		T89	1		T237	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T75	1		T134	1		T77	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T139	1		T203	1		T330	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T106	1		T82	1		T113	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T49	2		T242	1		T122	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T85	1		T218	1		T49	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T14	1		T16	1		T87	2
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T78	1		T357	1		T358	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	7	1			T252	1		T253	1		T359	1
auto[6]	auto[StInvalid]	auto[OpGenId]	11	1			T45	1		T52	1		T249	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T256	1		T360	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T91	1		T361	1		T362	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T363	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T288	1		T301	1		T364	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T49	1		T324	1		T7	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	28	1			T278	2		T223	1		T330	1
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T227	1		T92	2		T365	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T12	1		T122	1		T99	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T285	1		T143	1		T203	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T242	1		T149	1		T100	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T107	1		T63	1		T7	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T3	1		T50	1		T366	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T285	1		T97	1		T367	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T145	1		T132	1		T291	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T13	1		T274	1		T145	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T75	1		T301	1		T79	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T13	1		T224	1		T60	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T16	1		T210	1		T368	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T141	1		T257	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T13	1		T16	1		T370	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T201	1		T313	1		T333	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	16	1			T137	1		T145	1		T149	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T16	1		T86	1		T145	3
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T106	1		T219	1		T274	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	93	1			T87	1		T221	1		T224	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T49	1		T232	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T90	1		T307	1		T290	1
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T52	1		T361	1		T272	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T256	1		T372	1		T364	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T345	1		T288	1		T372	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1454

1

T1

2

T2

2

T3

1

clear_one[1]

auto[0]

auto[0]

auto[0]

383

1

T2

1

T12

2

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

116

1

T16

1

T88

1

T212

1

clear_one[1]

auto[0]

auto[1]

auto[0]

111

1

T1

4

T2

1

T16

2

clear_one[1]

auto[0]

auto[1]

auto[1]

55

1

T16

1

T49

2

T373

1

clear_one[2]

auto[0]

auto[0]

auto[0]

399

1

T12

1

T13

2

T16

1

clear_one[2]

auto[0]

auto[0]

auto[1]

124

1

T14

1

T212

1

T214

1

clear_one[2]

auto[1]

auto[0]

auto[0]

104

1

T224

1

T158

1

T159

1

clear_one[2]

auto[1]

auto[0]

auto[1]

31

1

T16

1

T106

1

T49

1

clear_one[3]

auto[0]

auto[0]

auto[0]

396

1

T14

1

T16

1

T86

1

clear_one[3]

auto[0]

auto[1]

auto[0]

129

1

T2

1

T15

1

T86

1

clear_one[3]

auto[1]

auto[0]

auto[0]

122

1

T16

2

T221

1

T224

2

clear_one[3]

auto[1]

auto[1]

auto[0]

44

1

T16

1

T216

1

T246

2

clear_none

auto[0]

auto[0]

auto[0]

1277

1

T1

1

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

147

1

T14

1

T16

1

T212

3

clear_none

auto[0]

auto[1]

auto[0]

148

1

T1

1

T12

1

T16

1

clear_none

auto[0]

auto[1]

auto[1]

50

1

T16

1

T162

3

T82

1

clear_none

auto[1]

auto[0]

auto[0]

127

1

T16

2

T221

1

T278

1

clear_none

auto[1]

auto[0]

auto[1]

31

1

T49

1

T137

1

T374

1

clear_none

auto[1]

auto[1]

auto[0]

38

1

T4

1

T16

1

T86

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T49

2

T142

1

T162

6

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1342	1			T1	2		T2	2		T3	1
clear_all	auto[1]	112	1			T137	1		T142	4		T144	2
clear_one[1]	auto[0]	622	1			T1	4		T2	2		T12	2
clear_one[1]	auto[1]	43	1			T137	1		T144	3		T146	3
clear_one[2]	auto[0]	625	1			T12	1		T13	2		T14	1
clear_one[2]	auto[1]	33	1			T80	1		T82	1		T283	4
clear_one[3]	auto[0]	645	1			T2	1		T14	1		T15	1
clear_one[3]	auto[1]	46	1			T144	2		T162	1		T110	2
clear_none	auto[0]	1725	1			T1	2		T2	1		T3	1
clear_none	auto[1]	118	1			T137	2		T142	6		T162	14