Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11089

1

T1

5

T2

10

T3

11

auto[Attestation]

7381

1

T1

3

T2

12

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2684	1			T2	6		T3	1		T4	3
auto[Aes]	3410	1			T2	4		T3	4		T4	4
auto[Kmac]	3298	1			T1	8		T2	5		T3	2
auto[Otbn]	3357	1			T2	1		T3	6		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7459	1			T1	8		T2	8		T3	3
auto[OpGenId]	5721	1			T2	6		T3	3		T4	7
auto[OpGenSwOut]	5811	1			T2	11		T3	5		T4	5
auto[OpGenHwOut]	6938	1			T1	8		T2	5		T3	8
auto[OpDisable]	143	1			T4	1		T13	1		T16	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10249

1

T1

8

T2

9

T3

11

auto[OpDoneFail]

15823

1

T1

8

T2

21

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6514	1			T1	1		T2	1		T3	6
auto[StInit]	3760	1			T1	2		T2	4		T3	4
auto[StCreatorRootKey]	3037	1			T1	2		T2	3		T3	5
auto[StOwnerIntKey]	2646	1			T1	2		T2	3		T3	4
auto[StOwnerKey]	2404	1			T1	2		T2	2		T4	4
auto[StDisabled]	7711	1			T1	7		T2	17		T4	4

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	330	1			T4	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T86	1		T60	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T3	1		T12	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T15	1		T16	1		T212	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T13	1		T16	2		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T2	2		T13	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	321	1			T15	2		T86	1		T213	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	104	1			T12	2		T13	1		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T13	1		T213	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T13	2		T15	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T138	1		T142	1		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	227	1			T2	2		T16	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	326	1			T12	2		T33	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	100	1			T2	1		T59	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T4	2		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T16	3		T33	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	66	1			T2	1		T13	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	218	1			T4	1		T13	1		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	327	1			T3	2		T12	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T13	1		T88	1		T213	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	68	1			T3	1		T86	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T15	1		T16	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T13	1		T88	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T2	1		T16	2		T212	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T16	1		T50	3		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	119	1			T2	1		T15	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T13	1		T16	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T13	1		T85	1		T216	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T13	2		T217	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	234	1			T2	2		T16	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	92	1			T49	5		T50	5		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T13	4		T88	2		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	85	1			T16	2		T213	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T49	1		T141	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T88	1		T214	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	214	1			T13	1		T106	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T16	1		T88	1		T49	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T2	1		T3	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	71	1			T16	1		T49	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T4	1		T13	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T86	1		T218	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	207	1			T13	1		T16	1		T86	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T88	1		T49	4		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	100	1			T13	3		T16	2		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T16	1		T213	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T13	1		T86	1		T214	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T16	1		T86	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	202	1			T16	1		T85	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	281	1			T4	2		T12	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	116	1			T16	1		T49	3		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T16	1		T133	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	47	1			T13	1		T16	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	42	1			T220	1		T49	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	169	1			T16	3		T106	2		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	535	1			T12	3		T15	4		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T16	2		T33	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T3	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T3	2		T16	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T4	1		T221	1		T214	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	276	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	477	1			T3	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	101	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T1	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T16	1		T133	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T222	1		T217	2		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	277	1			T1	3		T16	3		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	528	1			T4	1		T12	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T3	1		T14	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T14	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T14	1		T15	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T214	1		T217	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	291	1			T14	3		T16	3		T88	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T49	2		T50	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T13	4		T85	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T2	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	47	1			T13	1		T16	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T16	1		T88	2		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	186	1			T16	2		T86	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T16	1		T49	6		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T16	1		T88	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	110	1			T13	1		T16	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T3	1		T4	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T224	1		T214	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	282	1			T2	1		T16	4		T86	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	43	1			T16	1		T49	6		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T13	3		T33	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T2	1		T12	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T1	1		T4	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	264	1			T1	1		T2	1		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T16	1		T88	1		T49	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	96	1			T33	1		T218	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T3	1		T12	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	78	1			T13	1		T14	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	272	1			T14	1		T16	2		T106	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T3	1		T12	1		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	646	1			T2	2		T4	1		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	189	1			T13	2		T15	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	668	1			T2	2		T12	2		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	217	1			T2	1		T4	2		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	668	1			T2	1		T4	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T3	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	660	1			T2	1		T3	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	170	1			T13	4		T16	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	423	1			T2	3		T15	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	197	1			T16	1		T88	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	433	1			T13	5		T16	1		T88	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T4	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	386	1			T2	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	192	1			T16	2		T86	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	387	1			T13	4		T16	3		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	161	1			T13	1		T16	2		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	576	1			T4	2		T12	1		T16	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	268	1			T3	3		T4	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	928	1			T2	1		T4	1		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	251	1			T1	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	874	1			T1	4		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T14	2		T15	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	959	1			T3	1		T4	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	161	1			T2	1		T13	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	358	1			T13	4		T16	2		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	254	1			T3	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	473	1			T2	1		T16	6		T86	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T1	2		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	432	1			T1	1		T2	2		T13	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T3	2		T12	2		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	432	1			T14	1		T16	4		T33	1