Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31965

1

T1

22

T2

38

T3

20

auto[1]

309

1

T137

3

T142

7

T144

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31981	1			T1	22		T2	38		T3	20
auto[134217728:268435455]	15	1			T142	1		T144	1		T331	1
auto[268435456:402653183]	15	1			T144	1		T145	1		T110	1
auto[402653184:536870911]	9	1			T162	1		T149	2		T282	1
auto[536870912:671088639]	9	1			T145	1		T147	1		T149	1
auto[671088640:805306367]	8	1			T162	1		T110	1		T331	1
auto[805306368:939524095]	11	1			T137	1		T144	1		T82	1
auto[939524096:1073741823]	15	1			T137	1		T110	1		T147	1
auto[1073741824:1207959551]	7	1			T144	1		T110	1		T283	1
auto[1207959552:1342177279]	4	1			T283	1		T347	1		T406	1
auto[1342177280:1476395007]	6	1			T144	1		T82	1		T291	2
auto[1476395008:1610612735]	16	1			T82	2		T145	1		T318	1
auto[1610612736:1744830463]	7	1			T144	1		T162	2		T331	1
auto[1744830464:1879048191]	8	1			T113	1		T386	1		T291	1
auto[1879048192:2013265919]	13	1			T142	1		T149	1		T282	1
auto[2013265920:2147483647]	14	1			T146	1		T147	1		T331	1
auto[2147483648:2281701375]	8	1			T162	1		T407	1		T314	1
auto[2281701376:2415919103]	7	1			T408	1		T245	1		T409	1
auto[2415919104:2550136831]	10	1			T113	1		T282	1		T410	1
auto[2550136832:2684354559]	9	1			T142	1		T162	1		T113	1
auto[2684354560:2818572287]	7	1			T408	1		T291	1		T410	1
auto[2818572288:2952790015]	8	1			T142	1		T149	1		T387	1
auto[2952790016:3087007743]	9	1			T162	1		T113	1		T331	1
auto[3087007744:3221225471]	4	1			T145	1		T110	1		T113	1
auto[3221225472:3355443199]	9	1			T144	1		T145	1		T146	1
auto[3355443200:3489660927]	7	1			T144	1		T146	1		T283	1
auto[3489660928:3623878655]	9	1			T144	1		T145	1		T331	1
auto[3623878656:3758096383]	9	1			T142	1		T145	1		T266	1
auto[3758096384:3892314111]	7	1			T149	1		T335	2		T411	1
auto[3892314112:4026531839]	11	1			T144	1		T110	1		T147	1
auto[4026531840:4160749567]	11	1			T137	1		T162	1		T282	1
auto[4160749568:4294967295]	11	1			T142	1		T145	1		T147	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31965	1			T1	22		T2	38		T3	20
auto[0:134217727]	auto[1]	16	1			T142	1		T146	1		T147	1
auto[134217728:268435455]	auto[1]	15	1			T142	1		T144	1		T331	1
auto[268435456:402653183]	auto[1]	15	1			T144	1		T145	1		T110	1
auto[402653184:536870911]	auto[1]	9	1			T162	1		T149	2		T282	1
auto[536870912:671088639]	auto[1]	9	1			T145	1		T147	1		T149	1
auto[671088640:805306367]	auto[1]	8	1			T162	1		T110	1		T331	1
auto[805306368:939524095]	auto[1]	11	1			T137	1		T144	1		T82	1
auto[939524096:1073741823]	auto[1]	15	1			T137	1		T110	1		T147	1
auto[1073741824:1207959551]	auto[1]	7	1			T144	1		T110	1		T283	1
auto[1207959552:1342177279]	auto[1]	4	1			T283	1		T347	1		T406	1
auto[1342177280:1476395007]	auto[1]	6	1			T144	1		T82	1		T291	2
auto[1476395008:1610612735]	auto[1]	16	1			T82	2		T145	1		T318	1
auto[1610612736:1744830463]	auto[1]	7	1			T144	1		T162	2		T331	1
auto[1744830464:1879048191]	auto[1]	8	1			T113	1		T386	1		T291	1
auto[1879048192:2013265919]	auto[1]	13	1			T142	1		T149	1		T282	1
auto[2013265920:2147483647]	auto[1]	14	1			T146	1		T147	1		T331	1
auto[2147483648:2281701375]	auto[1]	8	1			T162	1		T407	1		T314	1
auto[2281701376:2415919103]	auto[1]	7	1			T408	1		T245	1		T409	1
auto[2415919104:2550136831]	auto[1]	10	1			T113	1		T282	1		T410	1
auto[2550136832:2684354559]	auto[1]	9	1			T142	1		T162	1		T113	1
auto[2684354560:2818572287]	auto[1]	7	1			T408	1		T291	1		T410	1
auto[2818572288:2952790015]	auto[1]	8	1			T142	1		T149	1		T387	1
auto[2952790016:3087007743]	auto[1]	9	1			T162	1		T113	1		T331	1
auto[3087007744:3221225471]	auto[1]	4	1			T145	1		T110	1		T113	1
auto[3221225472:3355443199]	auto[1]	9	1			T144	1		T145	1		T146	1
auto[3355443200:3489660927]	auto[1]	7	1			T144	1		T146	1		T283	1
auto[3489660928:3623878655]	auto[1]	9	1			T144	1		T145	1		T331	1
auto[3623878656:3758096383]	auto[1]	9	1			T142	1		T145	1		T266	1
auto[3758096384:3892314111]	auto[1]	7	1			T149	1		T335	2		T411	1
auto[3892314112:4026531839]	auto[1]	11	1			T144	1		T110	1		T147	1
auto[4026531840:4160749567]	auto[1]	11	1			T137	1		T162	1		T282	1
auto[4160749568:4294967295]	auto[1]	11	1			T142	1		T145	1		T147	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1563

1

T2

1

T4

1

T13

6

auto[1]

1734

1

T2

1

T3

1

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	83	1			T5	2		T16	2		T49	2
auto[134217728:268435455]	102	1			T15	2		T86	1		T49	2
auto[268435456:402653183]	106	1			T88	1		T212	1		T49	2
auto[402653184:536870911]	91	1			T86	1		T213	1		T41	1
auto[536870912:671088639]	108	1			T218	1		T106	1		T49	2
auto[671088640:805306367]	113	1			T3	1		T4	1		T16	1
auto[805306368:939524095]	95	1			T13	1		T217	1		T106	2
auto[939524096:1073741823]	109	1			T13	1		T15	1		T16	1
auto[1073741824:1207959551]	112	1			T15	1		T16	2		T220	2
auto[1207959552:1342177279]	111	1			T13	1		T15	1		T16	1
auto[1342177280:1476395007]	121	1			T16	2		T106	1		T49	1
auto[1476395008:1610612735]	94	1			T13	1		T16	1		T133	1
auto[1610612736:1744830463]	110	1			T5	1		T218	1		T49	1
auto[1744830464:1879048191]	99	1			T12	1		T13	1		T15	1
auto[1879048192:2013265919]	102	1			T13	1		T15	1		T16	1
auto[2013265920:2147483647]	86	1			T16	1		T34	1		T88	1
auto[2147483648:2281701375]	110	1			T13	1		T5	2		T16	1
auto[2281701376:2415919103]	111	1			T2	1		T88	1		T59	1
auto[2415919104:2550136831]	97	1			T213	1		T212	1		T216	1
auto[2550136832:2684354559]	97	1			T4	1		T16	1		T218	1
auto[2684354560:2818572287]	119	1			T16	2		T34	2		T88	3
auto[2818572288:2952790015]	96	1			T2	1		T13	1		T16	1
auto[2952790016:3087007743]	128	1			T13	2		T16	1		T60	1
auto[3087007744:3221225471]	106	1			T13	2		T15	1		T16	1
auto[3221225472:3355443199]	98	1			T12	1		T15	1		T34	1
auto[3355443200:3489660927]	93	1			T13	1		T214	1		T19	1
auto[3489660928:3623878655]	109	1			T12	1		T13	1		T218	1
auto[3623878656:3758096383]	90	1			T86	1		T48	1		T88	1
auto[3758096384:3892314111]	103	1			T13	2		T16	1		T106	1
auto[3892314112:4026531839]	94	1			T5	1		T49	2		T142	1
auto[4026531840:4160749567]	104	1			T4	1		T13	1		T88	1
auto[4160749568:4294967295]	100	1			T4	1		T15	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T5	2		T49	1		T44	1
auto[0:134217727]	auto[1]	40	1			T16	2		T49	1		T141	1
auto[134217728:268435455]	auto[0]	37	1			T15	1		T72	1		T110	1
auto[134217728:268435455]	auto[1]	65	1			T15	1		T86	1		T49	2
auto[268435456:402653183]	auto[0]	60	1			T212	1		T49	2		T45	1
auto[268435456:402653183]	auto[1]	46	1			T88	1		T144	1		T50	1
auto[402653184:536870911]	auto[0]	45	1			T213	1		T50	1		T107	1
auto[402653184:536870911]	auto[1]	46	1			T86	1		T41	1		T49	1
auto[536870912:671088639]	auto[0]	57	1			T218	1		T49	1		T22	1
auto[536870912:671088639]	auto[1]	51	1			T106	1		T49	1		T215	1
auto[671088640:805306367]	auto[0]	47	1			T106	1		T216	1		T49	1
auto[671088640:805306367]	auto[1]	66	1			T3	1		T4	1		T16	1
auto[805306368:939524095]	auto[0]	49	1			T106	2		T66	1		T90	2
auto[805306368:939524095]	auto[1]	46	1			T13	1		T217	1		T219	1
auto[939524096:1073741823]	auto[0]	46	1			T15	1		T86	1		T49	2
auto[939524096:1073741823]	auto[1]	63	1			T13	1		T16	1		T49	3
auto[1073741824:1207959551]	auto[0]	42	1			T82	1		T122	1		T111	1
auto[1073741824:1207959551]	auto[1]	70	1			T15	1		T16	2		T220	2
auto[1207959552:1342177279]	auto[0]	61	1			T16	1		T159	1		T22	1
auto[1207959552:1342177279]	auto[1]	50	1			T13	1		T15	1		T218	1
auto[1342177280:1476395007]	auto[0]	59	1			T49	1		T142	1		T50	1
auto[1342177280:1476395007]	auto[1]	62	1			T16	2		T106	1		T162	1
auto[1476395008:1610612735]	auto[0]	52	1			T16	1		T60	1		T252	1
auto[1476395008:1610612735]	auto[1]	42	1			T13	1		T133	1		T48	1
auto[1610612736:1744830463]	auto[0]	53	1			T5	1		T218	1		T139	1
auto[1610612736:1744830463]	auto[1]	57	1			T49	1		T50	1		T42	2
auto[1744830464:1879048191]	auto[0]	47	1			T13	1		T16	1		T218	1
auto[1744830464:1879048191]	auto[1]	52	1			T12	1		T15	1		T17	1
auto[1879048192:2013265919]	auto[0]	51	1			T15	1		T16	1		T34	1
auto[1879048192:2013265919]	auto[1]	51	1			T13	1		T88	1		T106	1
auto[2013265920:2147483647]	auto[0]	40	1			T252	1		T107	1		T298	1
auto[2013265920:2147483647]	auto[1]	46	1			T16	1		T34	1		T88	1
auto[2147483648:2281701375]	auto[0]	50	1			T13	1		T5	1		T218	1
auto[2147483648:2281701375]	auto[1]	60	1			T5	1		T16	1		T142	1
auto[2281701376:2415919103]	auto[0]	46	1			T88	1		T59	1		T162	1
auto[2281701376:2415919103]	auto[1]	65	1			T2	1		T49	2		T50	1
auto[2415919104:2550136831]	auto[0]	41	1			T213	1		T216	1		T49	1
auto[2415919104:2550136831]	auto[1]	56	1			T212	1		T49	2		T52	1
auto[2550136832:2684354559]	auto[0]	51	1			T16	1		T159	1		T250	1
auto[2550136832:2684354559]	auto[1]	46	1			T4	1		T218	1		T60	1
auto[2684354560:2818572287]	auto[0]	54	1			T34	1		T88	2		T212	1
auto[2684354560:2818572287]	auto[1]	65	1			T16	2		T34	1		T88	1
auto[2818572288:2952790015]	auto[0]	50	1			T2	1		T86	1		T216	1
auto[2818572288:2952790015]	auto[1]	46	1			T13	1		T16	1		T49	1
auto[2952790016:3087007743]	auto[0]	61	1			T16	1		T159	1		T144	1
auto[2952790016:3087007743]	auto[1]	67	1			T13	2		T60	1		T49	1
auto[3087007744:3221225471]	auto[0]	50	1			T13	2		T15	1		T212	1
auto[3087007744:3221225471]	auto[1]	56	1			T16	1		T86	1		T49	1
auto[3221225472:3355443199]	auto[0]	41	1			T15	1		T34	1		T49	1
auto[3221225472:3355443199]	auto[1]	57	1			T12	1		T106	1		T219	1
auto[3355443200:3489660927]	auto[0]	49	1			T214	1		T289	1		T91	1
auto[3355443200:3489660927]	auto[1]	44	1			T13	1		T19	1		T261	1
auto[3489660928:3623878655]	auto[0]	54	1			T13	1		T218	1		T49	1
auto[3489660928:3623878655]	auto[1]	55	1			T12	1		T55	1		T82	1
auto[3623878656:3758096383]	auto[0]	35	1			T86	1		T88	1		T22	1
auto[3623878656:3758096383]	auto[1]	55	1			T48	1		T137	1		T45	1
auto[3758096384:3892314111]	auto[0]	50	1			T13	1		T16	1		T49	1
auto[3758096384:3892314111]	auto[1]	53	1			T13	1		T106	1		T219	1
auto[3892314112:4026531839]	auto[0]	47	1			T5	1		T50	2		T72	1
auto[3892314112:4026531839]	auto[1]	47	1			T49	2		T142	1		T56	1
auto[4026531840:4160749567]	auto[0]	46	1			T41	1		T220	1		T49	2
auto[4026531840:4160749567]	auto[1]	58	1			T4	1		T13	1		T88	1
auto[4160749568:4294967295]	auto[0]	49	1			T4	1		T15	1		T86	1
auto[4160749568:4294967295]	auto[1]	51	1			T16	1		T49	1		T304	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1579

1

T2

1

T4

1

T13

6

auto[1]

1717

1

T2

1

T3

1

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T34	1		T88	1		T49	4
auto[134217728:268435455]	99	1			T218	1		T49	1		T44	1
auto[268435456:402653183]	102	1			T16	1		T86	1		T212	2
auto[402653184:536870911]	104	1			T16	2		T86	1		T218	1
auto[536870912:671088639]	96	1			T4	1		T15	1		T88	1
auto[671088640:805306367]	102	1			T5	2		T86	1		T217	1
auto[805306368:939524095]	95	1			T5	1		T16	2		T88	1
auto[939524096:1073741823]	107	1			T15	1		T41	1		T106	2
auto[1073741824:1207959551]	113	1			T13	1		T15	1		T16	2
auto[1207959552:1342177279]	110	1			T13	3		T16	1		T86	1
auto[1342177280:1476395007]	112	1			T13	2		T86	1		T216	1
auto[1476395008:1610612735]	109	1			T12	1		T15	2		T88	1
auto[1610612736:1744830463]	102	1			T5	1		T16	1		T218	1
auto[1744830464:1879048191]	90	1			T13	2		T15	1		T16	1
auto[1879048192:2013265919]	110	1			T12	1		T16	1		T86	1
auto[2013265920:2147483647]	96	1			T13	2		T34	1		T88	1
auto[2147483648:2281701375]	112	1			T5	2		T15	1		T218	1
auto[2281701376:2415919103]	84	1			T3	1		T13	1		T16	2
auto[2415919104:2550136831]	107	1			T2	2		T218	1		T49	4
auto[2550136832:2684354559]	87	1			T49	1		T159	1		T22	1
auto[2684354560:2818572287]	98	1			T4	1		T12	1		T13	1
auto[2818572288:2952790015]	117	1			T16	2		T49	1		T142	1
auto[2952790016:3087007743]	103	1			T13	1		T16	1		T17	1
auto[3087007744:3221225471]	103	1			T13	1		T34	1		T49	2
auto[3221225472:3355443199]	121	1			T16	1		T41	1		T49	3
auto[3355443200:3489660927]	114	1			T16	1		T86	1		T34	1
auto[3489660928:3623878655]	106	1			T13	2		T159	1		T50	1
auto[3623878656:3758096383]	100	1			T15	1		T16	1		T49	2
auto[3758096384:3892314111]	99	1			T88	1		T212	1		T49	1
auto[3892314112:4026531839]	116	1			T13	1		T16	1		T48	1
auto[4026531840:4160749567]	99	1			T4	1		T15	1		T16	1
auto[4160749568:4294967295]	79	1			T4	1		T218	1		T60	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T34	1		T22	1		T162	1
auto[0:134217727]	auto[1]	56	1			T88	1		T49	4		T50	1
auto[134217728:268435455]	auto[0]	43	1			T218	1		T44	1		T122	1
auto[134217728:268435455]	auto[1]	56	1			T49	1		T107	1		T281	1
auto[268435456:402653183]	auto[0]	47	1			T16	1		T86	1		T212	2
auto[268435456:402653183]	auto[1]	55	1			T60	1		T49	3		T374	1
auto[402653184:536870911]	auto[0]	52	1			T218	1		T49	2		T50	1
auto[402653184:536870911]	auto[1]	52	1			T16	2		T86	1		T60	1
auto[536870912:671088639]	auto[0]	44	1			T4	1		T15	1		T214	1
auto[536870912:671088639]	auto[1]	52	1			T88	1		T216	1		T49	1
auto[671088640:805306367]	auto[0]	44	1			T5	2		T159	1		T50	1
auto[671088640:805306367]	auto[1]	58	1			T86	1		T217	1		T219	1
auto[805306368:939524095]	auto[0]	51	1			T5	1		T41	1		T220	1
auto[805306368:939524095]	auto[1]	44	1			T16	2		T88	1		T82	1
auto[939524096:1073741823]	auto[0]	50	1			T22	1		T144	1		T91	1
auto[939524096:1073741823]	auto[1]	57	1			T15	1		T41	1		T106	2
auto[1073741824:1207959551]	auto[0]	57	1			T88	1		T214	1		T137	1
auto[1073741824:1207959551]	auto[1]	56	1			T13	1		T15	1		T16	2
auto[1207959552:1342177279]	auto[0]	58	1			T13	1		T86	1		T219	1
auto[1207959552:1342177279]	auto[1]	52	1			T13	2		T16	1		T212	1
auto[1342177280:1476395007]	auto[0]	44	1			T13	1		T50	1		T89	1
auto[1342177280:1476395007]	auto[1]	68	1			T13	1		T86	1		T216	1
auto[1476395008:1610612735]	auto[0]	56	1			T15	1		T212	1		T106	1
auto[1476395008:1610612735]	auto[1]	53	1			T12	1		T15	1		T88	1
auto[1610612736:1744830463]	auto[0]	51	1			T5	1		T218	1		T106	1
auto[1610612736:1744830463]	auto[1]	51	1			T16	1		T162	1		T412	1
auto[1744830464:1879048191]	auto[0]	42	1			T15	1		T218	1		T49	1
auto[1744830464:1879048191]	auto[1]	48	1			T13	2		T16	1		T34	1
auto[1879048192:2013265919]	auto[0]	48	1			T16	1		T88	1		T213	1
auto[1879048192:2013265919]	auto[1]	62	1			T12	1		T86	1		T49	1
auto[2013265920:2147483647]	auto[0]	46	1			T13	1		T34	1		T256	1
auto[2013265920:2147483647]	auto[1]	50	1			T13	1		T88	1		T41	1
auto[2147483648:2281701375]	auto[0]	51	1			T5	1		T45	1		T293	1
auto[2147483648:2281701375]	auto[1]	61	1			T5	1		T15	1		T218	1
auto[2281701376:2415919103]	auto[0]	41	1			T16	1		T60	1		T46	1
auto[2281701376:2415919103]	auto[1]	43	1			T3	1		T13	1		T16	1
auto[2415919104:2550136831]	auto[0]	48	1			T2	1		T218	1		T49	2
auto[2415919104:2550136831]	auto[1]	59	1			T2	1		T49	2		T139	1
auto[2550136832:2684354559]	auto[0]	42	1			T22	1		T50	1		T107	1
auto[2550136832:2684354559]	auto[1]	45	1			T49	1		T159	1		T36	1
auto[2684354560:2818572287]	auto[0]	49	1			T13	1		T15	1		T49	1
auto[2684354560:2818572287]	auto[1]	49	1			T4	1		T12	1		T16	1
auto[2818572288:2952790015]	auto[0]	48	1			T142	1		T66	1		T412	1
auto[2818572288:2952790015]	auto[1]	69	1			T16	2		T49	1		T50	1
auto[2952790016:3087007743]	auto[0]	41	1			T212	1		T218	1		T122	1
auto[2952790016:3087007743]	auto[1]	62	1			T13	1		T16	1		T17	1
auto[3087007744:3221225471]	auto[0]	53	1			T34	1		T49	1		T141	1
auto[3087007744:3221225471]	auto[1]	50	1			T13	1		T49	1		T45	1
auto[3221225472:3355443199]	auto[0]	63	1			T16	1		T49	3		T66	1
auto[3221225472:3355443199]	auto[1]	58	1			T41	1		T52	1		T56	1
auto[3355443200:3489660927]	auto[0]	52	1			T16	1		T86	1		T106	2
auto[3355443200:3489660927]	auto[1]	62	1			T34	1		T48	1		T106	1
auto[3489660928:3623878655]	auto[0]	53	1			T13	1		T159	1		T50	1
auto[3489660928:3623878655]	auto[1]	53	1			T13	1		T66	1		T122	2
auto[3623878656:3758096383]	auto[0]	49	1			T15	1		T49	1		T137	1
auto[3623878656:3758096383]	auto[1]	51	1			T16	1		T49	1		T142	1
auto[3758096384:3892314111]	auto[0]	59	1			T88	1		T212	1		T110	1
auto[3758096384:3892314111]	auto[1]	40	1			T49	1		T142	1		T52	1
auto[3892314112:4026531839]	auto[0]	62	1			T13	1		T16	1		T88	1
auto[3892314112:4026531839]	auto[1]	54	1			T48	1		T137	1		T50	1
auto[4026531840:4160749567]	auto[0]	52	1			T15	1		T213	1		T144	1
auto[4026531840:4160749567]	auto[1]	47	1			T4	1		T16	1		T141	1
auto[4160749568:4294967295]	auto[0]	35	1			T60	1		T50	1		T252	1
auto[4160749568:4294967295]	auto[1]	44	1			T4	1		T218	1		T60	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1527

1

T4

1

T13

5

T5

5

auto[1]

1770

1

T2

2

T3

1

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T13	1		T15	1		T16	4
auto[134217728:268435455]	91	1			T15	1		T16	2		T49	2
auto[268435456:402653183]	109	1			T13	1		T88	1		T212	2
auto[402653184:536870911]	103	1			T3	1		T15	1		T212	1
auto[536870912:671088639]	102	1			T15	1		T16	1		T88	1
auto[671088640:805306367]	107	1			T13	1		T5	1		T16	1
auto[805306368:939524095]	90	1			T13	1		T49	1		T139	1
auto[939524096:1073741823]	104	1			T13	1		T5	1		T15	1
auto[1073741824:1207959551]	98	1			T12	1		T15	1		T16	1
auto[1207959552:1342177279]	112	1			T2	1		T4	1		T12	1
auto[1342177280:1476395007]	115	1			T13	1		T60	1		T106	1
auto[1476395008:1610612735]	98	1			T88	1		T49	1		T142	1
auto[1610612736:1744830463]	91	1			T4	1		T13	1		T5	1
auto[1744830464:1879048191]	117	1			T34	1		T49	1		T44	1
auto[1879048192:2013265919]	120	1			T213	1		T49	1		T139	1
auto[2013265920:2147483647]	103	1			T13	2		T16	3		T86	1
auto[2147483648:2281701375]	107	1			T13	2		T16	1		T88	1
auto[2281701376:2415919103]	100	1			T5	1		T16	2		T86	1
auto[2415919104:2550136831]	96	1			T16	1		T86	1		T17	1
auto[2550136832:2684354559]	91	1			T13	1		T16	2		T218	1
auto[2684354560:2818572287]	118	1			T12	1		T5	1		T16	1
auto[2818572288:2952790015]	84	1			T2	1		T4	1		T218	1
auto[2952790016:3087007743]	112	1			T15	1		T137	1		T141	1
auto[3087007744:3221225471]	118	1			T13	1		T16	1		T88	1
auto[3221225472:3355443199]	97	1			T86	1		T34	1		T106	1
auto[3355443200:3489660927]	93	1			T15	1		T88	1		T49	2
auto[3489660928:3623878655]	99	1			T15	1		T133	1		T212	1
auto[3623878656:3758096383]	109	1			T13	1		T218	1		T142	1
auto[3758096384:3892314111]	105	1			T13	1		T49	3		T50	1
auto[3892314112:4026531839]	102	1			T13	1		T15	1		T214	1
auto[4026531840:4160749567]	93	1			T16	1		T86	1		T41	1
auto[4160749568:4294967295]	100	1			T4	1		T16	1		T88	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T15	1		T16	1		T34	1
auto[0:134217727]	auto[1]	66	1			T13	1		T16	3		T48	2
auto[134217728:268435455]	auto[0]	37	1			T15	1		T49	1		T46	1
auto[134217728:268435455]	auto[1]	54	1			T16	2		T49	1		T107	1
auto[268435456:402653183]	auto[0]	50	1			T212	2		T218	1		T216	1
auto[268435456:402653183]	auto[1]	59	1			T13	1		T88	1		T214	1
auto[402653184:536870911]	auto[0]	50	1			T220	1		T49	1		T252	1
auto[402653184:536870911]	auto[1]	53	1			T3	1		T15	1		T212	1
auto[536870912:671088639]	auto[0]	54	1			T16	1		T49	2		T82	1
auto[536870912:671088639]	auto[1]	48	1			T15	1		T88	1		T59	1
auto[671088640:805306367]	auto[0]	51	1			T16	1		T34	1		T49	3
auto[671088640:805306367]	auto[1]	56	1			T13	1		T5	1		T88	1
auto[805306368:939524095]	auto[0]	34	1			T49	1		T144	1		T107	1
auto[805306368:939524095]	auto[1]	56	1			T13	1		T139	1		T142	1
auto[939524096:1073741823]	auto[0]	47	1			T5	1		T15	1		T218	1
auto[939524096:1073741823]	auto[1]	57	1			T13	1		T41	2		T220	1
auto[1073741824:1207959551]	auto[0]	47	1			T16	1		T162	1		T50	2
auto[1073741824:1207959551]	auto[1]	51	1			T12	1		T15	1		T218	1
auto[1207959552:1342177279]	auto[0]	53	1			T4	1		T13	1		T5	1
auto[1207959552:1342177279]	auto[1]	59	1			T2	1		T12	1		T86	1
auto[1342177280:1476395007]	auto[0]	47	1			T106	1		T19	1		T293	1
auto[1342177280:1476395007]	auto[1]	68	1			T13	1		T60	1		T216	1
auto[1476395008:1610612735]	auto[0]	38	1			T88	1		T45	1		T51	1
auto[1476395008:1610612735]	auto[1]	60	1			T49	1		T142	1		T45	1
auto[1610612736:1744830463]	auto[0]	39	1			T5	1		T50	1		T46	1
auto[1610612736:1744830463]	auto[1]	52	1			T4	1		T13	1		T217	1
auto[1744830464:1879048191]	auto[0]	65	1			T34	1		T49	1		T44	1
auto[1744830464:1879048191]	auto[1]	52	1			T56	1		T107	1		T122	1
auto[1879048192:2013265919]	auto[0]	58	1			T213	1		T141	1		T66	1
auto[1879048192:2013265919]	auto[1]	62	1			T49	1		T139	1		T22	1
auto[2013265920:2147483647]	auto[0]	44	1			T13	1		T16	1		T86	1
auto[2013265920:2147483647]	auto[1]	59	1			T13	1		T16	2		T49	2
auto[2147483648:2281701375]	auto[0]	48	1			T88	1		T106	1		T49	1
auto[2147483648:2281701375]	auto[1]	59	1			T13	2		T16	1		T49	1
auto[2281701376:2415919103]	auto[0]	44	1			T5	1		T86	1		T107	1
auto[2281701376:2415919103]	auto[1]	56	1			T16	2		T60	1		T137	1
auto[2415919104:2550136831]	auto[0]	45	1			T88	1		T60	1		T159	1
auto[2415919104:2550136831]	auto[1]	51	1			T16	1		T86	1		T17	1
auto[2550136832:2684354559]	auto[0]	38	1			T13	1		T16	1		T218	1
auto[2550136832:2684354559]	auto[1]	53	1			T16	1		T49	1		T122	1
auto[2684354560:2818572287]	auto[0]	54	1			T5	1		T218	1		T219	1
auto[2684354560:2818572287]	auto[1]	64	1			T12	1		T16	1		T86	1
auto[2818572288:2952790015]	auto[0]	47	1			T106	1		T49	1		T144	1
auto[2818572288:2952790015]	auto[1]	37	1			T2	1		T4	1		T218	1
auto[2952790016:3087007743]	auto[0]	53	1			T91	1		T250	1		T310	1
auto[2952790016:3087007743]	auto[1]	59	1			T15	1		T137	1		T141	1
auto[3087007744:3221225471]	auto[0]	56	1			T13	1		T49	3		T137	1
auto[3087007744:3221225471]	auto[1]	62	1			T16	1		T88	1		T106	1
auto[3221225472:3355443199]	auto[0]	51	1			T34	1		T49	1		T50	1
auto[3221225472:3355443199]	auto[1]	46	1			T86	1		T106	1		T220	1
auto[3355443200:3489660927]	auto[0]	36	1			T15	1		T72	1		T122	1
auto[3355443200:3489660927]	auto[1]	57	1			T88	1		T49	2		T142	1
auto[3489660928:3623878655]	auto[0]	44	1			T15	1		T219	1		T49	1
auto[3489660928:3623878655]	auto[1]	55	1			T133	1		T212	1		T41	1
auto[3623878656:3758096383]	auto[0]	57	1			T37	1		T122	1		T89	1
auto[3623878656:3758096383]	auto[1]	52	1			T13	1		T218	1		T142	1
auto[3758096384:3892314111]	auto[0]	44	1			T49	2		T66	1		T91	1
auto[3758096384:3892314111]	auto[1]	61	1			T13	1		T49	1		T50	1
auto[3892314112:4026531839]	auto[0]	53	1			T13	1		T106	1		T101	1
auto[3892314112:4026531839]	auto[1]	49	1			T15	1		T214	1		T218	1
auto[4026531840:4160749567]	auto[0]	39	1			T86	1		T42	1		T90	1
auto[4026531840:4160749567]	auto[1]	54	1			T16	1		T41	1		T142	1
auto[4160749568:4294967295]	auto[0]	57	1			T16	1		T212	1		T101	1
auto[4160749568:4294967295]	auto[1]	43	1			T4	1		T88	1		T141	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1566

1

T2

1

T3

1

T4

1

auto[1]

1732

1

T2

1

T4

3

T12

3