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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4538 1 T2 2 T3 2 T4 6
auto[1] 2056 1 T2 2 T4 2 T12 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 194 1 T13 4 T15 2 T16 2
auto[134217728:268435455] 172 1 T3 2 T214 2 T106 2
auto[268435456:402653183] 214 1 T48 2 T212 2 T49 2
auto[402653184:536870911] 174 1 T13 2 T16 4 T141 2
auto[536870912:671088639] 224 1 T2 2 T13 2 T88 4
auto[671088640:805306367] 202 1 T16 4 T88 2 T106 2
auto[805306368:939524095] 222 1 T13 2 T15 2 T133 2
auto[939524096:1073741823] 184 1 T13 2 T60 2 T106 2
auto[1073741824:1207959551] 190 1 T16 2 T218 2 T217 2
auto[1207959552:1342177279] 202 1 T5 2 T86 2 T219 2
auto[1342177280:1476395007] 206 1 T4 4 T15 2 T213 4
auto[1476395008:1610612735] 218 1 T15 2 T16 4 T218 2
auto[1610612736:1744830463] 188 1 T16 2 T49 2 T45 2
auto[1744830464:1879048191] 198 1 T13 2 T59 2 T219 2
auto[1879048192:2013265919] 212 1 T16 2 T212 4 T41 2
auto[2013265920:2147483647] 214 1 T13 2 T16 2 T86 2
auto[2147483648:2281701375] 198 1 T49 4 T19 2 T42 2
auto[2281701376:2415919103] 218 1 T4 2 T13 2 T15 2
auto[2415919104:2550136831] 210 1 T86 2 T88 4 T49 2
auto[2550136832:2684354559] 214 1 T13 2 T16 4 T34 2
auto[2684354560:2818572287] 198 1 T13 2 T34 4 T220 2
auto[2818572288:2952790015] 222 1 T13 2 T15 2 T34 4
auto[2952790016:3087007743] 216 1 T12 2 T15 2 T214 2
auto[3087007744:3221225471] 202 1 T13 4 T15 2 T16 4
auto[3221225472:3355443199] 238 1 T13 2 T5 6 T49 6
auto[3355443200:3489660927] 194 1 T86 2 T88 2 T49 6
auto[3489660928:3623878655] 238 1 T2 2 T4 2 T12 4
auto[3623878656:3758096383] 218 1 T15 2 T16 4 T88 2
auto[3758096384:3892314111] 206 1 T16 4 T218 2 T106 4
auto[3892314112:4026531839] 192 1 T13 4 T5 2 T60 2
auto[4026531840:4160749567] 208 1 T49 2 T142 2 T36 2
auto[4160749568:4294967295] 208 1 T5 2 T15 2 T16 4


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 122 1 T13 2 T15 2 T16 2
auto[0:134217727] auto[1] 72 1 T13 2 T17 2 T106 2
auto[134217728:268435455] auto[0] 118 1 T3 2 T214 2 T106 2
auto[134217728:268435455] auto[1] 54 1 T216 2 T141 2 T50 2
auto[268435456:402653183] auto[0] 146 1 T212 2 T144 2 T50 2
auto[268435456:402653183] auto[1] 68 1 T48 2 T49 2 T42 2
auto[402653184:536870911] auto[0] 108 1 T13 2 T141 2 T22 2
auto[402653184:536870911] auto[1] 66 1 T16 4 T58 2 T63 4
auto[536870912:671088639] auto[0] 150 1 T88 2 T49 4 T141 2
auto[536870912:671088639] auto[1] 74 1 T2 2 T13 2 T88 2
auto[671088640:805306367] auto[0] 132 1 T16 2 T88 2 T106 2
auto[671088640:805306367] auto[1] 70 1 T16 2 T159 4 T256 2
auto[805306368:939524095] auto[0] 152 1 T13 2 T15 2 T133 2
auto[805306368:939524095] auto[1] 70 1 T49 2 T68 2 T63 2
auto[939524096:1073741823] auto[0] 110 1 T22 2 T101 2 T242 2
auto[939524096:1073741823] auto[1] 74 1 T13 2 T60 2 T106 2
auto[1073741824:1207959551] auto[0] 140 1 T16 2 T218 2 T217 2
auto[1073741824:1207959551] auto[1] 50 1 T49 4 T215 2 T68 2
auto[1207959552:1342177279] auto[0] 146 1 T5 2 T86 2 T219 2
auto[1207959552:1342177279] auto[1] 56 1 T49 2 T52 2 T252 2
auto[1342177280:1476395007] auto[0] 146 1 T4 2 T15 2 T212 2
auto[1342177280:1476395007] auto[1] 60 1 T4 2 T213 4 T41 2
auto[1476395008:1610612735] auto[0] 152 1 T15 2 T16 4 T218 2
auto[1476395008:1610612735] auto[1] 66 1 T122 2 T58 2 T370 2
auto[1610612736:1744830463] auto[0] 126 1 T16 2 T49 2 T45 2
auto[1610612736:1744830463] auto[1] 62 1 T101 2 T91 2 T63 2
auto[1744830464:1879048191] auto[0] 152 1 T13 2 T219 2 T49 4
auto[1744830464:1879048191] auto[1] 46 1 T59 2 T37 2 T8 2
auto[1879048192:2013265919] auto[0] 152 1 T16 2 T212 4 T41 2
auto[1879048192:2013265919] auto[1] 60 1 T139 2 T22 2 T26 2
auto[2013265920:2147483647] auto[0] 136 1 T13 2 T16 2 T86 2
auto[2013265920:2147483647] auto[1] 78 1 T142 2 T46 2 T101 2
auto[2147483648:2281701375] auto[0] 136 1 T49 4 T42 2 T101 2
auto[2147483648:2281701375] auto[1] 62 1 T19 2 T122 2 T280 2
auto[2281701376:2415919103] auto[0] 158 1 T4 2 T13 2 T212 2
auto[2281701376:2415919103] auto[1] 60 1 T15 2 T16 2 T49 6
auto[2415919104:2550136831] auto[0] 150 1 T86 2 T49 2 T22 2
auto[2415919104:2550136831] auto[1] 60 1 T88 4 T122 2 T58 2
auto[2550136832:2684354559] auto[0] 132 1 T13 2 T16 4 T217 2
auto[2550136832:2684354559] auto[1] 82 1 T34 2 T139 2 T55 2
auto[2684354560:2818572287] auto[0] 134 1 T13 2 T34 4 T220 2
auto[2684354560:2818572287] auto[1] 64 1 T49 2 T63 2 T70 4
auto[2818572288:2952790015] auto[0] 166 1 T13 2 T34 2 T218 2
auto[2818572288:2952790015] auto[1] 56 1 T15 2 T34 2 T49 2
auto[2952790016:3087007743] auto[0] 140 1 T12 2 T49 2 T142 2
auto[2952790016:3087007743] auto[1] 76 1 T15 2 T214 2 T216 2
auto[3087007744:3221225471] auto[0] 146 1 T13 4 T15 2 T16 4
auto[3087007744:3221225471] auto[1] 56 1 T48 2 T159 2 T162 2
auto[3221225472:3355443199] auto[0] 180 1 T5 6 T49 6 T44 2
auto[3221225472:3355443199] auto[1] 58 1 T13 2 T215 2 T66 2
auto[3355443200:3489660927] auto[0] 134 1 T86 2 T49 6 T56 2
auto[3355443200:3489660927] auto[1] 60 1 T88 2 T107 2 T66 2
auto[3489660928:3623878655] auto[0] 176 1 T2 2 T4 2 T12 2
auto[3489660928:3623878655] auto[1] 62 1 T12 2 T49 2 T141 2
auto[3623878656:3758096383] auto[0] 142 1 T16 2 T88 2 T218 2
auto[3623878656:3758096383] auto[1] 76 1 T15 2 T16 2 T60 2
auto[3758096384:3892314111] auto[0] 132 1 T218 2 T106 4 T220 2
auto[3758096384:3892314111] auto[1] 74 1 T16 4 T50 2 T101 2
auto[3892314112:4026531839] auto[0] 146 1 T13 4 T5 2 T60 2
auto[3892314112:4026531839] auto[1] 46 1 T52 2 T391 2 T298 2
auto[4026531840:4160749567] auto[0] 132 1 T49 2 T144 2 T373 2
auto[4026531840:4160749567] auto[1] 76 1 T142 2 T36 2 T45 2
auto[4160749568:4294967295] auto[0] 146 1 T5 2 T15 2 T16 2
auto[4160749568:4294967295] auto[1] 62 1 T16 2 T412 2 T328 2

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