Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2880

1

T2

2

T3

1

T4

4

auto[1]

327

1

T142

9

T144

10

T162

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T2	1		T12	1		T15	1
auto[134217728:268435455]	97	1			T13	1		T15	1		T212	1
auto[268435456:402653183]	95	1			T5	1		T86	1		T106	1
auto[402653184:536870911]	91	1			T218	1		T106	1		T142	1
auto[536870912:671088639]	101	1			T13	1		T16	1		T213	1
auto[671088640:805306367]	95	1			T13	1		T86	1		T34	1
auto[805306368:939524095]	81	1			T214	1		T218	1		T60	1
auto[939524096:1073741823]	91	1			T12	1		T88	1		T212	1
auto[1073741824:1207959551]	81	1			T15	1		T86	1		T49	2
auto[1207959552:1342177279]	88	1			T13	1		T16	1		T218	1
auto[1342177280:1476395007]	119	1			T16	1		T34	1		T88	1
auto[1476395008:1610612735]	93	1			T4	1		T13	1		T16	1
auto[1610612736:1744830463]	92	1			T4	1		T16	1		T86	1
auto[1744830464:1879048191]	117	1			T2	1		T13	1		T16	1
auto[1879048192:2013265919]	102	1			T86	1		T218	1		T49	1
auto[2013265920:2147483647]	88	1			T16	1		T106	2		T216	1
auto[2147483648:2281701375]	109	1			T12	1		T15	1		T60	1
auto[2281701376:2415919103]	103	1			T88	1		T60	1		T106	1
auto[2415919104:2550136831]	95	1			T218	2		T219	1		T220	1
auto[2550136832:2684354559]	111	1			T13	1		T34	1		T49	1
auto[2684354560:2818572287]	85	1			T15	2		T16	1		T159	1
auto[2818572288:2952790015]	121	1			T13	1		T15	1		T16	1
auto[2952790016:3087007743]	110	1			T13	1		T34	1		T59	1
auto[3087007744:3221225471]	113	1			T3	1		T13	2		T16	1
auto[3221225472:3355443199]	100	1			T13	1		T16	3		T88	1
auto[3355443200:3489660927]	106	1			T13	1		T213	1		T212	1
auto[3489660928:3623878655]	91	1			T214	1		T49	2		T137	1
auto[3623878656:3758096383]	117	1			T4	1		T13	1		T15	2
auto[3758096384:3892314111]	106	1			T16	1		T88	1		T212	1
auto[3892314112:4026531839]	99	1			T13	1		T133	1		T48	1
auto[4026531840:4160749567]	107	1			T13	1		T15	1		T16	1
auto[4160749568:4294967295]	96	1			T4	1		T212	1		T142	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	102	1			T2	1		T12	1		T15	1
auto[0:134217727]	auto[1]	5	1			T82	1		T283	1		T347	1
auto[134217728:268435455]	auto[0]	85	1			T13	1		T15	1		T212	1
auto[134217728:268435455]	auto[1]	12	1			T162	2		T80	1		T110	1
auto[268435456:402653183]	auto[0]	85	1			T5	1		T86	1		T106	1
auto[268435456:402653183]	auto[1]	10	1			T149	1		T331	1		T283	1
auto[402653184:536870911]	auto[0]	80	1			T218	1		T106	1		T142	1
auto[402653184:536870911]	auto[1]	11	1			T145	1		T147	1		T331	2
auto[536870912:671088639]	auto[0]	91	1			T13	1		T16	1		T213	1
auto[536870912:671088639]	auto[1]	10	1			T142	1		T162	1		T146	1
auto[671088640:805306367]	auto[0]	89	1			T13	1		T86	1		T34	1
auto[671088640:805306367]	auto[1]	6	1			T283	1		T282	1		T291	1
auto[805306368:939524095]	auto[0]	71	1			T214	1		T218	1		T60	1
auto[805306368:939524095]	auto[1]	10	1			T147	1		T388	3		T347	1
auto[939524096:1073741823]	auto[0]	85	1			T12	1		T88	1		T212	1
auto[939524096:1073741823]	auto[1]	6	1			T266	1		T408	1		T407	1
auto[1073741824:1207959551]	auto[0]	73	1			T15	1		T86	1		T49	2
auto[1073741824:1207959551]	auto[1]	8	1			T162	1		T145	1		T318	1
auto[1207959552:1342177279]	auto[0]	73	1			T13	1		T16	1		T218	1
auto[1207959552:1342177279]	auto[1]	15	1			T162	1		T145	1		T147	1
auto[1342177280:1476395007]	auto[0]	108	1			T16	1		T34	1		T88	1
auto[1342177280:1476395007]	auto[1]	11	1			T331	1		T408	1		T245	1
auto[1476395008:1610612735]	auto[0]	83	1			T4	1		T13	1		T16	1
auto[1476395008:1610612735]	auto[1]	10	1			T162	1		T145	1		T147	1
auto[1610612736:1744830463]	auto[0]	84	1			T4	1		T16	1		T86	1
auto[1610612736:1744830463]	auto[1]	8	1			T82	2		T283	1		T282	1
auto[1744830464:1879048191]	auto[0]	112	1			T2	1		T13	1		T16	1
auto[1744830464:1879048191]	auto[1]	5	1			T144	1		T146	1		T147	1
auto[1879048192:2013265919]	auto[0]	88	1			T86	1		T218	1		T49	1
auto[1879048192:2013265919]	auto[1]	14	1			T162	2		T110	2		T149	1
auto[2013265920:2147483647]	auto[0]	79	1			T16	1		T106	2		T216	1
auto[2013265920:2147483647]	auto[1]	9	1			T144	1		T146	1		T282	1
auto[2147483648:2281701375]	auto[0]	93	1			T12	1		T15	1		T60	1
auto[2147483648:2281701375]	auto[1]	16	1			T144	2		T162	1		T147	1
auto[2281701376:2415919103]	auto[0]	97	1			T88	1		T60	1		T106	1
auto[2281701376:2415919103]	auto[1]	6	1			T144	1		T147	1		T266	1
auto[2415919104:2550136831]	auto[0]	83	1			T218	2		T219	1		T220	1
auto[2415919104:2550136831]	auto[1]	12	1			T162	1		T82	1		T147	1
auto[2550136832:2684354559]	auto[0]	100	1			T13	1		T34	1		T49	1
auto[2550136832:2684354559]	auto[1]	11	1			T331	1		T291	2		T352	1
auto[2684354560:2818572287]	auto[0]	77	1			T15	2		T16	1		T159	1
auto[2684354560:2818572287]	auto[1]	8	1			T144	1		T162	1		T146	1
auto[2818572288:2952790015]	auto[0]	104	1			T13	1		T15	1		T16	1
auto[2818572288:2952790015]	auto[1]	17	1			T162	1		T110	1		T149	2
auto[2952790016:3087007743]	auto[0]	96	1			T13	1		T34	1		T59	1
auto[2952790016:3087007743]	auto[1]	14	1			T144	3		T80	1		T331	1
auto[3087007744:3221225471]	auto[0]	105	1			T3	1		T13	2		T16	1
auto[3087007744:3221225471]	auto[1]	8	1			T142	1		T80	1		T266	1
auto[3221225472:3355443199]	auto[0]	90	1			T13	1		T16	3		T88	1
auto[3221225472:3355443199]	auto[1]	10	1			T146	1		T408	1		T407	2
auto[3355443200:3489660927]	auto[0]	95	1			T13	1		T213	1		T212	1
auto[3355443200:3489660927]	auto[1]	11	1			T142	1		T282	1		T415	1
auto[3489660928:3623878655]	auto[0]	82	1			T214	1		T49	2		T137	1
auto[3489660928:3623878655]	auto[1]	9	1			T407	1		T386	1		T314	1
auto[3623878656:3758096383]	auto[0]	104	1			T4	1		T13	1		T15	2
auto[3623878656:3758096383]	auto[1]	13	1			T162	1		T147	1		T282	2
auto[3758096384:3892314111]	auto[0]	96	1			T16	1		T88	1		T212	1
auto[3758096384:3892314111]	auto[1]	10	1			T142	3		T144	1		T146	1
auto[3892314112:4026531839]	auto[0]	87	1			T13	1		T133	1		T48	1
auto[3892314112:4026531839]	auto[1]	12	1			T142	2		T82	1		T146	1
auto[4026531840:4160749567]	auto[0]	98	1			T13	1		T15	1		T16	1
auto[4026531840:4160749567]	auto[1]	9	1			T162	1		T113	1		T282	2
auto[4160749568:4294967295]	auto[0]	85	1			T4	1		T212	1		T45	1
auto[4160749568:4294967295]	auto[1]	11	1			T142	1		T147	1		T388	1