Unified Coverage Report :: Group Instance : attest_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1554

1

T2

1

T3

1

T4

1

auto[1]

1743

1

T2

1

T4

3

T12

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T13	2		T86	2		T17	1
auto[134217728:268435455]	109	1			T2	1		T16	1		T48	1
auto[268435456:402653183]	104	1			T13	2		T15	1		T49	4
auto[402653184:536870911]	119	1			T16	2		T137	2		T56	1
auto[536870912:671088639]	111	1			T13	3		T15	1		T16	1
auto[671088640:805306367]	113	1			T16	1		T34	1		T219	1
auto[805306368:939524095]	93	1			T13	1		T15	1		T16	1
auto[939524096:1073741823]	100	1			T5	1		T15	1		T16	1
auto[1073741824:1207959551]	100	1			T4	1		T88	1		T213	1
auto[1207959552:1342177279]	97	1			T4	1		T5	1		T88	1
auto[1342177280:1476395007]	102	1			T4	1		T16	1		T88	1
auto[1476395008:1610612735]	104	1			T218	1		T159	1		T144	1
auto[1610612736:1744830463]	85	1			T88	1		T141	1		T50	1
auto[1744830464:1879048191]	94	1			T12	1		T5	1		T15	2
auto[1879048192:2013265919]	98	1			T16	1		T218	1		T60	2
auto[2013265920:2147483647]	92	1			T16	1		T133	1		T212	1
auto[2147483648:2281701375]	89	1			T16	1		T214	1		T106	1
auto[2281701376:2415919103]	96	1			T13	1		T15	1		T214	1
auto[2415919104:2550136831]	96	1			T3	1		T49	3		T44	1
auto[2550136832:2684354559]	96	1			T16	3		T86	1		T212	1
auto[2684354560:2818572287]	109	1			T5	1		T16	2		T86	2
auto[2818572288:2952790015]	105	1			T13	1		T86	1		T218	1
auto[2952790016:3087007743]	96	1			T16	1		T213	1		T212	1
auto[3087007744:3221225471]	96	1			T86	1		T60	1		T106	1
auto[3221225472:3355443199]	110	1			T12	1		T34	1		T48	1
auto[3355443200:3489660927]	124	1			T13	2		T5	1		T16	1
auto[3489660928:3623878655]	113	1			T2	1		T15	1		T16	1
auto[3623878656:3758096383]	117	1			T13	1		T16	1		T88	1
auto[3758096384:3892314111]	108	1			T13	1		T34	1		T49	1
auto[3892314112:4026531839]	86	1			T12	1		T13	2		T218	1
auto[4026531840:4160749567]	122	1			T13	1		T5	1		T15	1
auto[4160749568:4294967295]	102	1			T4	1		T15	1		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T13	1		T86	1		T49	1
auto[0:134217727]	auto[1]	57	1			T13	1		T86	1		T17	1
auto[134217728:268435455]	auto[0]	45	1			T46	1		T107	1		T293	1
auto[134217728:268435455]	auto[1]	64	1			T2	1		T16	1		T48	1
auto[268435456:402653183]	auto[0]	54	1			T13	1		T15	1		T49	3
auto[268435456:402653183]	auto[1]	50	1			T13	1		T49	1		T66	1
auto[402653184:536870911]	auto[0]	55	1			T252	1		T66	2		T58	2
auto[402653184:536870911]	auto[1]	64	1			T16	2		T137	2		T56	1
auto[536870912:671088639]	auto[0]	46	1			T13	1		T15	1		T144	1
auto[536870912:671088639]	auto[1]	65	1			T13	2		T16	1		T49	3
auto[671088640:805306367]	auto[0]	54	1			T219	1		T293	1		T90	1
auto[671088640:805306367]	auto[1]	59	1			T16	1		T34	1		T220	1
auto[805306368:939524095]	auto[0]	46	1			T16	1		T49	1		T66	1
auto[805306368:939524095]	auto[1]	47	1			T13	1		T15	1		T218	1
auto[939524096:1073741823]	auto[0]	41	1			T5	1		T88	1		T22	1
auto[939524096:1073741823]	auto[1]	59	1			T15	1		T16	1		T56	1
auto[1073741824:1207959551]	auto[0]	32	1			T4	1		T88	1		T218	1
auto[1073741824:1207959551]	auto[1]	68	1			T213	1		T49	1		T137	1
auto[1207959552:1342177279]	auto[0]	51	1			T5	1		T212	1		T106	2
auto[1207959552:1342177279]	auto[1]	46	1			T4	1		T88	1		T45	1
auto[1342177280:1476395007]	auto[0]	49	1			T88	1		T212	1		T49	1
auto[1342177280:1476395007]	auto[1]	53	1			T4	1		T16	1		T219	1
auto[1476395008:1610612735]	auto[0]	62	1			T218	1		T159	1		T144	1
auto[1476395008:1610612735]	auto[1]	42	1			T97	1		T58	1		T7	3
auto[1610612736:1744830463]	auto[0]	41	1			T141	1		T50	1		T63	1
auto[1610612736:1744830463]	auto[1]	44	1			T88	1		T261	1		T97	1
auto[1744830464:1879048191]	auto[0]	47	1			T5	1		T15	2		T49	1
auto[1744830464:1879048191]	auto[1]	47	1			T12	1		T16	1		T49	1
auto[1879048192:2013265919]	auto[0]	52	1			T16	1		T218	1		T60	1
auto[1879048192:2013265919]	auto[1]	46	1			T60	1		T106	1		T49	1
auto[2013265920:2147483647]	auto[0]	35	1			T299	1		T63	1		T414	1
auto[2013265920:2147483647]	auto[1]	57	1			T16	1		T133	1		T212	1
auto[2147483648:2281701375]	auto[0]	49	1			T16	1		T50	1		T66	1
auto[2147483648:2281701375]	auto[1]	40	1			T214	1		T106	1		T50	1
auto[2281701376:2415919103]	auto[0]	43	1			T214	1		T218	1		T49	1
auto[2281701376:2415919103]	auto[1]	53	1			T13	1		T15	1		T49	1
auto[2415919104:2550136831]	auto[0]	45	1			T3	1		T49	2		T44	1
auto[2415919104:2550136831]	auto[1]	51	1			T49	1		T261	1		T122	1
auto[2550136832:2684354559]	auto[0]	52	1			T16	1		T212	1		T106	1
auto[2550136832:2684354559]	auto[1]	44	1			T16	2		T86	1		T60	1
auto[2684354560:2818572287]	auto[0]	59	1			T5	1		T16	1		T86	1
auto[2684354560:2818572287]	auto[1]	50	1			T16	1		T86	1		T88	1
auto[2818572288:2952790015]	auto[0]	53	1			T13	1		T86	1		T218	1
auto[2818572288:2952790015]	auto[1]	52	1			T216	1		T18	1		T281	1
auto[2952790016:3087007743]	auto[0]	41	1			T213	1		T212	1		T49	1
auto[2952790016:3087007743]	auto[1]	55	1			T16	1		T41	1		T49	1
auto[3087007744:3221225471]	auto[0]	45	1			T86	1		T49	1		T139	1
auto[3087007744:3221225471]	auto[1]	51	1			T60	1		T106	1		T49	1
auto[3221225472:3355443199]	auto[0]	43	1			T34	1		T106	1		T220	1
auto[3221225472:3355443199]	auto[1]	67	1			T12	1		T48	1		T106	1
auto[3355443200:3489660927]	auto[0]	62	1			T13	1		T5	1		T218	1
auto[3355443200:3489660927]	auto[1]	62	1			T13	1		T16	1		T217	1
auto[3489660928:3623878655]	auto[0]	47	1			T2	1		T15	1		T16	1
auto[3489660928:3623878655]	auto[1]	66	1			T49	1		T50	3		T246	1
auto[3623878656:3758096383]	auto[0]	52	1			T212	1		T49	1		T137	1
auto[3623878656:3758096383]	auto[1]	65	1			T13	1		T16	1		T88	1
auto[3758096384:3892314111]	auto[0]	55	1			T159	1		T256	1		T72	1
auto[3758096384:3892314111]	auto[1]	53	1			T13	1		T34	1		T49	1
auto[3892314112:4026531839]	auto[0]	44	1			T13	1		T60	1		T50	1
auto[3892314112:4026531839]	auto[1]	42	1			T12	1		T13	1		T218	1
auto[4026531840:4160749567]	auto[0]	51	1			T16	1		T44	1		T72	1
auto[4026531840:4160749567]	auto[1]	71	1			T13	1		T5	1		T15	1
auto[4160749568:4294967295]	auto[0]	49	1			T15	1		T34	1		T88	1
auto[4160749568:4294967295]	auto[1]	53	1			T4	1		T88	1		T41	1