Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6806

1

T2

11

T3

2

T4

8

auto[1]

319

1

T137

2

T142

6

T144

19

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2864	1			T2	4		T3	1		T4	3
auto[134217728:268435455]	163	1			T15	1		T86	1		T212	1
auto[268435456:402653183]	163	1			T2	1		T13	1		T16	1
auto[402653184:536870911]	130	1			T212	1		T106	1		T49	3
auto[536870912:671088639]	156	1			T13	1		T212	1		T214	1
auto[671088640:805306367]	128	1			T13	1		T16	1		T218	1
auto[805306368:939524095]	144	1			T16	1		T88	1		T212	1
auto[939524096:1073741823]	145	1			T13	1		T133	1		T218	1
auto[1073741824:1207959551]	130	1			T13	1		T15	2		T16	1
auto[1207959552:1342177279]	130	1			T2	1		T13	1		T212	1
auto[1342177280:1476395007]	144	1			T86	1		T34	1		T49	3
auto[1476395008:1610612735]	139	1			T13	4		T16	2		T86	1
auto[1610612736:1744830463]	132	1			T13	1		T15	2		T16	1
auto[1744830464:1879048191]	130	1			T2	1		T13	2		T86	1
auto[1879048192:2013265919]	130	1			T2	1		T13	1		T218	2
auto[2013265920:2147483647]	133	1			T4	1		T13	1		T15	1
auto[2147483648:2281701375]	133	1			T12	1		T13	1		T16	1
auto[2281701376:2415919103]	135	1			T15	1		T16	1		T86	1
auto[2415919104:2550136831]	138	1			T86	1		T212	2		T106	1
auto[2550136832:2684354559]	116	1			T13	1		T86	1		T48	1
auto[2684354560:2818572287]	151	1			T4	2		T13	1		T16	3
auto[2818572288:2952790015]	127	1			T3	1		T12	1		T219	1
auto[2952790016:3087007743]	147	1			T4	1		T13	1		T16	2
auto[3087007744:3221225471]	136	1			T13	2		T212	1		T216	1
auto[3221225472:3355443199]	127	1			T2	1		T13	1		T5	1
auto[3355443200:3489660927]	135	1			T16	1		T59	1		T217	1
auto[3489660928:3623878655]	162	1			T13	2		T16	1		T86	1
auto[3623878656:3758096383]	131	1			T2	1		T4	1		T13	1
auto[3758096384:3892314111]	100	1			T2	1		T212	1		T218	2
auto[3892314112:4026531839]	131	1			T13	2		T16	1		T86	1
auto[4026531840:4160749567]	140	1			T88	1		T49	1		T44	1
auto[4160749568:4294967295]	155	1			T12	1		T13	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2856	1			T2	4		T3	1		T4	3
auto[0:134217727]	auto[1]	8	1			T144	1		T145	1		T110	1
auto[134217728:268435455]	auto[0]	155	1			T15	1		T86	1		T212	1
auto[134217728:268435455]	auto[1]	8	1			T142	1		T144	1		T113	1
auto[268435456:402653183]	auto[0]	149	1			T2	1		T13	1		T16	1
auto[268435456:402653183]	auto[1]	14	1			T144	2		T283	1		T282	1
auto[402653184:536870911]	auto[0]	120	1			T212	1		T106	1		T49	3
auto[402653184:536870911]	auto[1]	10	1			T142	1		T162	2		T408	2
auto[536870912:671088639]	auto[0]	147	1			T13	1		T212	1		T214	1
auto[536870912:671088639]	auto[1]	9	1			T147	1		T408	1		T410	1
auto[671088640:805306367]	auto[0]	121	1			T13	1		T16	1		T218	1
auto[671088640:805306367]	auto[1]	7	1			T137	1		T318	1		T283	1
auto[805306368:939524095]	auto[0]	133	1			T16	1		T88	1		T212	1
auto[805306368:939524095]	auto[1]	11	1			T144	1		T388	1		T415	1
auto[939524096:1073741823]	auto[0]	135	1			T13	1		T133	1		T218	1
auto[939524096:1073741823]	auto[1]	10	1			T162	2		T147	1		T331	1
auto[1073741824:1207959551]	auto[0]	124	1			T13	1		T15	2		T16	1
auto[1073741824:1207959551]	auto[1]	6	1			T144	1		T147	1		T283	1
auto[1207959552:1342177279]	auto[0]	123	1			T2	1		T13	1		T212	1
auto[1207959552:1342177279]	auto[1]	7	1			T144	1		T113	1		T147	1
auto[1342177280:1476395007]	auto[0]	135	1			T86	1		T34	1		T49	3
auto[1342177280:1476395007]	auto[1]	9	1			T144	3		T282	1		T415	1
auto[1476395008:1610612735]	auto[0]	127	1			T13	4		T16	2		T86	1
auto[1476395008:1610612735]	auto[1]	12	1			T82	1		T145	1		T146	1
auto[1610612736:1744830463]	auto[0]	117	1			T13	1		T15	2		T16	1
auto[1610612736:1744830463]	auto[1]	15	1			T144	1		T162	1		T147	3
auto[1744830464:1879048191]	auto[0]	117	1			T2	1		T13	2		T86	1
auto[1744830464:1879048191]	auto[1]	13	1			T113	1		T146	2		T147	1
auto[1879048192:2013265919]	auto[0]	117	1			T2	1		T13	1		T218	2
auto[1879048192:2013265919]	auto[1]	13	1			T162	1		T82	1		T318	1
auto[2013265920:2147483647]	auto[0]	118	1			T4	1		T13	1		T15	1
auto[2013265920:2147483647]	auto[1]	15	1			T144	1		T110	1		T147	1
auto[2147483648:2281701375]	auto[0]	122	1			T12	1		T13	1		T16	1
auto[2147483648:2281701375]	auto[1]	11	1			T145	1		T113	1		T147	2
auto[2281701376:2415919103]	auto[0]	120	1			T15	1		T16	1		T86	1
auto[2281701376:2415919103]	auto[1]	15	1			T82	1		T113	2		T149	1
auto[2415919104:2550136831]	auto[0]	130	1			T86	1		T212	2		T106	1
auto[2415919104:2550136831]	auto[1]	8	1			T144	2		T110	1		T387	1
auto[2550136832:2684354559]	auto[0]	107	1			T13	1		T86	1		T48	1
auto[2550136832:2684354559]	auto[1]	9	1			T146	1		T283	1		T408	1
auto[2684354560:2818572287]	auto[0]	137	1			T4	2		T13	1		T16	3
auto[2684354560:2818572287]	auto[1]	14	1			T162	1		T82	1		T146	1
auto[2818572288:2952790015]	auto[0]	114	1			T3	1		T12	1		T219	1
auto[2818572288:2952790015]	auto[1]	13	1			T142	1		T144	2		T145	1
auto[2952790016:3087007743]	auto[0]	133	1			T4	1		T13	1		T16	2
auto[2952790016:3087007743]	auto[1]	14	1			T142	1		T144	1		T149	1
auto[3087007744:3221225471]	auto[0]	128	1			T13	2		T212	1		T216	1
auto[3087007744:3221225471]	auto[1]	8	1			T137	1		T386	1		T410	2
auto[3221225472:3355443199]	auto[0]	119	1			T2	1		T13	1		T5	1
auto[3221225472:3355443199]	auto[1]	8	1			T147	1		T318	1		T282	1
auto[3355443200:3489660927]	auto[0]	127	1			T16	1		T59	1		T217	1
auto[3355443200:3489660927]	auto[1]	8	1			T142	1		T146	1		T408	2
auto[3489660928:3623878655]	auto[0]	155	1			T13	2		T16	1		T86	1
auto[3489660928:3623878655]	auto[1]	7	1			T282	1		T415	1		T245	1
auto[3623878656:3758096383]	auto[0]	120	1			T2	1		T4	1		T13	1
auto[3623878656:3758096383]	auto[1]	11	1			T144	1		T145	2		T113	1
auto[3758096384:3892314111]	auto[0]	96	1			T2	1		T212	1		T218	2
auto[3758096384:3892314111]	auto[1]	4	1			T147	1		T386	1		T387	1
auto[3892314112:4026531839]	auto[0]	122	1			T13	2		T16	1		T86	1
auto[3892314112:4026531839]	auto[1]	9	1			T142	1		T144	1		T415	2
auto[4026531840:4160749567]	auto[0]	136	1			T88	1		T49	1		T44	1
auto[4026531840:4160749567]	auto[1]	4	1			T146	1		T147	1		T291	1
auto[4160749568:4294967295]	auto[0]	146	1			T12	1		T13	1		T16	1
auto[4160749568:4294967295]	auto[1]	9	1			T145	1		T146	1		T149	1