Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4462

1

T4

4

T12

4

T13

18

auto[1]

2134

1

T2

4

T3

2

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	196	1			T5	2		T59	2		T218	2
auto[134217728:268435455]	186	1			T4	2		T13	2		T15	2
auto[268435456:402653183]	236	1			T5	2		T16	2		T34	2
auto[402653184:536870911]	188	1			T2	2		T16	2		T48	2
auto[536870912:671088639]	220	1			T13	2		T15	4		T34	2
auto[671088640:805306367]	238	1			T5	2		T34	2		T88	2
auto[805306368:939524095]	198	1			T15	4		T16	2		T219	2
auto[939524096:1073741823]	190	1			T5	4		T88	2		T49	2
auto[1073741824:1207959551]	224	1			T16	2		T86	2		T106	2
auto[1207959552:1342177279]	216	1			T4	2		T86	2		T60	2
auto[1342177280:1476395007]	232	1			T12	2		T13	4		T16	4
auto[1476395008:1610612735]	200	1			T4	2		T15	2		T217	2
auto[1610612736:1744830463]	228	1			T13	8		T16	2		T212	2
auto[1744830464:1879048191]	198	1			T5	2		T88	2		T49	2
auto[1879048192:2013265919]	210	1			T15	2		T88	2		T41	2
auto[2013265920:2147483647]	212	1			T12	2		T16	4		T34	2
auto[2147483648:2281701375]	212	1			T218	2		T106	2		T219	2
auto[2281701376:2415919103]	218	1			T16	2		T220	2		T49	4
auto[2415919104:2550136831]	176	1			T86	2		T49	2		T137	2
auto[2550136832:2684354559]	210	1			T2	2		T16	2		T86	4
auto[2684354560:2818572287]	236	1			T13	6		T16	2		T17	2
auto[2818572288:2952790015]	184	1			T15	2		T34	2		T212	2
auto[2952790016:3087007743]	192	1			T3	2		T16	2		T133	2
auto[3087007744:3221225471]	172	1			T13	2		T49	4		T142	2
auto[3221225472:3355443199]	196	1			T4	2		T16	2		T49	8
auto[3355443200:3489660927]	188	1			T12	2		T13	4		T16	4
auto[3489660928:3623878655]	210	1			T13	4		T16	4		T217	2
auto[3623878656:3758096383]	238	1			T16	4		T88	2		T214	2
auto[3758096384:3892314111]	212	1			T15	2		T48	2		T218	2
auto[3892314112:4026531839]	200	1			T49	6		T22	6		T55	2
auto[4026531840:4160749567]	202	1			T13	2		T15	2		T86	2
auto[4160749568:4294967295]	178	1			T16	2		T60	2		T106	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	120	1			T5	2		T106	4		T50	2
auto[0:134217727]	auto[1]	76	1			T59	2		T218	2		T41	2
auto[134217728:268435455]	auto[0]	112	1			T4	2		T15	2		T16	2
auto[134217728:268435455]	auto[1]	74	1			T13	2		T106	2		T37	2
auto[268435456:402653183]	auto[0]	158	1			T5	2		T16	2		T34	2
auto[268435456:402653183]	auto[1]	78	1			T88	2		T49	2		T36	2
auto[402653184:536870911]	auto[0]	124	1			T16	2		T48	2		T218	2
auto[402653184:536870911]	auto[1]	64	1			T2	2		T49	2		T101	2
auto[536870912:671088639]	auto[0]	166	1			T15	4		T34	2		T49	2
auto[536870912:671088639]	auto[1]	54	1			T13	2		T145	2		T414	2
auto[671088640:805306367]	auto[0]	152	1			T34	2		T88	2		T218	2
auto[671088640:805306367]	auto[1]	86	1			T5	2		T212	2		T361	2
auto[805306368:939524095]	auto[0]	124	1			T15	2		T16	2		T49	2
auto[805306368:939524095]	auto[1]	74	1			T15	2		T219	2		T216	2
auto[939524096:1073741823]	auto[0]	132	1			T5	4		T49	2		T22	2
auto[939524096:1073741823]	auto[1]	58	1			T88	2		T107	2		T42	2
auto[1073741824:1207959551]	auto[0]	160	1			T16	2		T106	2		T49	4
auto[1073741824:1207959551]	auto[1]	64	1			T86	2		T252	2		T256	2
auto[1207959552:1342177279]	auto[0]	136	1			T4	2		T86	2		T60	2
auto[1207959552:1342177279]	auto[1]	80	1			T52	2		T50	2		T412	2
auto[1342177280:1476395007]	auto[0]	156	1			T13	2		T16	4		T88	2
auto[1342177280:1476395007]	auto[1]	76	1			T12	2		T13	2		T162	2
auto[1476395008:1610612735]	auto[0]	148	1			T15	2		T217	2		T106	2
auto[1476395008:1610612735]	auto[1]	52	1			T4	2		T261	2		T122	4
auto[1610612736:1744830463]	auto[0]	168	1			T13	4		T16	2		T212	2
auto[1610612736:1744830463]	auto[1]	60	1			T13	4		T106	2		T252	2
auto[1744830464:1879048191]	auto[0]	126	1			T5	2		T88	2		T50	2
auto[1744830464:1879048191]	auto[1]	72	1			T49	2		T142	2		T24	2
auto[1879048192:2013265919]	auto[0]	130	1			T15	2		T88	2		T41	2
auto[1879048192:2013265919]	auto[1]	80	1			T142	2		T24	2		T113	2
auto[2013265920:2147483647]	auto[0]	142	1			T12	2		T16	4		T49	2
auto[2013265920:2147483647]	auto[1]	70	1			T34	2		T106	2		T52	2
auto[2147483648:2281701375]	auto[0]	152	1			T218	2		T219	2		T141	4
auto[2147483648:2281701375]	auto[1]	60	1			T106	2		T252	2		T66	2
auto[2281701376:2415919103]	auto[0]	148	1			T16	2		T49	4		T159	2
auto[2281701376:2415919103]	auto[1]	70	1			T220	2		T107	2		T122	4
auto[2415919104:2550136831]	auto[0]	140	1			T86	2		T49	2		T137	2
auto[2415919104:2550136831]	auto[1]	36	1			T145	2		T413	2		T53	2
auto[2550136832:2684354559]	auto[0]	130	1			T16	2		T86	4		T218	2
auto[2550136832:2684354559]	auto[1]	80	1			T2	2		T212	2		T220	2
auto[2684354560:2818572287]	auto[0]	166	1			T13	4		T213	2		T49	2
auto[2684354560:2818572287]	auto[1]	70	1			T13	2		T16	2		T17	2
auto[2818572288:2952790015]	auto[0]	128	1			T15	2		T34	2		T49	4
auto[2818572288:2952790015]	auto[1]	56	1			T212	2		T220	2		T122	2
auto[2952790016:3087007743]	auto[0]	130	1			T16	2		T133	2		T106	2
auto[2952790016:3087007743]	auto[1]	62	1			T3	2		T213	2		T56	2
auto[3087007744:3221225471]	auto[0]	112	1			T49	2		T142	2		T66	2
auto[3087007744:3221225471]	auto[1]	60	1			T13	2		T49	2		T50	2
auto[3221225472:3355443199]	auto[0]	130	1			T16	2		T49	6		T144	2
auto[3221225472:3355443199]	auto[1]	66	1			T4	2		T49	2		T55	2
auto[3355443200:3489660927]	auto[0]	134	1			T12	2		T13	4		T16	4
auto[3355443200:3489660927]	auto[1]	54	1			T88	2		T212	2		T416	2
auto[3489660928:3623878655]	auto[0]	134	1			T13	2		T16	2		T217	2
auto[3489660928:3623878655]	auto[1]	76	1			T13	2		T16	2		T66	2
auto[3623878656:3758096383]	auto[0]	160	1			T88	2		T214	2		T218	2
auto[3623878656:3758096383]	auto[1]	78	1			T16	4		T60	2		T122	2
auto[3758096384:3892314111]	auto[0]	144	1			T48	2		T218	2		T49	8
auto[3758096384:3892314111]	auto[1]	68	1			T15	2		T41	2		T141	2
auto[3892314112:4026531839]	auto[0]	146	1			T49	6		T22	4		T55	2
auto[3892314112:4026531839]	auto[1]	54	1			T22	2		T46	2		T417	2
auto[4026531840:4160749567]	auto[0]	150	1			T13	2		T15	2		T86	2
auto[4026531840:4160749567]	auto[1]	52	1			T162	2		T252	2		T107	2
auto[4160749568:4294967295]	auto[0]	104	1			T60	2		T141	2		T144	2
auto[4160749568:4294967295]	auto[1]	74	1			T16	2		T106	2		T66	2