Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 97.95 98.53 100.00 99.02 98.41 91.07


Total test records in report: 1079
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4294080339 Jul 24 06:02:30 PM PDT 24 Jul 24 06:02:31 PM PDT 24 523438373 ps
T1008 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2163781908 Jul 24 06:02:55 PM PDT 24 Jul 24 06:02:57 PM PDT 24 17350362 ps
T1009 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1536537293 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:08 PM PDT 24 58602004 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.445607252 Jul 24 06:02:29 PM PDT 24 Jul 24 06:02:39 PM PDT 24 2671563447 ps
T1011 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.392334014 Jul 24 06:03:08 PM PDT 24 Jul 24 06:03:10 PM PDT 24 135042077 ps
T1012 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1419544825 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:01 PM PDT 24 26192880 ps
T1013 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.433401892 Jul 24 06:02:47 PM PDT 24 Jul 24 06:02:49 PM PDT 24 26930123 ps
T1014 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3572350298 Jul 24 06:02:33 PM PDT 24 Jul 24 06:02:38 PM PDT 24 304562076 ps
T1015 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3122965947 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:06 PM PDT 24 8693071 ps
T1016 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.779617311 Jul 24 06:03:13 PM PDT 24 Jul 24 06:03:14 PM PDT 24 32685311 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.888048397 Jul 24 06:02:41 PM PDT 24 Jul 24 06:02:49 PM PDT 24 349220142 ps
T1018 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3066745990 Jul 24 06:02:57 PM PDT 24 Jul 24 06:03:00 PM PDT 24 35240797 ps
T1019 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.418978263 Jul 24 06:02:54 PM PDT 24 Jul 24 06:02:59 PM PDT 24 525037319 ps
T1020 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.283710326 Jul 24 06:02:39 PM PDT 24 Jul 24 06:02:45 PM PDT 24 255651572 ps
T1021 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.376362919 Jul 24 06:02:55 PM PDT 24 Jul 24 06:02:56 PM PDT 24 62697637 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2365025507 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:05 PM PDT 24 247146210 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3630111264 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:09 PM PDT 24 745432751 ps
T1024 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1039125709 Jul 24 06:02:45 PM PDT 24 Jul 24 06:02:58 PM PDT 24 1280703726 ps
T1025 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2818468207 Jul 24 06:03:03 PM PDT 24 Jul 24 06:03:05 PM PDT 24 46640995 ps
T1026 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2377532975 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:01 PM PDT 24 16321770 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1070833455 Jul 24 06:02:24 PM PDT 24 Jul 24 06:02:26 PM PDT 24 138361816 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2405841748 Jul 24 06:02:34 PM PDT 24 Jul 24 06:02:48 PM PDT 24 1014414805 ps
T1029 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1015461052 Jul 24 06:03:04 PM PDT 24 Jul 24 06:03:05 PM PDT 24 60723601 ps
T187 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1783997591 Jul 24 06:02:59 PM PDT 24 Jul 24 06:03:07 PM PDT 24 358191400 ps
T1030 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1102103811 Jul 24 06:03:01 PM PDT 24 Jul 24 06:03:07 PM PDT 24 490715896 ps
T184 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2201404733 Jul 24 06:03:01 PM PDT 24 Jul 24 06:03:06 PM PDT 24 128280514 ps
T1031 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1133123298 Jul 24 06:02:47 PM PDT 24 Jul 24 06:02:48 PM PDT 24 7558682 ps
T1032 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.974149124 Jul 24 06:02:59 PM PDT 24 Jul 24 06:03:00 PM PDT 24 146360450 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.412862930 Jul 24 06:02:35 PM PDT 24 Jul 24 06:02:38 PM PDT 24 516480403 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.765172432 Jul 24 06:02:33 PM PDT 24 Jul 24 06:02:34 PM PDT 24 15768764 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3929619308 Jul 24 06:02:24 PM PDT 24 Jul 24 06:02:28 PM PDT 24 1168436382 ps
T1036 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1987343289 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:07 PM PDT 24 41235333 ps
T179 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1335836312 Jul 24 06:02:42 PM PDT 24 Jul 24 06:02:45 PM PDT 24 94890160 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1854364921 Jul 24 06:02:26 PM PDT 24 Jul 24 06:02:27 PM PDT 24 495421214 ps
T1038 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1875239638 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:07 PM PDT 24 94426564 ps
T1039 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3759735130 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:01 PM PDT 24 33743165 ps
T1040 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3022621467 Jul 24 06:02:28 PM PDT 24 Jul 24 06:02:30 PM PDT 24 71805618 ps
T1041 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.41425492 Jul 24 06:02:49 PM PDT 24 Jul 24 06:03:02 PM PDT 24 430227582 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2580714132 Jul 24 06:02:29 PM PDT 24 Jul 24 06:02:30 PM PDT 24 34730162 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2501542649 Jul 24 06:02:35 PM PDT 24 Jul 24 06:02:50 PM PDT 24 415391829 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3397130034 Jul 24 06:02:30 PM PDT 24 Jul 24 06:02:31 PM PDT 24 38410419 ps
T1045 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3745556567 Jul 24 06:02:33 PM PDT 24 Jul 24 06:02:34 PM PDT 24 13990757 ps
T1046 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3105388379 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:07 PM PDT 24 12377846 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3385744689 Jul 24 06:02:30 PM PDT 24 Jul 24 06:02:32 PM PDT 24 17516017 ps
T1048 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.33779285 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:07 PM PDT 24 33497187 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4252948560 Jul 24 06:02:31 PM PDT 24 Jul 24 06:02:33 PM PDT 24 360109708 ps
T1050 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3916896633 Jul 24 06:02:35 PM PDT 24 Jul 24 06:02:36 PM PDT 24 48673143 ps
T1051 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.167390045 Jul 24 06:02:31 PM PDT 24 Jul 24 06:02:33 PM PDT 24 41548751 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2084469038 Jul 24 06:02:24 PM PDT 24 Jul 24 06:02:27 PM PDT 24 68495209 ps
T1053 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3659073930 Jul 24 06:03:09 PM PDT 24 Jul 24 06:03:12 PM PDT 24 250394714 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3365136458 Jul 24 06:02:56 PM PDT 24 Jul 24 06:02:58 PM PDT 24 23146382 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1830624478 Jul 24 06:02:34 PM PDT 24 Jul 24 06:02:36 PM PDT 24 177243428 ps
T1056 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3186079661 Jul 24 06:02:40 PM PDT 24 Jul 24 06:02:41 PM PDT 24 30133860 ps
T1057 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.678681857 Jul 24 06:03:08 PM PDT 24 Jul 24 06:03:09 PM PDT 24 41875920 ps
T1058 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4237103811 Jul 24 06:02:44 PM PDT 24 Jul 24 06:02:46 PM PDT 24 77078544 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.760647859 Jul 24 06:02:53 PM PDT 24 Jul 24 06:02:57 PM PDT 24 123509654 ps
T1060 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2735492620 Jul 24 06:02:51 PM PDT 24 Jul 24 06:02:52 PM PDT 24 34291772 ps
T1061 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.370366556 Jul 24 06:02:24 PM PDT 24 Jul 24 06:02:27 PM PDT 24 283462767 ps
T1062 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2166985462 Jul 24 06:02:49 PM PDT 24 Jul 24 06:02:52 PM PDT 24 339516083 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.690933965 Jul 24 06:02:32 PM PDT 24 Jul 24 06:02:46 PM PDT 24 790167701 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.852418274 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:04 PM PDT 24 993099997 ps
T1065 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4133606972 Jul 24 06:02:50 PM PDT 24 Jul 24 06:02:54 PM PDT 24 323803533 ps
T173 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2710204853 Jul 24 06:02:40 PM PDT 24 Jul 24 06:02:44 PM PDT 24 108993165 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2610866522 Jul 24 06:02:50 PM PDT 24 Jul 24 06:02:51 PM PDT 24 7544336 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3176255144 Jul 24 06:02:57 PM PDT 24 Jul 24 06:03:08 PM PDT 24 369019382 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3847070846 Jul 24 06:02:54 PM PDT 24 Jul 24 06:02:56 PM PDT 24 34496789 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1417171682 Jul 24 06:02:31 PM PDT 24 Jul 24 06:02:33 PM PDT 24 70184036 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2387455866 Jul 24 06:02:32 PM PDT 24 Jul 24 06:02:36 PM PDT 24 311693473 ps
T1071 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1159339087 Jul 24 06:02:26 PM PDT 24 Jul 24 06:02:30 PM PDT 24 108856681 ps
T1072 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3704571128 Jul 24 06:03:00 PM PDT 24 Jul 24 06:03:05 PM PDT 24 166429107 ps
T1073 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2166514309 Jul 24 06:02:59 PM PDT 24 Jul 24 06:03:00 PM PDT 24 15187506 ps
T174 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3395731888 Jul 24 06:02:30 PM PDT 24 Jul 24 06:02:40 PM PDT 24 1175776342 ps
T1074 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4114885528 Jul 24 06:02:24 PM PDT 24 Jul 24 06:02:27 PM PDT 24 89847193 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3788028817 Jul 24 06:02:51 PM PDT 24 Jul 24 06:02:54 PM PDT 24 210442804 ps
T176 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3401039482 Jul 24 06:03:05 PM PDT 24 Jul 24 06:03:11 PM PDT 24 147134385 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.893458783 Jul 24 06:02:47 PM PDT 24 Jul 24 06:02:48 PM PDT 24 8694853 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2591932628 Jul 24 06:02:33 PM PDT 24 Jul 24 06:02:34 PM PDT 24 50373473 ps
T1078 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.220402010 Jul 24 06:02:58 PM PDT 24 Jul 24 06:02:59 PM PDT 24 72823490 ps
T1079 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4182420013 Jul 24 06:02:50 PM PDT 24 Jul 24 06:02:52 PM PDT 24 33562393 ps

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.917810397
Short name T13
Test name
Test status
Simulation time 403368589 ps
CPU time 13.29 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:04:05 PM PDT 24
Peak memory 222348 kb
Host smart-94b7014e-f7c1-4cef-a37f-435feef5dd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917810397 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.917810397
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3471153524
Short name T49
Test name
Test status
Simulation time 2908162372 ps
CPU time 71.48 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:07:17 PM PDT 24
Peak memory 221508 kb
Host smart-69c9d774-2b3a-44b9-ba7f-81f37c9ec646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471153524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3471153524
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2568249382
Short name T16
Test name
Test status
Simulation time 1265297861 ps
CPU time 30.82 seconds
Started Jul 24 07:03:50 PM PDT 24
Finished Jul 24 07:04:21 PM PDT 24
Peak memory 215100 kb
Host smart-39a23c90-3bd5-43c1-a3dc-083e8285bedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568249382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2568249382
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1487464781
Short name T10
Test name
Test status
Simulation time 1593684775 ps
CPU time 5.65 seconds
Started Jul 24 07:04:14 PM PDT 24
Finished Jul 24 07:04:20 PM PDT 24
Peak memory 237432 kb
Host smart-7d47d863-4e9e-41f0-b2e7-27c1a03cee03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487464781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1487464781
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.594144183
Short name T121
Test name
Test status
Simulation time 401088777 ps
CPU time 14.08 seconds
Started Jul 24 06:03:04 PM PDT 24
Finished Jul 24 06:03:19 PM PDT 24
Peak memory 214684 kb
Host smart-31d5f4d2-4b0d-4196-be06-0106837d4b6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594144183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.594144183
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1828600715
Short name T8
Test name
Test status
Simulation time 267304442 ps
CPU time 5.21 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 214396 kb
Host smart-14f6acae-81f7-4cea-8000-05bef10e685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828600715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1828600715
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.859515237
Short name T43
Test name
Test status
Simulation time 2628461406 ps
CPU time 33.55 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 215736 kb
Host smart-f4d930cc-dbcc-4fc2-83c4-963c23771e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859515237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.859515237
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4232545453
Short name T144
Test name
Test status
Simulation time 249218984 ps
CPU time 14.1 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:46 PM PDT 24
Peak memory 215628 kb
Host smart-95f2c426-b4b4-4ec2-8d42-cd945573a242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232545453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4232545453
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2470839911
Short name T252
Test name
Test status
Simulation time 48839508 ps
CPU time 2.71 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:48 PM PDT 24
Peak memory 205808 kb
Host smart-f5de3fdf-2118-4fac-9d81-4cf366d72f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470839911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2470839911
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1783304938
Short name T122
Test name
Test status
Simulation time 2265326185 ps
CPU time 28.84 seconds
Started Jul 24 07:04:32 PM PDT 24
Finished Jul 24 07:05:01 PM PDT 24
Peak memory 222568 kb
Host smart-cd494e03-3902-496a-ba2b-d85146c34100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783304938 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1783304938
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2093980132
Short name T147
Test name
Test status
Simulation time 753096355 ps
CPU time 10.58 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 215420 kb
Host smart-0da4b714-bda0-4be5-ab59-0f57b04a93cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093980132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2093980132
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1041285947
Short name T33
Test name
Test status
Simulation time 241398559 ps
CPU time 2.85 seconds
Started Jul 24 07:04:57 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 210384 kb
Host smart-47b6c951-682b-43da-a5e4-1ab57a490af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041285947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1041285947
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2141515046
Short name T142
Test name
Test status
Simulation time 389837558 ps
CPU time 19.72 seconds
Started Jul 24 07:05:02 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 214488 kb
Host smart-8ea0d540-0f64-4406-b4e9-30a300db0f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141515046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2141515046
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.204654280
Short name T50
Test name
Test status
Simulation time 2570540274 ps
CPU time 26.89 seconds
Started Jul 24 07:05:49 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 215664 kb
Host smart-9d45cfa9-faf0-4e9c-83bf-33d648a63043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204654280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.204654280
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2602800215
Short name T96
Test name
Test status
Simulation time 428402567 ps
CPU time 4.1 seconds
Started Jul 24 07:05:50 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 214068 kb
Host smart-4a37585f-da44-4731-85fd-0a34b548df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602800215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2602800215
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2421966745
Short name T119
Test name
Test status
Simulation time 76208416 ps
CPU time 3.77 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:38 PM PDT 24
Peak memory 222872 kb
Host smart-f2b6ed85-d7c5-4ad6-82a7-3b4fc5cf66b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421966745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2421966745
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2319912020
Short name T162
Test name
Test status
Simulation time 568160845 ps
CPU time 7.53 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:08 PM PDT 24
Peak memory 214060 kb
Host smart-8cc772f3-ce42-4749-91ee-30f1ff3fb39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319912020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2319912020
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3009249196
Short name T145
Test name
Test status
Simulation time 108234842 ps
CPU time 5.22 seconds
Started Jul 24 07:05:17 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 214420 kb
Host smart-da7e9f4d-f85d-4db9-a835-dd99585e3fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009249196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3009249196
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3525809765
Short name T22
Test name
Test status
Simulation time 8921687192 ps
CPU time 52.66 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 222288 kb
Host smart-818f3c5c-e7f0-443d-89a5-b6e7229c0231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525809765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3525809765
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3208712078
Short name T282
Test name
Test status
Simulation time 272497301 ps
CPU time 7.93 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 214856 kb
Host smart-23dbeb75-2f3f-47d6-8325-b881a318d896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208712078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3208712078
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1350716042
Short name T7
Test name
Test status
Simulation time 1034204614 ps
CPU time 35.74 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:59 PM PDT 24
Peak memory 221212 kb
Host smart-b13cd173-1338-43b8-9805-1877a823d549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350716042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1350716042
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3533299412
Short name T2
Test name
Test status
Simulation time 100650615 ps
CPU time 4.8 seconds
Started Jul 24 07:05:02 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 208600 kb
Host smart-77f3a72c-da64-4b17-a593-c2ca41727387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533299412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3533299412
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3120449895
Short name T408
Test name
Test status
Simulation time 883689266 ps
CPU time 20.32 seconds
Started Jul 24 07:03:46 PM PDT 24
Finished Jul 24 07:04:07 PM PDT 24
Peak memory 214620 kb
Host smart-378940f4-dce2-4369-aa91-00890f550034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120449895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3120449895
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4205149353
Short name T37
Test name
Test status
Simulation time 57946916 ps
CPU time 1.86 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:07 PM PDT 24
Peak memory 208316 kb
Host smart-840f35c0-98a6-4ad9-88b9-3b0b13ba04e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205149353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4205149353
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.741453485
Short name T164
Test name
Test status
Simulation time 107604252 ps
CPU time 5.38 seconds
Started Jul 24 07:05:09 PM PDT 24
Finished Jul 24 07:05:15 PM PDT 24
Peak memory 222436 kb
Host smart-71d493a6-5610-4c86-ad74-85c897be1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741453485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.741453485
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4234560987
Short name T70
Test name
Test status
Simulation time 1068945021 ps
CPU time 25.96 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:27 PM PDT 24
Peak memory 215568 kb
Host smart-ba95fa09-cc6f-4c62-a636-139c88b57a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234560987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4234560987
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3979994739
Short name T953
Test name
Test status
Simulation time 111260607 ps
CPU time 2.05 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 214564 kb
Host smart-bff083b5-cffd-4e8e-8dd4-4a1e704f143c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979994739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3979994739
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.617069775
Short name T376
Test name
Test status
Simulation time 106511106 ps
CPU time 3.88 seconds
Started Jul 24 07:04:27 PM PDT 24
Finished Jul 24 07:04:32 PM PDT 24
Peak memory 209376 kb
Host smart-ad0f5c01-72fa-4199-b414-332b3a8345c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617069775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.617069775
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1729410762
Short name T61
Test name
Test status
Simulation time 1005957829 ps
CPU time 4.08 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:08 PM PDT 24
Peak memory 221376 kb
Host smart-dabadd89-b33e-4b91-b031-c337c2207735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729410762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1729410762
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2287029453
Short name T363
Test name
Test status
Simulation time 460105905 ps
CPU time 12.92 seconds
Started Jul 24 07:05:25 PM PDT 24
Finished Jul 24 07:05:38 PM PDT 24
Peak memory 215252 kb
Host smart-e9295dba-502f-43d3-b1a3-06240f69ca39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287029453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2287029453
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2441543359
Short name T88
Test name
Test status
Simulation time 1814492861 ps
CPU time 14.86 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 222452 kb
Host smart-d6e08bb9-0ed0-48b7-851c-72bb8d27e196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441543359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2441543359
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1350629673
Short name T856
Test name
Test status
Simulation time 181143827 ps
CPU time 4.77 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 214092 kb
Host smart-ce4e069d-79e6-49b9-ba6d-94648f235817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350629673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1350629673
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2241666487
Short name T21
Test name
Test status
Simulation time 162188085 ps
CPU time 2.11 seconds
Started Jul 24 07:05:37 PM PDT 24
Finished Jul 24 07:05:40 PM PDT 24
Peak memory 209304 kb
Host smart-1ad49616-364c-4384-a940-b6b30a6c29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241666487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2241666487
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3654816561
Short name T270
Test name
Test status
Simulation time 38616043 ps
CPU time 2.26 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:06 PM PDT 24
Peak memory 214492 kb
Host smart-b411a77c-0146-4cd8-9763-c8b189c53ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654816561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3654816561
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1303218655
Short name T227
Test name
Test status
Simulation time 4439545386 ps
CPU time 60.76 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 222408 kb
Host smart-f8c9d211-5241-43f1-ab41-cecb49dfc1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303218655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1303218655
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.173730988
Short name T104
Test name
Test status
Simulation time 47038506 ps
CPU time 0.74 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:44 PM PDT 24
Peak memory 205864 kb
Host smart-539f7d32-f7f2-4aee-853a-c42800137d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173730988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.173730988
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1508533308
Short name T186
Test name
Test status
Simulation time 219224756 ps
CPU time 5.95 seconds
Started Jul 24 06:02:46 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 214400 kb
Host smart-1169256b-ecfa-4384-805f-941002df68f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508533308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1508533308
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.708506291
Short name T97
Test name
Test status
Simulation time 106210048 ps
CPU time 4.51 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 221036 kb
Host smart-582214dd-ee34-4b5c-8ff7-a689d63905f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708506291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.708506291
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.986774161
Short name T386
Test name
Test status
Simulation time 124395520 ps
CPU time 5.71 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:03:57 PM PDT 24
Peak memory 214972 kb
Host smart-5e70a0a4-5197-4778-9ed8-611f2903d5b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986774161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.986774161
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.685933358
Short name T353
Test name
Test status
Simulation time 2592685165 ps
CPU time 32.89 seconds
Started Jul 24 07:04:30 PM PDT 24
Finished Jul 24 07:05:03 PM PDT 24
Peak memory 216004 kb
Host smart-f2f30bd1-7955-494b-a37f-e649575a36b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685933358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.685933358
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.350394754
Short name T347
Test name
Test status
Simulation time 109297243 ps
CPU time 4.08 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:50 PM PDT 24
Peak memory 215052 kb
Host smart-49a1d099-0cff-4b28-bb9c-1f426a27a82b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350394754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.350394754
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1538557192
Short name T107
Test name
Test status
Simulation time 674440023 ps
CPU time 13.89 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:33 PM PDT 24
Peak memory 222436 kb
Host smart-67f608dd-c9f6-4981-83ab-d113ce22ec34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538557192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1538557192
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2021151991
Short name T79
Test name
Test status
Simulation time 664939986 ps
CPU time 33.43 seconds
Started Jul 24 07:06:28 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 222236 kb
Host smart-1e862024-12d3-4171-a0f9-4a174e7f649c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021151991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2021151991
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2395878169
Short name T180
Test name
Test status
Simulation time 204502130 ps
CPU time 8.27 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:58 PM PDT 24
Peak memory 214428 kb
Host smart-1dc2d219-b111-4d56-be9c-400516f63e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395878169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2395878169
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1796779297
Short name T52
Test name
Test status
Simulation time 156381521 ps
CPU time 2.91 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 221936 kb
Host smart-e01f0a7b-abdc-41ad-8f76-b844f3ad8c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796779297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1796779297
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.241645883
Short name T254
Test name
Test status
Simulation time 136823130 ps
CPU time 2.77 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 214452 kb
Host smart-deef5505-5087-43e1-a589-848cac4f82bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241645883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.241645883
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2625701906
Short name T146
Test name
Test status
Simulation time 108975728 ps
CPU time 5.34 seconds
Started Jul 24 07:06:07 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 222128 kb
Host smart-dfb22517-5424-4ca7-bac4-29bd0a3fbf7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625701906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2625701906
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1235752840
Short name T163
Test name
Test status
Simulation time 84247921 ps
CPU time 2.91 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:13 PM PDT 24
Peak memory 217132 kb
Host smart-6c10d535-2e27-4587-b937-f05d6458a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235752840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1235752840
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2415885126
Short name T166
Test name
Test status
Simulation time 99362646 ps
CPU time 2.97 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 216768 kb
Host smart-76b8ec5c-925f-49ee-ba11-090a86bdcbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415885126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2415885126
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2934341619
Short name T72
Test name
Test status
Simulation time 529691980 ps
CPU time 4.44 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 222384 kb
Host smart-7d1c98e1-8f3c-4766-9e62-d748434154d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934341619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2934341619
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1547906772
Short name T66
Test name
Test status
Simulation time 852397404 ps
CPU time 18.1 seconds
Started Jul 24 07:03:47 PM PDT 24
Finished Jul 24 07:04:05 PM PDT 24
Peak memory 222272 kb
Host smart-3fa7c329-ba5b-4471-af1a-a92579078d16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547906772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1547906772
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1324518709
Short name T572
Test name
Test status
Simulation time 503627408 ps
CPU time 3.01 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:36 PM PDT 24
Peak memory 210256 kb
Host smart-e59b7f54-5642-4412-a4d8-542f2aa1b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324518709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1324518709
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4228984858
Short name T256
Test name
Test status
Simulation time 100280800 ps
CPU time 2.35 seconds
Started Jul 24 07:04:35 PM PDT 24
Finished Jul 24 07:04:37 PM PDT 24
Peak memory 214004 kb
Host smart-644c84c3-7fe4-4014-85c8-c2e806a1ef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228984858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4228984858
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2604635409
Short name T362
Test name
Test status
Simulation time 129058380 ps
CPU time 3.96 seconds
Started Jul 24 07:05:47 PM PDT 24
Finished Jul 24 07:05:51 PM PDT 24
Peak memory 220328 kb
Host smart-9e8927b7-b625-4284-bd35-155b3e7a5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604635409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2604635409
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2705351758
Short name T318
Test name
Test status
Simulation time 46777669 ps
CPU time 3.19 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:15 PM PDT 24
Peak memory 213984 kb
Host smart-3a5b793e-047c-46a3-974c-c37f4223813e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705351758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2705351758
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2189872769
Short name T170
Test name
Test status
Simulation time 194813008 ps
CPU time 3.21 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:06 PM PDT 24
Peak memory 214372 kb
Host smart-e08dfb73-4fe6-457b-a019-9151ee33e59e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189872769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2189872769
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3982802370
Short name T158
Test name
Test status
Simulation time 409399249 ps
CPU time 11.65 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 208660 kb
Host smart-2bc4547f-b3d3-4bbc-a8b5-dd75abf8804f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982802370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3982802370
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2710204853
Short name T173
Test name
Test status
Simulation time 108993165 ps
CPU time 3.44 seconds
Started Jul 24 06:02:40 PM PDT 24
Finished Jul 24 06:02:44 PM PDT 24
Peak memory 214328 kb
Host smart-36fb25a4-fdce-450f-9804-c97573291205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710204853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2710204853
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1335836312
Short name T179
Test name
Test status
Simulation time 94890160 ps
CPU time 3.1 seconds
Started Jul 24 06:02:42 PM PDT 24
Finished Jul 24 06:02:45 PM PDT 24
Peak memory 214412 kb
Host smart-86640e02-e95c-4d74-81df-48ac6acea36b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335836312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1335836312
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2700610594
Short name T183
Test name
Test status
Simulation time 2334439562 ps
CPU time 7.71 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:55 PM PDT 24
Peak memory 215876 kb
Host smart-b20b138f-4006-42bd-97fd-ee25bb314ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700610594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2700610594
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2441329365
Short name T47
Test name
Test status
Simulation time 304398945 ps
CPU time 3.54 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 205856 kb
Host smart-c83181bf-e0e8-438c-bbf9-9086496242af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441329365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2441329365
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3896611012
Short name T48
Test name
Test status
Simulation time 79652308 ps
CPU time 2.84 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 222424 kb
Host smart-9350d988-578c-4c08-aa98-32c6772df809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896611012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3896611012
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3872017957
Short name T330
Test name
Test status
Simulation time 249279274 ps
CPU time 3.87 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:27 PM PDT 24
Peak memory 208704 kb
Host smart-2a4192c7-73bc-4fb3-92d2-b10a5383ba33
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872017957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3872017957
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.141501715
Short name T245
Test name
Test status
Simulation time 128537626 ps
CPU time 6.61 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 215376 kb
Host smart-8f9263f1-010b-4af4-a4df-a6c3cf229c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141501715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.141501715
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3008647200
Short name T291
Test name
Test status
Simulation time 898434901 ps
CPU time 14.53 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:06:03 PM PDT 24
Peak memory 215372 kb
Host smart-7b16cbb7-bbf1-4c1e-9588-3c65eb0eb513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008647200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3008647200
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2384698863
Short name T345
Test name
Test status
Simulation time 424466997 ps
CPU time 4.43 seconds
Started Jul 24 07:05:53 PM PDT 24
Finished Jul 24 07:05:58 PM PDT 24
Peak memory 222104 kb
Host smart-3250cf3c-1034-4b42-94d3-1de9af4a2d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384698863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2384698863
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1880364427
Short name T19
Test name
Test status
Simulation time 125914861 ps
CPU time 5.47 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:50 PM PDT 24
Peak memory 213988 kb
Host smart-5e5a8e0a-7fc4-411f-b6d3-edf80481fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880364427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1880364427
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.179493359
Short name T583
Test name
Test status
Simulation time 3806940927 ps
CPU time 29.34 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 214600 kb
Host smart-0a4d304a-27f9-40d2-aab2-d0ab9f59c0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179493359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.179493359
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3039253338
Short name T192
Test name
Test status
Simulation time 120716645 ps
CPU time 2.93 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 209612 kb
Host smart-b7c4c71d-616a-4115-9b61-870172e7b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039253338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3039253338
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2724282232
Short name T167
Test name
Test status
Simulation time 373005677 ps
CPU time 3.3 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 222512 kb
Host smart-26ac0a0d-ecd8-4389-a147-e5bf64484ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724282232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2724282232
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4078467493
Short name T165
Test name
Test status
Simulation time 179938661 ps
CPU time 5.22 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:06:01 PM PDT 24
Peak memory 218168 kb
Host smart-e0652767-5d13-4308-b264-56b0b08c2919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078467493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4078467493
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2123523460
Short name T333
Test name
Test status
Simulation time 572183746 ps
CPU time 10.45 seconds
Started Jul 24 07:03:42 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 207936 kb
Host smart-386e123a-7ea4-4a0e-9ff0-176bbe5ee1e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123523460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2123523460
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3423658008
Short name T307
Test name
Test status
Simulation time 82535900 ps
CPU time 2.92 seconds
Started Jul 24 07:04:34 PM PDT 24
Finished Jul 24 07:04:37 PM PDT 24
Peak memory 214068 kb
Host smart-bda2b5f9-291c-49f8-910f-9b29ec121990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423658008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3423658008
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2471308628
Short name T199
Test name
Test status
Simulation time 590778111 ps
CPU time 22.03 seconds
Started Jul 24 07:04:34 PM PDT 24
Finished Jul 24 07:04:56 PM PDT 24
Peak memory 222368 kb
Host smart-02896219-2e4d-4bcb-b469-1ac16e6eea8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471308628 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2471308628
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2443582772
Short name T149
Test name
Test status
Simulation time 99694025 ps
CPU time 3.73 seconds
Started Jul 24 07:04:39 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 214044 kb
Host smart-3b9915da-0aa4-41b4-b21e-b2da1209d345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443582772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2443582772
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4033653338
Short name T110
Test name
Test status
Simulation time 117045934 ps
CPU time 4.61 seconds
Started Jul 24 07:05:08 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 215320 kb
Host smart-77cc262c-620c-42ac-9308-5309d294cb54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033653338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4033653338
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.443322776
Short name T327
Test name
Test status
Simulation time 138618399 ps
CPU time 2.5 seconds
Started Jul 24 07:03:50 PM PDT 24
Finished Jul 24 07:03:53 PM PDT 24
Peak memory 214036 kb
Host smart-e390d231-d12a-4fe7-b1f9-add583345766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443322776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.443322776
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1056716200
Short name T240
Test name
Test status
Simulation time 968219974 ps
CPU time 33.9 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 215048 kb
Host smart-0be159ea-2fb3-49ac-a756-b688c0983e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056716200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1056716200
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2540187706
Short name T258
Test name
Test status
Simulation time 64180226 ps
CPU time 3.59 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 208528 kb
Host smart-8c3de2dd-7551-4aa8-8b7a-9ba99ae87837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540187706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2540187706
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1138905335
Short name T237
Test name
Test status
Simulation time 3504554732 ps
CPU time 87 seconds
Started Jul 24 07:06:08 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 222288 kb
Host smart-910b9c1e-ca17-4aaf-9af0-ef91b9779d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138905335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1138905335
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1200910316
Short name T268
Test name
Test status
Simulation time 54576340 ps
CPU time 2.49 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 213968 kb
Host smart-6e6ed50e-0c1e-4487-8dc7-6ab33fa83445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200910316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1200910316
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2698357593
Short name T132
Test name
Test status
Simulation time 708341434 ps
CPU time 21.7 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 220236 kb
Host smart-c81acf18-a360-4375-b584-78fd748404dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698357593 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2698357593
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3395731888
Short name T174
Test name
Test status
Simulation time 1175776342 ps
CPU time 9.29 seconds
Started Jul 24 06:02:30 PM PDT 24
Finished Jul 24 06:02:40 PM PDT 24
Peak memory 214416 kb
Host smart-d20d8076-20ef-4b2a-a37e-30a1771e13a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395731888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3395731888
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1783997591
Short name T187
Test name
Test status
Simulation time 358191400 ps
CPU time 7.08 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 216716 kb
Host smart-0f06d2dd-73a6-4313-80d2-3f7a3751a28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783997591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1783997591
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1685890716
Short name T188
Test name
Test status
Simulation time 2248280190 ps
CPU time 5.69 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:38 PM PDT 24
Peak memory 210048 kb
Host smart-4930fa72-b1d2-4b66-be48-d7fbcfcb920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685890716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1685890716
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2619151637
Short name T148
Test name
Test status
Simulation time 101926602 ps
CPU time 5.5 seconds
Started Jul 24 07:06:29 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 222384 kb
Host smart-41f55287-6545-4f3a-944d-19caf8eb613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619151637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2619151637
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.401200500
Short name T168
Test name
Test status
Simulation time 74669407 ps
CPU time 2.6 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 222424 kb
Host smart-82c4e9c1-8192-4803-8e42-17932916ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401200500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.401200500
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2591055589
Short name T229
Test name
Test status
Simulation time 141530625 ps
CPU time 3.64 seconds
Started Jul 24 07:03:36 PM PDT 24
Finished Jul 24 07:03:40 PM PDT 24
Peak memory 220152 kb
Host smart-b6a93510-fe1b-499b-b96c-614f1b26b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591055589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2591055589
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1955161070
Short name T231
Test name
Test status
Simulation time 172874940 ps
CPU time 3.28 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:47 PM PDT 24
Peak memory 214104 kb
Host smart-3ca74798-82e1-44c6-9950-ffd71726dc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955161070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1955161070
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.823413872
Short name T210
Test name
Test status
Simulation time 5939227638 ps
CPU time 55.13 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 222060 kb
Host smart-1e1ea431-d0a5-4726-8599-fa88c55a2435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823413872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.823413872
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2121005594
Short name T226
Test name
Test status
Simulation time 109753435 ps
CPU time 3.42 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:33 PM PDT 24
Peak memory 222096 kb
Host smart-2bbe8e71-6665-4904-be82-eb1d2bc7001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121005594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2121005594
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1684509206
Short name T519
Test name
Test status
Simulation time 1603626783 ps
CPU time 19.57 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 208508 kb
Host smart-dc58b98b-f6a9-4120-a127-9288acb0d75a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684509206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1684509206
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4146285757
Short name T14
Test name
Test status
Simulation time 802230401 ps
CPU time 5.64 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:39 PM PDT 24
Peak memory 208328 kb
Host smart-16d22862-998e-496f-8963-d8da485530f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146285757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4146285757
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1598022252
Short name T808
Test name
Test status
Simulation time 186098959 ps
CPU time 4.67 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 214040 kb
Host smart-9c4fb1b4-beb5-4298-b57b-7b00ef11f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598022252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1598022252
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1037768262
Short name T116
Test name
Test status
Simulation time 214437528 ps
CPU time 3.08 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:49 PM PDT 24
Peak memory 214100 kb
Host smart-b80b2c2f-2d2b-4e05-9947-05c7a3c5b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037768262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1037768262
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4009798001
Short name T358
Test name
Test status
Simulation time 2477542335 ps
CPU time 21.08 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 208460 kb
Host smart-4086686b-5fb8-45b8-a4a3-9b58028e8f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009798001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4009798001
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1070734969
Short name T6
Test name
Test status
Simulation time 122826223 ps
CPU time 2.46 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 216580 kb
Host smart-7a8c080d-2bf1-43d0-aeed-f90d6a43a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070734969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1070734969
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.844084729
Short name T894
Test name
Test status
Simulation time 62139129 ps
CPU time 3.12 seconds
Started Jul 24 07:05:15 PM PDT 24
Finished Jul 24 07:05:18 PM PDT 24
Peak memory 209476 kb
Host smart-3a07d876-b964-452a-88d7-da04fb73f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844084729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.844084729
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2992130205
Short name T67
Test name
Test status
Simulation time 51009925 ps
CPU time 2.88 seconds
Started Jul 24 07:05:19 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 207140 kb
Host smart-1658fb03-250f-4862-9846-0368b25fa729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992130205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2992130205
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2130154649
Short name T375
Test name
Test status
Simulation time 1185052374 ps
CPU time 19.34 seconds
Started Jul 24 07:06:11 PM PDT 24
Finished Jul 24 07:06:31 PM PDT 24
Peak memory 220952 kb
Host smart-07cc6c3a-ab0b-4b88-aad4-bf47824b8d34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130154649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2130154649
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.137364903
Short name T241
Test name
Test status
Simulation time 1660654095 ps
CPU time 18.4 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 216112 kb
Host smart-d981fecc-e595-4975-b4ec-c2cc43b31781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137364903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.137364903
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.228411869
Short name T314
Test name
Test status
Simulation time 43887502 ps
CPU time 3.52 seconds
Started Jul 24 07:06:23 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 214108 kb
Host smart-dbde1d38-37b8-48dd-b4da-089e904338ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228411869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.228411869
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1338717749
Short name T156
Test name
Test status
Simulation time 129300152 ps
CPU time 6.87 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:31 PM PDT 24
Peak memory 206312 kb
Host smart-2cf58f54-880f-41de-9b47-305e9ccb7f84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338717749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
338717749
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1758723551
Short name T169
Test name
Test status
Simulation time 250474580 ps
CPU time 14.76 seconds
Started Jul 24 06:02:26 PM PDT 24
Finished Jul 24 06:02:41 PM PDT 24
Peak memory 206236 kb
Host smart-701ba1db-ab8d-43ae-a412-d1935ec5d9d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758723551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
758723551
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4294080339
Short name T1007
Test name
Test status
Simulation time 523438373 ps
CPU time 1.15 seconds
Started Jul 24 06:02:30 PM PDT 24
Finished Jul 24 06:02:31 PM PDT 24
Peak memory 206236 kb
Host smart-1bacedf6-e131-4346-babf-ab7d10b35064
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294080339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
294080339
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1070833455
Short name T1027
Test name
Test status
Simulation time 138361816 ps
CPU time 1.61 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:26 PM PDT 24
Peak memory 206248 kb
Host smart-94aae67c-ad00-4891-9544-97c023f08a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070833455 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1070833455
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.472282908
Short name T981
Test name
Test status
Simulation time 28387697 ps
CPU time 1.51 seconds
Started Jul 24 06:02:25 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 206164 kb
Host smart-3bb9e2dc-424a-4a25-825b-5532679c22cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472282908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.472282908
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3745556567
Short name T1045
Test name
Test status
Simulation time 13990757 ps
CPU time 0.87 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:34 PM PDT 24
Peak memory 206036 kb
Host smart-222021a5-5e26-4aa6-9d56-42fc3d5e1404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745556567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3745556567
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3929619308
Short name T1035
Test name
Test status
Simulation time 1168436382 ps
CPU time 4.45 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:28 PM PDT 24
Peak memory 206216 kb
Host smart-0312493e-5341-48ed-88f1-31425131e3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929619308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3929619308
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1159339087
Short name T1071
Test name
Test status
Simulation time 108856681 ps
CPU time 3.83 seconds
Started Jul 24 06:02:26 PM PDT 24
Finished Jul 24 06:02:30 PM PDT 24
Peak memory 214664 kb
Host smart-c8b1f5f5-2492-4c5c-8843-1dfd68958a7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159339087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1159339087
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.770894705
Short name T975
Test name
Test status
Simulation time 407129311 ps
CPU time 14.39 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 214652 kb
Host smart-73b5d32b-4990-49c6-aecd-8e8a7e2bae4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770894705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.770894705
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3098971256
Short name T938
Test name
Test status
Simulation time 51446188 ps
CPU time 2.73 seconds
Started Jul 24 06:02:25 PM PDT 24
Finished Jul 24 06:02:28 PM PDT 24
Peak memory 214508 kb
Host smart-79ddefc8-b29f-4cf5-8958-68b81f484d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098971256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3098971256
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1622182738
Short name T944
Test name
Test status
Simulation time 733539213 ps
CPU time 5.64 seconds
Started Jul 24 06:02:34 PM PDT 24
Finished Jul 24 06:02:40 PM PDT 24
Peak memory 206296 kb
Host smart-878f46b2-9339-453e-8d78-f3a860e9557e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622182738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
622182738
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3592953050
Short name T973
Test name
Test status
Simulation time 565741670 ps
CPU time 7.89 seconds
Started Jul 24 06:02:28 PM PDT 24
Finished Jul 24 06:02:36 PM PDT 24
Peak memory 206240 kb
Host smart-fbb9affc-07ce-4d4e-8ae5-53be15cea170
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592953050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
592953050
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.539859886
Short name T992
Test name
Test status
Simulation time 30969590 ps
CPU time 0.92 seconds
Started Jul 24 06:02:27 PM PDT 24
Finished Jul 24 06:02:28 PM PDT 24
Peak memory 206020 kb
Host smart-f100b786-b954-4b36-b5f8-ca4fff60b9cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539859886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.539859886
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2580714132
Short name T1042
Test name
Test status
Simulation time 34730162 ps
CPU time 1.32 seconds
Started Jul 24 06:02:29 PM PDT 24
Finished Jul 24 06:02:30 PM PDT 24
Peak memory 206204 kb
Host smart-6cd56f7d-2dc5-4d61-84e4-5640926af8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580714132 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2580714132
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3336052075
Short name T942
Test name
Test status
Simulation time 30596244 ps
CPU time 1.15 seconds
Started Jul 24 06:02:25 PM PDT 24
Finished Jul 24 06:02:26 PM PDT 24
Peak memory 206268 kb
Host smart-d99524bb-b773-42c7-8612-c910d42ed002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336052075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3336052075
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4282494867
Short name T961
Test name
Test status
Simulation time 119265754 ps
CPU time 0.74 seconds
Started Jul 24 06:02:22 PM PDT 24
Finished Jul 24 06:02:23 PM PDT 24
Peak memory 206004 kb
Host smart-bcfe9990-9f43-4adc-bb62-391af2fae9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282494867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4282494867
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2084469038
Short name T1052
Test name
Test status
Simulation time 68495209 ps
CPU time 2.42 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 206288 kb
Host smart-46d45779-115e-434b-860f-9706c8aba598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084469038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2084469038
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1827466366
Short name T126
Test name
Test status
Simulation time 118066722 ps
CPU time 2.32 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:26 PM PDT 24
Peak memory 214668 kb
Host smart-7625f7ce-88d8-4694-92ee-527f787dbc4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827466366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1827466366
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2148772078
Short name T954
Test name
Test status
Simulation time 93765643 ps
CPU time 4.85 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:29 PM PDT 24
Peak memory 214716 kb
Host smart-edcffde6-97c0-4e46-bcf5-e60b38423c0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148772078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2148772078
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2842662499
Short name T958
Test name
Test status
Simulation time 135361562 ps
CPU time 2.52 seconds
Started Jul 24 06:02:23 PM PDT 24
Finished Jul 24 06:02:25 PM PDT 24
Peak memory 222644 kb
Host smart-b52a8bb2-fe95-44ff-91df-5849ad9dd084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842662499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2842662499
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2719485641
Short name T181
Test name
Test status
Simulation time 309459015 ps
CPU time 6.62 seconds
Started Jul 24 06:02:32 PM PDT 24
Finished Jul 24 06:02:39 PM PDT 24
Peak memory 205992 kb
Host smart-022b56c4-72ee-4fae-aaf2-0923520a38b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719485641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2719485641
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3066973552
Short name T957
Test name
Test status
Simulation time 203642598 ps
CPU time 2.09 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 214368 kb
Host smart-b59d0c5d-de7c-496e-a721-2cd7cd27dc93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066973552 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3066973552
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.302427919
Short name T940
Test name
Test status
Simulation time 44918635 ps
CPU time 1.78 seconds
Started Jul 24 06:02:44 PM PDT 24
Finished Jul 24 06:02:46 PM PDT 24
Peak memory 206240 kb
Host smart-9fda2de0-4402-4785-9966-fdbe3d6113f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302427919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.302427919
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.755465378
Short name T917
Test name
Test status
Simulation time 9117030 ps
CPU time 0.73 seconds
Started Jul 24 06:02:55 PM PDT 24
Finished Jul 24 06:02:55 PM PDT 24
Peak memory 205980 kb
Host smart-87b57066-879c-4dd2-8292-2aa6d679ceae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755465378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.755465378
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.433401892
Short name T1013
Test name
Test status
Simulation time 26930123 ps
CPU time 1.74 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:49 PM PDT 24
Peak memory 206156 kb
Host smart-814464e7-7d09-4752-b191-4c0cda1adf5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433401892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.433401892
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4133606972
Short name T1065
Test name
Test status
Simulation time 323803533 ps
CPU time 3.96 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:54 PM PDT 24
Peak memory 214672 kb
Host smart-27d82a91-d445-4036-ab48-59fe09f009b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133606972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4133606972
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2365025507
Short name T1022
Test name
Test status
Simulation time 247146210 ps
CPU time 3.91 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 221336 kb
Host smart-b616e3a3-a7c7-400a-ae6c-c5797f90a938
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365025507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2365025507
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.704936324
Short name T972
Test name
Test status
Simulation time 78609823 ps
CPU time 3.26 seconds
Started Jul 24 06:02:43 PM PDT 24
Finished Jul 24 06:02:46 PM PDT 24
Peak memory 214448 kb
Host smart-7eea4495-d9e1-4b2a-82d6-2b042830c22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704936324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.704936324
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.383169498
Short name T962
Test name
Test status
Simulation time 28987641 ps
CPU time 2.12 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 222720 kb
Host smart-7ba95a69-71c9-4c5f-8e56-f053098990d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383169498 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.383169498
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.392334014
Short name T1011
Test name
Test status
Simulation time 135042077 ps
CPU time 1.17 seconds
Started Jul 24 06:03:08 PM PDT 24
Finished Jul 24 06:03:10 PM PDT 24
Peak memory 206080 kb
Host smart-0642e020-6338-4254-ad98-abfba4260a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392334014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.392334014
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1146672574
Short name T952
Test name
Test status
Simulation time 36706817 ps
CPU time 0.76 seconds
Started Jul 24 06:02:37 PM PDT 24
Finished Jul 24 06:02:37 PM PDT 24
Peak memory 205972 kb
Host smart-961d684e-76be-403c-a90c-2390ac3d0307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146672574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1146672574
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3322014347
Short name T956
Test name
Test status
Simulation time 191878147 ps
CPU time 2.12 seconds
Started Jul 24 06:02:55 PM PDT 24
Finished Jul 24 06:02:57 PM PDT 24
Peak memory 206144 kb
Host smart-dfd7ba7a-d895-4ea5-8c4f-ee0d9eba8d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322014347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3322014347
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.171327868
Short name T124
Test name
Test status
Simulation time 270012053 ps
CPU time 1.82 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 214568 kb
Host smart-379930c4-8c82-4f1f-a0c3-9c3aeb4a8c20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171327868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.171327868
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.888048397
Short name T1017
Test name
Test status
Simulation time 349220142 ps
CPU time 7.64 seconds
Started Jul 24 06:02:41 PM PDT 24
Finished Jul 24 06:02:49 PM PDT 24
Peak memory 214732 kb
Host smart-d5dbb3f6-3afa-401f-93c3-773ccda5be87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888048397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.888048397
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1102103811
Short name T1030
Test name
Test status
Simulation time 490715896 ps
CPU time 4.17 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 214472 kb
Host smart-3b05c53a-8138-4634-b77f-b7e9db3a0bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102103811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1102103811
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.212235853
Short name T948
Test name
Test status
Simulation time 47599656 ps
CPU time 2.22 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 214472 kb
Host smart-cdc29d11-5cbd-43b6-a85d-3867358653f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212235853 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.212235853
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2769866553
Short name T968
Test name
Test status
Simulation time 217272571 ps
CPU time 1.56 seconds
Started Jul 24 06:02:56 PM PDT 24
Finished Jul 24 06:02:58 PM PDT 24
Peak memory 206136 kb
Host smart-f669a952-8db5-45e1-ad47-2676df18d30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769866553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2769866553
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3718277292
Short name T998
Test name
Test status
Simulation time 14833393 ps
CPU time 0.73 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:51 PM PDT 24
Peak memory 206020 kb
Host smart-302fdcac-4f7c-4ed8-8de5-f3104722fac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718277292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3718277292
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3847070846
Short name T1068
Test name
Test status
Simulation time 34496789 ps
CPU time 1.92 seconds
Started Jul 24 06:02:54 PM PDT 24
Finished Jul 24 06:02:56 PM PDT 24
Peak memory 206292 kb
Host smart-1710a9ad-a376-41b4-9ed8-f27efe4d241d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847070846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3847070846
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.760647859
Short name T1059
Test name
Test status
Simulation time 123509654 ps
CPU time 3.87 seconds
Started Jul 24 06:02:53 PM PDT 24
Finished Jul 24 06:02:57 PM PDT 24
Peak memory 214764 kb
Host smart-c5d5a694-b65b-43bb-a490-bc1929ea0535
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760647859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.760647859
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.390176845
Short name T125
Test name
Test status
Simulation time 742511466 ps
CPU time 7.69 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:13 PM PDT 24
Peak memory 214728 kb
Host smart-7fd77414-370d-4dfd-8498-0f85db294438
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390176845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.390176845
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1782345611
Short name T205
Test name
Test status
Simulation time 1468936485 ps
CPU time 5.33 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 214456 kb
Host smart-7da295b4-a1fd-4767-b8f7-44a3fdf8edf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782345611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1782345611
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3170811234
Short name T929
Test name
Test status
Simulation time 119957966 ps
CPU time 4.45 seconds
Started Jul 24 06:02:57 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 214388 kb
Host smart-0832c8e8-678d-413d-93fb-b8d44703b471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170811234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3170811234
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3066745990
Short name T1018
Test name
Test status
Simulation time 35240797 ps
CPU time 2.2 seconds
Started Jul 24 06:02:57 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 214508 kb
Host smart-b23f49b9-ddd9-43f1-bd75-3000aebbf46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066745990 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3066745990
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3924154933
Short name T949
Test name
Test status
Simulation time 21280816 ps
CPU time 1.25 seconds
Started Jul 24 06:02:53 PM PDT 24
Finished Jul 24 06:02:54 PM PDT 24
Peak memory 206164 kb
Host smart-6be5f7f7-ec0f-452e-9afe-9d44c2ae9005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924154933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3924154933
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2735492620
Short name T1060
Test name
Test status
Simulation time 34291772 ps
CPU time 0.86 seconds
Started Jul 24 06:02:51 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 205944 kb
Host smart-74a4c314-af17-48c0-ab26-009e0455f747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735492620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2735492620
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1536537293
Short name T1009
Test name
Test status
Simulation time 58602004 ps
CPU time 2.34 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:08 PM PDT 24
Peak memory 206268 kb
Host smart-3a752597-1038-44a1-a10d-d9d7a4f99ba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536537293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1536537293
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3659073930
Short name T1053
Test name
Test status
Simulation time 250394714 ps
CPU time 2.2 seconds
Started Jul 24 06:03:09 PM PDT 24
Finished Jul 24 06:03:12 PM PDT 24
Peak memory 214676 kb
Host smart-0cc8e069-c73b-4499-b4af-05edb987e986
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659073930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3659073930
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1476053128
Short name T996
Test name
Test status
Simulation time 359688254 ps
CPU time 9.69 seconds
Started Jul 24 06:03:03 PM PDT 24
Finished Jul 24 06:03:13 PM PDT 24
Peak memory 214764 kb
Host smart-8bf3dc12-1c72-4809-a23c-536027fe9b7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476053128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1476053128
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2925917433
Short name T997
Test name
Test status
Simulation time 960176374 ps
CPU time 2.3 seconds
Started Jul 24 06:02:55 PM PDT 24
Finished Jul 24 06:02:57 PM PDT 24
Peak memory 216744 kb
Host smart-e3e4bc24-1f0b-44a8-aaeb-cd9066648bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925917433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2925917433
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2927638933
Short name T172
Test name
Test status
Simulation time 322172214 ps
CPU time 5.45 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:11 PM PDT 24
Peak memory 214424 kb
Host smart-114624fa-2bc0-434b-a1c3-62db226a4444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927638933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2927638933
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2818468207
Short name T1025
Test name
Test status
Simulation time 46640995 ps
CPU time 1.75 seconds
Started Jul 24 06:03:03 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 214512 kb
Host smart-d006e204-75d1-4f9d-a43e-dbe2e0d5d87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818468207 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2818468207
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3105388379
Short name T1046
Test name
Test status
Simulation time 12377846 ps
CPU time 1.08 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206128 kb
Host smart-54b65b7d-df72-4ef0-8464-faf9ecb39f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105388379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3105388379
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.893458783
Short name T1076
Test name
Test status
Simulation time 8694853 ps
CPU time 0.71 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 205936 kb
Host smart-9d5d700f-8e34-4360-995f-7eede99b1ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893458783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.893458783
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.331402085
Short name T1000
Test name
Test status
Simulation time 104174145 ps
CPU time 2.33 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 206216 kb
Host smart-7c027698-1d8d-472d-80aa-8c9d5b335f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331402085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.331402085
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3630111264
Short name T1023
Test name
Test status
Simulation time 745432751 ps
CPU time 3.66 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:09 PM PDT 24
Peak memory 214616 kb
Host smart-19096954-3986-4fdc-9c15-d0cdc9672f96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630111264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3630111264
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3176255144
Short name T1067
Test name
Test status
Simulation time 369019382 ps
CPU time 10.76 seconds
Started Jul 24 06:02:57 PM PDT 24
Finished Jul 24 06:03:08 PM PDT 24
Peak memory 214756 kb
Host smart-eeedc56a-6412-4323-bd6f-dab8842e55a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176255144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3176255144
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2064441450
Short name T935
Test name
Test status
Simulation time 52487109 ps
CPU time 3.1 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:06 PM PDT 24
Peak memory 214480 kb
Host smart-ff3150c9-8602-471a-b17b-7d1e0f2268e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064441450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2064441450
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3788028817
Short name T1075
Test name
Test status
Simulation time 210442804 ps
CPU time 2.39 seconds
Started Jul 24 06:02:51 PM PDT 24
Finished Jul 24 06:02:54 PM PDT 24
Peak memory 218228 kb
Host smart-9134d75b-eea4-4047-9378-2470599e2584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788028817 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3788028817
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.891250669
Short name T150
Test name
Test status
Simulation time 30046630 ps
CPU time 1.03 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 206244 kb
Host smart-e70bf9dd-a4d4-4c23-b372-2ee0ec08249e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891250669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.891250669
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.945323706
Short name T1006
Test name
Test status
Simulation time 56290631 ps
CPU time 0.82 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:03 PM PDT 24
Peak memory 205928 kb
Host smart-5e12c6ef-71e2-4500-91dc-84416bb54c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945323706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.945323706
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2752915914
Short name T967
Test name
Test status
Simulation time 66214257 ps
CPU time 1.83 seconds
Started Jul 24 06:02:51 PM PDT 24
Finished Jul 24 06:02:53 PM PDT 24
Peak memory 206232 kb
Host smart-7a35c21a-06aa-450d-9a5c-a71a6d721230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752915914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2752915914
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.852418274
Short name T1064
Test name
Test status
Simulation time 993099997 ps
CPU time 3.2 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 214676 kb
Host smart-7017c6d6-fc25-4749-8274-e4a71196234c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852418274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.852418274
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3502498718
Short name T970
Test name
Test status
Simulation time 166333121 ps
CPU time 6.61 seconds
Started Jul 24 06:02:57 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 214672 kb
Host smart-fb45b661-2156-442a-b171-cc5e17391083
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502498718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3502498718
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3500565190
Short name T943
Test name
Test status
Simulation time 132528975 ps
CPU time 2.78 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 214356 kb
Host smart-7c8d78ca-41e0-4df5-8b35-577f7a21d894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500565190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3500565190
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3401039482
Short name T176
Test name
Test status
Simulation time 147134385 ps
CPU time 4.8 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:11 PM PDT 24
Peak memory 214356 kb
Host smart-db4c88ae-e8f7-4cee-9ab6-cbeb4062c1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401039482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3401039482
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1875239638
Short name T1038
Test name
Test status
Simulation time 94426564 ps
CPU time 1.24 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206236 kb
Host smart-85d834bd-7473-4924-8451-f984ad9e78a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875239638 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1875239638
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1179844580
Short name T959
Test name
Test status
Simulation time 61056013 ps
CPU time 1.12 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:51 PM PDT 24
Peak memory 206132 kb
Host smart-a72195b7-a5f5-4aa5-a030-76aade2f8cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179844580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1179844580
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2163781908
Short name T1008
Test name
Test status
Simulation time 17350362 ps
CPU time 0.75 seconds
Started Jul 24 06:02:55 PM PDT 24
Finished Jul 24 06:02:57 PM PDT 24
Peak memory 206000 kb
Host smart-ab822ed7-7a97-4e18-8bce-e2d426669859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163781908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2163781908
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.495269856
Short name T985
Test name
Test status
Simulation time 314057971 ps
CPU time 1.73 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 206148 kb
Host smart-de4cefb8-b42d-40c7-95dd-db14ace929f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495269856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.495269856
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3181478458
Short name T129
Test name
Test status
Simulation time 83181005 ps
CPU time 2.08 seconds
Started Jul 24 06:02:52 PM PDT 24
Finished Jul 24 06:02:54 PM PDT 24
Peak memory 214656 kb
Host smart-d67eed90-edd1-4fa4-a608-86bcedf2d851
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181478458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3181478458
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1862330639
Short name T127
Test name
Test status
Simulation time 226698329 ps
CPU time 7.26 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:56 PM PDT 24
Peak memory 214524 kb
Host smart-e99ead9c-f4c9-4698-ab2d-4e26e8d07edf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862330639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1862330639
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2166985462
Short name T1062
Test name
Test status
Simulation time 339516083 ps
CPU time 3.08 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 216776 kb
Host smart-a0121f9d-d077-4ebb-8172-883f6bcf5daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166985462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2166985462
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1072192654
Short name T379
Test name
Test status
Simulation time 488676073 ps
CPU time 3.76 seconds
Started Jul 24 06:02:57 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 214348 kb
Host smart-80103b81-09b1-48b1-9d55-229596f1af5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072192654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1072192654
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2388857163
Short name T931
Test name
Test status
Simulation time 64671652 ps
CPU time 2 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 214488 kb
Host smart-54caa591-7a38-43ab-8109-ac7cd42d53f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388857163 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2388857163
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1492989404
Short name T157
Test name
Test status
Simulation time 21541594 ps
CPU time 0.96 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 206008 kb
Host smart-6485ad65-b5fc-4f0f-89e1-ae236d188e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492989404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1492989404
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.286217990
Short name T924
Test name
Test status
Simulation time 23740194 ps
CPU time 0.85 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 205980 kb
Host smart-8ec210eb-486d-4fc9-8d44-5183c182fa09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286217990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.286217990
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2714273856
Short name T945
Test name
Test status
Simulation time 600542544 ps
CPU time 3.91 seconds
Started Jul 24 06:03:16 PM PDT 24
Finished Jul 24 06:03:20 PM PDT 24
Peak memory 206236 kb
Host smart-466bdabb-1ba4-45cc-9e96-bde97bc34563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714273856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2714273856
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.605126758
Short name T128
Test name
Test status
Simulation time 160522543 ps
CPU time 4.84 seconds
Started Jul 24 06:03:15 PM PDT 24
Finished Jul 24 06:03:20 PM PDT 24
Peak memory 214676 kb
Host smart-9d144f3d-ee27-455b-b7bf-5e48e9e7cda5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605126758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.605126758
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1403817987
Short name T995
Test name
Test status
Simulation time 387728118 ps
CPU time 4 seconds
Started Jul 24 06:03:12 PM PDT 24
Finished Jul 24 06:03:17 PM PDT 24
Peak memory 214668 kb
Host smart-1f4e5d2f-54b8-4bad-9100-d9861b39e1e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403817987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1403817987
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1995812654
Short name T986
Test name
Test status
Simulation time 106810242 ps
CPU time 2.57 seconds
Started Jul 24 06:03:07 PM PDT 24
Finished Jul 24 06:03:10 PM PDT 24
Peak memory 214432 kb
Host smart-ae5325bb-a3da-4f16-aa9d-9e141dfa2915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995812654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1995812654
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3480123995
Short name T182
Test name
Test status
Simulation time 217773928 ps
CPU time 3.29 seconds
Started Jul 24 06:03:13 PM PDT 24
Finished Jul 24 06:03:16 PM PDT 24
Peak memory 215768 kb
Host smart-1ab5542a-3f1c-42ea-91d1-4776ebb86cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480123995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3480123995
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3365136458
Short name T1054
Test name
Test status
Simulation time 23146382 ps
CPU time 1.31 seconds
Started Jul 24 06:02:56 PM PDT 24
Finished Jul 24 06:02:58 PM PDT 24
Peak memory 206228 kb
Host smart-0cfdbb6f-5571-48c4-a576-456596ca024e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365136458 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3365136458
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2490560225
Short name T153
Test name
Test status
Simulation time 91745670 ps
CPU time 1.23 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206204 kb
Host smart-e5f143d7-1830-493a-aefe-94c81d1a4703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490560225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2490560225
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3271769346
Short name T918
Test name
Test status
Simulation time 43867615 ps
CPU time 0.75 seconds
Started Jul 24 06:03:04 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 205948 kb
Host smart-d83072cc-693a-4d82-8b64-5e01a1b75ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271769346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3271769346
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1902700696
Short name T974
Test name
Test status
Simulation time 132602847 ps
CPU time 2.33 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 206252 kb
Host smart-379f0550-65d4-427d-a465-45dfc06a28e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902700696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1902700696
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2743936726
Short name T993
Test name
Test status
Simulation time 267898833 ps
CPU time 1.66 seconds
Started Jul 24 06:03:09 PM PDT 24
Finished Jul 24 06:03:10 PM PDT 24
Peak memory 214656 kb
Host smart-a1173eb7-90ad-4e0e-8553-991c6537a591
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743936726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2743936726
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2657992623
Short name T927
Test name
Test status
Simulation time 48546332 ps
CPU time 2.86 seconds
Started Jul 24 06:02:56 PM PDT 24
Finished Jul 24 06:02:59 PM PDT 24
Peak memory 214400 kb
Host smart-309f2491-aa98-4372-bba8-dc3ac3627392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657992623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2657992623
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2201404733
Short name T184
Test name
Test status
Simulation time 128280514 ps
CPU time 3.51 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:06 PM PDT 24
Peak memory 214528 kb
Host smart-21f5f9d1-58fe-4138-84b0-31baf85bc99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201404733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2201404733
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1141896946
Short name T928
Test name
Test status
Simulation time 43413049 ps
CPU time 2.06 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 214484 kb
Host smart-9a807350-4215-4b4b-95f9-76619fe41f9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141896946 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1141896946
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.33779285
Short name T1048
Test name
Test status
Simulation time 33497187 ps
CPU time 0.89 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206064 kb
Host smart-0ecba61b-f957-43dc-91cd-f1e3e3683fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33779285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.33779285
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2064403473
Short name T919
Test name
Test status
Simulation time 71426915 ps
CPU time 0.7 seconds
Started Jul 24 06:03:09 PM PDT 24
Finished Jul 24 06:03:10 PM PDT 24
Peak memory 206016 kb
Host smart-1b209650-ca6f-4363-9bef-e253180ed5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064403473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2064403473
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1210837146
Short name T979
Test name
Test status
Simulation time 22347229 ps
CPU time 1.31 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 206244 kb
Host smart-71b816c6-9022-472a-a363-4b0d010393bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210837146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1210837146
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3759735130
Short name T1039
Test name
Test status
Simulation time 33743165 ps
CPU time 1.21 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 214600 kb
Host smart-fd8463a9-55c4-4c8e-a7af-5e9b041b9195
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759735130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3759735130
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3704571128
Short name T1072
Test name
Test status
Simulation time 166429107 ps
CPU time 4.71 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 214720 kb
Host smart-c17acd24-1de8-40f2-bd19-d9287d1dd64f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704571128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3704571128
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.418654201
Short name T947
Test name
Test status
Simulation time 166892350 ps
CPU time 2.37 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 214532 kb
Host smart-5fe41ffb-8d4d-47c2-aaf2-75f669e4c387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418654201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.418654201
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3890541712
Short name T939
Test name
Test status
Simulation time 71942636 ps
CPU time 4.6 seconds
Started Jul 24 06:02:37 PM PDT 24
Finished Jul 24 06:02:42 PM PDT 24
Peak memory 206124 kb
Host smart-454bc45e-c2c7-4702-96db-049a2b347c42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890541712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
890541712
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4180736939
Short name T980
Test name
Test status
Simulation time 1599284014 ps
CPU time 8.82 seconds
Started Jul 24 06:02:34 PM PDT 24
Finished Jul 24 06:02:43 PM PDT 24
Peak memory 206264 kb
Host smart-f78b62e8-59f5-4b57-9496-d5bad45ae9a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180736939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
180736939
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3385744689
Short name T1047
Test name
Test status
Simulation time 17516017 ps
CPU time 0.87 seconds
Started Jul 24 06:02:30 PM PDT 24
Finished Jul 24 06:02:32 PM PDT 24
Peak memory 205928 kb
Host smart-760cbcee-a5f3-41fe-9fb6-2ed559f710ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385744689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
385744689
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.546820473
Short name T999
Test name
Test status
Simulation time 137460045 ps
CPU time 2.17 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 214580 kb
Host smart-5f722862-50fe-480d-8114-b021679c2ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546820473 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.546820473
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3916896633
Short name T1050
Test name
Test status
Simulation time 48673143 ps
CPU time 0.89 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:36 PM PDT 24
Peak memory 206068 kb
Host smart-43b3ecf9-16ff-447e-8904-e28dd5432f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916896633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3916896633
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2610866522
Short name T1066
Test name
Test status
Simulation time 7544336 ps
CPU time 0.76 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:51 PM PDT 24
Peak memory 206004 kb
Host smart-2ef79003-0ab9-48db-89c9-0cf46e91a38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610866522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2610866522
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1174314900
Short name T151
Test name
Test status
Simulation time 37775054 ps
CPU time 2.09 seconds
Started Jul 24 06:02:41 PM PDT 24
Finished Jul 24 06:02:43 PM PDT 24
Peak memory 206324 kb
Host smart-f041e28a-c46b-4cb7-bf41-088d31fb2405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174314900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1174314900
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4114885528
Short name T1074
Test name
Test status
Simulation time 89847193 ps
CPU time 2.86 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 214612 kb
Host smart-42a2f15f-b213-40f1-848c-de1e2f9bfdfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114885528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4114885528
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1026143899
Short name T984
Test name
Test status
Simulation time 1788440134 ps
CPU time 10.08 seconds
Started Jul 24 06:02:40 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 222480 kb
Host smart-003f713f-6434-4aec-81c1-e76c46f8690b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026143899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1026143899
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1141973546
Short name T936
Test name
Test status
Simulation time 216184996 ps
CPU time 3.81 seconds
Started Jul 24 06:02:36 PM PDT 24
Finished Jul 24 06:02:40 PM PDT 24
Peak memory 214436 kb
Host smart-64c2b461-a87b-4e4a-8a8b-f04963bfd47f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141973546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1141973546
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2713187075
Short name T193
Test name
Test status
Simulation time 261306833 ps
CPU time 5.44 seconds
Started Jul 24 06:02:28 PM PDT 24
Finished Jul 24 06:02:39 PM PDT 24
Peak memory 214408 kb
Host smart-2a6233da-0158-40c2-a015-a7636ea67f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713187075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2713187075
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3132784907
Short name T964
Test name
Test status
Simulation time 45749356 ps
CPU time 0.82 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:02:59 PM PDT 24
Peak memory 205956 kb
Host smart-c2bb4465-4bf6-4488-becf-4138b4fac2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132784907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3132784907
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1419544825
Short name T1012
Test name
Test status
Simulation time 26192880 ps
CPU time 0.68 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 205988 kb
Host smart-e794231e-4bd2-43c4-b5f2-024a00eb4240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419544825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1419544825
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4080779127
Short name T1001
Test name
Test status
Simulation time 10727016 ps
CPU time 0.74 seconds
Started Jul 24 06:03:13 PM PDT 24
Finished Jul 24 06:03:14 PM PDT 24
Peak memory 206012 kb
Host smart-d1fddcf4-b9da-47a2-ae8c-8567164198eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080779127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4080779127
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1392955976
Short name T963
Test name
Test status
Simulation time 11612924 ps
CPU time 0.73 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 206004 kb
Host smart-98f60a46-e2e0-4733-a8cd-0bf629785857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392955976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1392955976
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1364704963
Short name T1003
Test name
Test status
Simulation time 25224642 ps
CPU time 0.76 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 206016 kb
Host smart-75eba996-977a-4662-af6f-5e9cd012502f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364704963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1364704963
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.461032540
Short name T994
Test name
Test status
Simulation time 31798991 ps
CPU time 0.85 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206204 kb
Host smart-e8ee693a-d1e4-4564-b2dc-c8bf67410a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461032540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.461032540
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2166514309
Short name T1073
Test name
Test status
Simulation time 15187506 ps
CPU time 0.72 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206004 kb
Host smart-6eb1aa82-1166-42e7-ac97-fd6c7e3ac013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166514309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2166514309
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.220402010
Short name T1078
Test name
Test status
Simulation time 72823490 ps
CPU time 0.77 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:02:59 PM PDT 24
Peak memory 205952 kb
Host smart-890fa2c0-84e9-4bfa-87c4-22abd96cc8cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220402010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.220402010
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1015461052
Short name T1029
Test name
Test status
Simulation time 60723601 ps
CPU time 0.81 seconds
Started Jul 24 06:03:04 PM PDT 24
Finished Jul 24 06:03:05 PM PDT 24
Peak memory 206008 kb
Host smart-1ebd185c-a9d2-44ba-a892-d237e52f13ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015461052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1015461052
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.547143263
Short name T1004
Test name
Test status
Simulation time 14367583 ps
CPU time 0.76 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 205992 kb
Host smart-92f50e18-c06e-4314-afb8-15046841e89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547143263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.547143263
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.690933965
Short name T1063
Test name
Test status
Simulation time 790167701 ps
CPU time 13.73 seconds
Started Jul 24 06:02:32 PM PDT 24
Finished Jul 24 06:02:46 PM PDT 24
Peak memory 206260 kb
Host smart-16f96714-a33c-4630-868e-220dd56d040d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690933965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.690933965
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.445607252
Short name T1010
Test name
Test status
Simulation time 2671563447 ps
CPU time 9.64 seconds
Started Jul 24 06:02:29 PM PDT 24
Finished Jul 24 06:02:39 PM PDT 24
Peak memory 206140 kb
Host smart-a6166474-b2cb-436a-84dc-0ede4f02583a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445607252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.445607252
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3864679704
Short name T983
Test name
Test status
Simulation time 17794519 ps
CPU time 1.06 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:37 PM PDT 24
Peak memory 206224 kb
Host smart-2b92ae65-abe9-49c3-88ad-a5a8457dc386
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864679704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
864679704
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1854364921
Short name T1037
Test name
Test status
Simulation time 495421214 ps
CPU time 1.26 seconds
Started Jul 24 06:02:26 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 206208 kb
Host smart-78ac4617-4aa6-4b93-aa4e-522b2fd7c17c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854364921 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1854364921
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.367092447
Short name T154
Test name
Test status
Simulation time 16592252 ps
CPU time 1.06 seconds
Started Jul 24 06:02:31 PM PDT 24
Finished Jul 24 06:02:32 PM PDT 24
Peak memory 206100 kb
Host smart-ade73c41-f8c3-4351-90b4-b14a66e0dfb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367092447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.367092447
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.765172432
Short name T1034
Test name
Test status
Simulation time 15768764 ps
CPU time 0.89 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:34 PM PDT 24
Peak memory 206108 kb
Host smart-ac927882-1efa-4eac-94c2-3e149bdda470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765172432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.765172432
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3022621467
Short name T1040
Test name
Test status
Simulation time 71805618 ps
CPU time 2.37 seconds
Started Jul 24 06:02:28 PM PDT 24
Finished Jul 24 06:02:30 PM PDT 24
Peak memory 214616 kb
Host smart-529667e5-5033-4a65-91ca-e01a276289ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022621467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3022621467
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4252948560
Short name T1049
Test name
Test status
Simulation time 360109708 ps
CPU time 1.83 seconds
Started Jul 24 06:02:31 PM PDT 24
Finished Jul 24 06:02:33 PM PDT 24
Peak memory 214716 kb
Host smart-a7a83f5f-b79c-4bfb-9161-f4d471541046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252948560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4252948560
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1830624478
Short name T1055
Test name
Test status
Simulation time 177243428 ps
CPU time 2.2 seconds
Started Jul 24 06:02:34 PM PDT 24
Finished Jul 24 06:02:36 PM PDT 24
Peak memory 214548 kb
Host smart-d20c01da-f12c-4c4f-84bd-997297c8219c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830624478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1830624478
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2656625111
Short name T920
Test name
Test status
Simulation time 31990638 ps
CPU time 0.69 seconds
Started Jul 24 06:03:06 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206032 kb
Host smart-41631eb8-d786-4978-8aa5-d0086acbfa85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656625111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2656625111
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.684363327
Short name T932
Test name
Test status
Simulation time 43609460 ps
CPU time 0.73 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:03 PM PDT 24
Peak memory 206024 kb
Host smart-238be3dc-c147-4847-bce4-8ec454d55400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684363327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.684363327
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.678681857
Short name T1057
Test name
Test status
Simulation time 41875920 ps
CPU time 0.78 seconds
Started Jul 24 06:03:08 PM PDT 24
Finished Jul 24 06:03:09 PM PDT 24
Peak memory 206024 kb
Host smart-2acd8599-ae13-4bf4-a840-c17f1cbc0327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678681857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.678681857
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2811621849
Short name T976
Test name
Test status
Simulation time 10478753 ps
CPU time 0.76 seconds
Started Jul 24 06:03:03 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 206016 kb
Host smart-bbe39fdb-407c-474e-8a7f-9cbed5c55498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811621849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2811621849
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3347664489
Short name T991
Test name
Test status
Simulation time 49033294 ps
CPU time 0.78 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 206036 kb
Host smart-e7bc9b91-5a7f-43e4-8d6c-3fd12e5d0f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347664489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3347664489
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.182974837
Short name T978
Test name
Test status
Simulation time 31851634 ps
CPU time 0.67 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206028 kb
Host smart-737c39f8-ea49-4acc-a060-fdf91a299879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182974837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.182974837
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.919080582
Short name T941
Test name
Test status
Simulation time 31205423 ps
CPU time 0.78 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206020 kb
Host smart-147c1421-ef1d-4e52-a941-8ab1d30cae51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919080582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.919080582
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3122965947
Short name T1015
Test name
Test status
Simulation time 8693071 ps
CPU time 0.82 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:06 PM PDT 24
Peak memory 206056 kb
Host smart-d9d8cbfb-b65e-4213-8c12-5163525ee72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122965947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3122965947
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3700758169
Short name T946
Test name
Test status
Simulation time 21996125 ps
CPU time 0.73 seconds
Started Jul 24 06:03:15 PM PDT 24
Finished Jul 24 06:03:16 PM PDT 24
Peak memory 205944 kb
Host smart-3dc4794b-281a-4fe9-a648-0bcb5104e792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700758169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3700758169
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3184066437
Short name T969
Test name
Test status
Simulation time 9077312 ps
CPU time 0.68 seconds
Started Jul 24 06:03:06 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206176 kb
Host smart-bf97163b-552b-4c3e-b56c-aae58246d90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184066437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3184066437
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2501542649
Short name T1043
Test name
Test status
Simulation time 415391829 ps
CPU time 14.93 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 206248 kb
Host smart-aced4685-589e-4b22-bd90-05331d4e188c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501542649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
501542649
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2405841748
Short name T1028
Test name
Test status
Simulation time 1014414805 ps
CPU time 14.26 seconds
Started Jul 24 06:02:34 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 206068 kb
Host smart-8e74eab0-6ca5-4f2e-b199-6d2acb049269
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405841748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
405841748
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1761775623
Short name T933
Test name
Test status
Simulation time 31612417 ps
CPU time 1.23 seconds
Started Jul 24 06:02:30 PM PDT 24
Finished Jul 24 06:02:31 PM PDT 24
Peak memory 206192 kb
Host smart-cb83e1d5-0f2b-4fe5-8462-f381b30cb35b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761775623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
761775623
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3506452298
Short name T200
Test name
Test status
Simulation time 28925736 ps
CPU time 1.22 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 206268 kb
Host smart-d6f436a6-c529-4d1b-8d8c-2126670e4481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506452298 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3506452298
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.62570350
Short name T955
Test name
Test status
Simulation time 13599520 ps
CPU time 0.88 seconds
Started Jul 24 06:02:41 PM PDT 24
Finished Jul 24 06:02:42 PM PDT 24
Peak memory 206060 kb
Host smart-f64a1513-e722-469d-97fd-2d6ff7ca7062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62570350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.62570350
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2591932628
Short name T1077
Test name
Test status
Simulation time 50373473 ps
CPU time 0.77 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:34 PM PDT 24
Peak memory 206028 kb
Host smart-0b3ffbd7-c24b-4bed-890b-169d6cbde0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591932628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2591932628
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.412862930
Short name T1033
Test name
Test status
Simulation time 516480403 ps
CPU time 2.7 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:38 PM PDT 24
Peak memory 214452 kb
Host smart-299508ce-4bce-462d-b3c9-3d95a2e6ee58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412862930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.412862930
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.408644201
Short name T120
Test name
Test status
Simulation time 87209654 ps
CPU time 1.81 seconds
Started Jul 24 06:02:37 PM PDT 24
Finished Jul 24 06:02:39 PM PDT 24
Peak memory 214664 kb
Host smart-f607541b-fcda-43d7-ade8-4fb14f595164
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408644201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.408644201
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1266624476
Short name T971
Test name
Test status
Simulation time 219304113 ps
CPU time 3.71 seconds
Started Jul 24 06:02:45 PM PDT 24
Finished Jul 24 06:02:49 PM PDT 24
Peak memory 214744 kb
Host smart-d4204de0-14de-46bb-be91-6761a08e1188
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266624476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1266624476
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.370366556
Short name T1061
Test name
Test status
Simulation time 283462767 ps
CPU time 2.26 seconds
Started Jul 24 06:02:24 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 214476 kb
Host smart-ae18e3cb-7f1b-45fd-8be6-ada9fad5bcd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370366556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.370366556
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.974149124
Short name T1032
Test name
Test status
Simulation time 146360450 ps
CPU time 0.78 seconds
Started Jul 24 06:02:59 PM PDT 24
Finished Jul 24 06:03:00 PM PDT 24
Peak memory 206056 kb
Host smart-7093a720-1b32-4621-aacc-4855d8fc337e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974149124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.974149124
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2595962095
Short name T926
Test name
Test status
Simulation time 22245680 ps
CPU time 0.75 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:02:58 PM PDT 24
Peak memory 205944 kb
Host smart-3d32a6c6-92ba-4e5c-b283-c2915cb27e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595962095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2595962095
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1883650925
Short name T987
Test name
Test status
Simulation time 40815336 ps
CPU time 0.77 seconds
Started Jul 24 06:03:12 PM PDT 24
Finished Jul 24 06:03:13 PM PDT 24
Peak memory 206016 kb
Host smart-0048e80c-831c-46b3-b48f-643d20618d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883650925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1883650925
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3179382119
Short name T925
Test name
Test status
Simulation time 40607814 ps
CPU time 0.86 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 206032 kb
Host smart-81e4986e-d1af-4cfb-bad5-6532fe5fc4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179382119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3179382119
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.779617311
Short name T1016
Test name
Test status
Simulation time 32685311 ps
CPU time 0.72 seconds
Started Jul 24 06:03:13 PM PDT 24
Finished Jul 24 06:03:14 PM PDT 24
Peak memory 206020 kb
Host smart-3d39dc4d-d8e8-4961-a93e-a56642bbd1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779617311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.779617311
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1987343289
Short name T1036
Test name
Test status
Simulation time 41235333 ps
CPU time 0.91 seconds
Started Jul 24 06:03:05 PM PDT 24
Finished Jul 24 06:03:07 PM PDT 24
Peak memory 206060 kb
Host smart-8fe4a599-441c-490d-96f7-6f70329eee35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987343289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1987343289
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3419153541
Short name T934
Test name
Test status
Simulation time 21153881 ps
CPU time 0.81 seconds
Started Jul 24 06:03:02 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 206128 kb
Host smart-a259a1ba-8782-45b0-a3da-7fa9138a670d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419153541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3419153541
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2377532975
Short name T1026
Test name
Test status
Simulation time 16321770 ps
CPU time 0.74 seconds
Started Jul 24 06:03:00 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 206008 kb
Host smart-fd66604c-21ad-4354-a1b2-87aa439cf64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377532975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2377532975
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3292695361
Short name T966
Test name
Test status
Simulation time 68325604 ps
CPU time 0.8 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 205952 kb
Host smart-898ed0e7-8aa7-4996-bc9a-59c4a5b00dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292695361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3292695361
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4038193059
Short name T1002
Test name
Test status
Simulation time 22294791 ps
CPU time 0.85 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:04 PM PDT 24
Peak memory 206128 kb
Host smart-0c125bf0-ada4-4dfc-aa13-c4d502d5ae47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038193059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4038193059
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3096088996
Short name T923
Test name
Test status
Simulation time 91239624 ps
CPU time 2.25 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:36 PM PDT 24
Peak memory 214536 kb
Host smart-76e6ebd4-ab35-4bb2-bf8c-aaa09e542c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096088996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3096088996
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.644123662
Short name T982
Test name
Test status
Simulation time 64428651 ps
CPU time 1.59 seconds
Started Jul 24 06:02:35 PM PDT 24
Finished Jul 24 06:02:37 PM PDT 24
Peak memory 206296 kb
Host smart-b72a633e-d0b9-4c3e-8927-546ea51e30be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644123662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.644123662
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1517308640
Short name T922
Test name
Test status
Simulation time 10637847 ps
CPU time 0.86 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:51 PM PDT 24
Peak memory 206000 kb
Host smart-5372c480-7662-4c38-b355-19c93bba4c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517308640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1517308640
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1308601194
Short name T950
Test name
Test status
Simulation time 467271113 ps
CPU time 2.78 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:51 PM PDT 24
Peak memory 206244 kb
Host smart-bc0cefb7-eb1d-4bd9-91ca-22490b763670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308601194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1308601194
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.283710326
Short name T1020
Test name
Test status
Simulation time 255651572 ps
CPU time 5.97 seconds
Started Jul 24 06:02:39 PM PDT 24
Finished Jul 24 06:02:45 PM PDT 24
Peak memory 214684 kb
Host smart-0283b356-4637-40e0-9471-c58af40f4867
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283710326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.283710326
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.4065176088
Short name T960
Test name
Test status
Simulation time 704389564 ps
CPU time 4.65 seconds
Started Jul 24 06:02:42 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 214704 kb
Host smart-3edcc108-54dc-47b4-8afa-50c7b3aadf8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065176088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.4065176088
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.167390045
Short name T1051
Test name
Test status
Simulation time 41548751 ps
CPU time 1.74 seconds
Started Jul 24 06:02:31 PM PDT 24
Finished Jul 24 06:02:33 PM PDT 24
Peak memory 214416 kb
Host smart-f917801f-28a3-4b7a-970c-c51689a60269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167390045 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.167390045
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.376362919
Short name T1021
Test name
Test status
Simulation time 62697637 ps
CPU time 1.08 seconds
Started Jul 24 06:02:55 PM PDT 24
Finished Jul 24 06:02:56 PM PDT 24
Peak memory 206248 kb
Host smart-df40103f-b19d-4f5f-9dad-a5c86e17fdd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376362919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.376362919
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4134423200
Short name T951
Test name
Test status
Simulation time 11406037 ps
CPU time 0.74 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:49 PM PDT 24
Peak memory 206056 kb
Host smart-f95ff8a8-eef1-4228-b513-fbb149ef8d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134423200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4134423200
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1417171682
Short name T1069
Test name
Test status
Simulation time 70184036 ps
CPU time 2.16 seconds
Started Jul 24 06:02:31 PM PDT 24
Finished Jul 24 06:02:33 PM PDT 24
Peak memory 206352 kb
Host smart-20e554e5-3b04-4b8b-9342-b9b044083931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417171682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1417171682
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2387455866
Short name T1070
Test name
Test status
Simulation time 311693473 ps
CPU time 3.9 seconds
Started Jul 24 06:02:32 PM PDT 24
Finished Jul 24 06:02:36 PM PDT 24
Peak memory 214644 kb
Host smart-2975f5d6-ff15-4efd-a1b3-d04d2057d266
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387455866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2387455866
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3572350298
Short name T1014
Test name
Test status
Simulation time 304562076 ps
CPU time 4.21 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:38 PM PDT 24
Peak memory 214672 kb
Host smart-0acda2bc-c8d8-491d-a65b-46a3ee1fb15d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572350298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3572350298
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2894071471
Short name T989
Test name
Test status
Simulation time 144826778 ps
CPU time 2.55 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 214384 kb
Host smart-91d56b08-c627-4e81-b78e-89893514d579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894071471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2894071471
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3222388527
Short name T175
Test name
Test status
Simulation time 173060408 ps
CPU time 3 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 214588 kb
Host smart-3b39e04f-f011-4689-b3bc-24ac07ea87aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222388527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3222388527
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3186079661
Short name T1056
Test name
Test status
Simulation time 30133860 ps
CPU time 1.42 seconds
Started Jul 24 06:02:40 PM PDT 24
Finished Jul 24 06:02:41 PM PDT 24
Peak memory 206336 kb
Host smart-d54758b3-c7de-492d-8995-af4d80ebe1a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186079661 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3186079661
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1474003212
Short name T385
Test name
Test status
Simulation time 31139568 ps
CPU time 1.12 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 206236 kb
Host smart-12949e16-4257-4792-b0a4-9768958e765a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474003212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1474003212
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3397130034
Short name T1044
Test name
Test status
Simulation time 38410419 ps
CPU time 0.82 seconds
Started Jul 24 06:02:30 PM PDT 24
Finished Jul 24 06:02:31 PM PDT 24
Peak memory 206036 kb
Host smart-bf4bd167-10f5-48ed-ab3f-b5106f7b58a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397130034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3397130034
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2202255066
Short name T990
Test name
Test status
Simulation time 109305910 ps
CPU time 2.52 seconds
Started Jul 24 06:02:34 PM PDT 24
Finished Jul 24 06:02:37 PM PDT 24
Peak memory 206348 kb
Host smart-5cae8ccb-3211-4479-ad73-e921bf1e690e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202255066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2202255066
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3156725910
Short name T988
Test name
Test status
Simulation time 100736029 ps
CPU time 1.86 seconds
Started Jul 24 06:02:46 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 214652 kb
Host smart-f72b04a9-6021-4985-95c1-6b5352d1f003
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156725910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3156725910
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.41425492
Short name T1041
Test name
Test status
Simulation time 430227582 ps
CPU time 13.59 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 214604 kb
Host smart-a454e1ec-b8f2-4e9b-af9b-3acba739c3df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_shadow_reg_errors_with_csr_rw.41425492
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.516000468
Short name T930
Test name
Test status
Simulation time 1078474905 ps
CPU time 1.76 seconds
Started Jul 24 06:02:39 PM PDT 24
Finished Jul 24 06:02:41 PM PDT 24
Peak memory 215400 kb
Host smart-ddb654f7-6ee5-422e-b7ba-0d56f1e02d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516000468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.516000468
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.398957542
Short name T190
Test name
Test status
Simulation time 141747747 ps
CPU time 3.87 seconds
Started Jul 24 06:02:33 PM PDT 24
Finished Jul 24 06:02:37 PM PDT 24
Peak memory 214316 kb
Host smart-9bb968d9-458f-4450-b0fe-d733d7358dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398957542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
398957542
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4182420013
Short name T1079
Test name
Test status
Simulation time 33562393 ps
CPU time 2.09 seconds
Started Jul 24 06:02:50 PM PDT 24
Finished Jul 24 06:02:52 PM PDT 24
Peak memory 214376 kb
Host smart-dd3905c1-96a0-4289-bb5b-71141d91b0c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182420013 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4182420013
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1894925030
Short name T152
Test name
Test status
Simulation time 14247870 ps
CPU time 0.95 seconds
Started Jul 24 06:02:41 PM PDT 24
Finished Jul 24 06:02:42 PM PDT 24
Peak memory 206068 kb
Host smart-21474944-8de7-4e5f-a630-050da2c27fdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894925030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1894925030
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4160707653
Short name T921
Test name
Test status
Simulation time 11104069 ps
CPU time 0.69 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 205952 kb
Host smart-6b22e6ac-904b-45cc-aafc-02ca4a19cf00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160707653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4160707653
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.256277046
Short name T977
Test name
Test status
Simulation time 174446153 ps
CPU time 1.97 seconds
Started Jul 24 06:02:58 PM PDT 24
Finished Jul 24 06:03:01 PM PDT 24
Peak memory 206128 kb
Host smart-59d1545d-1d14-46f9-bd25-422443f1f82a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256277046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.256277046
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2625104663
Short name T123
Test name
Test status
Simulation time 164547794 ps
CPU time 1.98 seconds
Started Jul 24 06:02:54 PM PDT 24
Finished Jul 24 06:02:56 PM PDT 24
Peak memory 214648 kb
Host smart-aae259b0-a0cc-48a1-8f0d-ac7b4b149a30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625104663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2625104663
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1039125709
Short name T1024
Test name
Test status
Simulation time 1280703726 ps
CPU time 12.75 seconds
Started Jul 24 06:02:45 PM PDT 24
Finished Jul 24 06:02:58 PM PDT 24
Peak memory 214688 kb
Host smart-f0e4e5ec-a750-4510-8940-0368d099cb10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039125709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1039125709
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.216704348
Short name T965
Test name
Test status
Simulation time 51339334 ps
CPU time 3.16 seconds
Started Jul 24 06:02:45 PM PDT 24
Finished Jul 24 06:02:49 PM PDT 24
Peak memory 214416 kb
Host smart-1670395b-3710-4ed6-b96b-3f7c7fdb1e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216704348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.216704348
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2087709056
Short name T178
Test name
Test status
Simulation time 181279073 ps
CPU time 3.18 seconds
Started Jul 24 06:02:56 PM PDT 24
Finished Jul 24 06:02:59 PM PDT 24
Peak memory 214472 kb
Host smart-fe47bd81-57bc-421d-8701-f0a279d1c24e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087709056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2087709056
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.789155431
Short name T171
Test name
Test status
Simulation time 52055352 ps
CPU time 2.43 seconds
Started Jul 24 06:02:42 PM PDT 24
Finished Jul 24 06:02:44 PM PDT 24
Peak memory 214500 kb
Host smart-1d445d66-6569-4169-80da-448c1b4d22e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789155431 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.789155431
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3957530705
Short name T937
Test name
Test status
Simulation time 16716761 ps
CPU time 0.89 seconds
Started Jul 24 06:02:49 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 206004 kb
Host smart-10d0ce13-2771-46e0-a08b-94a935c960d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957530705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3957530705
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1133123298
Short name T1031
Test name
Test status
Simulation time 7558682 ps
CPU time 0.79 seconds
Started Jul 24 06:02:47 PM PDT 24
Finished Jul 24 06:02:48 PM PDT 24
Peak memory 206000 kb
Host smart-725b789d-c366-4f88-b50a-875140c964dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133123298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1133123298
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2911597782
Short name T155
Test name
Test status
Simulation time 34646372 ps
CPU time 2.37 seconds
Started Jul 24 06:02:48 PM PDT 24
Finished Jul 24 06:02:50 PM PDT 24
Peak memory 206256 kb
Host smart-9544da00-f851-4f5b-b70e-2c5e0355786d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911597782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2911597782
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4237103811
Short name T1058
Test name
Test status
Simulation time 77078544 ps
CPU time 1.78 seconds
Started Jul 24 06:02:44 PM PDT 24
Finished Jul 24 06:02:46 PM PDT 24
Peak memory 214600 kb
Host smart-04976c12-9954-4e8d-a678-e7207513de0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237103811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4237103811
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3474478488
Short name T1005
Test name
Test status
Simulation time 1620577049 ps
CPU time 10.47 seconds
Started Jul 24 06:02:51 PM PDT 24
Finished Jul 24 06:03:02 PM PDT 24
Peak memory 214696 kb
Host smart-48606d80-8df2-4906-b0cb-792b8914b709
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474478488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3474478488
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.418978263
Short name T1019
Test name
Test status
Simulation time 525037319 ps
CPU time 4.63 seconds
Started Jul 24 06:02:54 PM PDT 24
Finished Jul 24 06:02:59 PM PDT 24
Peak memory 217384 kb
Host smart-2d1ff6b9-edb0-4b54-aa97-a8c6698f9e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418978263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.418978263
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4235907599
Short name T380
Test name
Test status
Simulation time 194482603 ps
CPU time 2.97 seconds
Started Jul 24 06:03:01 PM PDT 24
Finished Jul 24 06:03:06 PM PDT 24
Peak memory 214424 kb
Host smart-a6de2f2e-c317-45d3-9b25-c668d2e2f0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235907599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4235907599
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2212078388
Short name T388
Test name
Test status
Simulation time 52767730 ps
CPU time 3.6 seconds
Started Jul 24 07:03:43 PM PDT 24
Finished Jul 24 07:03:46 PM PDT 24
Peak memory 214796 kb
Host smart-abb2ae80-de44-47f3-b70f-43b8ae2eadac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212078388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2212078388
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2367715209
Short name T735
Test name
Test status
Simulation time 112748751 ps
CPU time 3.14 seconds
Started Jul 24 07:03:42 PM PDT 24
Finished Jul 24 07:03:45 PM PDT 24
Peak memory 221508 kb
Host smart-acd4095c-ab9c-4b53-8b6d-9dc48c77bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367715209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2367715209
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2483739987
Short name T446
Test name
Test status
Simulation time 47497794 ps
CPU time 2.28 seconds
Started Jul 24 07:03:38 PM PDT 24
Finished Jul 24 07:03:40 PM PDT 24
Peak memory 207284 kb
Host smart-cc94a813-b91a-4b2d-a6a1-4d6f982734f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483739987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2483739987
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3259023501
Short name T44
Test name
Test status
Simulation time 112896505 ps
CPU time 2.3 seconds
Started Jul 24 07:03:39 PM PDT 24
Finished Jul 24 07:03:41 PM PDT 24
Peak memory 214056 kb
Host smart-5e5ba8c7-2120-4c89-b172-eed9609c2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259023501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3259023501
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2240452889
Short name T709
Test name
Test status
Simulation time 71643215 ps
CPU time 2.42 seconds
Started Jul 24 07:03:37 PM PDT 24
Finished Jul 24 07:03:39 PM PDT 24
Peak memory 221824 kb
Host smart-c6338f2d-3501-46a7-8f45-8c3156126b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240452889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2240452889
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.2084154388
Short name T672
Test name
Test status
Simulation time 2104737822 ps
CPU time 43.14 seconds
Started Jul 24 07:03:35 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 209280 kb
Host smart-83acb4ad-c762-4435-9aff-3709f394d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084154388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2084154388
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1720942026
Short name T108
Test name
Test status
Simulation time 1154852098 ps
CPU time 6.75 seconds
Started Jul 24 07:03:48 PM PDT 24
Finished Jul 24 07:03:55 PM PDT 24
Peak memory 237344 kb
Host smart-741b1db7-a26b-47f2-a35d-d7856bb7d666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720942026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1720942026
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3008463226
Short name T701
Test name
Test status
Simulation time 205319981 ps
CPU time 5.47 seconds
Started Jul 24 07:03:41 PM PDT 24
Finished Jul 24 07:03:46 PM PDT 24
Peak memory 208236 kb
Host smart-cbe2a6eb-8ec2-4bc3-a512-5ebbec5797ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008463226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3008463226
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.961579733
Short name T514
Test name
Test status
Simulation time 34304569 ps
CPU time 2.36 seconds
Started Jul 24 07:03:38 PM PDT 24
Finished Jul 24 07:03:41 PM PDT 24
Peak memory 206708 kb
Host smart-be99251d-b794-43cc-8a77-1d9d8ea82e91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961579733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.961579733
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3258195746
Short name T705
Test name
Test status
Simulation time 46133210 ps
CPU time 2.59 seconds
Started Jul 24 07:03:43 PM PDT 24
Finished Jul 24 07:03:45 PM PDT 24
Peak memory 208308 kb
Host smart-c25c3c82-9edb-45a6-be12-709238c180d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258195746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3258195746
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1199587216
Short name T811
Test name
Test status
Simulation time 90500472 ps
CPU time 3.09 seconds
Started Jul 24 07:03:38 PM PDT 24
Finished Jul 24 07:03:41 PM PDT 24
Peak memory 207924 kb
Host smart-e30ba86c-df8c-4bbd-900e-39d6603fc19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199587216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1199587216
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3319618302
Short name T648
Test name
Test status
Simulation time 63151396 ps
CPU time 2.9 seconds
Started Jul 24 07:03:42 PM PDT 24
Finished Jul 24 07:03:45 PM PDT 24
Peak memory 208240 kb
Host smart-246eebf5-5129-4d55-8c56-2dcc688013fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319618302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3319618302
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3283272406
Short name T588
Test name
Test status
Simulation time 142024183 ps
CPU time 6.47 seconds
Started Jul 24 07:03:39 PM PDT 24
Finished Jul 24 07:03:45 PM PDT 24
Peak memory 209328 kb
Host smart-53c609e1-929f-4b64-bafd-e8abbafb9eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283272406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3283272406
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4193577828
Short name T860
Test name
Test status
Simulation time 2245834409 ps
CPU time 31.4 seconds
Started Jul 24 07:03:43 PM PDT 24
Finished Jul 24 07:04:14 PM PDT 24
Peak memory 209512 kb
Host smart-b86b207b-944e-42c2-9d38-d480aaf86448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193577828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4193577828
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.970657181
Short name T546
Test name
Test status
Simulation time 78703247 ps
CPU time 2.63 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 210148 kb
Host smart-f4f507e1-85b0-420e-8b41-031833b75d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970657181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.970657181
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2504385541
Short name T523
Test name
Test status
Simulation time 20579650 ps
CPU time 1.02 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:45 PM PDT 24
Peak memory 205968 kb
Host smart-33cc15ed-b0ea-49db-afb9-e0ac65ae7fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504385541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2504385541
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2633258739
Short name T799
Test name
Test status
Simulation time 225803679 ps
CPU time 4.26 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 219280 kb
Host smart-41ee737d-f939-4cb6-8b01-390aff60bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633258739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2633258739
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2519032114
Short name T4
Test name
Test status
Simulation time 81955133 ps
CPU time 3.47 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 217992 kb
Host smart-d9d647e1-6c6e-4300-809f-ffc37cf71555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519032114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2519032114
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1004010889
Short name T699
Test name
Test status
Simulation time 107827313 ps
CPU time 4.56 seconds
Started Jul 24 07:03:48 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 220844 kb
Host smart-a183ae74-2aa9-4b0c-805e-6901b8bf919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004010889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1004010889
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.3590057407
Short name T608
Test name
Test status
Simulation time 50740109 ps
CPU time 3.27 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:47 PM PDT 24
Peak memory 207444 kb
Host smart-c44187a7-3c7f-4208-8fed-344ea1488d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590057407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3590057407
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1238887856
Short name T40
Test name
Test status
Simulation time 660010831 ps
CPU time 14.18 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:04:00 PM PDT 24
Peak memory 234304 kb
Host smart-f3cededf-5cff-4e57-b909-cf0fa2325690
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238887856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1238887856
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1607049021
Short name T595
Test name
Test status
Simulation time 61404954 ps
CPU time 2.89 seconds
Started Jul 24 07:03:49 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 206708 kb
Host smart-e4b35c37-1832-4baf-ad65-528d43cf4534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607049021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1607049021
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3192927345
Short name T433
Test name
Test status
Simulation time 217442561 ps
CPU time 2.68 seconds
Started Jul 24 07:03:47 PM PDT 24
Finished Jul 24 07:03:50 PM PDT 24
Peak memory 206656 kb
Host smart-1f31730a-8e3e-4199-99c5-ed1ad17b631f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192927345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3192927345
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3599673521
Short name T557
Test name
Test status
Simulation time 93670109 ps
CPU time 4.15 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 208628 kb
Host smart-a051b31a-375f-4a65-9879-6bc30f199560
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599673521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3599673521
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3668945962
Short name T350
Test name
Test status
Simulation time 202564091 ps
CPU time 7.74 seconds
Started Jul 24 07:03:50 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 208516 kb
Host smart-7bf95b72-20ce-485d-86e9-acf68329a702
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668945962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3668945962
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.713861335
Short name T12
Test name
Test status
Simulation time 139899847 ps
CPU time 2.65 seconds
Started Jul 24 07:03:47 PM PDT 24
Finished Jul 24 07:03:50 PM PDT 24
Peak memory 209224 kb
Host smart-398a4f69-c862-4587-beef-b2bdf8e522cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713861335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.713861335
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4270471981
Short name T610
Test name
Test status
Simulation time 32552027 ps
CPU time 1.87 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:47 PM PDT 24
Peak memory 206548 kb
Host smart-1a5fc962-387e-4052-a2ff-9e7aaec99555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270471981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4270471981
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.643238518
Short name T264
Test name
Test status
Simulation time 90334664 ps
CPU time 4.11 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:50 PM PDT 24
Peak memory 207956 kb
Host smart-62d764d4-ca36-41c9-87f2-a3a5ba87122a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643238518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.643238518
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3662669596
Short name T57
Test name
Test status
Simulation time 729211475 ps
CPU time 8.62 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 210188 kb
Host smart-92b3b520-6d45-416b-be53-c39fc6e288b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662669596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3662669596
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1613570795
Short name T637
Test name
Test status
Simulation time 13325565 ps
CPU time 0.81 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:04:24 PM PDT 24
Peak memory 205776 kb
Host smart-9943f469-42c2-4911-a82a-a68533904d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613570795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1613570795
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3882857686
Short name T297
Test name
Test status
Simulation time 122103370 ps
CPU time 3 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 215040 kb
Host smart-8a9b7753-a543-491c-97ed-c70513ec340b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882857686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3882857686
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3571718912
Short name T831
Test name
Test status
Simulation time 273324911 ps
CPU time 3.21 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:28 PM PDT 24
Peak memory 207600 kb
Host smart-8bc0b7e0-1ad0-43ac-85bd-fa69dca7c7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571718912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3571718912
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3338947266
Short name T365
Test name
Test status
Simulation time 98904688 ps
CPU time 4.48 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:27 PM PDT 24
Peak memory 209208 kb
Host smart-e0a43c34-0b49-49b5-b66b-6293cee22e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338947266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3338947266
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2572570705
Short name T260
Test name
Test status
Simulation time 46383055 ps
CPU time 3.13 seconds
Started Jul 24 07:04:25 PM PDT 24
Finished Jul 24 07:04:28 PM PDT 24
Peak memory 213992 kb
Host smart-3b74b5fb-2139-4491-9950-35c510e89fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572570705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2572570705
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2775021434
Short name T665
Test name
Test status
Simulation time 853669557 ps
CPU time 3.34 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:25 PM PDT 24
Peak memory 214544 kb
Host smart-41695a3e-dc98-4e43-bb26-e9f49fc8a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775021434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2775021434
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2411430323
Short name T315
Test name
Test status
Simulation time 662129343 ps
CPU time 7.97 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 207300 kb
Host smart-6d95620a-2c2e-45f7-93d5-dd554159c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411430323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2411430323
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1039385143
Short name T533
Test name
Test status
Simulation time 439035669 ps
CPU time 9.12 seconds
Started Jul 24 07:04:21 PM PDT 24
Finished Jul 24 07:04:31 PM PDT 24
Peak memory 207756 kb
Host smart-79997cd9-900b-4211-b32d-d8e7a42e09c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039385143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1039385143
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1359276569
Short name T278
Test name
Test status
Simulation time 135532236 ps
CPU time 2.63 seconds
Started Jul 24 07:04:21 PM PDT 24
Finished Jul 24 07:04:24 PM PDT 24
Peak memory 208500 kb
Host smart-1fb7d5b1-e729-4263-bf0c-06c34f7a8403
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359276569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1359276569
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2197462952
Short name T463
Test name
Test status
Simulation time 171798040 ps
CPU time 3.94 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:29 PM PDT 24
Peak memory 208704 kb
Host smart-43b14734-70fb-4d31-b8b9-b4b92f37ff02
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197462952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2197462952
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2874960553
Short name T603
Test name
Test status
Simulation time 248867246 ps
CPU time 3.17 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:04:27 PM PDT 24
Peak memory 208392 kb
Host smart-ef8f5a6c-c120-470c-b48a-10a72c1a0d1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874960553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2874960553
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.677692930
Short name T537
Test name
Test status
Simulation time 23664947 ps
CPU time 1.79 seconds
Started Jul 24 07:04:21 PM PDT 24
Finished Jul 24 07:04:24 PM PDT 24
Peak memory 207624 kb
Host smart-c91b7b4b-378d-4255-b124-f323cffd7809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677692930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.677692930
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1217335464
Short name T869
Test name
Test status
Simulation time 411370022 ps
CPU time 4.91 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:27 PM PDT 24
Peak memory 208368 kb
Host smart-99bf31b5-58f1-41cb-a19c-5073db8fe8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217335464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1217335464
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3804263597
Short name T58
Test name
Test status
Simulation time 489572504 ps
CPU time 18.17 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 216136 kb
Host smart-a25f96cb-f35e-4aa1-9743-ff00ba3faf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804263597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3804263597
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3651933247
Short name T276
Test name
Test status
Simulation time 182941701 ps
CPU time 4.39 seconds
Started Jul 24 07:04:25 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 208760 kb
Host smart-f577cdc7-b86f-41aa-a7d2-45e8cfd6ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651933247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3651933247
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2092856245
Short name T32
Test name
Test status
Simulation time 49673274 ps
CPU time 1.7 seconds
Started Jul 24 07:04:21 PM PDT 24
Finished Jul 24 07:04:23 PM PDT 24
Peak memory 209580 kb
Host smart-e231fc76-aefd-4b6e-a2ec-79874bc5a2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092856245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2092856245
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3288631451
Short name T476
Test name
Test status
Simulation time 21600901 ps
CPU time 0.71 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 205864 kb
Host smart-cc735f65-a371-4dcf-94cc-8780f4149c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288631451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3288631451
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3218395849
Short name T915
Test name
Test status
Simulation time 775135525 ps
CPU time 23.17 seconds
Started Jul 24 07:04:30 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 214432 kb
Host smart-56ae5299-98d4-4d0a-a7a6-9d9446534c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218395849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3218395849
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3478397515
Short name T515
Test name
Test status
Simulation time 1218093668 ps
CPU time 11.73 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:49 PM PDT 24
Peak memory 218116 kb
Host smart-6b6e9671-4b74-4a5a-b78b-78814b0a4a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478397515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3478397515
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3328443799
Short name T499
Test name
Test status
Simulation time 1472178762 ps
CPU time 14.6 seconds
Started Jul 24 07:04:28 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 208980 kb
Host smart-0c22144a-0cb1-426f-ae26-e8c57f781dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328443799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3328443799
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.198135432
Short name T861
Test name
Test status
Simulation time 61072779 ps
CPU time 3.68 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:35 PM PDT 24
Peak memory 221128 kb
Host smart-fccfd234-bd46-4cdd-803c-aefdd8c844cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198135432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.198135432
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3632561124
Short name T837
Test name
Test status
Simulation time 214214516 ps
CPU time 4.51 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:33 PM PDT 24
Peak memory 222140 kb
Host smart-d3d9e30e-f091-4815-8a9a-1cb54683411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632561124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3632561124
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.2009938164
Short name T293
Test name
Test status
Simulation time 150698575 ps
CPU time 4.98 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 209544 kb
Host smart-b82b7666-79de-4c10-9cfd-c0374e0f2454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009938164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2009938164
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3750651860
Short name T564
Test name
Test status
Simulation time 333154271 ps
CPU time 3.04 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 206444 kb
Host smart-c48f7961-06e4-4ff5-8fc1-f646d0060b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750651860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3750651860
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.519260384
Short name T720
Test name
Test status
Simulation time 75408690 ps
CPU time 3.23 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 208424 kb
Host smart-393984a2-17a1-486c-b8a4-f3da85701895
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519260384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.519260384
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1195202134
Short name T3
Test name
Test status
Simulation time 30284345 ps
CPU time 1.91 seconds
Started Jul 24 07:04:32 PM PDT 24
Finished Jul 24 07:04:34 PM PDT 24
Peak memory 209276 kb
Host smart-140067dc-6e3f-4019-9d98-483f8898724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195202134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1195202134
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.447064462
Short name T440
Test name
Test status
Simulation time 1096114262 ps
CPU time 30.78 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 207864 kb
Host smart-7a21155c-2aac-4b51-a367-8241815361d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447064462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.447064462
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1158362033
Short name T711
Test name
Test status
Simulation time 822735977 ps
CPU time 28.87 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:05:02 PM PDT 24
Peak memory 222256 kb
Host smart-9ac36fb1-e64d-451f-9f45-3d40129db8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158362033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1158362033
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3223990654
Short name T216
Test name
Test status
Simulation time 286216621 ps
CPU time 7.75 seconds
Started Jul 24 07:04:32 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 208872 kb
Host smart-50d7f084-e161-457d-93f1-1f227d9bd158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223990654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3223990654
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2407523758
Short name T521
Test name
Test status
Simulation time 159037453 ps
CPU time 2.29 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:35 PM PDT 24
Peak memory 209788 kb
Host smart-405440ee-abd4-48b5-889c-2b323a4d3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407523758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2407523758
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.712990576
Short name T848
Test name
Test status
Simulation time 16229840 ps
CPU time 0.76 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:31 PM PDT 24
Peak memory 205844 kb
Host smart-ca16831d-2389-4d18-b4dd-675d067d4343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712990576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.712990576
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1910233404
Short name T868
Test name
Test status
Simulation time 68910465 ps
CPU time 2.87 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:33 PM PDT 24
Peak memory 209064 kb
Host smart-e7067f02-4150-4788-9f39-be7b8ca1db64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910233404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1910233404
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2272940204
Short name T775
Test name
Test status
Simulation time 512227314 ps
CPU time 3.46 seconds
Started Jul 24 07:04:30 PM PDT 24
Finished Jul 24 07:04:34 PM PDT 24
Peak memory 220232 kb
Host smart-e746dd01-a131-48c2-ae7f-7a279e486566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272940204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2272940204
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.863955559
Short name T792
Test name
Test status
Simulation time 52102605 ps
CPU time 2.93 seconds
Started Jul 24 07:04:39 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 207212 kb
Host smart-2db95e12-fed7-43a9-85ad-1b8663cd29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863955559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.863955559
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2978505768
Short name T259
Test name
Test status
Simulation time 815914897 ps
CPU time 3.34 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:34 PM PDT 24
Peak memory 208332 kb
Host smart-33aea38e-41ab-48d1-a083-f7d34f964d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978505768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2978505768
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1524869088
Short name T676
Test name
Test status
Simulation time 53526977 ps
CPU time 2.05 seconds
Started Jul 24 07:04:34 PM PDT 24
Finished Jul 24 07:04:36 PM PDT 24
Peak memory 206764 kb
Host smart-83c1322c-81e0-46d3-a2a2-5eef1147c551
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524869088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1524869088
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.770773573
Short name T222
Test name
Test status
Simulation time 1475607486 ps
CPU time 5.32 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:34 PM PDT 24
Peak memory 207612 kb
Host smart-4cace745-7048-40a7-8d80-cb5d7bc1d3f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770773573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.770773573
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2045421435
Short name T624
Test name
Test status
Simulation time 2256020904 ps
CPU time 8.7 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 208900 kb
Host smart-98721e38-ec7b-4304-ab7d-b8ea3d6a6124
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045421435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2045421435
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3907079766
Short name T133
Test name
Test status
Simulation time 452270978 ps
CPU time 3.25 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:37 PM PDT 24
Peak memory 208416 kb
Host smart-73a063be-94f9-4f98-8878-a8feff8b7891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907079766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3907079766
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3148136700
Short name T447
Test name
Test status
Simulation time 511743431 ps
CPU time 5.24 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:39 PM PDT 24
Peak memory 206728 kb
Host smart-63270385-03f0-48c8-a5f4-bd16acd098a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148136700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3148136700
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3610963767
Short name T466
Test name
Test status
Simulation time 148585541 ps
CPU time 5.95 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:39 PM PDT 24
Peak memory 208944 kb
Host smart-78705b6d-96c5-4102-9e96-197a9cf4110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610963767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3610963767
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3820651909
Short name T784
Test name
Test status
Simulation time 197410941 ps
CPU time 2.56 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:36 PM PDT 24
Peak memory 209928 kb
Host smart-c2955b6c-3189-41af-bd41-52be8232d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820651909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3820651909
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1011592180
Short name T594
Test name
Test status
Simulation time 8994018 ps
CPU time 0.87 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 205816 kb
Host smart-24a73a52-b098-42db-b184-e5f882836f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011592180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1011592180
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2286320363
Short name T791
Test name
Test status
Simulation time 1541814345 ps
CPU time 78.19 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:05:51 PM PDT 24
Peak memory 214848 kb
Host smart-0f359655-8804-43dc-99b9-535ca6373a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286320363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2286320363
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3235427859
Short name T105
Test name
Test status
Simulation time 358268182 ps
CPU time 7.69 seconds
Started Jul 24 07:04:30 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 209524 kb
Host smart-a26049db-eea3-48cd-8faa-08453f043f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235427859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3235427859
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.749863761
Short name T723
Test name
Test status
Simulation time 50795329 ps
CPU time 1.99 seconds
Started Jul 24 07:04:28 PM PDT 24
Finished Jul 24 07:04:30 PM PDT 24
Peak memory 208040 kb
Host smart-82fa9be8-fac7-4c3b-acc7-5de0e21d34f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749863761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.749863761
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1658523291
Short name T823
Test name
Test status
Simulation time 1615411294 ps
CPU time 7.98 seconds
Started Jul 24 07:04:38 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 211588 kb
Host smart-1fc56d05-b8bc-4db7-8b7b-c3ba037723e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658523291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1658523291
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.788246990
Short name T795
Test name
Test status
Simulation time 97852281 ps
CPU time 2.28 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:33 PM PDT 24
Peak memory 208348 kb
Host smart-6c14cb89-755c-46af-85c0-27df6160255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788246990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.788246990
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.833082403
Short name T159
Test name
Test status
Simulation time 1296886445 ps
CPU time 7.13 seconds
Started Jul 24 07:04:32 PM PDT 24
Finished Jul 24 07:04:39 PM PDT 24
Peak memory 208224 kb
Host smart-5dcf035e-f454-480e-ac7a-20447d3f095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833082403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.833082403
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2646999670
Short name T739
Test name
Test status
Simulation time 51546375 ps
CPU time 2.88 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 206596 kb
Host smart-7bb58171-33d7-49ad-ac95-b5d9243fea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646999670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2646999670
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2337267597
Short name T700
Test name
Test status
Simulation time 3428225351 ps
CPU time 22.84 seconds
Started Jul 24 07:04:34 PM PDT 24
Finished Jul 24 07:04:57 PM PDT 24
Peak memory 208428 kb
Host smart-54617c52-3002-4958-9881-110a2b6dcef1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337267597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2337267597
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3998478437
Short name T392
Test name
Test status
Simulation time 89754918 ps
CPU time 3.37 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:35 PM PDT 24
Peak memory 207780 kb
Host smart-a73473d4-8ce6-46f4-bf6d-a188c85b9ea3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998478437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3998478437
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2306655459
Short name T115
Test name
Test status
Simulation time 75891755 ps
CPU time 2.46 seconds
Started Jul 24 07:04:30 PM PDT 24
Finished Jul 24 07:04:33 PM PDT 24
Peak memory 208344 kb
Host smart-69b3d792-7904-454e-9cf2-0abd4e913486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306655459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2306655459
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.248230498
Short name T912
Test name
Test status
Simulation time 87779828 ps
CPU time 2.88 seconds
Started Jul 24 07:04:31 PM PDT 24
Finished Jul 24 07:04:34 PM PDT 24
Peak memory 206572 kb
Host smart-152548c8-ebb9-49e2-befc-feb9038ba4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248230498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.248230498
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2811303959
Short name T211
Test name
Test status
Simulation time 7799539420 ps
CPU time 31.92 seconds
Started Jul 24 07:04:32 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 215956 kb
Host smart-17973494-5849-4488-bccf-9262f227ded9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811303959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2811303959
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3832957975
Short name T15
Test name
Test status
Simulation time 175117818 ps
CPU time 6.51 seconds
Started Jul 24 07:04:29 PM PDT 24
Finished Jul 24 07:04:36 PM PDT 24
Peak memory 217548 kb
Host smart-586ec2e1-ed68-40f0-b93d-e9fc592eb886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832957975 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3832957975
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.302785806
Short name T620
Test name
Test status
Simulation time 818722788 ps
CPU time 7.2 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 210176 kb
Host smart-2f251b0d-492b-42de-96d1-c4fecf2bc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302785806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.302785806
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4227387288
Short name T426
Test name
Test status
Simulation time 83639531 ps
CPU time 0.72 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 205828 kb
Host smart-ea17acdc-5288-41ae-b821-69873de70306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227387288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4227387288
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4225469015
Short name T524
Test name
Test status
Simulation time 460934386 ps
CPU time 3.73 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 219880 kb
Host smart-ad37d1cd-da59-4c9e-b475-40f4946b6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225469015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4225469015
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2696293466
Short name T76
Test name
Test status
Simulation time 27619230 ps
CPU time 1.99 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:44 PM PDT 24
Peak memory 207384 kb
Host smart-c11ab615-a4cb-4b5a-942b-d8cd13bbb76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696293466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2696293466
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1161015426
Short name T372
Test name
Test status
Simulation time 43458471 ps
CPU time 2.66 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:44 PM PDT 24
Peak memory 214164 kb
Host smart-dd25737c-21e6-4707-8912-2dc0618423df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161015426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1161015426
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1049169439
Short name T56
Test name
Test status
Simulation time 169885163 ps
CPU time 3.39 seconds
Started Jul 24 07:04:39 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 209376 kb
Host smart-4e8fd89e-2f25-4d84-b425-eb24a0af2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049169439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1049169439
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.288089361
Short name T281
Test name
Test status
Simulation time 112989488 ps
CPU time 4.21 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 207804 kb
Host smart-d05e7336-54fd-4d7c-a9c8-88190919c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288089361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.288089361
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2161846445
Short name T573
Test name
Test status
Simulation time 122066162 ps
CPU time 3.45 seconds
Started Jul 24 07:04:34 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 207832 kb
Host smart-20d26ecc-e441-464d-a26a-77a71612b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161846445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2161846445
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3690365573
Short name T740
Test name
Test status
Simulation time 7029154055 ps
CPU time 62.07 seconds
Started Jul 24 07:04:38 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 209216 kb
Host smart-f87c7bd6-008c-42c6-943a-858f2348f54d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690365573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3690365573
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3407461977
Short name T814
Test name
Test status
Simulation time 20115714 ps
CPU time 1.82 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 206812 kb
Host smart-6ecabaf7-56e6-42e1-b052-452e864a78cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407461977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3407461977
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1259254799
Short name T824
Test name
Test status
Simulation time 1948731528 ps
CPU time 14 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:50 PM PDT 24
Peak memory 208008 kb
Host smart-8e92addb-35df-4f92-99c1-905dff292742
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259254799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1259254799
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2130036995
Short name T606
Test name
Test status
Simulation time 203500236 ps
CPU time 2.26 seconds
Started Jul 24 07:04:35 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 208668 kb
Host smart-79bcb5ae-bdb3-41ef-adfe-c6940365395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130036995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2130036995
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2478775292
Short name T719
Test name
Test status
Simulation time 4766830000 ps
CPU time 20.13 seconds
Started Jul 24 07:04:33 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 207844 kb
Host smart-e3b64dd8-e40f-4346-97c8-3c03e4c410d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478775292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2478775292
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1962447852
Short name T106
Test name
Test status
Simulation time 421151877 ps
CPU time 14.24 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:52 PM PDT 24
Peak memory 215568 kb
Host smart-5b27c2be-8aed-4f0f-8ef2-3f2888d2321d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962447852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1962447852
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1901586696
Short name T177
Test name
Test status
Simulation time 39083066 ps
CPU time 1.91 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 210144 kb
Host smart-a13740ff-c951-4a2e-bfc2-ef7155065691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901586696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1901586696
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.670676645
Short name T625
Test name
Test status
Simulation time 55982751 ps
CPU time 0.88 seconds
Started Jul 24 07:04:52 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 205848 kb
Host smart-75621893-76b2-414a-bf4e-9c9f0df72dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670676645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.670676645
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2661765576
Short name T82
Test name
Test status
Simulation time 708466399 ps
CPU time 9.6 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:52 PM PDT 24
Peak memory 214108 kb
Host smart-b055270e-af85-4df0-94f3-75e23754263e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661765576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2661765576
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2139474769
Short name T881
Test name
Test status
Simulation time 390909815 ps
CPU time 7.79 seconds
Started Jul 24 07:04:40 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 222540 kb
Host smart-df71db8f-fba2-4a9f-95c1-7e70f217c6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139474769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2139474769
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3118293737
Short name T818
Test name
Test status
Simulation time 71588205 ps
CPU time 2.23 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:39 PM PDT 24
Peak memory 209308 kb
Host smart-97346247-b531-497e-bea3-b26f182117ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118293737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3118293737
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4213458671
Short name T343
Test name
Test status
Simulation time 104279831 ps
CPU time 1.7 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:38 PM PDT 24
Peak memory 214096 kb
Host smart-bd5deb8b-05a7-4e67-8672-28162df4b798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213458671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4213458671
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3811917252
Short name T111
Test name
Test status
Simulation time 92807312 ps
CPU time 3.41 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 214088 kb
Host smart-c22579a8-1201-4637-9abd-3da02e7407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811917252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3811917252
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.559031213
Short name T532
Test name
Test status
Simulation time 312825741 ps
CPU time 3.45 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 215216 kb
Host smart-3c041afa-e9f3-4e2f-a69a-43f9683f282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559031213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.559031213
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2730712869
Short name T682
Test name
Test status
Simulation time 2641086281 ps
CPU time 46.32 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 209024 kb
Host smart-83cf72b9-8353-4052-becf-1b76525f2338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730712869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2730712869
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1395128908
Short name T138
Test name
Test status
Simulation time 4120858975 ps
CPU time 22.39 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:05:08 PM PDT 24
Peak memory 208132 kb
Host smart-784cd33b-255d-43a9-9c12-81b4f29910e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395128908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1395128908
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3564099576
Short name T843
Test name
Test status
Simulation time 503940553 ps
CPU time 8.36 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:04:44 PM PDT 24
Peak memory 208732 kb
Host smart-bc740284-264f-4982-b672-7214b11914ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564099576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3564099576
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2727339472
Short name T562
Test name
Test status
Simulation time 658824252 ps
CPU time 5.16 seconds
Started Jul 24 07:04:52 PM PDT 24
Finished Jul 24 07:04:57 PM PDT 24
Peak memory 208640 kb
Host smart-211310b2-5ab4-4def-8912-fe05040cd53d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727339472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2727339472
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1356351467
Short name T870
Test name
Test status
Simulation time 3693178718 ps
CPU time 49.75 seconds
Started Jul 24 07:04:38 PM PDT 24
Finished Jul 24 07:05:28 PM PDT 24
Peak memory 208324 kb
Host smart-64558f30-4b44-43d3-ac62-a710d4bfeb31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356351467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1356351467
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3603581777
Short name T429
Test name
Test status
Simulation time 199630787 ps
CPU time 2.19 seconds
Started Jul 24 07:04:51 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 214056 kb
Host smart-fdfded69-c9ca-477d-aac3-2b7a59765312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603581777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3603581777
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2725188453
Short name T474
Test name
Test status
Simulation time 91205721 ps
CPU time 3.07 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:40 PM PDT 24
Peak memory 206448 kb
Host smart-12fabd3c-39a4-48ad-acdd-be1261f83c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725188453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2725188453
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2968689058
Short name T780
Test name
Test status
Simulation time 5218224928 ps
CPU time 30.57 seconds
Started Jul 24 07:04:36 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 215664 kb
Host smart-7c1cb8a0-1a76-4bc1-a5ef-6650d8cf76a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968689058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2968689058
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.584662733
Short name T356
Test name
Test status
Simulation time 66903754 ps
CPU time 3.99 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 218060 kb
Host smart-d7c1be12-1826-4ecf-a846-c3efe6b2a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584662733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.584662733
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.783304220
Short name T135
Test name
Test status
Simulation time 120287130 ps
CPU time 2.6 seconds
Started Jul 24 07:04:39 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 210184 kb
Host smart-7b29a5e6-9f7d-4354-b53e-07e0cc0cd998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783304220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.783304220
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1724975926
Short name T892
Test name
Test status
Simulation time 13042219 ps
CPU time 0.87 seconds
Started Jul 24 07:04:40 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 205812 kb
Host smart-a488b290-0f1d-4c9a-b751-272d6d35d6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724975926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1724975926
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.694568374
Short name T593
Test name
Test status
Simulation time 1477621911 ps
CPU time 7.46 seconds
Started Jul 24 07:04:35 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 216684 kb
Host smart-e993393f-44d8-4946-8cf4-965a50564b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694568374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.694568374
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2315304569
Short name T545
Test name
Test status
Simulation time 110080230 ps
CPU time 1.88 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 206880 kb
Host smart-6c4ff38c-abbe-4764-a3fa-dfa08ea0f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315304569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2315304569
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2503682277
Short name T94
Test name
Test status
Simulation time 682308738 ps
CPU time 4.46 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 214128 kb
Host smart-17a13460-ee18-47be-aec0-bc88a84ac297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503682277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2503682277
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2849170289
Short name T364
Test name
Test status
Simulation time 334555390 ps
CPU time 4.85 seconds
Started Jul 24 07:04:53 PM PDT 24
Finished Jul 24 07:04:58 PM PDT 24
Peak memory 205836 kb
Host smart-806f9e0f-5021-48b4-a3c7-94540dd1b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849170289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2849170289
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3229024218
Short name T348
Test name
Test status
Simulation time 152261168 ps
CPU time 4.96 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 222140 kb
Host smart-c2bba349-1d81-4aeb-84d6-4223813dd87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229024218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3229024218
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3276002968
Short name T630
Test name
Test status
Simulation time 98051172 ps
CPU time 3.94 seconds
Started Jul 24 07:04:53 PM PDT 24
Finished Jul 24 07:04:57 PM PDT 24
Peak memory 207764 kb
Host smart-87aadb46-c6d4-4af7-b9cd-37de87700b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276002968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3276002968
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2258809053
Short name T481
Test name
Test status
Simulation time 889725568 ps
CPU time 18.88 seconds
Started Jul 24 07:04:52 PM PDT 24
Finished Jul 24 07:05:11 PM PDT 24
Peak memory 207724 kb
Host smart-28bfb398-7083-4aa6-a90d-d51f0af49d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258809053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2258809053
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3505108129
Short name T737
Test name
Test status
Simulation time 681844309 ps
CPU time 5.97 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 207184 kb
Host smart-c185795c-f527-46b1-a1f0-578aacb20810
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505108129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3505108129
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.773889783
Short name T677
Test name
Test status
Simulation time 85811824 ps
CPU time 3.56 seconds
Started Jul 24 07:04:50 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 208180 kb
Host smart-f2b05a20-1fb3-40ce-ac99-060da7651610
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773889783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.773889783
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2246952338
Short name T663
Test name
Test status
Simulation time 250900660 ps
CPU time 3.35 seconds
Started Jul 24 07:04:37 PM PDT 24
Finished Jul 24 07:04:41 PM PDT 24
Peak memory 208456 kb
Host smart-bb857dcd-fb2d-4af5-b4a4-8f04d8de1ffb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246952338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2246952338
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1780600177
Short name T543
Test name
Test status
Simulation time 298595279 ps
CPU time 3.68 seconds
Started Jul 24 07:04:51 PM PDT 24
Finished Jul 24 07:04:55 PM PDT 24
Peak memory 215600 kb
Host smart-2aa27636-e03d-4499-951b-3908dd6590d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780600177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1780600177
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1010980386
Short name T589
Test name
Test status
Simulation time 162144461 ps
CPU time 3.75 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 207948 kb
Host smart-da179098-73fb-4db9-b9f4-f60e3bf4342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010980386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1010980386
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2428098927
Short name T317
Test name
Test status
Simulation time 12911563193 ps
CPU time 71.64 seconds
Started Jul 24 07:04:38 PM PDT 24
Finished Jul 24 07:05:50 PM PDT 24
Peak memory 216060 kb
Host smart-491fd8d5-4cc6-41ce-a755-edf50d0357a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428098927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2428098927
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.239574636
Short name T752
Test name
Test status
Simulation time 109315724 ps
CPU time 6.4 seconds
Started Jul 24 07:04:38 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 222396 kb
Host smart-56cae0cf-4d58-4661-ae56-c9bc445cef4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239574636 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.239574636
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.845438153
Short name T303
Test name
Test status
Simulation time 69670809 ps
CPU time 3.44 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 207832 kb
Host smart-b183087b-b65e-4e3d-870f-4d1e8d7b84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845438153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.845438153
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1141468506
Short name T402
Test name
Test status
Simulation time 2717676800 ps
CPU time 10.95 seconds
Started Jul 24 07:04:35 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 210980 kb
Host smart-64f1028d-57ad-45d9-a9df-03257ed74a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141468506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1141468506
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1034365235
Short name T473
Test name
Test status
Simulation time 11310760 ps
CPU time 0.87 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 205844 kb
Host smart-de1000f0-3cd9-4c9b-9323-c1f784d2fbf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034365235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1034365235
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3651428611
Short name T294
Test name
Test status
Simulation time 200816002 ps
CPU time 3.77 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 214880 kb
Host smart-531c9979-ccdc-4c5a-8004-42b6a84edd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651428611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3651428611
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.856024374
Short name T17
Test name
Test status
Simulation time 646282271 ps
CPU time 4.22 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208316 kb
Host smart-d8b2f407-8384-4ccb-b88c-6af40d15f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856024374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.856024374
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2393923015
Short name T850
Test name
Test status
Simulation time 54884835 ps
CPU time 2.48 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:04:51 PM PDT 24
Peak memory 207672 kb
Host smart-e95969f1-c07f-48f7-a926-c989b18add3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393923015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2393923015
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.839488369
Short name T867
Test name
Test status
Simulation time 347391446 ps
CPU time 2.99 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 214068 kb
Host smart-eb95a367-65e1-439d-89e5-ed7a47b8642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839488369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.839488369
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2723087806
Short name T730
Test name
Test status
Simulation time 64459121 ps
CPU time 2.24 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 213988 kb
Host smart-7866b692-93bf-4202-a9fe-c0e9cfb4a6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723087806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2723087806
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.2229360249
Short name T299
Test name
Test status
Simulation time 146557491 ps
CPU time 2.54 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 207932 kb
Host smart-f82ee2ab-1765-410b-905a-4959708dc94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229360249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2229360249
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3089659872
Short name T349
Test name
Test status
Simulation time 64813276 ps
CPU time 3.36 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208044 kb
Host smart-5471d76e-a3c5-4789-b2f4-e2570d9769ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089659872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3089659872
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3609968588
Short name T822
Test name
Test status
Simulation time 39239935 ps
CPU time 2.29 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 206716 kb
Host smart-9b1e467b-0645-4d07-876f-1de4a5cbf45a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609968588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3609968588
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2417446510
Short name T511
Test name
Test status
Simulation time 670156890 ps
CPU time 9.72 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:55 PM PDT 24
Peak memory 206952 kb
Host smart-e1e23fba-21f3-4b3d-a638-68c6e94d26f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417446510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2417446510
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1743457006
Short name T496
Test name
Test status
Simulation time 815022040 ps
CPU time 25.62 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 207584 kb
Host smart-6aa5420d-49d2-4793-a05d-4d34d400fed4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743457006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1743457006
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1650100658
Short name T733
Test name
Test status
Simulation time 32816089 ps
CPU time 2.2 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 209200 kb
Host smart-dcc4780a-f52d-4ab6-b459-39ce16e9374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650100658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1650100658
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2663550521
Short name T160
Test name
Test status
Simulation time 152714292 ps
CPU time 2.39 seconds
Started Jul 24 07:04:40 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 208272 kb
Host smart-f62e8a84-a57b-4a42-b536-ac0e9515cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663550521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2663550521
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3805066162
Short name T53
Test name
Test status
Simulation time 2151771643 ps
CPU time 58.61 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 216572 kb
Host smart-04764f8b-2137-4bf2-8e90-5aa5cf8c2a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805066162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3805066162
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3914775007
Short name T239
Test name
Test status
Simulation time 2463752169 ps
CPU time 20.71 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 219788 kb
Host smart-921ac011-28b9-415d-8792-3afa6475c585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914775007 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3914775007
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1846398201
Short name T298
Test name
Test status
Simulation time 37899276 ps
CPU time 2.71 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 214052 kb
Host smart-45209b8b-4a52-4039-8b09-a9ccf0f31630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846398201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1846398201
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2639052530
Short name T384
Test name
Test status
Simulation time 86141134 ps
CPU time 1.8 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 209640 kb
Host smart-1109f23c-7266-42df-b0da-de2b58a9860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639052530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2639052530
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1961596883
Short name T777
Test name
Test status
Simulation time 79296341 ps
CPU time 0.75 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:44 PM PDT 24
Peak memory 205764 kb
Host smart-55a699ba-eeda-417a-83b3-5d18a83b5c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961596883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1961596883
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2863892595
Short name T283
Test name
Test status
Simulation time 108914886 ps
CPU time 4.07 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 215028 kb
Host smart-f5b74f4f-c56b-4733-8ab8-aad278fec0e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863892595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2863892595
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2682046168
Short name T577
Test name
Test status
Simulation time 143486637 ps
CPU time 3.8 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 221600 kb
Host smart-a0a96197-e7d9-43a8-846e-cae64bebcc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682046168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2682046168
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2682123908
Short name T566
Test name
Test status
Simulation time 93924043 ps
CPU time 3.95 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 218012 kb
Host smart-43c2d9a9-e9a2-4f14-b062-bb45c1499a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682123908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2682123908
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1201544129
Short name T909
Test name
Test status
Simulation time 131857315 ps
CPU time 1.81 seconds
Started Jul 24 07:05:04 PM PDT 24
Finished Jul 24 07:05:06 PM PDT 24
Peak memory 214144 kb
Host smart-23c69674-ef3b-46ea-85d0-dae271408935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201544129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1201544129
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3401233510
Short name T289
Test name
Test status
Simulation time 150025525 ps
CPU time 5.65 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:49 PM PDT 24
Peak memory 214036 kb
Host smart-7c7ca1ac-b2f3-4880-ae56-1a6a520175f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401233510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3401233510
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1891856605
Short name T886
Test name
Test status
Simulation time 500358216 ps
CPU time 3.9 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 217876 kb
Host smart-0cd5eb3e-d605-43ae-a978-77a698478991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891856605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1891856605
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3300675489
Short name T651
Test name
Test status
Simulation time 925371361 ps
CPU time 9.54 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:52 PM PDT 24
Peak memory 218228 kb
Host smart-c19c352b-39a7-4458-b6dd-d8dcae36008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300675489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3300675489
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1650609425
Short name T807
Test name
Test status
Simulation time 2839087690 ps
CPU time 10.84 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 208452 kb
Host smart-045dafd1-4c8e-41f9-9a84-0265e4a55e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650609425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1650609425
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2017494880
Short name T443
Test name
Test status
Simulation time 124278334 ps
CPU time 3.38 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208388 kb
Host smart-03ceb25e-1b18-4cc8-b5c0-af7353ec913d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017494880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2017494880
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3004800354
Short name T732
Test name
Test status
Simulation time 83313541 ps
CPU time 2.92 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:47 PM PDT 24
Peak memory 208208 kb
Host smart-46b6b4b9-fece-4115-93bb-f1f6548726d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004800354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3004800354
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1244969187
Short name T726
Test name
Test status
Simulation time 277455783 ps
CPU time 3.54 seconds
Started Jul 24 07:04:42 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208576 kb
Host smart-6c677e01-0b39-4169-92b4-762b2bf3e8d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244969187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1244969187
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2863432981
Short name T277
Test name
Test status
Simulation time 97520036 ps
CPU time 3.87 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:04:48 PM PDT 24
Peak memory 217936 kb
Host smart-f928332f-664f-4e0b-8dd0-f0bdce74b90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863432981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2863432981
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.47651279
Short name T202
Test name
Test status
Simulation time 228627346 ps
CPU time 2.66 seconds
Started Jul 24 07:04:46 PM PDT 24
Finished Jul 24 07:04:49 PM PDT 24
Peak memory 207796 kb
Host smart-aa461dfd-6bd1-49d1-b9f8-6ffb181fcbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47651279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.47651279
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3761886101
Short name T783
Test name
Test status
Simulation time 13011226510 ps
CPU time 75.82 seconds
Started Jul 24 07:04:44 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 222340 kb
Host smart-c33f808b-a7eb-4a09-8d8a-94f4bae53dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761886101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3761886101
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.460080856
Short name T197
Test name
Test status
Simulation time 1203803903 ps
CPU time 9.95 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 222388 kb
Host smart-9903a4ab-f2e7-4ec2-9018-66652a4560cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460080856 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.460080856
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4126555935
Short name T141
Test name
Test status
Simulation time 41461366 ps
CPU time 3 seconds
Started Jul 24 07:04:45 PM PDT 24
Finished Jul 24 07:04:49 PM PDT 24
Peak memory 209664 kb
Host smart-1ae27e7b-47be-4b40-bd74-da67b8cce632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126555935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4126555935
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4084653208
Short name T626
Test name
Test status
Simulation time 78993950 ps
CPU time 1.86 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:43 PM PDT 24
Peak memory 209740 kb
Host smart-ec5e230f-5de3-45f8-9887-e97cffe3ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084653208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4084653208
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2808825825
Short name T640
Test name
Test status
Simulation time 16529169 ps
CPU time 0.82 seconds
Started Jul 24 07:04:51 PM PDT 24
Finished Jul 24 07:04:52 PM PDT 24
Peak memory 205840 kb
Host smart-93568639-faab-4789-8810-b20194de1194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808825825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2808825825
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3940224035
Short name T857
Test name
Test status
Simulation time 53081253 ps
CPU time 2.42 seconds
Started Jul 24 07:04:51 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 214076 kb
Host smart-3bb2951c-b64c-4640-907d-785cb1f470d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940224035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3940224035
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3973652552
Short name T101
Test name
Test status
Simulation time 147042527 ps
CPU time 3.01 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:04:51 PM PDT 24
Peak memory 214128 kb
Host smart-45bab1a8-43ea-43f9-ba3d-aa76c34b2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973652552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3973652552
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2052842262
Short name T271
Test name
Test status
Simulation time 201507924 ps
CPU time 4.07 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 220792 kb
Host smart-f0b3545a-321f-414b-a68e-8f74777e5a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052842262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2052842262
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.131616914
Short name T879
Test name
Test status
Simulation time 134061159 ps
CPU time 3.53 seconds
Started Jul 24 07:04:50 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 214180 kb
Host smart-7052e40a-7286-4937-8351-71499a69ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131616914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.131616914
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3883794686
Short name T903
Test name
Test status
Simulation time 175502822 ps
CPU time 6.61 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:04:55 PM PDT 24
Peak memory 208604 kb
Host smart-4ebff388-a7be-4433-a24f-07faf5504395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883794686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3883794686
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.403514639
Short name T815
Test name
Test status
Simulation time 225262022 ps
CPU time 3.05 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 206484 kb
Host smart-7207919d-fae5-4168-bc6c-e30f303bb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403514639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.403514639
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1390227260
Short name T397
Test name
Test status
Simulation time 1133000277 ps
CPU time 8.55 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:51 PM PDT 24
Peak memory 208140 kb
Host smart-e6997b92-4b6b-4763-ac15-61135bc6f91f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390227260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1390227260
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.686515840
Short name T548
Test name
Test status
Simulation time 77659344 ps
CPU time 3.7 seconds
Started Jul 24 07:04:41 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 208676 kb
Host smart-a356d73e-8dff-4310-9ff0-6549831bd3b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686515840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.686515840
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1943620728
Short name T500
Test name
Test status
Simulation time 70527015 ps
CPU time 3.32 seconds
Started Jul 24 07:04:46 PM PDT 24
Finished Jul 24 07:04:50 PM PDT 24
Peak memory 208388 kb
Host smart-fc71801d-4cff-4966-892e-18f6e18f85b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943620728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1943620728
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4246700667
Short name T215
Test name
Test status
Simulation time 85230808 ps
CPU time 3.85 seconds
Started Jul 24 07:04:47 PM PDT 24
Finished Jul 24 07:04:52 PM PDT 24
Peak memory 208872 kb
Host smart-89880d2b-d397-4cb1-b666-2f6d0b5db545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246700667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4246700667
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2468988065
Short name T559
Test name
Test status
Simulation time 124042245 ps
CPU time 2.54 seconds
Started Jul 24 07:04:43 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208212 kb
Host smart-04913e6b-0f91-4b1a-88b6-91343951df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468988065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2468988065
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3024286637
Short name T771
Test name
Test status
Simulation time 1175758985 ps
CPU time 36.12 seconds
Started Jul 24 07:04:48 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 215616 kb
Host smart-07087c7a-a4af-4a7b-b11e-7a927dd7bd31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024286637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3024286637
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1485139499
Short name T530
Test name
Test status
Simulation time 106623270 ps
CPU time 4.34 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 214068 kb
Host smart-9b26380d-d110-4c08-84b6-159453d6cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485139499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1485139499
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4002922836
Short name T832
Test name
Test status
Simulation time 133820870 ps
CPU time 2.74 seconds
Started Jul 24 07:04:51 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 209924 kb
Host smart-0e2059a1-54d3-4490-a44f-0fc375a5d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002922836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4002922836
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2715429526
Short name T103
Test name
Test status
Simulation time 12098075 ps
CPU time 0.85 seconds
Started Jul 24 07:03:55 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 205756 kb
Host smart-af59a8fc-8a07-471d-ad67-1905afffca98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715429526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2715429526
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.844321754
Short name T78
Test name
Test status
Simulation time 1364635544 ps
CPU time 5.45 seconds
Started Jul 24 07:03:47 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 209052 kb
Host smart-804e59c2-5244-40d6-a83c-a0d61c14a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844321754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.844321754
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4163012544
Short name T45
Test name
Test status
Simulation time 96467218 ps
CPU time 3.23 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 214200 kb
Host smart-657ac1df-38c0-4d1f-a045-0dba0f0d9499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163012544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4163012544
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3006404679
Short name T234
Test name
Test status
Simulation time 164357082 ps
CPU time 4.21 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 219324 kb
Host smart-f3bfd997-3eb4-46b3-9bd6-ef6274b7fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006404679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3006404679
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.4191181902
Short name T286
Test name
Test status
Simulation time 315502022 ps
CPU time 6.51 seconds
Started Jul 24 07:03:48 PM PDT 24
Finished Jul 24 07:03:55 PM PDT 24
Peak memory 219736 kb
Host smart-b590ccbb-0e4b-4ecd-b0aa-94036ee15b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191181902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4191181902
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3538971363
Short name T9
Test name
Test status
Simulation time 2849915166 ps
CPU time 10.27 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 235364 kb
Host smart-6ed1160a-6f3d-47f4-b8f6-e4c0cee108af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538971363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3538971363
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2923964946
Short name T683
Test name
Test status
Simulation time 501256113 ps
CPU time 3.44 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 208268 kb
Host smart-16f5a631-7d5d-4e55-8621-f0b6843fc6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923964946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2923964946
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.70624770
Short name T767
Test name
Test status
Simulation time 101294786 ps
CPU time 3.04 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:47 PM PDT 24
Peak memory 206772 kb
Host smart-84e3a663-e5d4-4295-83c2-e3a96712ec14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70624770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.70624770
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3505566345
Short name T556
Test name
Test status
Simulation time 93585697 ps
CPU time 2.73 seconds
Started Jul 24 07:03:46 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 206768 kb
Host smart-56a28330-4ed9-4a1f-9cca-bdf0bfe509e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505566345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3505566345
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2621926642
Short name T708
Test name
Test status
Simulation time 122381196 ps
CPU time 4.72 seconds
Started Jul 24 07:03:46 PM PDT 24
Finished Jul 24 07:03:51 PM PDT 24
Peak memory 208172 kb
Host smart-a70c56d5-eae4-4bed-8f3d-e78b166eb17d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621926642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2621926642
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1057367150
Short name T819
Test name
Test status
Simulation time 969395085 ps
CPU time 6.72 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 209280 kb
Host smart-d95ef6c3-f587-4a66-8e96-01887f2a578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057367150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1057367150
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2267829876
Short name T394
Test name
Test status
Simulation time 302596173 ps
CPU time 3.4 seconds
Started Jul 24 07:03:48 PM PDT 24
Finished Jul 24 07:03:52 PM PDT 24
Peak memory 208476 kb
Host smart-140df07a-7d58-44e6-b4fb-a55dc4df4f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267829876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2267829876
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3979919142
Short name T195
Test name
Test status
Simulation time 2172694096 ps
CPU time 22.4 seconds
Started Jul 24 07:03:49 PM PDT 24
Finished Jul 24 07:04:11 PM PDT 24
Peak memory 220696 kb
Host smart-c1bd2cbf-a862-44a5-8054-8834af887a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979919142 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3979919142
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3279783880
Short name T644
Test name
Test status
Simulation time 47524750 ps
CPU time 3.34 seconds
Started Jul 24 07:03:45 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 214044 kb
Host smart-031f3f06-ec12-4b8a-8dfe-ea613402f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279783880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3279783880
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3766267599
Short name T383
Test name
Test status
Simulation time 225812937 ps
CPU time 2.27 seconds
Started Jul 24 07:03:44 PM PDT 24
Finished Jul 24 07:03:46 PM PDT 24
Peak memory 209900 kb
Host smart-e9c79f1f-2c93-4988-b486-79bed47ad26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766267599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3766267599
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1062757621
Short name T817
Test name
Test status
Simulation time 19824341 ps
CPU time 0.85 seconds
Started Jul 24 07:04:56 PM PDT 24
Finished Jul 24 07:04:57 PM PDT 24
Peak memory 205876 kb
Host smart-385700b9-f3a5-4e18-9bd1-f47eb33632bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062757621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1062757621
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.229856891
Short name T420
Test name
Test status
Simulation time 55567838 ps
CPU time 3.95 seconds
Started Jul 24 07:04:50 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 215348 kb
Host smart-1810bd65-bf37-4831-a6df-788c6cea46ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229856891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.229856891
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1646633570
Short name T368
Test name
Test status
Simulation time 156724108 ps
CPU time 6.24 seconds
Started Jul 24 07:04:58 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 209916 kb
Host smart-1e69c71d-b9c6-4830-8ba5-b6331b70fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646633570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1646633570
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2623046223
Short name T801
Test name
Test status
Simulation time 89060587 ps
CPU time 2.83 seconds
Started Jul 24 07:04:55 PM PDT 24
Finished Jul 24 07:04:58 PM PDT 24
Peak memory 214056 kb
Host smart-e48d72c8-c2fa-4eae-9fa5-2e6dbea5e81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623046223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2623046223
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2873017172
Short name T748
Test name
Test status
Simulation time 51575302 ps
CPU time 2.96 seconds
Started Jul 24 07:04:57 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 214124 kb
Host smart-a1d0df7d-7948-4f42-8594-b0adcd9330ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873017172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2873017172
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.341827444
Short name T46
Test name
Test status
Simulation time 1015886429 ps
CPU time 4.3 seconds
Started Jul 24 07:04:55 PM PDT 24
Finished Jul 24 07:04:59 PM PDT 24
Peak memory 214028 kb
Host smart-094038d3-ae24-4717-ac0d-f43a217891a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341827444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.341827444
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.866872097
Short name T773
Test name
Test status
Simulation time 269253026 ps
CPU time 2.8 seconds
Started Jul 24 07:04:57 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 214552 kb
Host smart-3b3784fe-f983-45e6-836a-d701f6103547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866872097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.866872097
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.977283247
Short name T641
Test name
Test status
Simulation time 78461148 ps
CPU time 4.33 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 209392 kb
Host smart-c9dcd466-1439-4739-b445-9b5cbac03c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977283247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.977283247
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.33523236
Short name T574
Test name
Test status
Simulation time 70042795 ps
CPU time 3.09 seconds
Started Jul 24 07:04:50 PM PDT 24
Finished Jul 24 07:04:53 PM PDT 24
Peak memory 207932 kb
Host smart-b49e0a1f-4629-487f-8283-f14d7338a0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33523236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.33523236
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3383996376
Short name T320
Test name
Test status
Simulation time 34051411 ps
CPU time 2.34 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:04:51 PM PDT 24
Peak memory 206792 kb
Host smart-33a69c26-4210-4b51-9340-c1f2e9f5575e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383996376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3383996376
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1819706596
Short name T143
Test name
Test status
Simulation time 89820237 ps
CPU time 3.81 seconds
Started Jul 24 07:04:50 PM PDT 24
Finished Jul 24 07:04:54 PM PDT 24
Peak memory 208456 kb
Host smart-9e0894ea-5834-4026-a8d2-40569911833f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819706596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1819706596
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2436187875
Short name T913
Test name
Test status
Simulation time 70248512 ps
CPU time 2.9 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:03 PM PDT 24
Peak memory 208848 kb
Host smart-d2a0a76d-a4fb-4e17-b7e5-884585104796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436187875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2436187875
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1059158954
Short name T834
Test name
Test status
Simulation time 3977310372 ps
CPU time 17.84 seconds
Started Jul 24 07:04:49 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 208508 kb
Host smart-9f1e5655-9258-4b5a-8b00-248469e1e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059158954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1059158954
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2338436005
Short name T275
Test name
Test status
Simulation time 106610715 ps
CPU time 4.94 seconds
Started Jul 24 07:04:55 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 206112 kb
Host smart-ea514e76-603f-4c78-a23f-c88b42deef5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338436005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2338436005
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3288210812
Short name T745
Test name
Test status
Simulation time 3035392600 ps
CPU time 22.05 seconds
Started Jul 24 07:04:55 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 209504 kb
Host smart-e10bd13e-69d1-419a-877f-5b2cbf9866a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288210812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3288210812
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3446044975
Short name T585
Test name
Test status
Simulation time 10355016 ps
CPU time 0.87 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:02 PM PDT 24
Peak memory 206004 kb
Host smart-7e1804f5-4b8c-4894-8920-b1ec2c77e60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446044975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3446044975
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3972578871
Short name T65
Test name
Test status
Simulation time 713226884 ps
CPU time 7.11 seconds
Started Jul 24 07:04:56 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 221672 kb
Host smart-da4e15a5-6d80-4bfd-8b3c-d10966b112b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972578871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3972578871
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.293666018
Short name T653
Test name
Test status
Simulation time 166509408 ps
CPU time 1.85 seconds
Started Jul 24 07:04:58 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 206896 kb
Host smart-5cd1d014-d52c-47c2-a71e-fbc1ef990b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293666018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.293666018
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.368185590
Short name T813
Test name
Test status
Simulation time 207226730 ps
CPU time 3.21 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 217900 kb
Host smart-9fb2ad4b-2b98-418a-a79d-67919a36e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368185590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.368185590
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.735498342
Short name T889
Test name
Test status
Simulation time 512314523 ps
CPU time 5.46 seconds
Started Jul 24 07:04:54 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 214112 kb
Host smart-f2e27c82-7b0f-4602-bfae-d328d0aac0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735498342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.735498342
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1958827783
Short name T793
Test name
Test status
Simulation time 314399454 ps
CPU time 4.85 seconds
Started Jul 24 07:04:55 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 219624 kb
Host smart-023bf24a-9ec0-462a-97b6-71bd3fcc72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958827783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1958827783
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1250455512
Short name T351
Test name
Test status
Simulation time 107869985 ps
CPU time 2.99 seconds
Started Jul 24 07:04:54 PM PDT 24
Finished Jul 24 07:04:58 PM PDT 24
Peak memory 217944 kb
Host smart-1f4bd1ed-6402-45cc-b078-2f82a0de131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250455512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1250455512
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2753861
Short name T710
Test name
Test status
Simulation time 69293351 ps
CPU time 3.05 seconds
Started Jul 24 07:04:56 PM PDT 24
Finished Jul 24 07:04:59 PM PDT 24
Peak memory 208392 kb
Host smart-d1fa1967-0571-4002-b7b8-b0f3d06b7143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2753861
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4078222458
Short name T221
Test name
Test status
Simulation time 225417917 ps
CPU time 5.85 seconds
Started Jul 24 07:04:57 PM PDT 24
Finished Jul 24 07:05:03 PM PDT 24
Peak memory 208056 kb
Host smart-358074f5-5279-4459-8352-387cf8b95b8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078222458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4078222458
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1900430508
Short name T876
Test name
Test status
Simulation time 2882960462 ps
CPU time 26.72 seconds
Started Jul 24 07:04:59 PM PDT 24
Finished Jul 24 07:05:26 PM PDT 24
Peak memory 208044 kb
Host smart-58f87c97-f3a6-4a0f-824d-eaf9ee3d0414
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900430508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1900430508
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1985343966
Short name T464
Test name
Test status
Simulation time 179731950 ps
CPU time 6.49 seconds
Started Jul 24 07:04:57 PM PDT 24
Finished Jul 24 07:05:04 PM PDT 24
Peak memory 208392 kb
Host smart-5b9c5b9c-fde1-4bd5-8b98-ba908f19e75b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985343966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1985343966
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1270843498
Short name T484
Test name
Test status
Simulation time 164371831 ps
CPU time 3.86 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 208988 kb
Host smart-7274f520-736a-4a4d-911e-0ee77af5854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270843498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1270843498
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3890508257
Short name T438
Test name
Test status
Simulation time 159442230 ps
CPU time 2.34 seconds
Started Jul 24 07:04:58 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 206780 kb
Host smart-95873cee-c085-42e1-b47b-f9f2d114746d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890508257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3890508257
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4197167768
Short name T357
Test name
Test status
Simulation time 168526735 ps
CPU time 7.84 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:08 PM PDT 24
Peak memory 222216 kb
Host smart-45572e15-2f09-4cf0-9519-e6b9a20b6391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197167768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4197167768
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1825178145
Short name T470
Test name
Test status
Simulation time 496137415 ps
CPU time 6.39 seconds
Started Jul 24 07:04:54 PM PDT 24
Finished Jul 24 07:05:01 PM PDT 24
Peak memory 207824 kb
Host smart-7e3bcbf7-2baf-4fa4-b996-3471cf8b1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825178145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1825178145
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2938970595
Short name T842
Test name
Test status
Simulation time 581950208 ps
CPU time 3.44 seconds
Started Jul 24 07:05:02 PM PDT 24
Finished Jul 24 07:05:05 PM PDT 24
Peak memory 210204 kb
Host smart-7c10c95b-7005-4460-af91-3e147b990c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938970595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2938970595
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.189795007
Short name T520
Test name
Test status
Simulation time 37764867 ps
CPU time 0.73 seconds
Started Jul 24 07:04:59 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 205860 kb
Host smart-27a1e759-8633-431a-9bdb-86ad63bca351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189795007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.189795007
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.672751713
Short name T659
Test name
Test status
Simulation time 329279200 ps
CPU time 5.81 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:06 PM PDT 24
Peak memory 214296 kb
Host smart-31766aca-757a-4001-bab5-aa5fb5f8fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672751713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.672751713
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4290941148
Short name T220
Test name
Test status
Simulation time 651772793 ps
CPU time 4.68 seconds
Started Jul 24 07:05:05 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 208480 kb
Host smart-c130346c-5a27-4ae2-bdd3-999c5efbb0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290941148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4290941148
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2480750658
Short name T95
Test name
Test status
Simulation time 159493386 ps
CPU time 4.12 seconds
Started Jul 24 07:05:06 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 209524 kb
Host smart-1b49c287-a815-489b-be57-142adcd8394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480750658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2480750658
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3116332489
Short name T790
Test name
Test status
Simulation time 46595161 ps
CPU time 2.47 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:05 PM PDT 24
Peak memory 214076 kb
Host smart-15139510-6011-4385-aaab-719202696583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116332489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3116332489
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2508499380
Short name T849
Test name
Test status
Simulation time 651728617 ps
CPU time 4.63 seconds
Started Jul 24 07:05:02 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 220240 kb
Host smart-d11c0134-0cd9-4817-8a39-93bf6a74870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508499380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2508499380
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.241554967
Short name T322
Test name
Test status
Simulation time 70452451 ps
CPU time 2.4 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:03 PM PDT 24
Peak memory 207296 kb
Host smart-9973da1b-ceae-458a-ba19-9e7e549c2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241554967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.241554967
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4261382373
Short name T597
Test name
Test status
Simulation time 35891690 ps
CPU time 2.42 seconds
Started Jul 24 07:05:00 PM PDT 24
Finished Jul 24 07:05:02 PM PDT 24
Peak memory 206620 kb
Host smart-41d7ff45-34c6-43ff-88bf-dbae4fbf7180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261382373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4261382373
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2205573943
Short name T454
Test name
Test status
Simulation time 45925095 ps
CPU time 2.61 seconds
Started Jul 24 07:05:04 PM PDT 24
Finished Jul 24 07:05:06 PM PDT 24
Peak memory 208356 kb
Host smart-51c0cbf0-22e9-4f55-851e-f0ec5e5038c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205573943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2205573943
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.321139033
Short name T713
Test name
Test status
Simulation time 2611230609 ps
CPU time 29.33 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 208760 kb
Host smart-b439cf54-77ca-4bb4-b8aa-c80a6b3ad70b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321139033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.321139033
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3284754574
Short name T81
Test name
Test status
Simulation time 63103156 ps
CPU time 3.06 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:06 PM PDT 24
Peak memory 206720 kb
Host smart-83fbf745-892d-4922-8ae5-3e320c5ac22a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284754574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3284754574
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1914234804
Short name T467
Test name
Test status
Simulation time 37338193 ps
CPU time 1.47 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:03 PM PDT 24
Peak memory 206712 kb
Host smart-64a9c19d-4c9c-46fe-8764-0c408878f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914234804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1914234804
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3416735539
Short name T504
Test name
Test status
Simulation time 147088047 ps
CPU time 4.92 seconds
Started Jul 24 07:04:59 PM PDT 24
Finished Jul 24 07:05:05 PM PDT 24
Peak memory 206664 kb
Host smart-77768d55-a26e-4ad5-8ddd-764c1365577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416735539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3416735539
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1739737353
Short name T636
Test name
Test status
Simulation time 13807958 ps
CPU time 0.9 seconds
Started Jul 24 07:05:06 PM PDT 24
Finished Jul 24 07:05:07 PM PDT 24
Peak memory 205860 kb
Host smart-aab9e025-4a53-4d68-8ab9-af76b089457f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739737353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1739737353
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4265546857
Short name T137
Test name
Test status
Simulation time 157153631 ps
CPU time 3.21 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:11 PM PDT 24
Peak memory 214180 kb
Host smart-db81d4e8-c2b2-4249-b03b-e5cf1b93d126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265546857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4265546857
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1313589975
Short name T727
Test name
Test status
Simulation time 255529332 ps
CPU time 4.39 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:11 PM PDT 24
Peak memory 209844 kb
Host smart-470a6359-6d28-45e4-bfd0-9c2d094bf3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313589975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1313589975
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2067766891
Short name T90
Test name
Test status
Simulation time 105059019 ps
CPU time 2.77 seconds
Started Jul 24 07:05:09 PM PDT 24
Finished Jul 24 07:05:12 PM PDT 24
Peak memory 214224 kb
Host smart-22a64a05-e881-4ce9-92dc-7cb3a72fe5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067766891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2067766891
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1914151382
Short name T249
Test name
Test status
Simulation time 258385365 ps
CPU time 2.61 seconds
Started Jul 24 07:05:18 PM PDT 24
Finished Jul 24 07:05:21 PM PDT 24
Peak memory 213940 kb
Host smart-6e6c8872-8e95-4c43-b0cb-c811f222fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914151382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1914151382
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3716147358
Short name T301
Test name
Test status
Simulation time 55929050 ps
CPU time 4.12 seconds
Started Jul 24 07:05:09 PM PDT 24
Finished Jul 24 07:05:14 PM PDT 24
Peak memory 222316 kb
Host smart-38941f45-0b7a-4128-a22f-0d26da9e9da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716147358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3716147358
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.12112648
Short name T489
Test name
Test status
Simulation time 158560351 ps
CPU time 7.1 seconds
Started Jul 24 07:05:05 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 209828 kb
Host smart-2deacb99-936d-4b20-9a08-de14b3021a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12112648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.12112648
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2217483384
Short name T369
Test name
Test status
Simulation time 2695494225 ps
CPU time 36.9 seconds
Started Jul 24 07:05:17 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 208304 kb
Host smart-875c408d-7cb5-4ba0-9eb4-8a8f3231de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217483384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2217483384
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1579134093
Short name T542
Test name
Test status
Simulation time 584560685 ps
CPU time 3.46 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:05 PM PDT 24
Peak memory 206908 kb
Host smart-ed477f8a-8c96-4ef0-8b02-be8d7525a281
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579134093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1579134093
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2269743965
Short name T201
Test name
Test status
Simulation time 2773039392 ps
CPU time 18.51 seconds
Started Jul 24 07:05:03 PM PDT 24
Finished Jul 24 07:05:21 PM PDT 24
Peak memory 208032 kb
Host smart-b8ff4b0f-a234-4786-83f6-954c2ebbedaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269743965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2269743965
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.492384926
Short name T544
Test name
Test status
Simulation time 177479314 ps
CPU time 5.03 seconds
Started Jul 24 07:05:04 PM PDT 24
Finished Jul 24 07:05:09 PM PDT 24
Peak memory 207908 kb
Host smart-4472d045-0850-4678-a096-37273fc87908
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492384926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.492384926
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3631467026
Short name T613
Test name
Test status
Simulation time 73297828 ps
CPU time 3.5 seconds
Started Jul 24 07:05:06 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 215620 kb
Host smart-eb6d3a8d-32a7-47da-b761-570f58cbe3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631467026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3631467026
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4294356702
Short name T904
Test name
Test status
Simulation time 758299219 ps
CPU time 11.97 seconds
Started Jul 24 07:05:01 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 208552 kb
Host smart-d21d7de5-db13-4f66-9621-31b65679aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294356702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4294356702
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3993824184
Short name T632
Test name
Test status
Simulation time 428289056 ps
CPU time 11.74 seconds
Started Jul 24 07:05:08 PM PDT 24
Finished Jul 24 07:05:20 PM PDT 24
Peak memory 222340 kb
Host smart-b6bb4801-5583-467b-bab7-e378c8a516b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993824184 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3993824184
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1453880685
Short name T212
Test name
Test status
Simulation time 279702284 ps
CPU time 4.45 seconds
Started Jul 24 07:05:10 PM PDT 24
Finished Jul 24 07:05:14 PM PDT 24
Peak memory 222108 kb
Host smart-355a2330-e5d7-4d4b-8cf4-ecbf2d6b3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453880685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1453880685
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1128571699
Short name T62
Test name
Test status
Simulation time 468389337 ps
CPU time 3.5 seconds
Started Jul 24 07:05:10 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 210148 kb
Host smart-c795761f-dedb-4b3f-8520-11e175ad9531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128571699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1128571699
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2015433984
Short name T424
Test name
Test status
Simulation time 31931806 ps
CPU time 0.78 seconds
Started Jul 24 07:05:12 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 205724 kb
Host smart-aee8e6b9-e3ce-4cc4-bbe1-88dffc2be9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015433984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2015433984
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2149340188
Short name T337
Test name
Test status
Simulation time 130222593 ps
CPU time 3.04 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:16 PM PDT 24
Peak memory 209028 kb
Host smart-e5b78942-d8de-4b28-aa1d-e5288c285448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149340188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2149340188
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.231773095
Short name T786
Test name
Test status
Simulation time 445858198 ps
CPU time 2.64 seconds
Started Jul 24 07:05:10 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 209280 kb
Host smart-db8c1419-83f7-48cc-a586-41a8bd7e137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231773095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.231773095
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1819102281
Short name T896
Test name
Test status
Simulation time 1276701080 ps
CPU time 4.29 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:12 PM PDT 24
Peak memory 214132 kb
Host smart-3aef5858-1b3f-44be-8e88-f8b406d1e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819102281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1819102281
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2094445599
Short name T250
Test name
Test status
Simulation time 186424311 ps
CPU time 2.96 seconds
Started Jul 24 07:05:10 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 213968 kb
Host smart-33557d3e-fd9e-4b90-a946-8cbaed95031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094445599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2094445599
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1531728598
Short name T479
Test name
Test status
Simulation time 85392233 ps
CPU time 3.96 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:11 PM PDT 24
Peak memory 209956 kb
Host smart-e56211ea-76c0-4dba-bec8-b89e3bbbaf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531728598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1531728598
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1823849286
Short name T340
Test name
Test status
Simulation time 876436259 ps
CPU time 4.29 seconds
Started Jul 24 07:05:08 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 207684 kb
Host smart-86bdea05-7b47-4a86-b56c-19d52313dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823849286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1823849286
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3936665661
Short name T851
Test name
Test status
Simulation time 448360544 ps
CPU time 2.81 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:10 PM PDT 24
Peak memory 206472 kb
Host smart-59dfbcf9-783b-4342-b5b0-506ce5e5daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936665661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3936665661
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4144133204
Short name T527
Test name
Test status
Simulation time 198863524 ps
CPU time 4.88 seconds
Started Jul 24 07:05:08 PM PDT 24
Finished Jul 24 07:05:13 PM PDT 24
Peak memory 208324 kb
Host smart-a741642b-9b48-401a-ab15-4e6f0bef32aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144133204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4144133204
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3525168432
Short name T507
Test name
Test status
Simulation time 83011358 ps
CPU time 2.68 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:09 PM PDT 24
Peak memory 206724 kb
Host smart-da9d5db8-3f9d-4946-ac84-472dfbb5ff97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525168432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3525168432
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1711917563
Short name T494
Test name
Test status
Simulation time 123962050 ps
CPU time 3.52 seconds
Started Jul 24 07:05:07 PM PDT 24
Finished Jul 24 07:05:11 PM PDT 24
Peak memory 208640 kb
Host smart-34ffb48a-fd10-475d-9276-6dfc39363c38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711917563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1711917563
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3593018579
Short name T802
Test name
Test status
Simulation time 127748491 ps
CPU time 2.46 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 214048 kb
Host smart-a86b5276-2e15-484c-b348-cf90b671c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593018579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3593018579
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3111022357
Short name T623
Test name
Test status
Simulation time 917524166 ps
CPU time 5.05 seconds
Started Jul 24 07:05:09 PM PDT 24
Finished Jul 24 07:05:14 PM PDT 24
Peak memory 207992 kb
Host smart-12f48771-f6a5-4345-bfb9-ba06f1f920de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111022357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3111022357
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3870453654
Short name T336
Test name
Test status
Simulation time 7385591230 ps
CPU time 26.11 seconds
Started Jul 24 07:05:15 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 222424 kb
Host smart-946a6975-cdcf-417c-b8a4-437cad9ff7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870453654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3870453654
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1649145887
Short name T696
Test name
Test status
Simulation time 185865918 ps
CPU time 7.21 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:21 PM PDT 24
Peak memory 222712 kb
Host smart-734d720f-43c2-4763-9cde-752f258f926e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649145887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1649145887
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2194623401
Short name T540
Test name
Test status
Simulation time 504006904 ps
CPU time 5.82 seconds
Started Jul 24 07:05:09 PM PDT 24
Finished Jul 24 07:05:15 PM PDT 24
Peak memory 207864 kb
Host smart-3a08db26-5bee-40b3-8443-c295d8d33b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194623401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2194623401
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2382590124
Short name T914
Test name
Test status
Simulation time 87248040 ps
CPU time 2.16 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 209804 kb
Host smart-cbd424c6-55f7-4d61-8d8d-b43a301e071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382590124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2382590124
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2823165475
Short name T658
Test name
Test status
Simulation time 15704325 ps
CPU time 0.84 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:14 PM PDT 24
Peak memory 205904 kb
Host smart-dfd5b002-2d9c-4e28-adf5-2143aa53e4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823165475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2823165475
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3557719189
Short name T23
Test name
Test status
Simulation time 6645274754 ps
CPU time 19.52 seconds
Started Jul 24 07:05:17 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 214212 kb
Host smart-2d12b431-7f3a-4755-b421-1575e521d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557719189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3557719189
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2518422806
Short name T328
Test name
Test status
Simulation time 90258996 ps
CPU time 4.17 seconds
Started Jul 24 07:05:15 PM PDT 24
Finished Jul 24 07:05:20 PM PDT 24
Peak memory 214040 kb
Host smart-943fe6a6-ac9a-4625-b6d9-31d2a9bdcae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518422806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2518422806
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.625064506
Short name T54
Test name
Test status
Simulation time 131241921 ps
CPU time 2.91 seconds
Started Jul 24 07:05:17 PM PDT 24
Finished Jul 24 07:05:20 PM PDT 24
Peak memory 216032 kb
Host smart-1b014e3a-651c-4b36-b9b2-3fcba779eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625064506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.625064506
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2690668970
Short name T246
Test name
Test status
Simulation time 784645236 ps
CPU time 18.01 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 208924 kb
Host smart-e46ae737-7f15-434c-b73f-fea785bfe235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690668970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2690668970
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3124854184
Short name T471
Test name
Test status
Simulation time 67069219 ps
CPU time 2.86 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:16 PM PDT 24
Peak memory 207700 kb
Host smart-2aa5374c-21be-4ecf-b029-ebef9e5af5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124854184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3124854184
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2231227512
Short name T680
Test name
Test status
Simulation time 1061417911 ps
CPU time 3.93 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 206600 kb
Host smart-ab6d312d-7ee3-4924-a336-6020f561ec14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231227512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2231227512
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2820403532
Short name T501
Test name
Test status
Simulation time 320985426 ps
CPU time 3.83 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 208352 kb
Host smart-e20119ea-5ae6-4c66-b1a7-ad75e5a5c47a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820403532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2820403532
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1347413888
Short name T612
Test name
Test status
Simulation time 2504930373 ps
CPU time 17.68 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 207996 kb
Host smart-41c1ded6-f379-470d-970d-66ca93e24f32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347413888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1347413888
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2319111282
Short name T697
Test name
Test status
Simulation time 55890723 ps
CPU time 3.14 seconds
Started Jul 24 07:05:17 PM PDT 24
Finished Jul 24 07:05:20 PM PDT 24
Peak memory 215860 kb
Host smart-065d8770-bd51-4e9c-be73-0640f0c7f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319111282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2319111282
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3283709443
Short name T428
Test name
Test status
Simulation time 359305416 ps
CPU time 2.31 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:15 PM PDT 24
Peak memory 206704 kb
Host smart-711b6a33-5b4e-4c97-9335-7c322de92692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283709443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3283709443
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1026142282
Short name T51
Test name
Test status
Simulation time 59708120 ps
CPU time 2.75 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:17 PM PDT 24
Peak memory 209136 kb
Host smart-beafc67e-1e5d-40b3-bfb7-ff1edf61cfc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026142282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1026142282
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1354286972
Short name T880
Test name
Test status
Simulation time 13091912154 ps
CPU time 52.93 seconds
Started Jul 24 07:05:12 PM PDT 24
Finished Jul 24 07:06:05 PM PDT 24
Peak memory 208200 kb
Host smart-ec74f531-de87-4706-803c-96cadda8c136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354286972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1354286972
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2691963223
Short name T35
Test name
Test status
Simulation time 354312092 ps
CPU time 1.87 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:16 PM PDT 24
Peak memory 210340 kb
Host smart-aae42c8d-26aa-46b2-bcc2-396c7c441f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691963223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2691963223
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2743751383
Short name T508
Test name
Test status
Simulation time 46181706 ps
CPU time 0.84 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 205840 kb
Host smart-315ac3a4-b8ac-4255-ba55-34766ccbabbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743751383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2743751383
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.788780347
Short name T407
Test name
Test status
Simulation time 79059373 ps
CPU time 5.06 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 214024 kb
Host smart-ca491d04-56d9-48ee-9f0a-d9b56a9091c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788780347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.788780347
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.833467553
Short name T654
Test name
Test status
Simulation time 46238672 ps
CPU time 3.24 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 210532 kb
Host smart-28931e50-2d96-4b50-b678-2555125edc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833467553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.833467553
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4090260242
Short name T643
Test name
Test status
Simulation time 104220545 ps
CPU time 2.1 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 219336 kb
Host smart-14a3bcba-d2ec-4aa7-86c2-0738784ae24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090260242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4090260242
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.868533107
Short name T98
Test name
Test status
Simulation time 118718157 ps
CPU time 5.01 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 221136 kb
Host smart-a07aa883-2f09-4e0a-9cfc-5e979234c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868533107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.868533107
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3949629685
Short name T761
Test name
Test status
Simulation time 197454056 ps
CPU time 3.58 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 217140 kb
Host smart-6417a3b3-6465-40ec-bbe2-8d732dc10a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949629685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3949629685
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.3012310942
Short name T893
Test name
Test status
Simulation time 190846234 ps
CPU time 3.37 seconds
Started Jul 24 07:05:25 PM PDT 24
Finished Jul 24 07:05:29 PM PDT 24
Peak memory 209556 kb
Host smart-29692f79-1611-41d9-a0aa-fb73f765a112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012310942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3012310942
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3477995547
Short name T629
Test name
Test status
Simulation time 214759031 ps
CPU time 2.8 seconds
Started Jul 24 07:05:13 PM PDT 24
Finished Jul 24 07:05:16 PM PDT 24
Peak memory 208376 kb
Host smart-a42eec69-855a-4d84-bf8b-0bbd40d1e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477995547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3477995547
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1424998867
Short name T224
Test name
Test status
Simulation time 447330250 ps
CPU time 4.11 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:18 PM PDT 24
Peak memory 206624 kb
Host smart-ea5db74b-11cb-4eae-9a4c-24bcd49dac0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424998867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1424998867
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3123854700
Short name T313
Test name
Test status
Simulation time 2168975412 ps
CPU time 28.32 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 208320 kb
Host smart-bc38ef1f-a8b4-474a-a52f-4bf595988049
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123854700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3123854700
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4020376116
Short name T114
Test name
Test status
Simulation time 628214336 ps
CPU time 4.82 seconds
Started Jul 24 07:05:26 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 208644 kb
Host smart-91964d0d-f675-4055-80dc-df0136cb33f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020376116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4020376116
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.699748254
Short name T689
Test name
Test status
Simulation time 354650258 ps
CPU time 6.14 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:29 PM PDT 24
Peak memory 208724 kb
Host smart-048544c0-1ace-4c11-99aa-e027702cb312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699748254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.699748254
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3525163460
Short name T401
Test name
Test status
Simulation time 195097222 ps
CPU time 4.01 seconds
Started Jul 24 07:05:14 PM PDT 24
Finished Jul 24 07:05:18 PM PDT 24
Peak memory 207700 kb
Host smart-95e2333c-a19b-49ac-a043-9ddfe0c6af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525163460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3525163460
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1212617259
Short name T68
Test name
Test status
Simulation time 183736389 ps
CPU time 9.25 seconds
Started Jul 24 07:05:23 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 220044 kb
Host smart-8a9609e5-eae8-41aa-962a-1c5cd1ee0f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212617259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1212617259
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3384004562
Short name T77
Test name
Test status
Simulation time 520282772 ps
CPU time 8.33 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 222340 kb
Host smart-32b68bb4-1aed-496e-8a0f-0ea859072a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384004562 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3384004562
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2441122205
Short name T590
Test name
Test status
Simulation time 1951563439 ps
CPU time 35.38 seconds
Started Jul 24 07:05:23 PM PDT 24
Finished Jul 24 07:05:59 PM PDT 24
Peak memory 209296 kb
Host smart-fb172c88-e230-4d58-88c0-1a79864a70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441122205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2441122205
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1045830297
Short name T455
Test name
Test status
Simulation time 407940402 ps
CPU time 2.87 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 210196 kb
Host smart-4ce4f14d-18cd-44bc-96e3-893dce70461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045830297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1045830297
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2681800422
Short name T102
Test name
Test status
Simulation time 30247164 ps
CPU time 0.95 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 205908 kb
Host smart-e85fa49d-e212-4e67-ae33-a8e03068ec2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681800422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2681800422
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.138218274
Short name T415
Test name
Test status
Simulation time 304827400 ps
CPU time 5.46 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:25 PM PDT 24
Peak memory 214084 kb
Host smart-116b7885-4cbc-48b4-b726-50110255e26d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138218274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.138218274
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.915038215
Short name T55
Test name
Test status
Simulation time 109248911 ps
CPU time 2.92 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 208600 kb
Host smart-21ef0e1a-62a1-431e-a70a-c2402a963d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915038215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.915038215
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3222934405
Short name T272
Test name
Test status
Simulation time 46053556 ps
CPU time 2.56 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:24 PM PDT 24
Peak memory 221556 kb
Host smart-03b37edb-7596-4f8c-9fe5-fe9f0690d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222934405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3222934405
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2514322395
Short name T497
Test name
Test status
Simulation time 111576843 ps
CPU time 2.96 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 214052 kb
Host smart-e7915715-729c-4ab2-ab62-5472089f0d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514322395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2514322395
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2075105243
Short name T638
Test name
Test status
Simulation time 98774752 ps
CPU time 3.12 seconds
Started Jul 24 07:05:23 PM PDT 24
Finished Jul 24 07:05:27 PM PDT 24
Peak memory 207404 kb
Host smart-e547a94c-6964-439a-946b-63cd70c749a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075105243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2075105243
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1634190261
Short name T435
Test name
Test status
Simulation time 2869697609 ps
CPU time 8.58 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 208572 kb
Host smart-d02deed2-cbf7-41b5-8ffb-b9e98df56619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634190261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1634190261
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.561238494
Short name T203
Test name
Test status
Simulation time 340733543 ps
CPU time 9.43 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 208640 kb
Host smart-0ad1e584-c7d3-479a-bb1d-49d7e67f09e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561238494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.561238494
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3126719047
Short name T478
Test name
Test status
Simulation time 152643869 ps
CPU time 4.47 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:28 PM PDT 24
Peak memory 207648 kb
Host smart-16ddf919-7662-4087-85bd-5c7075d91798
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126719047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3126719047
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2679729063
Short name T742
Test name
Test status
Simulation time 208928647 ps
CPU time 7.79 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:28 PM PDT 24
Peak memory 208440 kb
Host smart-35f2c857-c347-49ad-a746-19e2c379f978
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679729063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2679729063
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3649553155
Short name T213
Test name
Test status
Simulation time 225153405 ps
CPU time 2.57 seconds
Started Jul 24 07:05:23 PM PDT 24
Finished Jul 24 07:05:26 PM PDT 24
Peak memory 214072 kb
Host smart-25632215-889a-4036-a09d-74593e0586cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649553155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3649553155
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.779444212
Short name T835
Test name
Test status
Simulation time 197084394 ps
CPU time 3.6 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:28 PM PDT 24
Peak memory 206552 kb
Host smart-cc661dee-e05b-4bcc-bb52-b59e1898b034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779444212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.779444212
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1434211575
Short name T570
Test name
Test status
Simulation time 135858481 ps
CPU time 6.54 seconds
Started Jul 24 07:05:23 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 215164 kb
Host smart-d17076c7-db3d-4f96-8b61-2c730164f3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434211575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1434211575
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2500206751
Short name T131
Test name
Test status
Simulation time 837781383 ps
CPU time 11.5 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 222320 kb
Host smart-0ec43c9e-92cd-4893-9897-c85e75e59594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500206751 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2500206751
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4284384119
Short name T355
Test name
Test status
Simulation time 318174422 ps
CPU time 5.92 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:27 PM PDT 24
Peak memory 208536 kb
Host smart-5be3c157-e1e0-4bdc-8676-7c2834b888a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284384119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4284384119
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3774945084
Short name T453
Test name
Test status
Simulation time 100782418 ps
CPU time 2.24 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 209684 kb
Host smart-87218e65-1bc4-4f86-aeb2-61b27ecc2323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774945084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3774945084
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.865292240
Short name T656
Test name
Test status
Simulation time 9973895 ps
CPU time 0.85 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 205860 kb
Host smart-1c8ae69f-a477-4984-a202-a77a46fce9c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865292240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.865292240
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.531452329
Short name T891
Test name
Test status
Simulation time 664216532 ps
CPU time 7.46 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 214612 kb
Host smart-40f24645-c88d-4cff-bc40-9b54668b54b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531452329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.531452329
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2665895897
Short name T830
Test name
Test status
Simulation time 32519584 ps
CPU time 2.27 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 209944 kb
Host smart-11770adb-0954-40c1-96a3-6296623f9427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665895897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2665895897
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3626029856
Short name T846
Test name
Test status
Simulation time 384105772 ps
CPU time 3.24 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:26 PM PDT 24
Peak memory 219536 kb
Host smart-71b89faf-fbfa-40c4-8d12-df5a56e5e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626029856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3626029856
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4232293932
Short name T642
Test name
Test status
Simulation time 144866841 ps
CPU time 3.92 seconds
Started Jul 24 07:05:22 PM PDT 24
Finished Jul 24 07:05:26 PM PDT 24
Peak memory 207136 kb
Host smart-ba438b27-6b2d-4dd5-9d76-f3a53ce4fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232293932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4232293932
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3805606372
Short name T652
Test name
Test status
Simulation time 175322479 ps
CPU time 4.84 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:29 PM PDT 24
Peak memory 208004 kb
Host smart-1456564f-9201-47db-a773-a26e34b6a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805606372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3805606372
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1715125994
Short name T898
Test name
Test status
Simulation time 67362076 ps
CPU time 2.33 seconds
Started Jul 24 07:05:24 PM PDT 24
Finished Jul 24 07:05:26 PM PDT 24
Peak memory 206568 kb
Host smart-7498bacc-fc7e-44ee-a702-6b5e3546b55f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715125994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1715125994
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4287754893
Short name T622
Test name
Test status
Simulation time 215303204 ps
CPU time 5.93 seconds
Started Jul 24 07:05:21 PM PDT 24
Finished Jul 24 07:05:27 PM PDT 24
Peak memory 208444 kb
Host smart-01de57f1-bfce-4f15-bdfe-0dafdaa5c0ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287754893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4287754893
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1103811158
Short name T248
Test name
Test status
Simulation time 300477870 ps
CPU time 3.06 seconds
Started Jul 24 07:05:19 PM PDT 24
Finished Jul 24 07:05:22 PM PDT 24
Peak memory 207060 kb
Host smart-5afeaeef-9e0f-47dc-b9c8-ce09b9960095
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103811158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1103811158
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1624370936
Short name T895
Test name
Test status
Simulation time 3609810291 ps
CPU time 16.56 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:44 PM PDT 24
Peak memory 216528 kb
Host smart-59b85e2b-54f2-4ea6-82b2-15be43e8841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624370936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1624370936
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1455756364
Short name T816
Test name
Test status
Simulation time 98184774 ps
CPU time 2.3 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 206588 kb
Host smart-3c04f2d3-1b8c-40ed-837b-c05b0618b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455756364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1455756364
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1920703192
Short name T747
Test name
Test status
Simulation time 26499041 ps
CPU time 1.94 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 207056 kb
Host smart-831bf92f-1986-40cc-85e4-a1dd459b5b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920703192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1920703192
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2999698530
Short name T134
Test name
Test status
Simulation time 1457521794 ps
CPU time 8.5 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 219424 kb
Host smart-14e2a6e5-93f7-48a3-b237-ba0b0e35f6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999698530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2999698530
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1900374168
Short name T292
Test name
Test status
Simulation time 5156948805 ps
CPU time 19.21 seconds
Started Jul 24 07:05:20 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 208964 kb
Host smart-6b25b4ab-7ec2-4e14-a1dd-37019122e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900374168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1900374168
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1137447206
Short name T645
Test name
Test status
Simulation time 63887061 ps
CPU time 2.82 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 209828 kb
Host smart-267d9fff-c714-4a6b-b3ee-cc86b960d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137447206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1137447206
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.589429631
Short name T517
Test name
Test status
Simulation time 14547245 ps
CPU time 0.92 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 205840 kb
Host smart-12b13083-86f8-41fb-ab44-d9b8b09bea96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589429631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.589429631
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.994953448
Short name T596
Test name
Test status
Simulation time 47121425 ps
CPU time 2.36 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 214020 kb
Host smart-0c134d27-d4dc-4df6-b6a7-daf6dc0d87c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994953448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.994953448
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2817362122
Short name T99
Test name
Test status
Simulation time 85430004 ps
CPU time 3.96 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 208388 kb
Host smart-37b471d8-8025-4f15-9ab0-5f9369c7e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817362122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2817362122
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.199934706
Short name T782
Test name
Test status
Simulation time 296319438 ps
CPU time 5.69 seconds
Started Jul 24 07:05:26 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 215048 kb
Host smart-d470e9be-ce1f-4d17-9738-cded3426164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199934706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.199934706
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_random.52396944
Short name T117
Test name
Test status
Simulation time 229027819 ps
CPU time 5.77 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 217888 kb
Host smart-f9a538b5-6fad-41e5-870a-4ace4f052c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52396944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.52396944
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2993161861
Short name T398
Test name
Test status
Simulation time 115815848 ps
CPU time 2.4 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 206572 kb
Host smart-9b5f8f86-2834-481f-a365-fd59cee33098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993161861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2993161861
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.364572465
Short name T855
Test name
Test status
Simulation time 145332969 ps
CPU time 4.81 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 207928 kb
Host smart-093c6114-2f73-4828-be19-ebbe3ae40f83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364572465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.364572465
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1376959977
Short name T878
Test name
Test status
Simulation time 340892552 ps
CPU time 4.4 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 208336 kb
Host smart-0acc8936-1864-459a-a5b6-b51b110955c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376959977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1376959977
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2447079103
Short name T605
Test name
Test status
Simulation time 410487937 ps
CPU time 3.77 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 206608 kb
Host smart-767d1b07-1535-489d-880e-51fe0aba219d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447079103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2447079103
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.169646966
Short name T621
Test name
Test status
Simulation time 698652801 ps
CPU time 12.23 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:44 PM PDT 24
Peak memory 208812 kb
Host smart-b507b265-6ac3-4496-9d6a-186a92fdecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169646966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.169646966
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3243922872
Short name T552
Test name
Test status
Simulation time 855368720 ps
CPU time 7.96 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 206544 kb
Host smart-6a1051f1-67ab-4713-93af-b14e788e9331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243922872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3243922872
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2135998137
Short name T724
Test name
Test status
Simulation time 292613773 ps
CPU time 6.74 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 214904 kb
Host smart-3caeccc5-32e9-4114-9a61-fa0bdbf5b954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135998137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2135998137
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4071158062
Short name T685
Test name
Test status
Simulation time 162238972 ps
CPU time 6.88 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:38 PM PDT 24
Peak memory 208816 kb
Host smart-1a5299cf-94e9-4e9d-a5e8-4f6d6affe923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071158062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4071158062
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3846382096
Short name T485
Test name
Test status
Simulation time 34350730 ps
CPU time 1.98 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 209960 kb
Host smart-5089065f-83d9-4b07-9e00-45b77262d0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846382096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3846382096
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4217187600
Short name T535
Test name
Test status
Simulation time 12850904 ps
CPU time 0.94 seconds
Started Jul 24 07:03:53 PM PDT 24
Finished Jul 24 07:03:54 PM PDT 24
Peak memory 205872 kb
Host smart-db56b917-0f01-4884-b352-247cac9c36cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217187600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4217187600
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3823117092
Short name T80
Test name
Test status
Simulation time 32100325 ps
CPU time 2.62 seconds
Started Jul 24 07:03:48 PM PDT 24
Finished Jul 24 07:03:51 PM PDT 24
Peak memory 214052 kb
Host smart-70c23c68-3fe9-4645-9160-313d50f2fdd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823117092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3823117092
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1412308746
Short name T18
Test name
Test status
Simulation time 34329797 ps
CPU time 2.57 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:03:54 PM PDT 24
Peak memory 214292 kb
Host smart-8e7a7588-d090-4031-bc7e-387e56af225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412308746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1412308746
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3976329160
Short name T668
Test name
Test status
Simulation time 228342674 ps
CPU time 2.67 seconds
Started Jul 24 07:03:55 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 208972 kb
Host smart-1b170140-57e6-465d-8e48-aea552386f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976329160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3976329160
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.976594355
Short name T91
Test name
Test status
Simulation time 125959494 ps
CPU time 3.41 seconds
Started Jul 24 07:03:53 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 214056 kb
Host smart-c244246b-2c7e-4c88-bb53-baeeb57c721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976594355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.976594355
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_random.1314435772
Short name T505
Test name
Test status
Simulation time 1347960047 ps
CPU time 5.47 seconds
Started Jul 24 07:03:54 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 207280 kb
Host smart-e906690b-3d69-4292-ab93-3b493ffecd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314435772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1314435772
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2853281597
Short name T11
Test name
Test status
Simulation time 470090010 ps
CPU time 10 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 229044 kb
Host smart-49726b31-59e9-44cd-aa6b-8b686b728aad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853281597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2853281597
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2674667303
Short name T877
Test name
Test status
Simulation time 1714079143 ps
CPU time 11.43 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 208600 kb
Host smart-2a6f7650-ba3a-4618-b5ef-f66c58346839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674667303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2674667303
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3063783574
Short name T161
Test name
Test status
Simulation time 1130978440 ps
CPU time 25.6 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:04:21 PM PDT 24
Peak memory 208224 kb
Host smart-a611d366-fac5-44f2-a195-f9080f74ca99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063783574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3063783574
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1439393127
Short name T692
Test name
Test status
Simulation time 68411818 ps
CPU time 2.71 seconds
Started Jul 24 07:03:53 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 207896 kb
Host smart-83542626-0ac9-4f39-91bb-f857d91fc35b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439393127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1439393127
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.163468116
Short name T560
Test name
Test status
Simulation time 28752366 ps
CPU time 2.39 seconds
Started Jul 24 07:03:53 PM PDT 24
Finished Jul 24 07:03:55 PM PDT 24
Peak memory 208760 kb
Host smart-a0e4bf43-359a-4953-8b60-02d825083a20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163468116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.163468116
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3914127056
Short name T279
Test name
Test status
Simulation time 276006964 ps
CPU time 3.21 seconds
Started Jul 24 07:03:53 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 217940 kb
Host smart-56d995ef-a4a6-4080-8901-7f2861ae602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914127056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3914127056
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3860891427
Short name T669
Test name
Test status
Simulation time 185602312 ps
CPU time 2.68 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:03:54 PM PDT 24
Peak memory 206680 kb
Host smart-c534f970-0a9f-4985-b9ca-4b14f61325d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860891427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3860891427
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2676954727
Short name T342
Test name
Test status
Simulation time 3179302271 ps
CPU time 27.73 seconds
Started Jul 24 07:03:50 PM PDT 24
Finished Jul 24 07:04:18 PM PDT 24
Peak memory 222356 kb
Host smart-774f46f0-0f50-4efe-b5ff-31c570b9ceea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676954727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2676954727
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2649848145
Short name T480
Test name
Test status
Simulation time 27567613 ps
CPU time 2.47 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 208180 kb
Host smart-0a578e1e-2812-404f-aed0-15e706859610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649848145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2649848145
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3960410338
Short name T185
Test name
Test status
Simulation time 164637884 ps
CPU time 2.71 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:03:54 PM PDT 24
Peak memory 209760 kb
Host smart-37d0b500-bb56-4483-ae0f-e56ec6a0a430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960410338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3960410338
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.476752781
Short name T598
Test name
Test status
Simulation time 35714400 ps
CPU time 0.98 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 205900 kb
Host smart-34702b2b-67ff-4942-be29-38b82d410434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476752781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.476752781
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.39589795
Short name T335
Test name
Test status
Simulation time 144608521 ps
CPU time 7.73 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 215276 kb
Host smart-da711005-da5d-4c2b-b1cd-adccfb846fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39589795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.39589795
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2730393756
Short name T875
Test name
Test status
Simulation time 164002809 ps
CPU time 4.21 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:31 PM PDT 24
Peak memory 222536 kb
Host smart-03246d95-6d9c-4a00-a473-0e72ecc47fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730393756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2730393756
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.577432499
Short name T646
Test name
Test status
Simulation time 1180726063 ps
CPU time 9.26 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 209628 kb
Host smart-0dc2a9c5-9b30-4e4f-a2e4-f0ec43d6b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577432499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.577432499
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3305249349
Short name T553
Test name
Test status
Simulation time 86265667 ps
CPU time 3.08 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 214056 kb
Host smart-a8fd8531-124f-4e69-9556-20ee4b811369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305249349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3305249349
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4226060876
Short name T269
Test name
Test status
Simulation time 147746383 ps
CPU time 2.77 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 222168 kb
Host smart-d1c9741e-2a97-48a7-9e3f-6b7318941cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226060876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4226060876
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2428020939
Short name T236
Test name
Test status
Simulation time 72669122 ps
CPU time 3.72 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 214132 kb
Host smart-f8ff2b27-8135-4e41-81c4-2b38855e3098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428020939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2428020939
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.260372347
Short name T684
Test name
Test status
Simulation time 1773598988 ps
CPU time 5.81 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 208892 kb
Host smart-76357193-b8eb-4010-a9c4-dfc83170b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260372347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.260372347
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3038207090
Short name T687
Test name
Test status
Simulation time 202025144 ps
CPU time 6.32 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 207728 kb
Host smart-af8b1951-9827-4fe1-aae5-a8d9237f4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038207090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3038207090
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1440339332
Short name T396
Test name
Test status
Simulation time 62052022 ps
CPU time 3.16 seconds
Started Jul 24 07:05:26 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 206668 kb
Host smart-12723bd2-8298-4bb4-9d37-6ed11726d190
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440339332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1440339332
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4130138620
Short name T885
Test name
Test status
Simulation time 120186166 ps
CPU time 2.45 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 206300 kb
Host smart-df0771a4-4bdd-42fd-ad63-6f9105ff962f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130138620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4130138620
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1970927180
Short name T766
Test name
Test status
Simulation time 882053842 ps
CPU time 5.73 seconds
Started Jul 24 07:05:28 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 208444 kb
Host smart-06dd98fc-6bec-47f3-8792-47146e6d51e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970927180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1970927180
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1382080350
Short name T845
Test name
Test status
Simulation time 49046371 ps
CPU time 2.27 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:33 PM PDT 24
Peak memory 209060 kb
Host smart-1f8f8da0-0590-4e84-9b66-379ec9ad4d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382080350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1382080350
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.271182266
Short name T432
Test name
Test status
Simulation time 127771141 ps
CPU time 3 seconds
Started Jul 24 07:05:27 PM PDT 24
Finished Jul 24 07:05:30 PM PDT 24
Peak memory 206524 kb
Host smart-1f6660f1-d6e8-488d-ac49-fcb97430fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271182266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.271182266
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4169037936
Short name T549
Test name
Test status
Simulation time 129331495 ps
CPU time 3.58 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 207228 kb
Host smart-e4999a32-436e-4435-9291-3933057039fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169037936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4169037936
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.428713166
Short name T112
Test name
Test status
Simulation time 131252773 ps
CPU time 4.62 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 207216 kb
Host smart-bb86d9d9-90e9-48db-ba3e-acc3917d15eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428713166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.428713166
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3808560118
Short name T551
Test name
Test status
Simulation time 228024271 ps
CPU time 2.24 seconds
Started Jul 24 07:05:30 PM PDT 24
Finished Jul 24 07:05:32 PM PDT 24
Peak memory 209880 kb
Host smart-6f078d70-6a22-4e68-a93d-d9842191f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808560118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3808560118
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2233701764
Short name T591
Test name
Test status
Simulation time 22724040 ps
CPU time 0.91 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 205836 kb
Host smart-3c1c69d8-eced-4f24-a14e-ea7b9d7d3d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233701764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2233701764
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2461727087
Short name T409
Test name
Test status
Simulation time 61542865 ps
CPU time 4.36 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 215540 kb
Host smart-a2161cce-7ce7-4cbe-b30c-f81b1fb8abc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461727087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2461727087
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3913539166
Short name T864
Test name
Test status
Simulation time 182294162 ps
CPU time 2.7 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 218160 kb
Host smart-8089680d-218c-4778-a234-982b3f35849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913539166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3913539166
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2574514787
Short name T607
Test name
Test status
Simulation time 171658029 ps
CPU time 2.83 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 205816 kb
Host smart-ff0e9b6b-d60c-4ebf-84de-2223a7d52e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574514787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2574514787
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3833146249
Short name T796
Test name
Test status
Simulation time 49744253 ps
CPU time 2.27 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 218904 kb
Host smart-27fc06a8-59c0-4508-8f76-86c53db5daa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833146249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3833146249
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.40522431
Short name T64
Test name
Test status
Simulation time 114810415 ps
CPU time 4.18 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 214256 kb
Host smart-bb24b4cb-e391-420c-8e7e-6be4389a7a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40522431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.40522431
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4178007514
Short name T907
Test name
Test status
Simulation time 933757266 ps
CPU time 10.86 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 217964 kb
Host smart-406fe74d-7ed9-49e8-9359-381fe6c56341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178007514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4178007514
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4258911500
Short name T534
Test name
Test status
Simulation time 42744257 ps
CPU time 2.18 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 206672 kb
Host smart-400cdc3f-166e-443d-b881-8e0c03ef47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258911500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4258911500
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.819012391
Short name T430
Test name
Test status
Simulation time 57702456 ps
CPU time 2.65 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 207920 kb
Host smart-dd78355f-016b-4aee-8743-e65c7b8cdf5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819012391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.819012391
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4144549881
Short name T755
Test name
Test status
Simulation time 150444430 ps
CPU time 4.53 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:34 PM PDT 24
Peak memory 208632 kb
Host smart-54b16ef9-e304-412c-987c-14771779ba29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144549881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4144549881
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3895239969
Short name T703
Test name
Test status
Simulation time 199408888 ps
CPU time 5.84 seconds
Started Jul 24 07:05:29 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 207632 kb
Host smart-9d5855b2-09d4-469e-b15c-62d74ab77e94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895239969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3895239969
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1889632782
Short name T214
Test name
Test status
Simulation time 794077130 ps
CPU time 3.11 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 208140 kb
Host smart-371752a1-c549-45c4-80ef-bf4260b5c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889632782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1889632782
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3145048807
Short name T826
Test name
Test status
Simulation time 62866195 ps
CPU time 2.3 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 208400 kb
Host smart-88b62894-a37e-40d2-82b7-8bed1e49462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145048807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3145048807
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.485217459
Short name T86
Test name
Test status
Simulation time 688487075 ps
CPU time 5.64 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:38 PM PDT 24
Peak memory 214116 kb
Host smart-ddc729a0-77be-4134-b204-7affd8287f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485217459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.485217459
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2283085821
Short name T601
Test name
Test status
Simulation time 11595076 ps
CPU time 0.91 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 205852 kb
Host smart-7b108d26-639a-4cde-99f2-d724a75ba77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283085821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2283085821
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1034849882
Short name T352
Test name
Test status
Simulation time 316201570 ps
CPU time 2.82 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 214892 kb
Host smart-5b8b934f-f270-4060-9a7b-180a4b65cfce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034849882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1034849882
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3339094214
Short name T24
Test name
Test status
Simulation time 492173061 ps
CPU time 3.22 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 222612 kb
Host smart-344ee910-0496-472b-b3eb-763673b645c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339094214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3339094214
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1517548717
Short name T863
Test name
Test status
Simulation time 36183109 ps
CPU time 1.96 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 206836 kb
Host smart-21ba11b5-23c6-4bd0-8403-51fe55581508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517548717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1517548717
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.54152892
Short name T836
Test name
Test status
Simulation time 73906264 ps
CPU time 2.16 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 215328 kb
Host smart-371e46ea-e89a-4d82-93ed-dc13850d1b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54152892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.54152892
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.396140618
Short name T326
Test name
Test status
Simulation time 69945986 ps
CPU time 3 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 222088 kb
Host smart-6b620f97-92a6-4eb5-b999-d2c3ec851911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396140618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.396140618
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1110701689
Short name T673
Test name
Test status
Simulation time 703879250 ps
CPU time 3.02 seconds
Started Jul 24 07:05:31 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 219920 kb
Host smart-844d4770-eff3-43f3-8116-abbc1c0a7da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110701689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1110701689
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1737664644
Short name T873
Test name
Test status
Simulation time 185745237 ps
CPU time 5.27 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 218064 kb
Host smart-2569997f-780f-41e3-95f1-637a93e47aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737664644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1737664644
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3627596791
Short name T243
Test name
Test status
Simulation time 21829172 ps
CPU time 1.84 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 206652 kb
Host smart-b0ab2d48-4014-4b59-81a3-1b7a660b725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627596791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3627596791
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1337602747
Short name T442
Test name
Test status
Simulation time 228294043 ps
CPU time 3.11 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 208604 kb
Host smart-9ef93524-3e5b-46fd-ad11-6d801bdaf7df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337602747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1337602747
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.970643329
Short name T695
Test name
Test status
Simulation time 511456744 ps
CPU time 4.67 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:40 PM PDT 24
Peak memory 208332 kb
Host smart-40892f17-9668-42ad-9607-c83797314993
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970643329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.970643329
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2010579903
Short name T866
Test name
Test status
Simulation time 156253830 ps
CPU time 4.33 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 207780 kb
Host smart-8a5ffe36-72ce-497c-86f1-47053126f4b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010579903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2010579903
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2699298644
Short name T309
Test name
Test status
Simulation time 312590580 ps
CPU time 3.09 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:35 PM PDT 24
Peak memory 220040 kb
Host smart-a2c448b3-a196-41f5-995b-cc213c60e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699298644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2699298644
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3089601027
Short name T744
Test name
Test status
Simulation time 2052203886 ps
CPU time 5.12 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:40 PM PDT 24
Peak memory 207668 kb
Host smart-3e9ba280-49c3-4eca-9927-07ad7db66442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089601027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3089601027
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3855319707
Short name T63
Test name
Test status
Simulation time 417413019 ps
CPU time 18.02 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 222136 kb
Host smart-4d025303-8bdf-4d98-971a-37286361d839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855319707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3855319707
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.192840542
Short name T634
Test name
Test status
Simulation time 289555209 ps
CPU time 3.4 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 209560 kb
Host smart-c234b921-5836-494e-a7ed-449db5d18d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192840542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.192840542
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3037667236
Short name T441
Test name
Test status
Simulation time 52486889 ps
CPU time 2.18 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 209632 kb
Host smart-4fd1841b-62c2-4596-a80d-e8bcda152648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037667236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3037667236
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.17780653
Short name T561
Test name
Test status
Simulation time 27737218 ps
CPU time 0.81 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 205844 kb
Host smart-0bb853d0-dc9b-4632-ace6-7088a0a4e24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17780653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.17780653
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1077680001
Short name T729
Test name
Test status
Simulation time 192631215 ps
CPU time 4.04 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 210580 kb
Host smart-4f6c5640-a4f6-4bf2-a6dc-c6a654106dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077680001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1077680001
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3393683331
Short name T609
Test name
Test status
Simulation time 532375044 ps
CPU time 4.25 seconds
Started Jul 24 07:05:41 PM PDT 24
Finished Jul 24 07:05:45 PM PDT 24
Peak memory 214092 kb
Host smart-a1f4e9d8-8cc9-41a6-b459-94d4338e6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393683331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3393683331
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.706367653
Short name T306
Test name
Test status
Simulation time 120242756 ps
CPU time 2.62 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 214096 kb
Host smart-b1e92f2d-56a1-4b26-b2bb-02aad060103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706367653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.706367653
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3385700701
Short name T346
Test name
Test status
Simulation time 687578462 ps
CPU time 4.42 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:44 PM PDT 24
Peak memory 214032 kb
Host smart-af5d6659-68c5-42f1-99e3-60ab4f273421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385700701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3385700701
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2710620954
Short name T238
Test name
Test status
Simulation time 1060425138 ps
CPU time 3.73 seconds
Started Jul 24 07:05:41 PM PDT 24
Finished Jul 24 07:05:45 PM PDT 24
Peak memory 220140 kb
Host smart-b9e7c904-345f-46f4-912d-c55b1a8d74b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710620954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2710620954
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4294499884
Short name T776
Test name
Test status
Simulation time 49490111 ps
CPU time 2.82 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:38 PM PDT 24
Peak memory 208120 kb
Host smart-e4e9c10b-4cf9-4af2-b738-0a5afff9482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294499884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4294499884
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2501711401
Short name T568
Test name
Test status
Simulation time 138447464 ps
CPU time 3.73 seconds
Started Jul 24 07:05:33 PM PDT 24
Finished Jul 24 07:05:37 PM PDT 24
Peak memory 207964 kb
Host smart-7338a8a9-f277-4c89-aac2-b7069a3c4bfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501711401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2501711401
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1835551148
Short name T664
Test name
Test status
Simulation time 388355536 ps
CPU time 5.1 seconds
Started Jul 24 07:05:34 PM PDT 24
Finished Jul 24 07:05:39 PM PDT 24
Peak memory 206836 kb
Host smart-c26b43c3-f53e-4def-903d-0e9ac476cdc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835551148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1835551148
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3853326463
Short name T437
Test name
Test status
Simulation time 222375965 ps
CPU time 7.83 seconds
Started Jul 24 07:05:35 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 208264 kb
Host smart-c214423d-6e8a-4aaf-9a75-0470f2ea6c47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853326463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3853326463
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.321510129
Short name T852
Test name
Test status
Simulation time 459047258 ps
CPU time 3.13 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:05:52 PM PDT 24
Peak memory 214068 kb
Host smart-7de52c3f-5e42-452d-b552-af1261445f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321510129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.321510129
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.83112635
Short name T631
Test name
Test status
Simulation time 777102628 ps
CPU time 2.88 seconds
Started Jul 24 07:05:32 PM PDT 24
Finished Jul 24 07:05:36 PM PDT 24
Peak memory 208292 kb
Host smart-fb66d73c-ee7d-4f83-ba79-3c4728fe78b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83112635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.83112635
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1485505280
Short name T354
Test name
Test status
Simulation time 2214010228 ps
CPU time 63.08 seconds
Started Jul 24 07:05:38 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 216660 kb
Host smart-e2c5dfec-1eba-488d-b6a2-7eac5b09ba89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485505280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1485505280
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1563395669
Short name T198
Test name
Test status
Simulation time 546315867 ps
CPU time 18.9 seconds
Started Jul 24 07:05:37 PM PDT 24
Finished Jul 24 07:05:56 PM PDT 24
Peak memory 219852 kb
Host smart-fc8e3e10-6de4-4299-8a82-d6a3d4d317a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563395669 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1563395669
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2361131273
Short name T219
Test name
Test status
Simulation time 282144090 ps
CPU time 4.1 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:44 PM PDT 24
Peak memory 207256 kb
Host smart-9d0e3915-2504-4d13-8197-97e94d9a52bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361131273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2361131273
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.891996222
Short name T39
Test name
Test status
Simulation time 590035457 ps
CPU time 2.67 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 209584 kb
Host smart-98fcb941-b5d2-49c1-8274-664da3dec9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891996222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.891996222
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.583030522
Short name T423
Test name
Test status
Simulation time 34713682 ps
CPU time 0.85 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 205760 kb
Host smart-d878acdd-2cc7-4dee-b963-9a9695c54215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583030522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.583030522
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1082555232
Short name T25
Test name
Test status
Simulation time 542456919 ps
CPU time 15.35 seconds
Started Jul 24 07:05:42 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 210212 kb
Host smart-df847e58-8eb3-4e22-8b24-55f219ddcff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082555232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1082555232
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2236688545
Short name T325
Test name
Test status
Simulation time 87952246 ps
CPU time 2.89 seconds
Started Jul 24 07:05:38 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 206716 kb
Host smart-300e65a3-a390-4b11-b543-630478687f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236688545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2236688545
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2363373560
Short name T722
Test name
Test status
Simulation time 176006272 ps
CPU time 3.38 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 214448 kb
Host smart-d63e053d-eee4-4991-866e-fa497b8b841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363373560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2363373560
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2129694241
Short name T675
Test name
Test status
Simulation time 63115975 ps
CPU time 2.61 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 219464 kb
Host smart-2b510ff1-c6be-4e84-8937-98d5110ba0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129694241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2129694241
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.549045327
Short name T233
Test name
Test status
Simulation time 1399797908 ps
CPU time 3.25 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 207424 kb
Host smart-8a70d59d-cbfd-4a7d-9857-a57a379c59fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549045327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.549045327
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2040713429
Short name T619
Test name
Test status
Simulation time 147039278 ps
CPU time 2.42 seconds
Started Jul 24 07:05:43 PM PDT 24
Finished Jul 24 07:05:45 PM PDT 24
Peak memory 207340 kb
Host smart-948ab0b5-5f83-4bf0-ac6f-68579f355c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040713429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2040713429
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3307772334
Short name T312
Test name
Test status
Simulation time 92212790 ps
CPU time 2.9 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 206644 kb
Host smart-20676770-ec50-4e35-b07f-90d1e85bbd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307772334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3307772334
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.470686962
Short name T493
Test name
Test status
Simulation time 1138144072 ps
CPU time 5.73 seconds
Started Jul 24 07:05:43 PM PDT 24
Finished Jul 24 07:05:49 PM PDT 24
Peak memory 208768 kb
Host smart-be65c225-d9a5-46f1-9a90-64c75c9a215e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470686962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.470686962
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.927416397
Short name T452
Test name
Test status
Simulation time 69420900 ps
CPU time 2.13 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 206584 kb
Host smart-0b9c39e0-3648-410c-a484-cfcb3d5a5368
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927416397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.927416397
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2294911941
Short name T223
Test name
Test status
Simulation time 749867636 ps
CPU time 5.67 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 208516 kb
Host smart-23a0a369-a8b9-4eb1-ab43-ad49a8084cda
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294911941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2294911941
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.745045971
Short name T789
Test name
Test status
Simulation time 167862239 ps
CPU time 1.77 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:05:50 PM PDT 24
Peak memory 206840 kb
Host smart-f95bee82-b7cb-4fae-bfeb-406b1baf4bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745045971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.745045971
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4024493646
Short name T510
Test name
Test status
Simulation time 1316446255 ps
CPU time 27.93 seconds
Started Jul 24 07:05:41 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 207644 kb
Host smart-e96ec27c-a1d5-4944-9bc7-fd9e5e1955d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024493646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4024493646
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.106228278
Short name T458
Test name
Test status
Simulation time 1204143364 ps
CPU time 31.44 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:06:20 PM PDT 24
Peak memory 209404 kb
Host smart-93780696-57e9-4991-97e0-a9c333ef6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106228278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.106228278
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.917435904
Short name T206
Test name
Test status
Simulation time 174113572 ps
CPU time 2.09 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 209600 kb
Host smart-9b67b15a-90a0-4727-acd2-2e19a8dc2c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917435904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.917435904
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1322911037
Short name T670
Test name
Test status
Simulation time 16623507 ps
CPU time 0.79 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:45 PM PDT 24
Peak memory 205848 kb
Host smart-9e70f35d-abab-40dc-8cde-507a1bdea349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322911037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1322911037
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2679763855
Short name T411
Test name
Test status
Simulation time 62911272 ps
CPU time 4.38 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:49 PM PDT 24
Peak memory 222320 kb
Host smart-3fb6d7c3-4fbf-4b01-8d46-72dff0e597bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679763855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2679763855
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.127524871
Short name T30
Test name
Test status
Simulation time 102130185 ps
CPU time 4.27 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:50 PM PDT 24
Peak memory 222552 kb
Host smart-6a9101ab-3602-46ad-8e4e-34e8d4655db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127524871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.127524871
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3592312895
Short name T73
Test name
Test status
Simulation time 286699813 ps
CPU time 2.66 seconds
Started Jul 24 07:05:46 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 209316 kb
Host smart-e457cb8e-dcf2-4707-a54a-a16abf3025b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592312895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3592312895
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.418797887
Short name T627
Test name
Test status
Simulation time 44390087 ps
CPU time 2.38 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:47 PM PDT 24
Peak memory 222168 kb
Host smart-1c1f50e8-fc59-4cdb-9cb5-e604f95978c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418797887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.418797887
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.607967560
Short name T803
Test name
Test status
Simulation time 71808901 ps
CPU time 2.78 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 209956 kb
Host smart-28aaa221-83d3-42f8-85eb-aee42ead5acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607967560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.607967560
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1972176214
Short name T267
Test name
Test status
Simulation time 92139016 ps
CPU time 3.5 seconds
Started Jul 24 07:05:47 PM PDT 24
Finished Jul 24 07:05:51 PM PDT 24
Peak memory 209716 kb
Host smart-01650cdd-ece8-428a-8d10-a2f259f7d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972176214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1972176214
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.360912166
Short name T339
Test name
Test status
Simulation time 36471530 ps
CPU time 2.69 seconds
Started Jul 24 07:05:49 PM PDT 24
Finished Jul 24 07:05:51 PM PDT 24
Peak memory 208456 kb
Host smart-d1256d92-0796-46af-a2d1-108be13dd3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360912166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.360912166
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1340154010
Short name T109
Test name
Test status
Simulation time 263343144 ps
CPU time 3.38 seconds
Started Jul 24 07:05:40 PM PDT 24
Finished Jul 24 07:05:43 PM PDT 24
Peak memory 206636 kb
Host smart-cd75588c-11b2-455a-9372-5fe16d713491
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340154010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1340154010
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1097424506
Short name T678
Test name
Test status
Simulation time 738651370 ps
CPU time 3.26 seconds
Started Jul 24 07:05:38 PM PDT 24
Finished Jul 24 07:05:41 PM PDT 24
Peak memory 206568 kb
Host smart-ae9cff19-73f3-4e48-a9e3-c0e4c7f87e67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097424506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1097424506
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.820293765
Short name T614
Test name
Test status
Simulation time 87251459 ps
CPU time 1.85 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:46 PM PDT 24
Peak memory 206576 kb
Host smart-622fb5f3-5967-48a0-805c-5daa1eca0df3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820293765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.820293765
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1312504584
Short name T759
Test name
Test status
Simulation time 36783686 ps
CPU time 2.64 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:47 PM PDT 24
Peak memory 214044 kb
Host smart-0d598923-494c-4758-81ce-95eb76ad499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312504584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1312504584
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.550014161
Short name T769
Test name
Test status
Simulation time 74066361 ps
CPU time 3.01 seconds
Started Jul 24 07:05:39 PM PDT 24
Finished Jul 24 07:05:42 PM PDT 24
Peak memory 208128 kb
Host smart-5d5c76ea-62f6-4245-8a6f-334b921f064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550014161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.550014161
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1398088840
Short name T910
Test name
Test status
Simulation time 2670466969 ps
CPU time 26.49 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:06:11 PM PDT 24
Peak memory 215908 kb
Host smart-c25dae08-a5fc-4db1-838e-6e70abcd980c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398088840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1398088840
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1830195105
Short name T528
Test name
Test status
Simulation time 461513646 ps
CPU time 5.29 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:50 PM PDT 24
Peak memory 218136 kb
Host smart-d2b38279-3fda-4f08-bf42-70925a0c515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830195105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1830195105
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.840783833
Short name T760
Test name
Test status
Simulation time 1062712693 ps
CPU time 11.66 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:56 PM PDT 24
Peak memory 210144 kb
Host smart-09541fd1-d164-4cad-a081-7ce42ea648ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840783833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.840783833
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3146619661
Short name T579
Test name
Test status
Simulation time 61013233 ps
CPU time 0.82 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:46 PM PDT 24
Peak memory 205836 kb
Host smart-80a12d42-caa1-4c91-bbd3-20bf6414ec6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146619661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3146619661
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2983900966
Short name T421
Test name
Test status
Simulation time 148355861 ps
CPU time 8.07 seconds
Started Jul 24 07:05:47 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 214020 kb
Host smart-386e3b1e-4a75-4e2e-9f28-a9e34e8ef21a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983900966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2983900966
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4136717017
Short name T31
Test name
Test status
Simulation time 222648214 ps
CPU time 2.07 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:47 PM PDT 24
Peak memory 217160 kb
Host smart-f42829d5-3373-4550-923a-f621237c1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136717017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4136717017
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.307604661
Short name T797
Test name
Test status
Simulation time 1067974075 ps
CPU time 6.61 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:52 PM PDT 24
Peak memory 217968 kb
Host smart-15d697b2-a4dd-4c59-8a91-ec99c334a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307604661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.307604661
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3913865381
Short name T900
Test name
Test status
Simulation time 65381618 ps
CPU time 2.31 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 214172 kb
Host smart-e37adc6b-1a0a-41df-bf48-c0df124b6310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913865381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3913865381
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.635297058
Short name T448
Test name
Test status
Simulation time 92788964 ps
CPU time 2.54 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:05:51 PM PDT 24
Peak memory 214056 kb
Host smart-6a61d588-30d8-4d5f-960f-dce480a7118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635297058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.635297058
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.366920343
Short name T436
Test name
Test status
Simulation time 54993329 ps
CPU time 2.35 seconds
Started Jul 24 07:05:50 PM PDT 24
Finished Jul 24 07:05:53 PM PDT 24
Peak memory 207356 kb
Host smart-2b8bda45-1909-4fe1-8795-6214f54a63eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366920343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.366920343
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1778383957
Short name T715
Test name
Test status
Simulation time 506692758 ps
CPU time 6.72 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 207680 kb
Host smart-1f702bcd-d994-4acf-b6cf-d4c08a4829fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778383957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1778383957
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1851876584
Short name T311
Test name
Test status
Simulation time 14690045547 ps
CPU time 27.34 seconds
Started Jul 24 07:05:48 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 208448 kb
Host smart-e67faf49-affb-4487-8d41-0830be4a4610
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851876584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1851876584
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3482703141
Short name T457
Test name
Test status
Simulation time 128705655 ps
CPU time 2.32 seconds
Started Jul 24 07:05:46 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 206668 kb
Host smart-158b3c93-e4a6-4468-a6d2-3169b00b2fd5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482703141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3482703141
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1138798215
Short name T468
Test name
Test status
Simulation time 393593854 ps
CPU time 5.05 seconds
Started Jul 24 07:05:44 PM PDT 24
Finished Jul 24 07:05:49 PM PDT 24
Peak memory 206848 kb
Host smart-a570e532-ab7c-4ec5-8cc3-911233d1501d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138798215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1138798215
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3024133128
Short name T749
Test name
Test status
Simulation time 271408411 ps
CPU time 2.97 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 215568 kb
Host smart-8fa19b88-0c09-457c-9c33-24213a65aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024133128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3024133128
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3771215574
Short name T444
Test name
Test status
Simulation time 124057702 ps
CPU time 3.02 seconds
Started Jul 24 07:05:45 PM PDT 24
Finished Jul 24 07:05:48 PM PDT 24
Peak memory 206568 kb
Host smart-42ef2bc8-7180-40e5-9a4d-45a795b4aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771215574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3771215574
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2832863506
Short name T788
Test name
Test status
Simulation time 91164832 ps
CPU time 4.11 seconds
Started Jul 24 07:05:50 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 214076 kb
Host smart-56176937-e18b-4a60-a939-812a6a9d2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832863506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2832863506
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1726266725
Short name T839
Test name
Test status
Simulation time 62400793 ps
CPU time 2.15 seconds
Started Jul 24 07:05:46 PM PDT 24
Finished Jul 24 07:05:49 PM PDT 24
Peak memory 209556 kb
Host smart-2b7f04b1-2615-496c-b2b0-96fe61994106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726266725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1726266725
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.782420060
Short name T425
Test name
Test status
Simulation time 10262443 ps
CPU time 0.75 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:05:52 PM PDT 24
Peak memory 205796 kb
Host smart-1076b81e-010b-4953-a0bc-647a0d936a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782420060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.782420060
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3984012675
Short name T266
Test name
Test status
Simulation time 156089350 ps
CPU time 4.81 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 215144 kb
Host smart-6deb9a0a-7036-4541-937e-6c52b11418a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984012675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3984012675
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2876838776
Short name T731
Test name
Test status
Simulation time 111079883 ps
CPU time 2.78 seconds
Started Jul 24 07:05:54 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 222488 kb
Host smart-53bef592-e26f-4531-a9eb-11b2153478df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876838776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2876838776
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.546132563
Short name T584
Test name
Test status
Simulation time 4661229778 ps
CPU time 33.76 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 214212 kb
Host smart-7f82fa5a-d959-46d2-820e-18a3eeadebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546132563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.546132563
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4062654240
Short name T194
Test name
Test status
Simulation time 44072224 ps
CPU time 2.16 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 209516 kb
Host smart-51bf50e2-6ae2-4017-ba61-1e628893d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062654240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4062654240
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.159506917
Short name T413
Test name
Test status
Simulation time 222669833 ps
CPU time 6.67 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:59 PM PDT 24
Peak memory 207644 kb
Host smart-13babf5d-391d-4cda-8180-4b5bc3de879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159506917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.159506917
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3326302313
Short name T490
Test name
Test status
Simulation time 84489826 ps
CPU time 3.24 seconds
Started Jul 24 07:05:50 PM PDT 24
Finished Jul 24 07:05:54 PM PDT 24
Peak memory 208444 kb
Host smart-bce1bbd5-ca99-4e2e-b850-27a139c37fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326302313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3326302313
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1340549502
Short name T399
Test name
Test status
Simulation time 156749412 ps
CPU time 4.91 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 208812 kb
Host smart-654f488a-7a14-4c24-83db-050da2b4dfd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340549502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1340549502
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.291532590
Short name T781
Test name
Test status
Simulation time 129036300 ps
CPU time 3.32 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 208372 kb
Host smart-1b4f1041-5337-4267-8b63-f215c97558ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291532590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.291532590
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3670255221
Short name T367
Test name
Test status
Simulation time 10331620639 ps
CPU time 17.44 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:06:10 PM PDT 24
Peak memory 208772 kb
Host smart-eb4383aa-ccd3-41d3-b1e8-563eb32305f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670255221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3670255221
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1485846573
Short name T492
Test name
Test status
Simulation time 355384933 ps
CPU time 4.03 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:56 PM PDT 24
Peak memory 209588 kb
Host smart-dc9db904-a333-45df-bc05-1218e640d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485846573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1485846573
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.496645322
Short name T787
Test name
Test status
Simulation time 92108777 ps
CPU time 3.5 seconds
Started Jul 24 07:05:54 PM PDT 24
Finished Jul 24 07:05:58 PM PDT 24
Peak memory 208240 kb
Host smart-69aba8f3-1625-428b-acda-4072fe826a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496645322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.496645322
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1523727527
Short name T371
Test name
Test status
Simulation time 3115789606 ps
CPU time 24.16 seconds
Started Jul 24 07:05:54 PM PDT 24
Finished Jul 24 07:06:18 PM PDT 24
Peak memory 221416 kb
Host smart-ecbe4856-d7a1-4e70-8e86-dbc3bce9fc40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523727527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1523727527
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1955575665
Short name T139
Test name
Test status
Simulation time 129431360 ps
CPU time 2.69 seconds
Started Jul 24 07:05:55 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 207244 kb
Host smart-2b92a066-eab5-4da6-812b-8779f1ca3a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955575665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1955575665
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.442064275
Short name T649
Test name
Test status
Simulation time 533416492 ps
CPU time 5.07 seconds
Started Jul 24 07:05:54 PM PDT 24
Finished Jul 24 07:05:59 PM PDT 24
Peak memory 210608 kb
Host smart-3145b042-b210-4ad5-b67e-83ada7fa5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442064275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.442064275
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.963386090
Short name T698
Test name
Test status
Simulation time 10927867 ps
CPU time 0.77 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:05:57 PM PDT 24
Peak memory 205832 kb
Host smart-dae28f05-5a55-4b02-83e9-da8d3c1937d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963386090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.963386090
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4159311271
Short name T302
Test name
Test status
Simulation time 769740681 ps
CPU time 11.43 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 215092 kb
Host smart-632a7644-0f1e-4075-a453-f7a10b631402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159311271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4159311271
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1802450018
Short name T717
Test name
Test status
Simulation time 33431822 ps
CPU time 1.83 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:05:53 PM PDT 24
Peak memory 207872 kb
Host smart-e22baf87-595e-4739-8ec9-30439853450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802450018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1802450018
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.32538139
Short name T862
Test name
Test status
Simulation time 252597938 ps
CPU time 7.6 seconds
Started Jul 24 07:05:59 PM PDT 24
Finished Jul 24 07:06:06 PM PDT 24
Peak memory 209144 kb
Host smart-a1236746-393f-4b13-86e7-4493b674ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32538139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.32538139
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2307459500
Short name T600
Test name
Test status
Simulation time 726287585 ps
CPU time 5.87 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:03 PM PDT 24
Peak memory 214080 kb
Host smart-b1952589-b366-45f1-99e2-0ed94818363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307459500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2307459500
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.744530268
Short name T688
Test name
Test status
Simulation time 277243518 ps
CPU time 3.11 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:01 PM PDT 24
Peak memory 206204 kb
Host smart-e733bf35-b8c2-403f-b0d6-2cf290586b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744530268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.744530268
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1088537070
Short name T768
Test name
Test status
Simulation time 507695636 ps
CPU time 7.01 seconds
Started Jul 24 07:05:53 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 208992 kb
Host smart-be6a69e0-5775-4a40-9eb0-290d81b89487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088537070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1088537070
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3220046002
Short name T274
Test name
Test status
Simulation time 578259628 ps
CPU time 10.95 seconds
Started Jul 24 07:05:53 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 208508 kb
Host smart-3dc4a7e8-fa14-4262-962b-7b9f28eb37de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220046002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3220046002
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4071741018
Short name T405
Test name
Test status
Simulation time 528886567 ps
CPU time 3.14 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 206764 kb
Host smart-4657a7ca-bcbc-4d80-a880-7740838574dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071741018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4071741018
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3374138962
Short name T204
Test name
Test status
Simulation time 2151953660 ps
CPU time 9.4 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:06:02 PM PDT 24
Peak memory 208736 kb
Host smart-04ebf04d-2fcc-4dda-b50d-86d1d114b9d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374138962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3374138962
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4176552254
Short name T516
Test name
Test status
Simulation time 205395292 ps
CPU time 3.5 seconds
Started Jul 24 07:05:52 PM PDT 24
Finished Jul 24 07:05:56 PM PDT 24
Peak memory 208420 kb
Host smart-ced35b87-f37a-4443-be34-a1c88a993ae3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176552254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4176552254
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3052476339
Short name T693
Test name
Test status
Simulation time 18555830 ps
CPU time 1.71 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:05:58 PM PDT 24
Peak memory 207900 kb
Host smart-f6826ee1-f1ca-401d-850c-f3d5ce8dc350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052476339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3052476339
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3329780163
Short name T763
Test name
Test status
Simulation time 3688856478 ps
CPU time 20.59 seconds
Started Jul 24 07:05:51 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 208480 kb
Host smart-fa23000b-6afd-4251-a6a7-cdbac73748a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329780163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3329780163
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.49338513
Short name T60
Test name
Test status
Simulation time 933735195 ps
CPU time 24.37 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 214032 kb
Host smart-3c88aaf3-5f9f-4114-8c13-a19b64a31c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49338513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.49338513
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3281304270
Short name T242
Test name
Test status
Simulation time 172323904 ps
CPU time 6.31 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 209124 kb
Host smart-97be575c-8c57-4fef-92c0-d038d7f82caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281304270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3281304270
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1837199382
Short name T674
Test name
Test status
Simulation time 60863062 ps
CPU time 1.82 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 209704 kb
Host smart-0944ef5f-9671-489c-a455-208ae742746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837199382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1837199382
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2919990011
Short name T554
Test name
Test status
Simulation time 28142166 ps
CPU time 0.92 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:05:59 PM PDT 24
Peak memory 205892 kb
Host smart-d5376740-692b-416a-a01f-042bae96aee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919990011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2919990011
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.33841667
Short name T419
Test name
Test status
Simulation time 154852168 ps
CPU time 8.02 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 213988 kb
Host smart-62b7c174-49f7-45c8-b6b3-1c4c1a44b128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33841667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.33841667
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4095407155
Short name T28
Test name
Test status
Simulation time 540012468 ps
CPU time 5.01 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:02 PM PDT 24
Peak memory 216300 kb
Host smart-5e643c71-db4a-4ccc-83bc-12b7290e8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095407155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4095407155
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4096098452
Short name T887
Test name
Test status
Simulation time 261577123 ps
CPU time 3.5 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 209012 kb
Host smart-188a2a4d-5704-4966-8334-cb820258021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096098452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4096098452
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2947551840
Short name T628
Test name
Test status
Simulation time 57131566 ps
CPU time 3.59 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:01 PM PDT 24
Peak memory 220600 kb
Host smart-e9bd169f-83a0-4339-adea-2914e963f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947551840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2947551840
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.379544120
Short name T854
Test name
Test status
Simulation time 464372098 ps
CPU time 9.12 seconds
Started Jul 24 07:05:55 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 214016 kb
Host smart-a5ce5e4d-1131-4123-99e9-ad66aeff2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379544120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.379544120
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3081652241
Short name T225
Test name
Test status
Simulation time 32480679 ps
CPU time 2.07 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 207868 kb
Host smart-e9e69d61-f171-4812-92e9-4cc143838dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081652241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3081652241
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2652619769
Short name T704
Test name
Test status
Simulation time 133054750 ps
CPU time 6.02 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 214276 kb
Host smart-19d57738-a9d3-4969-9ee7-4e25da61e862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652619769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2652619769
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.59511347
Short name T85
Test name
Test status
Simulation time 189172274 ps
CPU time 2.56 seconds
Started Jul 24 07:05:59 PM PDT 24
Finished Jul 24 07:06:02 PM PDT 24
Peak memory 206800 kb
Host smart-fc8409d1-d618-41b0-87e6-ab3cf0f9cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59511347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.59511347
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3718555991
Short name T449
Test name
Test status
Simulation time 86071125 ps
CPU time 2.58 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 206804 kb
Host smart-f1093c3c-92e1-4134-98c6-3ad3a41c8885
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718555991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3718555991
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.643508054
Short name T666
Test name
Test status
Simulation time 155599618 ps
CPU time 2.28 seconds
Started Jul 24 07:05:57 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 206696 kb
Host smart-bbdbdffa-e247-4534-bab9-e247b080f224
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643508054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.643508054
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.265182871
Short name T506
Test name
Test status
Simulation time 688389404 ps
CPU time 3.62 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:02 PM PDT 24
Peak memory 208604 kb
Host smart-7b67a3fe-7a60-4674-a87c-a76859bfebbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265182871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.265182871
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.714591266
Short name T662
Test name
Test status
Simulation time 45928499 ps
CPU time 2.76 seconds
Started Jul 24 07:05:59 PM PDT 24
Finished Jul 24 07:06:02 PM PDT 24
Peak memory 214016 kb
Host smart-13842c01-b981-469e-aac1-7f5f7145c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714591266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.714591266
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.231045712
Short name T599
Test name
Test status
Simulation time 124113308 ps
CPU time 4.08 seconds
Started Jul 24 07:05:56 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 206412 kb
Host smart-d94e33ca-29dd-43da-82af-dc9ad01c36f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231045712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.231045712
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2002865013
Short name T391
Test name
Test status
Simulation time 666332458 ps
CPU time 5.3 seconds
Started Jul 24 07:06:00 PM PDT 24
Finished Jul 24 07:06:05 PM PDT 24
Peak memory 209440 kb
Host smart-c30bc30e-bbc5-4d0c-be35-6219c34d4353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002865013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2002865013
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1867648318
Short name T118
Test name
Test status
Simulation time 53771770 ps
CPU time 1.9 seconds
Started Jul 24 07:05:58 PM PDT 24
Finished Jul 24 07:06:00 PM PDT 24
Peak memory 209656 kb
Host smart-b0869d29-a562-43c9-9889-d2a4e1d94e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867648318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1867648318
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1089408352
Short name T475
Test name
Test status
Simulation time 10045930 ps
CPU time 0.72 seconds
Started Jul 24 07:04:15 PM PDT 24
Finished Jul 24 07:04:16 PM PDT 24
Peak memory 205832 kb
Host smart-d16f158c-70fc-489d-a8cd-59b479b9d5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089408352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1089408352
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2292095664
Short name T20
Test name
Test status
Simulation time 73416039 ps
CPU time 1.47 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 217492 kb
Host smart-a0e0b08e-420f-4360-9205-c0bb17589201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292095664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2292095664
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1023885863
Short name T495
Test name
Test status
Simulation time 136583365 ps
CPU time 2.41 seconds
Started Jul 24 07:03:54 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 207264 kb
Host smart-623ba21f-a7bb-4ec3-8721-cebc4b561ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023885863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1023885863
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1056467510
Short name T764
Test name
Test status
Simulation time 98872813 ps
CPU time 4.97 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 214432 kb
Host smart-e51e43a2-2400-47fe-b99a-2bd8cbf60aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056467510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1056467510
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.18093592
Short name T908
Test name
Test status
Simulation time 284708506 ps
CPU time 5.08 seconds
Started Jul 24 07:03:59 PM PDT 24
Finished Jul 24 07:04:04 PM PDT 24
Peak memory 220540 kb
Host smart-ad2fe579-4f39-424d-b09c-bc3adf05ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18093592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.18093592
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2083045730
Short name T841
Test name
Test status
Simulation time 190185595 ps
CPU time 1.93 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:03:55 PM PDT 24
Peak memory 205884 kb
Host smart-203b1226-a377-4ff6-8201-251ec53aa55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083045730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2083045730
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2437482160
Short name T296
Test name
Test status
Simulation time 724800940 ps
CPU time 19.68 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:04:11 PM PDT 24
Peak memory 207704 kb
Host smart-7d4c63e8-b7cd-4441-bb2a-97e963e3d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437482160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2437482160
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.828087919
Short name T582
Test name
Test status
Simulation time 193619768 ps
CPU time 5.64 seconds
Started Jul 24 07:03:54 PM PDT 24
Finished Jul 24 07:04:00 PM PDT 24
Peak memory 207708 kb
Host smart-536e68a1-ed9c-41f6-a9e8-632840e30b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828087919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.828087919
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3770235601
Short name T390
Test name
Test status
Simulation time 121642370 ps
CPU time 4.58 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:03:57 PM PDT 24
Peak memory 208084 kb
Host smart-73fcb915-4c41-4e55-95c3-13b4ce09e3fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770235601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3770235601
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1195845944
Short name T522
Test name
Test status
Simulation time 1459930415 ps
CPU time 10.02 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 208576 kb
Host smart-b50f0604-69ef-4c64-bf02-03effc61706c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195845944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1195845944
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4253081409
Short name T487
Test name
Test status
Simulation time 24556331628 ps
CPU time 53.5 seconds
Started Jul 24 07:03:52 PM PDT 24
Finished Jul 24 07:04:46 PM PDT 24
Peak memory 208712 kb
Host smart-048ae73a-1b9b-4196-a632-217c506a5ed8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253081409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4253081409
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.951811373
Short name T728
Test name
Test status
Simulation time 194915469 ps
CPU time 2.68 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 209016 kb
Host smart-f4c3b7e8-7ec0-42e7-9298-097504b57bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951811373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.951811373
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4219812546
Short name T743
Test name
Test status
Simulation time 379281929 ps
CPU time 4.31 seconds
Started Jul 24 07:03:51 PM PDT 24
Finished Jul 24 07:03:56 PM PDT 24
Peak memory 208236 kb
Host smart-ef1246eb-cac1-4611-962d-f7808959ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219812546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4219812546
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1530499643
Short name T207
Test name
Test status
Simulation time 21299813347 ps
CPU time 47.95 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 221384 kb
Host smart-a82a339f-9294-4aa8-bff3-a92f8ef87dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530499643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1530499643
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.534421533
Short name T284
Test name
Test status
Simulation time 356249734 ps
CPU time 4.59 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:04:00 PM PDT 24
Peak memory 209144 kb
Host smart-21090e63-941f-4367-bffa-a551d85ede6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534421533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.534421533
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3185577241
Short name T382
Test name
Test status
Simulation time 135501133 ps
CPU time 3.04 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 210024 kb
Host smart-545dc10c-66c6-47fa-abb2-68dd3c8fa995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185577241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3185577241
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2432661029
Short name T422
Test name
Test status
Simulation time 20816446 ps
CPU time 0.84 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:06 PM PDT 24
Peak memory 205920 kb
Host smart-194c8ddd-e9b4-4e54-8157-03166a4c6df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432661029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2432661029
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3131213121
Short name T59
Test name
Test status
Simulation time 99161762 ps
CPU time 3.84 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 208596 kb
Host smart-a24aff84-f8c9-41fd-9de7-02dba67b4099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131213121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3131213121
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1278295548
Short name T290
Test name
Test status
Simulation time 85400916 ps
CPU time 2.8 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:08 PM PDT 24
Peak memory 214084 kb
Host smart-20ac003a-cc06-4f4f-9b3e-15191cd1af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278295548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1278295548
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3081042628
Short name T751
Test name
Test status
Simulation time 131081863 ps
CPU time 3.31 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 221936 kb
Host smart-d918c9cc-851d-4506-9b4b-a2a6c5db6977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081042628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3081042628
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2259467061
Short name T228
Test name
Test status
Simulation time 176140068 ps
CPU time 2.73 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 215460 kb
Host smart-b16ba400-0152-48a3-8070-aafdb03aeeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259467061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2259467061
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1953300176
Short name T247
Test name
Test status
Simulation time 318474140 ps
CPU time 2.92 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:07 PM PDT 24
Peak memory 207140 kb
Host smart-c66a2e67-cd0a-4dab-8690-7bcbeecb8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953300176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1953300176
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.973966197
Short name T319
Test name
Test status
Simulation time 154142709 ps
CPU time 3.44 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:08 PM PDT 24
Peak memory 208352 kb
Host smart-604d9eec-c610-4a06-9bef-66e6ec87cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973966197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.973966197
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.185229072
Short name T702
Test name
Test status
Simulation time 301390968 ps
CPU time 3.33 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 208864 kb
Host smart-9e987a8d-b2a6-4764-a5c4-7fd2c03f05e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185229072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.185229072
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1731829956
Short name T844
Test name
Test status
Simulation time 429459636 ps
CPU time 3.61 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 208536 kb
Host smart-fd048829-1f1f-44c9-935c-838ea4b1eaa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731829956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1731829956
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3395843932
Short name T465
Test name
Test status
Simulation time 77881677 ps
CPU time 3.55 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 208444 kb
Host smart-c816a9ce-7ecd-48ac-be06-268e317fc18e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395843932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3395843932
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2105290120
Short name T414
Test name
Test status
Simulation time 58698881 ps
CPU time 2 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:06 PM PDT 24
Peak memory 207492 kb
Host smart-c75c1102-af95-422a-a700-9b37c73d92f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105290120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2105290120
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2595891561
Short name T871
Test name
Test status
Simulation time 2068445949 ps
CPU time 5.18 seconds
Started Jul 24 07:05:59 PM PDT 24
Finished Jul 24 07:06:04 PM PDT 24
Peak memory 206540 kb
Host smart-46a53fd1-d79a-4446-bdbb-b0c84ec8ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595891561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2595891561
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1983913591
Short name T130
Test name
Test status
Simulation time 975912214 ps
CPU time 15.42 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 222400 kb
Host smart-4536a533-78c2-43f7-b3e3-fd1623435866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983913591 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1983913591
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1566814515
Short name T412
Test name
Test status
Simulation time 39630321 ps
CPU time 2.99 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 207704 kb
Host smart-b66990de-90aa-4159-a3ed-0672792546e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566814515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1566814515
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3899727513
Short name T810
Test name
Test status
Simulation time 102648608 ps
CPU time 2.78 seconds
Started Jul 24 07:06:11 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 210144 kb
Host smart-cba89e6c-108f-4633-9505-be505e2e7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899727513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3899727513
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4187562661
Short name T833
Test name
Test status
Simulation time 21077442 ps
CPU time 0.78 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:10 PM PDT 24
Peak memory 205796 kb
Host smart-d7dcbcbc-83f4-4698-aba5-0bc2cda46f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187562661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4187562661
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.344045169
Short name T389
Test name
Test status
Simulation time 124020488 ps
CPU time 2.88 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:07 PM PDT 24
Peak memory 214072 kb
Host smart-908613ac-ccac-4ae4-903f-c028b525709a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344045169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.344045169
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.838025111
Short name T667
Test name
Test status
Simulation time 1067342183 ps
CPU time 4.14 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:13 PM PDT 24
Peak memory 208524 kb
Host smart-f3506f4a-4346-4abf-8737-554e865a34b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838025111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.838025111
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1922675390
Short name T690
Test name
Test status
Simulation time 263739098 ps
CPU time 1.77 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:07 PM PDT 24
Peak memory 207176 kb
Host smart-d70f05b7-95e0-4865-954e-33b42303dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922675390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1922675390
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4185087857
Short name T360
Test name
Test status
Simulation time 125763149 ps
CPU time 1.85 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 219964 kb
Host smart-d98c1a63-92dc-4c2d-997e-82b7c8aabf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185087857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4185087857
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3833011820
Short name T563
Test name
Test status
Simulation time 283659817 ps
CPU time 3.5 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 209120 kb
Host smart-0aa38c66-cec9-4174-981e-ca3b51cc2f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833011820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3833011820
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2338524347
Short name T592
Test name
Test status
Simulation time 298867376 ps
CPU time 4.16 seconds
Started Jul 24 07:06:05 PM PDT 24
Finished Jul 24 07:06:10 PM PDT 24
Peak memory 209116 kb
Host smart-6e52ac93-7566-497b-8123-cff96990439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338524347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2338524347
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3250797175
Short name T772
Test name
Test status
Simulation time 911554751 ps
CPU time 4.17 seconds
Started Jul 24 07:06:07 PM PDT 24
Finished Jul 24 07:06:11 PM PDT 24
Peak memory 208588 kb
Host smart-022801fb-0737-438f-a9ef-e463ac003ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250797175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3250797175
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.111193853
Short name T611
Test name
Test status
Simulation time 25362148 ps
CPU time 2.21 seconds
Started Jul 24 07:06:07 PM PDT 24
Finished Jul 24 07:06:09 PM PDT 24
Peak memory 208132 kb
Host smart-487b73df-2cc6-4c15-88da-1dd2fd449e6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111193853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.111193853
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1628665752
Short name T604
Test name
Test status
Simulation time 115703573 ps
CPU time 3.88 seconds
Started Jul 24 07:06:04 PM PDT 24
Finished Jul 24 07:06:08 PM PDT 24
Peak memory 206592 kb
Host smart-3583ec4e-1c76-4d95-8564-94e539a64d5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628665752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1628665752
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3794910320
Short name T445
Test name
Test status
Simulation time 4294603764 ps
CPU time 31.08 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:38 PM PDT 24
Peak memory 207924 kb
Host smart-eefc1dd3-6884-43a0-9e8b-c55a71d6ec44
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794910320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3794910320
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3781022094
Short name T716
Test name
Test status
Simulation time 110725775 ps
CPU time 3.83 seconds
Started Jul 24 07:06:08 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 209848 kb
Host smart-f61bb5f5-03b0-4d79-b36b-391da5320c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781022094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3781022094
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4217468670
Short name T794
Test name
Test status
Simulation time 126352422 ps
CPU time 2.68 seconds
Started Jul 24 07:06:07 PM PDT 24
Finished Jul 24 07:06:10 PM PDT 24
Peak memory 208220 kb
Host smart-df3f6afa-3f94-4e16-9323-46ef31cdaad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217468670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4217468670
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3073401686
Short name T232
Test name
Test status
Simulation time 2366277393 ps
CPU time 31.15 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 222408 kb
Host smart-38c86448-9661-457c-b79c-51b43221fe4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073401686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3073401686
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1913670512
Short name T512
Test name
Test status
Simulation time 160510440 ps
CPU time 6.08 seconds
Started Jul 24 07:06:06 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 209908 kb
Host smart-d7f22efb-5c9b-489f-808a-e95eb6615a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913670512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1913670512
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2458795507
Short name T136
Test name
Test status
Simulation time 42231745 ps
CPU time 2.21 seconds
Started Jul 24 07:06:13 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 209808 kb
Host smart-9a8960e2-ba6f-48fc-ab8a-8b3a5f61c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458795507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2458795507
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1629811932
Short name T431
Test name
Test status
Simulation time 10515219 ps
CPU time 0.82 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 205816 kb
Host smart-9674b5ca-d36d-4652-a587-b9776ea5fc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629811932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1629811932
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1000643131
Short name T406
Test name
Test status
Simulation time 236912250 ps
CPU time 13.13 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 214684 kb
Host smart-e7ce359a-e24e-4b2b-a40b-9e8d6eb56132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000643131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1000643131
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.37859551
Short name T71
Test name
Test status
Simulation time 433015879 ps
CPU time 2.53 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:15 PM PDT 24
Peak memory 208848 kb
Host smart-19dd57c0-d86d-493b-b652-0fa37e6a955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37859551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.37859551
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.551909127
Short name T100
Test name
Test status
Simulation time 51435016 ps
CPU time 3.24 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:13 PM PDT 24
Peak memory 209492 kb
Host smart-14720fa0-9450-41da-b48b-bbf0ac84f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551909127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.551909127
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.136919769
Short name T273
Test name
Test status
Simulation time 339686050 ps
CPU time 2.85 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 214020 kb
Host smart-dfdf7a10-d224-41b8-8c70-21b44d38962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136919769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.136919769
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2627602453
Short name T5
Test name
Test status
Simulation time 79048271 ps
CPU time 2.4 seconds
Started Jul 24 07:06:08 PM PDT 24
Finished Jul 24 07:06:11 PM PDT 24
Peak memory 214572 kb
Host smart-8f77b0d6-4550-4fbd-8a09-466a3518d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627602453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2627602453
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1382191784
Short name T575
Test name
Test status
Simulation time 872138383 ps
CPU time 6.03 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 214044 kb
Host smart-d57b2452-0269-4fe5-b9d1-f4827fa2728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382191784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1382191784
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1388628833
Short name T615
Test name
Test status
Simulation time 10511245116 ps
CPU time 24.37 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 208172 kb
Host smart-eae4f578-5261-435a-9a54-9688dc59686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388628833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1388628833
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.869282336
Short name T714
Test name
Test status
Simulation time 172352250 ps
CPU time 2.62 seconds
Started Jul 24 07:06:08 PM PDT 24
Finished Jul 24 07:06:11 PM PDT 24
Peak memory 208564 kb
Host smart-8cf1474f-696c-4aa4-b8b7-651171d70c16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869282336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.869282336
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4223885524
Short name T434
Test name
Test status
Simulation time 113189227 ps
CPU time 4.39 seconds
Started Jul 24 07:06:08 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 207888 kb
Host smart-3f065085-496a-4fd5-a966-8353dbf525d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223885524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4223885524
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4204686453
Short name T905
Test name
Test status
Simulation time 3435566615 ps
CPU time 16.5 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 209012 kb
Host smart-eb3e7606-16a5-4912-aab3-00bff01c9dfd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204686453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4204686453
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3015961408
Short name T541
Test name
Test status
Simulation time 369445418 ps
CPU time 3.5 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 209564 kb
Host smart-58ad34c0-43a8-4bc1-9040-822ac688f719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015961408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3015961408
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2196664076
Short name T650
Test name
Test status
Simulation time 191956867 ps
CPU time 2.67 seconds
Started Jul 24 07:06:11 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 206492 kb
Host smart-b423a4e1-4450-4e80-bcbc-00762d6dd108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196664076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2196664076
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2353775585
Short name T746
Test name
Test status
Simulation time 222142077 ps
CPU time 2.79 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 219524 kb
Host smart-a3c6e5fa-b6a2-4eda-ae23-6b420a00eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353775585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2353775585
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.126199712
Short name T647
Test name
Test status
Simulation time 190676890 ps
CPU time 3.71 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 210132 kb
Host smart-6b4823ed-78f3-4058-ae83-1de49123f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126199712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.126199712
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1969040179
Short name T883
Test name
Test status
Simulation time 17917904 ps
CPU time 0.99 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 205828 kb
Host smart-9e965763-8424-4832-b1f7-1f0b895eaed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969040179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1969040179
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1788172627
Short name T874
Test name
Test status
Simulation time 233789893 ps
CPU time 4.47 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 215228 kb
Host smart-60922bec-2922-4bb7-8263-89bceb95db29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788172627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1788172627
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1594708750
Short name T36
Test name
Test status
Simulation time 354028235 ps
CPU time 4.61 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 213952 kb
Host smart-c34516a8-54c4-447c-8b71-a4198b2649da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594708750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1594708750
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1194904162
Short name T712
Test name
Test status
Simulation time 3232446359 ps
CPU time 11.91 seconds
Started Jul 24 07:06:13 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 208468 kb
Host smart-238b4885-7be9-47b9-a0ea-f645ab421571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194904162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1194904162
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2759759623
Short name T586
Test name
Test status
Simulation time 1567656725 ps
CPU time 3.94 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 214060 kb
Host smart-5760579e-670b-4b8f-811c-aff099d47c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759759623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2759759623
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2576865548
Short name T758
Test name
Test status
Simulation time 636989595 ps
CPU time 3.77 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:18 PM PDT 24
Peak memory 213912 kb
Host smart-c4215762-0373-4a51-8138-44fc1cb68ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576865548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2576865548
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3934916675
Short name T404
Test name
Test status
Simulation time 93563588 ps
CPU time 3.25 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 214088 kb
Host smart-de2f31a9-66ee-4004-b779-9a5531de09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934916675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3934916675
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3986167624
Short name T671
Test name
Test status
Simulation time 262667584 ps
CPU time 5.8 seconds
Started Jul 24 07:06:13 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 209028 kb
Host smart-63b7f8a5-a70f-443b-a08b-cdbc75d306aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986167624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3986167624
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.139831616
Short name T329
Test name
Test status
Simulation time 699411297 ps
CPU time 4.6 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 208656 kb
Host smart-2d60e2ef-69cd-4db9-b248-c9a00bc170cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139831616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.139831616
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.270012014
Short name T580
Test name
Test status
Simulation time 104851853 ps
CPU time 2.89 seconds
Started Jul 24 07:06:11 PM PDT 24
Finished Jul 24 07:06:14 PM PDT 24
Peak memory 206608 kb
Host smart-19bcb30c-9208-445f-8d2e-05770f4ab63a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270012014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.270012014
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2283278606
Short name T87
Test name
Test status
Simulation time 243864290 ps
CPU time 3.1 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 206780 kb
Host smart-5c5c62af-abfb-4458-9951-cf6057a0ac33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283278606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2283278606
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3192045555
Short name T482
Test name
Test status
Simulation time 212949267 ps
CPU time 3.82 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:18 PM PDT 24
Peak memory 206696 kb
Host smart-89461a82-1aec-4d30-b82d-2fc9b2a193f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192045555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3192045555
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1025142625
Short name T821
Test name
Test status
Simulation time 123151657 ps
CPU time 3.04 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 208120 kb
Host smart-2d3db699-8d59-410f-8f33-86da6f3c8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025142625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1025142625
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2638256362
Short name T427
Test name
Test status
Simulation time 163977641 ps
CPU time 2.11 seconds
Started Jul 24 07:06:09 PM PDT 24
Finished Jul 24 07:06:12 PM PDT 24
Peak memory 206728 kb
Host smart-fc71c248-eba6-43c6-911a-d2d0db983102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638256362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2638256362
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.468339524
Short name T208
Test name
Test status
Simulation time 5429276067 ps
CPU time 31.37 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 216824 kb
Host smart-79dd1511-c69a-49c3-a03e-69f67ab644d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468339524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.468339524
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4269663403
Short name T820
Test name
Test status
Simulation time 529161417 ps
CPU time 5.29 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 214064 kb
Host smart-f2c6fdde-c969-44a8-affe-fb4f5fcd36b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269663403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4269663403
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.119280510
Short name T381
Test name
Test status
Simulation time 155951191 ps
CPU time 2.29 seconds
Started Jul 24 07:06:13 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 210020 kb
Host smart-c2bdb4c0-edcc-425e-84db-d0cff9fce49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119280510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.119280510
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2120253773
Short name T635
Test name
Test status
Simulation time 50135869 ps
CPU time 0.89 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:15 PM PDT 24
Peak memory 205836 kb
Host smart-c017dfb7-ec13-4157-8463-4c85a0e085a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120253773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2120253773
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2489177822
Short name T525
Test name
Test status
Simulation time 214019617 ps
CPU time 2.97 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 218300 kb
Host smart-cd490527-58a8-48b2-b938-8c9f56da0748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489177822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2489177822
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1693186476
Short name T882
Test name
Test status
Simulation time 167809997 ps
CPU time 2.09 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 207348 kb
Host smart-302f21a4-9c70-47ab-b4ea-fe7b930fa098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693186476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1693186476
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2386505690
Short name T734
Test name
Test status
Simulation time 2261353769 ps
CPU time 32.48 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:45 PM PDT 24
Peak memory 214012 kb
Host smart-f8f3640c-2836-4388-a3f5-a79218689338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386505690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2386505690
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1592852777
Short name T828
Test name
Test status
Simulation time 254896780 ps
CPU time 6.44 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:24 PM PDT 24
Peak memory 214936 kb
Host smart-13fe820c-40ef-4318-bf12-c88cdf8176ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592852777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1592852777
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3276088701
Short name T865
Test name
Test status
Simulation time 163512757 ps
CPU time 2.63 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 214060 kb
Host smart-c825c5c3-1ff0-404a-b5ea-72920e4616cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276088701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3276088701
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1345745985
Short name T462
Test name
Test status
Simulation time 99234587 ps
CPU time 4.62 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 208256 kb
Host smart-a861c2a8-5825-44bd-ac5b-b8410eb9d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345745985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1345745985
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.234887446
Short name T785
Test name
Test status
Simulation time 106984034 ps
CPU time 1.9 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 206680 kb
Host smart-477af5d9-4bdf-4db1-bcc2-3c5763b75cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234887446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.234887446
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1973994070
Short name T616
Test name
Test status
Simulation time 62113027 ps
CPU time 2.34 seconds
Started Jul 24 07:06:16 PM PDT 24
Finished Jul 24 07:06:18 PM PDT 24
Peak memory 206556 kb
Host smart-00cea9e7-5067-4aa3-b069-5f03328db143
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973994070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1973994070
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1666900653
Short name T840
Test name
Test status
Simulation time 272045849 ps
CPU time 5.19 seconds
Started Jul 24 07:06:10 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 207916 kb
Host smart-cff4bfe3-15f7-4fdc-933f-23e2093069b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666900653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1666900653
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3408042661
Short name T853
Test name
Test status
Simulation time 180261652 ps
CPU time 5.74 seconds
Started Jul 24 07:06:11 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 206860 kb
Host smart-4d736e1e-31dc-434c-abbd-c3649c5e23cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408042661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3408042661
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3939135962
Short name T308
Test name
Test status
Simulation time 161551884 ps
CPU time 1.84 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 209592 kb
Host smart-37f8e3ea-2d45-4901-88dd-69da9d7652f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939135962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3939135962
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3962638845
Short name T829
Test name
Test status
Simulation time 955124641 ps
CPU time 3.15 seconds
Started Jul 24 07:06:12 PM PDT 24
Finished Jul 24 07:06:16 PM PDT 24
Peak memory 208208 kb
Host smart-a55eb981-e883-469a-a95b-7b8478be075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962638845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3962638845
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4288441284
Short name T196
Test name
Test status
Simulation time 1015254156 ps
CPU time 17.37 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 220392 kb
Host smart-fe6a8248-5676-4bfe-8c1b-3b7a7488dddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288441284 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4288441284
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1479945477
Short name T536
Test name
Test status
Simulation time 234630600 ps
CPU time 7.29 seconds
Started Jul 24 07:06:13 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 218016 kb
Host smart-c1de9873-bd2b-46bd-bb96-0d582516f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479945477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1479945477
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1686556280
Short name T681
Test name
Test status
Simulation time 100369061 ps
CPU time 3.24 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 209836 kb
Host smart-a1348373-e652-4ec0-8dee-f076491a3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686556280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1686556280
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3556252090
Short name T725
Test name
Test status
Simulation time 13494032 ps
CPU time 0.9 seconds
Started Jul 24 07:06:16 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 205876 kb
Host smart-1d15cbcb-2819-4fbb-9b06-2d5b3b8c2d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556252090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3556252090
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.135462108
Short name T331
Test name
Test status
Simulation time 217998494 ps
CPU time 12.08 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 215216 kb
Host smart-b58ec4fb-33d5-4d34-b786-cd09f3c221ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135462108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.135462108
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.888525081
Short name T26
Test name
Test status
Simulation time 70072202 ps
CPU time 2.63 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 214084 kb
Host smart-46e63ac2-d048-44b3-b549-e2de20ca61cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888525081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.888525081
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.285449181
Short name T69
Test name
Test status
Simulation time 41957567 ps
CPU time 1.33 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 206688 kb
Host smart-888930b1-caac-4612-a746-b52a25c76acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285449181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.285449181
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3051875343
Short name T359
Test name
Test status
Simulation time 159769310 ps
CPU time 2.63 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 214080 kb
Host smart-273d2453-a74e-407e-8088-2c31e1d60203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051875343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3051875343
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1301440166
Short name T344
Test name
Test status
Simulation time 82639567 ps
CPU time 1.69 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 213916 kb
Host smart-94594584-8240-4188-95d3-02dbf2271870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301440166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1301440166
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3713235100
Short name T618
Test name
Test status
Simulation time 213468986 ps
CPU time 3.15 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:18 PM PDT 24
Peak memory 209460 kb
Host smart-b7bd222f-af85-45fd-816e-1427521dbb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713235100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3713235100
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4220250553
Short name T370
Test name
Test status
Simulation time 1326384777 ps
CPU time 35.16 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 208276 kb
Host smart-85cbb576-1765-48f1-bbab-457b105876fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220250553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4220250553
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2199633570
Short name T287
Test name
Test status
Simulation time 108802427 ps
CPU time 4.74 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:22 PM PDT 24
Peak memory 206656 kb
Host smart-9006e004-cbb8-4373-9189-5ce8ce9e1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199633570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2199633570
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1782202415
Short name T472
Test name
Test status
Simulation time 136030367 ps
CPU time 3.35 seconds
Started Jul 24 07:06:16 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 207928 kb
Host smart-ca833ace-ddfa-425e-9655-1d608bcbe899
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782202415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1782202415
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3271682593
Short name T741
Test name
Test status
Simulation time 547330351 ps
CPU time 6.95 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 208564 kb
Host smart-1f619a08-337c-4517-9dbd-ca187cb5171c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271682593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3271682593
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4083112569
Short name T400
Test name
Test status
Simulation time 2303328919 ps
CPU time 18.04 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:53 PM PDT 24
Peak memory 208572 kb
Host smart-d2285e65-99fa-4a09-95f6-85057abd1bd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083112569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4083112569
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3490860667
Short name T750
Test name
Test status
Simulation time 822679970 ps
CPU time 20.66 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:40 PM PDT 24
Peak memory 214080 kb
Host smart-8e70aaee-fc72-4bcc-a446-eb35e96057d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490860667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3490860667
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2048276409
Short name T706
Test name
Test status
Simulation time 140290759 ps
CPU time 2.01 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 206496 kb
Host smart-b684f123-d8b3-4a69-a1dc-d796c6bc49d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048276409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2048276409
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2970561193
Short name T738
Test name
Test status
Simulation time 147396643 ps
CPU time 3.85 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 209708 kb
Host smart-a778b45d-39e7-4662-b862-a0553446b80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970561193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2970561193
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4034564563
Short name T189
Test name
Test status
Simulation time 1135222873 ps
CPU time 2.38 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 210612 kb
Host smart-efa69800-49ce-4f85-b40a-e17c0780c475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034564563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4034564563
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.475244683
Short name T502
Test name
Test status
Simulation time 46150301 ps
CPU time 0.91 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 205756 kb
Host smart-4d59044c-5c02-4929-940e-e5fb6d437ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475244683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.475244683
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1925271004
Short name T812
Test name
Test status
Simulation time 77840977 ps
CPU time 3.54 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 209800 kb
Host smart-a0f8598d-c8ab-4b20-9f6b-41c0facfa27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925271004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1925271004
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1156470657
Short name T901
Test name
Test status
Simulation time 74184235 ps
CPU time 1.87 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:17 PM PDT 24
Peak memory 207836 kb
Host smart-2de29465-00bc-4db6-ba61-ac18fe43ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156470657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1156470657
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2664776192
Short name T798
Test name
Test status
Simulation time 323630271 ps
CPU time 8.87 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 222076 kb
Host smart-62109b8a-490b-44af-afa5-c6287d5e55e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664776192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2664776192
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3739140953
Short name T361
Test name
Test status
Simulation time 97472006 ps
CPU time 2.44 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 214012 kb
Host smart-132f153b-a1c2-4d3d-bded-f249fd7ce4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739140953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3739140953
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3393790103
Short name T416
Test name
Test status
Simulation time 65154006 ps
CPU time 3.8 seconds
Started Jul 24 07:06:16 PM PDT 24
Finished Jul 24 07:06:20 PM PDT 24
Peak memory 209372 kb
Host smart-41f69632-0264-4fef-93f7-15a08262c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393790103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3393790103
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2299019354
Short name T373
Test name
Test status
Simulation time 481654560 ps
CPU time 5.32 seconds
Started Jul 24 07:06:26 PM PDT 24
Finished Jul 24 07:06:31 PM PDT 24
Peak memory 207404 kb
Host smart-6833b699-d1fc-41b6-9be7-ea605f95ac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299019354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2299019354
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2855998617
Short name T571
Test name
Test status
Simulation time 709102008 ps
CPU time 6.54 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 208660 kb
Host smart-3a974cb4-8d8c-4eb8-962e-233020041fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855998617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2855998617
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2757065017
Short name T567
Test name
Test status
Simulation time 1215265730 ps
CPU time 18.62 seconds
Started Jul 24 07:06:14 PM PDT 24
Finished Jul 24 07:06:33 PM PDT 24
Peak memory 208092 kb
Host smart-13f6ad41-af01-4c8a-9cad-8c2c96e4b61c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757065017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2757065017
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1704444014
Short name T694
Test name
Test status
Simulation time 37376628 ps
CPU time 2.64 seconds
Started Jul 24 07:06:16 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 208464 kb
Host smart-d31cd084-c93b-4002-8086-cba31446c350
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704444014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1704444014
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1365287841
Short name T334
Test name
Test status
Simulation time 135104457 ps
CPU time 5.64 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:24 PM PDT 24
Peak memory 208620 kb
Host smart-e9412fb5-bf62-4c1d-aaeb-ddc875b755c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365287841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1365287841
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3634069431
Short name T310
Test name
Test status
Simulation time 524847623 ps
CPU time 12.08 seconds
Started Jul 24 07:06:15 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 209476 kb
Host smart-a9aa7602-d513-4626-b538-d85385028ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634069431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3634069431
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2870908220
Short name T827
Test name
Test status
Simulation time 528415447 ps
CPU time 14.09 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 207676 kb
Host smart-085dc790-28d5-4bea-904a-557fd43cdf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870908220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2870908220
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.692086399
Short name T756
Test name
Test status
Simulation time 1730037439 ps
CPU time 24.11 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 214844 kb
Host smart-19cab022-5785-4d07-9856-17e0e32da84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692086399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.692086399
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2643752675
Short name T847
Test name
Test status
Simulation time 249817705 ps
CPU time 8.99 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 222484 kb
Host smart-8f3a5269-200f-4a0a-9611-4341dc141bb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643752675 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2643752675
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3076239784
Short name T661
Test name
Test status
Simulation time 142938323 ps
CPU time 3.61 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 207276 kb
Host smart-d3168306-0870-4d72-beee-4e203ed6f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076239784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3076239784
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2449610235
Short name T578
Test name
Test status
Simulation time 46449218 ps
CPU time 2.53 seconds
Started Jul 24 07:06:18 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 209924 kb
Host smart-b080e125-225d-4e32-9d05-b56200807e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449610235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2449610235
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1941420913
Short name T779
Test name
Test status
Simulation time 26004190 ps
CPU time 0.72 seconds
Started Jul 24 07:06:26 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 205840 kb
Host smart-6e727b7a-f099-4955-b77d-4f2f619471dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941420913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1941420913
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2120488615
Short name T410
Test name
Test status
Simulation time 6436730014 ps
CPU time 76.43 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 214276 kb
Host smart-d056309e-9e42-45cd-86be-54a66aff043b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120488615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2120488615
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1306854312
Short name T38
Test name
Test status
Simulation time 206602438 ps
CPU time 5.13 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:30 PM PDT 24
Peak memory 214040 kb
Host smart-9e000c3f-e9cc-4c0e-ab0e-295ab5ba14ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306854312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1306854312
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1641872738
Short name T393
Test name
Test status
Simulation time 310963653 ps
CPU time 1.91 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 209108 kb
Host smart-111f141c-1107-4dac-8717-7525b98d82d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641872738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1641872738
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2580132443
Short name T251
Test name
Test status
Simulation time 60226204 ps
CPU time 2.38 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 214036 kb
Host smart-b5e9354f-fd57-4bf1-81c9-7d4467bc770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580132443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2580132443
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2973209253
Short name T417
Test name
Test status
Simulation time 129441845 ps
CPU time 2.66 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 214208 kb
Host smart-b211c3a9-a3ab-4a2f-a9ab-9c053d6e26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973209253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2973209253
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3052416828
Short name T872
Test name
Test status
Simulation time 334922654 ps
CPU time 9.32 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:31 PM PDT 24
Peak memory 209588 kb
Host smart-129fe7eb-8e6a-4ca6-a9ad-8db650ccafa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052416828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3052416828
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1894411759
Short name T503
Test name
Test status
Simulation time 164765293 ps
CPU time 3.79 seconds
Started Jul 24 07:06:19 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 208372 kb
Host smart-a4e8c9d7-1b2f-46fc-a822-b27d43ad3ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894411759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1894411759
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1354106794
Short name T477
Test name
Test status
Simulation time 93593572 ps
CPU time 4.07 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 206640 kb
Host smart-f6fd4f1b-0300-45b7-a477-6e9694904f23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354106794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1354106794
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1771305822
Short name T753
Test name
Test status
Simulation time 122341023 ps
CPU time 2.41 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 207380 kb
Host smart-274db1d0-0274-4d0d-9037-5b2015dd6558
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771305822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1771305822
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2863024881
Short name T321
Test name
Test status
Simulation time 370783769 ps
CPU time 3.57 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 208692 kb
Host smart-19d30709-8e56-4e76-942f-64e9b0882dea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863024881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2863024881
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1651308364
Short name T217
Test name
Test status
Simulation time 275671802 ps
CPU time 3.21 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:24 PM PDT 24
Peak memory 209076 kb
Host smart-d3b4bdd3-2413-4f5e-9cd2-77c716b3da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651308364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1651308364
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2628854068
Short name T450
Test name
Test status
Simulation time 42486835 ps
CPU time 1.8 seconds
Started Jul 24 07:06:17 PM PDT 24
Finished Jul 24 07:06:19 PM PDT 24
Peak memory 206560 kb
Host smart-b9a97362-a6e6-4162-b4b5-c85a86e7b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628854068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2628854068
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.898533559
Short name T686
Test name
Test status
Simulation time 1083630593 ps
CPU time 16.43 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 222368 kb
Host smart-566ba8eb-669b-4749-ad23-ac23825b2bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898533559 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.898533559
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3265154322
Short name T456
Test name
Test status
Simulation time 194100654 ps
CPU time 7.27 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:32 PM PDT 24
Peak memory 214164 kb
Host smart-05039aea-87f3-4e28-b386-aa310eff7ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265154322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3265154322
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1241385593
Short name T378
Test name
Test status
Simulation time 1007160639 ps
CPU time 5.52 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 210760 kb
Host smart-4c18d052-fffd-4d6f-bfd2-402ebde88158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241385593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1241385593
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2368138405
Short name T587
Test name
Test status
Simulation time 51601105 ps
CPU time 0.91 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 205772 kb
Host smart-1de459ad-8b4c-4da4-a3c2-cfb081ae90ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368138405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2368138405
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4075485425
Short name T418
Test name
Test status
Simulation time 59776549 ps
CPU time 3.59 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 214788 kb
Host smart-55f48dfc-1f30-4daa-b2a6-0a09d752c62f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075485425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4075485425
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3761515195
Short name T736
Test name
Test status
Simulation time 78912043 ps
CPU time 2.93 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 218048 kb
Host smart-de2ff743-6661-4b85-9301-90a4fffd6fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761515195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3761515195
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1069721889
Short name T660
Test name
Test status
Simulation time 104645815 ps
CPU time 3.2 seconds
Started Jul 24 07:06:26 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 209028 kb
Host smart-55320748-2b50-47e7-bdc2-eb237db5331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069721889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1069721889
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1601055099
Short name T89
Test name
Test status
Simulation time 60300606 ps
CPU time 4.1 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 214076 kb
Host smart-772d0c46-09c9-4447-9f88-43e8226cc058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601055099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1601055099
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2528752697
Short name T721
Test name
Test status
Simulation time 40481576 ps
CPU time 2.65 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:24 PM PDT 24
Peak memory 213968 kb
Host smart-6a24281d-c6a2-4d63-9a62-1379e84a4588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528752697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2528752697
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2955194383
Short name T762
Test name
Test status
Simulation time 321381225 ps
CPU time 2.7 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 214088 kb
Host smart-37113541-5a8e-4f14-be1e-592e0d722880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955194383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2955194383
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1913813808
Short name T374
Test name
Test status
Simulation time 317811276 ps
CPU time 4.32 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 208876 kb
Host smart-5c31011a-c7ea-4085-b6d2-9e9cacbfdd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913813808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1913813808
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.245710098
Short name T439
Test name
Test status
Simulation time 301991932 ps
CPU time 3.41 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:24 PM PDT 24
Peak memory 207812 kb
Host smart-609936c5-093b-4591-82fc-87735bbe7145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245710098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.245710098
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2407413705
Short name T341
Test name
Test status
Simulation time 1923945527 ps
CPU time 5.81 seconds
Started Jul 24 07:06:23 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 207832 kb
Host smart-69dd9b3a-c317-40a4-b3f8-dfe56dc4d2e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407413705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2407413705
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3084011747
Short name T460
Test name
Test status
Simulation time 65244503 ps
CPU time 2.7 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 206624 kb
Host smart-82301f17-9f76-41c8-97b1-b3d0beeffeb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084011747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3084011747
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2806081046
Short name T888
Test name
Test status
Simulation time 228307476 ps
CPU time 3.55 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 208768 kb
Host smart-051fc353-5f7b-47b6-ae64-e69a04275bdb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806081046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2806081046
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3354617373
Short name T509
Test name
Test status
Simulation time 22090255 ps
CPU time 1.66 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:23 PM PDT 24
Peak memory 207664 kb
Host smart-5a01eb2a-a751-4e6d-acac-525c05a989f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354617373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3354617373
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1851948403
Short name T395
Test name
Test status
Simulation time 127165324 ps
CPU time 2.22 seconds
Started Jul 24 07:06:20 PM PDT 24
Finished Jul 24 07:06:22 PM PDT 24
Peak memory 206580 kb
Host smart-b4f5d7bc-2da8-4784-a9f4-bea0d67d5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851948403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1851948403
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2586161512
Short name T83
Test name
Test status
Simulation time 661817177 ps
CPU time 5.52 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 206768 kb
Host smart-4dfcfc55-4f4d-491c-b564-0db160342a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586161512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2586161512
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3690010572
Short name T825
Test name
Test status
Simulation time 64022923 ps
CPU time 3.61 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 207280 kb
Host smart-559efbc6-5088-4036-8b0b-a8fed12f5055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690010572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3690010572
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.643576943
Short name T191
Test name
Test status
Simulation time 52371733 ps
CPU time 2.27 seconds
Started Jul 24 07:06:23 PM PDT 24
Finished Jul 24 07:06:26 PM PDT 24
Peak memory 209872 kb
Host smart-29d8f7f5-9639-436a-8bc6-cb5249238d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643576943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.643576943
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1534434709
Short name T602
Test name
Test status
Simulation time 10221319 ps
CPU time 0.82 seconds
Started Jul 24 07:06:29 PM PDT 24
Finished Jul 24 07:06:30 PM PDT 24
Peak memory 205880 kb
Host smart-22d169b2-fd8b-46c2-930f-67b632b17496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534434709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1534434709
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1891926875
Short name T280
Test name
Test status
Simulation time 177547788 ps
CPU time 4.2 seconds
Started Jul 24 07:06:23 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 218136 kb
Host smart-965c39d5-fe81-423f-b92d-ab311a3c1a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891926875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1891926875
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2448070446
Short name T899
Test name
Test status
Simulation time 122462377 ps
CPU time 3.45 seconds
Started Jul 24 07:06:25 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 222324 kb
Host smart-c3e16751-7852-498b-9a98-1507d864e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448070446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2448070446
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4094796570
Short name T255
Test name
Test status
Simulation time 62915701 ps
CPU time 2.36 seconds
Started Jul 24 07:06:30 PM PDT 24
Finished Jul 24 07:06:33 PM PDT 24
Peak memory 213996 kb
Host smart-1b6e9699-e657-4fab-a80d-2070a0d52a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094796570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4094796570
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.2805005682
Short name T257
Test name
Test status
Simulation time 720314710 ps
CPU time 5.64 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 209844 kb
Host smart-989dcbfe-feeb-4a69-9656-1017a115cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805005682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2805005682
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.628084989
Short name T555
Test name
Test status
Simulation time 133199877 ps
CPU time 2.6 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:25 PM PDT 24
Peak memory 208456 kb
Host smart-88a3a3f0-196e-419d-86e7-c5b278c71970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628084989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.628084989
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2890037852
Short name T403
Test name
Test status
Simulation time 379085663 ps
CPU time 3.42 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 208648 kb
Host smart-3f2b78f1-84f2-49cf-b2fd-2398b5dd5795
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890037852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2890037852
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2337392375
Short name T451
Test name
Test status
Simulation time 1398798279 ps
CPU time 6.08 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:30 PM PDT 24
Peak memory 207900 kb
Host smart-b9c8dec9-0cdf-49f5-916b-4b228565401c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337392375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2337392375
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2105743238
Short name T804
Test name
Test status
Simulation time 537583466 ps
CPU time 6.14 seconds
Started Jul 24 07:06:22 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 207916 kb
Host smart-cd957fb4-1433-42b6-8ffd-02899d0c17e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105743238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2105743238
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1368592235
Short name T366
Test name
Test status
Simulation time 725412465 ps
CPU time 5.32 seconds
Started Jul 24 07:06:29 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 208608 kb
Host smart-9c21fe3c-1ed2-46bf-8696-c30af1d30646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368592235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1368592235
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4138966784
Short name T805
Test name
Test status
Simulation time 831548956 ps
CPU time 8 seconds
Started Jul 24 07:06:21 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 208240 kb
Host smart-e35eaf5f-bd37-4dfd-a4f9-988a5cfc5de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138966784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4138966784
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1803893166
Short name T617
Test name
Test status
Simulation time 831991874 ps
CPU time 12.14 seconds
Started Jul 24 07:06:28 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 222408 kb
Host smart-2b409699-3a70-43e9-a8ba-2474e7376fe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803893166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1803893166
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.149216312
Short name T633
Test name
Test status
Simulation time 194345430 ps
CPU time 5.03 seconds
Started Jul 24 07:06:24 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 207480 kb
Host smart-f5edb61e-dc4e-428c-a28f-329349e00360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149216312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.149216312
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.192178566
Short name T911
Test name
Test status
Simulation time 420914540 ps
CPU time 2.48 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:30 PM PDT 24
Peak memory 210744 kb
Host smart-43410af7-3a14-4330-b7ff-98fc1fae4379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192178566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.192178566
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2100813949
Short name T565
Test name
Test status
Simulation time 10555891 ps
CPU time 0.84 seconds
Started Jul 24 07:04:14 PM PDT 24
Finished Jul 24 07:04:16 PM PDT 24
Peak memory 205848 kb
Host smart-0b5357f4-a87f-40e5-924f-f48bcfeb8655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100813949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2100813949
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1643172691
Short name T657
Test name
Test status
Simulation time 52868012 ps
CPU time 3.62 seconds
Started Jul 24 07:03:59 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 214940 kb
Host smart-a16c7bb0-4806-4727-a2d9-95068db3083b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643172691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1643172691
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3462044926
Short name T547
Test name
Test status
Simulation time 102241621 ps
CPU time 2.96 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:00 PM PDT 24
Peak memory 209000 kb
Host smart-e4f57e70-4e18-4644-9283-6bf6a9a5c281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462044926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3462044926
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2188978110
Short name T774
Test name
Test status
Simulation time 30392462 ps
CPU time 2.09 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 214048 kb
Host smart-31fe0a03-308d-4a54-9e6b-37662b3e3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188978110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2188978110
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1322372341
Short name T253
Test name
Test status
Simulation time 623693837 ps
CPU time 3.65 seconds
Started Jul 24 07:03:59 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 214012 kb
Host smart-471a04bb-4fc1-4d67-a6ec-40eb39192fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322372341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1322372341
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.667725234
Short name T42
Test name
Test status
Simulation time 460554956 ps
CPU time 6.38 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:04 PM PDT 24
Peak memory 214048 kb
Host smart-4a89b0ef-3412-4c18-ae74-5261714492c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667725234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.667725234
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3099241068
Short name T218
Test name
Test status
Simulation time 613450865 ps
CPU time 5.64 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 219412 kb
Host smart-0c8934cc-a244-447a-9174-74c06005ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099241068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3099241068
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.570969399
Short name T679
Test name
Test status
Simulation time 56765261 ps
CPU time 2.78 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 208280 kb
Host smart-3abb60a9-106f-4b6f-a5c0-bba3f6e5fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570969399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.570969399
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1820724617
Short name T538
Test name
Test status
Simulation time 93669560 ps
CPU time 2.25 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 208708 kb
Host smart-535ce7bc-5766-4318-b579-bda69e61e942
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820724617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1820724617
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3977859649
Short name T84
Test name
Test status
Simulation time 255846220 ps
CPU time 3.91 seconds
Started Jul 24 07:03:59 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 208308 kb
Host smart-c1b45696-fc57-4bcd-a618-eb04568e4ab1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977859649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3977859649
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.910795454
Short name T800
Test name
Test status
Simulation time 207156027 ps
CPU time 2.52 seconds
Started Jul 24 07:03:59 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 206736 kb
Host smart-0116e389-4799-46a2-aa8d-134870ca089e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910795454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.910795454
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4133564792
Short name T244
Test name
Test status
Simulation time 156280837 ps
CPU time 3.58 seconds
Started Jul 24 07:04:05 PM PDT 24
Finished Jul 24 07:04:09 PM PDT 24
Peak memory 208716 kb
Host smart-56fba04a-5ca8-4f5d-a31d-231c1a738598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133564792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4133564792
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.505166617
Short name T513
Test name
Test status
Simulation time 129693430 ps
CPU time 3.96 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 208292 kb
Host smart-491adb32-3896-4755-a440-562b43dc1988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505166617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.505166617
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.237928739
Short name T75
Test name
Test status
Simulation time 1527770803 ps
CPU time 28.03 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 221320 kb
Host smart-f1fd03f2-341d-42a3-ba4b-a520ddfa3079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237928739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.237928739
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1079477036
Short name T235
Test name
Test status
Simulation time 1119585716 ps
CPU time 18.22 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:16 PM PDT 24
Peak memory 222804 kb
Host smart-0d0eb476-2f0e-41e2-a6ce-e101a250b851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079477036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1079477036
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.424555224
Short name T576
Test name
Test status
Simulation time 102384911 ps
CPU time 4.98 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 208864 kb
Host smart-25111b0a-c486-4c9b-8afb-4c3197d4a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424555224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.424555224
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2871003240
Short name T581
Test name
Test status
Simulation time 370647379 ps
CPU time 2.28 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 209672 kb
Host smart-2501a1a4-23dc-49b2-840e-cfda94a02878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871003240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2871003240
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3246262690
Short name T858
Test name
Test status
Simulation time 12251504 ps
CPU time 0.82 seconds
Started Jul 24 07:04:02 PM PDT 24
Finished Jul 24 07:04:03 PM PDT 24
Peak memory 205860 kb
Host smart-37f0fde2-dbf2-40f1-9317-19617edb4ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246262690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3246262690
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1586447939
Short name T387
Test name
Test status
Simulation time 81748209 ps
CPU time 4.71 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 213964 kb
Host smart-59e63315-c4eb-4359-b4fc-68cdcbcdfb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586447939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1586447939
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2141940572
Short name T718
Test name
Test status
Simulation time 123367016 ps
CPU time 2.24 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 214164 kb
Host smart-15f59595-20c7-4cfb-8670-a976fab02868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141940572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2141940572
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.707616895
Short name T93
Test name
Test status
Simulation time 163371563 ps
CPU time 5.43 seconds
Started Jul 24 07:04:04 PM PDT 24
Finished Jul 24 07:04:10 PM PDT 24
Peak memory 209360 kb
Host smart-7f5d4f3d-5807-4a3d-a4c1-9381233901b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707616895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.707616895
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2338050178
Short name T757
Test name
Test status
Simulation time 110324804 ps
CPU time 5.22 seconds
Started Jul 24 07:04:04 PM PDT 24
Finished Jul 24 07:04:09 PM PDT 24
Peak memory 214808 kb
Host smart-829a5f8f-6fe1-47e0-ac7d-43696c7d9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338050178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2338050178
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2044388413
Short name T526
Test name
Test status
Simulation time 373519512 ps
CPU time 2.84 seconds
Started Jul 24 07:03:55 PM PDT 24
Finished Jul 24 07:03:58 PM PDT 24
Peak memory 214100 kb
Host smart-69a451b5-c4c6-4c1c-8250-457702717696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044388413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2044388413
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3817730385
Short name T461
Test name
Test status
Simulation time 175266995 ps
CPU time 4.93 seconds
Started Jul 24 07:04:04 PM PDT 24
Finished Jul 24 07:04:09 PM PDT 24
Peak memory 214060 kb
Host smart-87d781e3-edfc-4aca-ba92-44cfed431bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817730385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3817730385
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2670914310
Short name T754
Test name
Test status
Simulation time 94151395 ps
CPU time 2.54 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:00 PM PDT 24
Peak memory 208388 kb
Host smart-6ab1713a-4d6b-40b0-8b7c-2331f1d7ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670914310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2670914310
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.240677525
Short name T518
Test name
Test status
Simulation time 132196604 ps
CPU time 2.7 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 208756 kb
Host smart-199acc6c-f31b-4c9d-807b-dda9c94d50cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240677525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.240677525
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3225130340
Short name T770
Test name
Test status
Simulation time 3344041048 ps
CPU time 37.64 seconds
Started Jul 24 07:03:58 PM PDT 24
Finished Jul 24 07:04:35 PM PDT 24
Peak memory 208432 kb
Host smart-5bbd3c68-49a5-4bd5-ad47-feb4120c41bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225130340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3225130340
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1697665732
Short name T469
Test name
Test status
Simulation time 134937834 ps
CPU time 2.38 seconds
Started Jul 24 07:03:56 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 208432 kb
Host smart-ef096966-c307-4da6-ba83-f387d7c0a987
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697665732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1697665732
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1206859703
Short name T265
Test name
Test status
Simulation time 387384420 ps
CPU time 3.4 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:07 PM PDT 24
Peak memory 208500 kb
Host smart-8c5136a5-a2b0-4ed8-a048-871f8d03f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206859703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1206859703
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2432699378
Short name T558
Test name
Test status
Simulation time 191123032 ps
CPU time 3.88 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 208440 kb
Host smart-42f3f89d-bce6-46a6-abdf-4d04a16c1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432699378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2432699378
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.258747731
Short name T890
Test name
Test status
Simulation time 7635479115 ps
CPU time 182.65 seconds
Started Jul 24 07:04:12 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 222396 kb
Host smart-cc886b2c-3231-4623-aadc-04c82afcea71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258747731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.258747731
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3715253754
Short name T304
Test name
Test status
Simulation time 1123192783 ps
CPU time 33.53 seconds
Started Jul 24 07:03:57 PM PDT 24
Finished Jul 24 07:04:31 PM PDT 24
Peak memory 210368 kb
Host smart-38cc8a92-3cf9-4ac1-9efe-9a1bfbf84a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715253754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3715253754
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1864752685
Short name T806
Test name
Test status
Simulation time 75990697 ps
CPU time 2.96 seconds
Started Jul 24 07:04:02 PM PDT 24
Finished Jul 24 07:04:05 PM PDT 24
Peak memory 210008 kb
Host smart-692b60e1-fb2d-4b9e-ae20-217d9102fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864752685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1864752685
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2219199493
Short name T897
Test name
Test status
Simulation time 42426661 ps
CPU time 0.82 seconds
Started Jul 24 07:04:15 PM PDT 24
Finished Jul 24 07:04:16 PM PDT 24
Peak memory 205848 kb
Host smart-0bbc8273-0145-4ae8-8a83-09d89c7d19cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219199493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2219199493
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1863124880
Short name T838
Test name
Test status
Simulation time 49494979 ps
CPU time 3.71 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:07 PM PDT 24
Peak memory 214036 kb
Host smart-3427c1e9-ae89-4856-9d29-eb861fc9d6a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863124880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1863124880
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.894099075
Short name T29
Test name
Test status
Simulation time 156447850 ps
CPU time 3.42 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:07 PM PDT 24
Peak memory 222404 kb
Host smart-87e17378-59aa-4039-a9a7-6e3ace1286b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894099075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.894099075
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3334022404
Short name T74
Test name
Test status
Simulation time 73494946 ps
CPU time 2.05 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:12 PM PDT 24
Peak memory 208476 kb
Host smart-d47d685e-a51b-4248-b5a1-dbbef6dcf323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334022404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3334022404
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.843385831
Short name T288
Test name
Test status
Simulation time 900938158 ps
CPU time 5.09 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:09 PM PDT 24
Peak memory 214536 kb
Host smart-f0264762-c995-4e01-b207-632387816462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843385831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.843385831
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.949135529
Short name T332
Test name
Test status
Simulation time 65658981 ps
CPU time 3.89 seconds
Started Jul 24 07:04:02 PM PDT 24
Finished Jul 24 07:04:06 PM PDT 24
Peak memory 217968 kb
Host smart-de01d84c-b920-4ab3-8337-29fa4085e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949135529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.949135529
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4206154820
Short name T263
Test name
Test status
Simulation time 102150929 ps
CPU time 4.14 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:14 PM PDT 24
Peak memory 207172 kb
Host smart-d1ece8db-0996-49dd-8a5e-4733df41ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206154820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4206154820
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1227678047
Short name T765
Test name
Test status
Simulation time 145832239 ps
CPU time 4.85 seconds
Started Jul 24 07:04:06 PM PDT 24
Finished Jul 24 07:04:11 PM PDT 24
Peak memory 208060 kb
Host smart-bfaa76ef-496c-4c0d-8231-f025821151bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227678047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1227678047
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2043633182
Short name T300
Test name
Test status
Simulation time 204418994 ps
CPU time 4.46 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:15 PM PDT 24
Peak memory 206732 kb
Host smart-b96e853d-4375-4f55-8eb3-c4279ec5dfe9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043633182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2043633182
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.457225612
Short name T1
Test name
Test status
Simulation time 155678899 ps
CPU time 3.17 seconds
Started Jul 24 07:04:04 PM PDT 24
Finished Jul 24 07:04:07 PM PDT 24
Peak memory 206544 kb
Host smart-bdcf10b0-87e5-4c32-96a8-bd23bba50d7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457225612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.457225612
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.602214603
Short name T531
Test name
Test status
Simulation time 97076791 ps
CPU time 2.19 seconds
Started Jul 24 07:04:04 PM PDT 24
Finished Jul 24 07:04:06 PM PDT 24
Peak memory 208616 kb
Host smart-2f60124d-aa01-4515-a3b7-3e88fa1b0fb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602214603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.602214603
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2872082338
Short name T884
Test name
Test status
Simulation time 221679093 ps
CPU time 2.71 seconds
Started Jul 24 07:04:13 PM PDT 24
Finished Jul 24 07:04:16 PM PDT 24
Peak memory 208512 kb
Host smart-823058f7-af12-42a8-ac06-63887f106bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872082338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2872082338
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3967524518
Short name T569
Test name
Test status
Simulation time 3528460452 ps
CPU time 4.96 seconds
Started Jul 24 07:04:03 PM PDT 24
Finished Jul 24 07:04:08 PM PDT 24
Peak memory 206848 kb
Host smart-b834c58b-450c-49d8-b776-782e007f78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967524518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3967524518
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4292836780
Short name T209
Test name
Test status
Simulation time 2251686434 ps
CPU time 46.55 seconds
Started Jul 24 07:04:11 PM PDT 24
Finished Jul 24 07:04:57 PM PDT 24
Peak memory 215368 kb
Host smart-364de0ec-498e-4ddf-b469-c8026589461e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292836780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4292836780
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3620672630
Short name T916
Test name
Test status
Simulation time 1412979665 ps
CPU time 16.61 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 220240 kb
Host smart-62eae2de-2e23-4b89-b003-16162c251f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620672630 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3620672630
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1520382192
Short name T859
Test name
Test status
Simulation time 195355302 ps
CPU time 5.09 seconds
Started Jul 24 07:04:05 PM PDT 24
Finished Jul 24 07:04:10 PM PDT 24
Peak memory 207092 kb
Host smart-f7ae04d0-17ec-4891-8020-a75c98632029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520382192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1520382192
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2332116079
Short name T902
Test name
Test status
Simulation time 29805647 ps
CPU time 1.5 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:11 PM PDT 24
Peak memory 208388 kb
Host smart-9a4a16d3-6729-4e14-ae1a-84e591d93055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332116079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2332116079
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.499766782
Short name T529
Test name
Test status
Simulation time 35416494 ps
CPU time 0.75 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:18 PM PDT 24
Peak memory 205864 kb
Host smart-d6158570-e77d-44d6-89bf-c99af6706471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499766782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.499766782
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2897983946
Short name T295
Test name
Test status
Simulation time 1168932922 ps
CPU time 62.11 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:05:19 PM PDT 24
Peak memory 214856 kb
Host smart-0f0b0164-1cbb-4414-9a52-ca5f71a28217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897983946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2897983946
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.856603456
Short name T324
Test name
Test status
Simulation time 52754607 ps
CPU time 2.18 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 218308 kb
Host smart-b0857ad3-58e6-414c-b900-640ff000c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856603456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.856603456
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1736305923
Short name T809
Test name
Test status
Simulation time 198605990 ps
CPU time 3.53 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 214124 kb
Host smart-43f1d8dd-dfce-43f0-be66-1a81a610b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736305923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1736305923
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1950718957
Short name T305
Test name
Test status
Simulation time 80316274 ps
CPU time 1.82 seconds
Started Jul 24 07:04:15 PM PDT 24
Finished Jul 24 07:04:17 PM PDT 24
Peak memory 214004 kb
Host smart-141c2824-f70e-4c5f-8da2-5dea36f3fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950718957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1950718957
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3696878192
Short name T230
Test name
Test status
Simulation time 337689971 ps
CPU time 6.72 seconds
Started Jul 24 07:04:18 PM PDT 24
Finished Jul 24 07:04:25 PM PDT 24
Peak memory 209620 kb
Host smart-b8d522aa-11bf-468a-bf28-693f58d77b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696878192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3696878192
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1537563015
Short name T691
Test name
Test status
Simulation time 1451831181 ps
CPU time 7.69 seconds
Started Jul 24 07:04:15 PM PDT 24
Finished Jul 24 07:04:23 PM PDT 24
Peak memory 218072 kb
Host smart-244f920c-8ff8-4eb6-a819-3e25984a2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537563015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1537563015
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1167496033
Short name T639
Test name
Test status
Simulation time 369838804 ps
CPU time 1.98 seconds
Started Jul 24 07:04:10 PM PDT 24
Finished Jul 24 07:04:13 PM PDT 24
Peak memory 205876 kb
Host smart-efae6b6a-06b9-4fb4-89e6-101188999f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167496033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1167496033
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4197972687
Short name T778
Test name
Test status
Simulation time 89358384 ps
CPU time 2.45 seconds
Started Jul 24 07:04:12 PM PDT 24
Finished Jul 24 07:04:15 PM PDT 24
Peak memory 206732 kb
Host smart-dc4f559f-9570-4da2-9498-65b29cb54c08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197972687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4197972687
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3713531059
Short name T498
Test name
Test status
Simulation time 162654699 ps
CPU time 3.08 seconds
Started Jul 24 07:04:10 PM PDT 24
Finished Jul 24 07:04:13 PM PDT 24
Peak memory 206600 kb
Host smart-11fa4c38-d127-417f-bb18-af3a356bc52d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713531059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3713531059
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2629075575
Short name T488
Test name
Test status
Simulation time 81239403 ps
CPU time 1.82 seconds
Started Jul 24 07:04:10 PM PDT 24
Finished Jul 24 07:04:13 PM PDT 24
Peak memory 206732 kb
Host smart-60ecf5b6-7bf5-459c-be16-7654bdd55b47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629075575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2629075575
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.167210832
Short name T707
Test name
Test status
Simulation time 2252037837 ps
CPU time 12.4 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:29 PM PDT 24
Peak memory 209856 kb
Host smart-9c15f2fd-b576-4772-8912-ae95d860e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167210832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.167210832
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1353502279
Short name T459
Test name
Test status
Simulation time 197375875 ps
CPU time 2.03 seconds
Started Jul 24 07:04:09 PM PDT 24
Finished Jul 24 07:04:11 PM PDT 24
Peak memory 206876 kb
Host smart-0c4d71ba-d4d9-4b10-b83c-2e2f4e20d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353502279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1353502279
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.749696099
Short name T539
Test name
Test status
Simulation time 226982919 ps
CPU time 7.89 seconds
Started Jul 24 07:04:24 PM PDT 24
Finished Jul 24 07:04:32 PM PDT 24
Peak memory 222404 kb
Host smart-3d2f9a89-8a26-4d04-939a-e0673bdd5e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749696099 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.749696099
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.803214989
Short name T550
Test name
Test status
Simulation time 152861830 ps
CPU time 3.04 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:21 PM PDT 24
Peak memory 214040 kb
Host smart-1be1859e-043c-462a-b2c4-62ce978f8ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803214989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.803214989
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2490186880
Short name T377
Test name
Test status
Simulation time 832221152 ps
CPU time 5.01 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:21 PM PDT 24
Peak memory 210320 kb
Host smart-ecf8a6ba-a0e1-4a67-b378-39936da9e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490186880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2490186880
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3257063153
Short name T140
Test name
Test status
Simulation time 48186454 ps
CPU time 0.76 seconds
Started Jul 24 07:04:22 PM PDT 24
Finished Jul 24 07:04:23 PM PDT 24
Peak memory 205848 kb
Host smart-9181091f-dccd-4101-81e4-698781c81cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257063153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3257063153
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4012017554
Short name T113
Test name
Test status
Simulation time 318006671 ps
CPU time 9.1 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 213980 kb
Host smart-58256f93-e9f6-4ef1-b9d3-103f7664b306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012017554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4012017554
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.170413259
Short name T27
Test name
Test status
Simulation time 33087150 ps
CPU time 1.45 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 208500 kb
Host smart-3bcf782b-f318-40aa-ada3-04b6f40dd79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170413259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.170413259
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4065508089
Short name T323
Test name
Test status
Simulation time 158386651 ps
CPU time 1.95 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 208528 kb
Host smart-59a23404-33bc-430b-be57-4b42a55fd4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065508089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4065508089
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2912173261
Short name T92
Test name
Test status
Simulation time 415753384 ps
CPU time 5 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:22 PM PDT 24
Peak memory 214036 kb
Host smart-209c4123-ca01-4ff7-8778-b18597f8dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912173261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2912173261
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.615654826
Short name T34
Test name
Test status
Simulation time 112658389 ps
CPU time 3.16 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:20 PM PDT 24
Peak memory 220860 kb
Host smart-36472dd0-e5d1-4451-af3f-8e8f262aa948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615654826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.615654826
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.212923033
Short name T41
Test name
Test status
Simulation time 110430314 ps
CPU time 2.7 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 208492 kb
Host smart-f2836918-2a87-4a1d-a32e-643acb1d04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212923033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.212923033
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.120883288
Short name T655
Test name
Test status
Simulation time 107537544 ps
CPU time 2.4 seconds
Started Jul 24 07:04:18 PM PDT 24
Finished Jul 24 07:04:20 PM PDT 24
Peak memory 207252 kb
Host smart-e8a6b5fb-3610-4471-8e26-3d92ffbb4aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120883288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.120883288
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1776350640
Short name T483
Test name
Test status
Simulation time 59639881 ps
CPU time 2.72 seconds
Started Jul 24 07:04:18 PM PDT 24
Finished Jul 24 07:04:21 PM PDT 24
Peak memory 208032 kb
Host smart-12142c09-11b3-44f0-bec6-ed1d199497ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776350640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1776350640
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4049919267
Short name T262
Test name
Test status
Simulation time 201076942 ps
CPU time 3.37 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 208480 kb
Host smart-7980e8b0-bacd-443f-8d62-492351b35bd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049919267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4049919267
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2941067220
Short name T486
Test name
Test status
Simulation time 4370636424 ps
CPU time 7.55 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:24 PM PDT 24
Peak memory 206904 kb
Host smart-8389da00-ead7-435d-adf0-e34cca352846
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941067220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2941067220
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.407687534
Short name T285
Test name
Test status
Simulation time 226350013 ps
CPU time 2.95 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 208452 kb
Host smart-0b8755f6-ae6a-47d6-9080-2319f1abe9a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407687534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.407687534
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1956034656
Short name T261
Test name
Test status
Simulation time 677237266 ps
CPU time 2.7 seconds
Started Jul 24 07:04:16 PM PDT 24
Finished Jul 24 07:04:19 PM PDT 24
Peak memory 210028 kb
Host smart-deb3060a-b0a4-4331-92aa-4a0d2b0ac61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956034656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1956034656
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3792970396
Short name T491
Test name
Test status
Simulation time 1208504513 ps
CPU time 4.66 seconds
Started Jul 24 07:04:17 PM PDT 24
Finished Jul 24 07:04:22 PM PDT 24
Peak memory 206464 kb
Host smart-e51c53a0-3519-4cf7-9e76-fcdf05cc9e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792970396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3792970396
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2996504686
Short name T338
Test name
Test status
Simulation time 224528890 ps
CPU time 14.15 seconds
Started Jul 24 07:04:28 PM PDT 24
Finished Jul 24 07:04:42 PM PDT 24
Peak memory 222248 kb
Host smart-b00a2fdc-8219-40e7-9026-4f126469a701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996504686 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2996504686
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.153452409
Short name T316
Test name
Test status
Simulation time 271539617 ps
CPU time 7.26 seconds
Started Jul 24 07:04:19 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 207484 kb
Host smart-0ce91b23-8b2a-4da7-9a13-b68bc3543451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153452409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.153452409
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1127904510
Short name T906
Test name
Test status
Simulation time 171368380 ps
CPU time 2.28 seconds
Started Jul 24 07:04:23 PM PDT 24
Finished Jul 24 07:04:26 PM PDT 24
Peak memory 209496 kb
Host smart-3d66f11a-6071-4e49-8445-186807ac4d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127904510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1127904510
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%