Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	57	1			T3	1		T36	1		T47	1
auto[OpGenId]	9	1			T1	1		T205	1		T206	1
auto[OpGenSwOut]	24	1			T60	1		T27	1		T207	1
auto[OpGenHwOut]	15	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1639	1			T1	1		T47	3		T54	1
auto[StInit]	80	1			T1	1		T34	1		T47	1
auto[StCreatorRootKey]	53	1			T95	1		T57	1		T60	1
auto[StOwnerIntKey]	61	1			T1	1		T35	1		T39	1
auto[StOwnerKey]	39	1			T3	1		T36	1		T47	1
auto[StDisabled]	520	1			T1	8		T47	12		T95	4
auto[StInvalid]	49	1			T37	1		T43	1		T96	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3417

1

T1

11

T2

1

T3

1

auto[1]

105

1

T1

1

T3

1

T36

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1632	1			T1	1		T47	3		T60	1
auto[StReset]	auto[1]	7	1			T54	1		T51	1		T52	1
auto[StInit]	auto[0]	33	1			T34	1		T47	1		T55	1
auto[StInit]	auto[1]	47	1			T1	1		T5	1		T26	1
auto[StCreatorRootKey]	auto[0]	35	1			T95	1		T57	1		T58	1
auto[StCreatorRootKey]	auto[1]	18	1			T60	1		T7	1		T208	1
auto[StOwnerIntKey]	auto[0]	45	1			T1	1		T35	1		T39	1
auto[StOwnerIntKey]	auto[1]	16	1			T48	1		T40	1		T18	1
auto[StOwnerKey]	auto[0]	30	1			T64	1		T51	1		T52	1
auto[StOwnerKey]	auto[1]	9	1			T3	1		T36	1		T47	1
auto[StDisabled]	auto[0]	512	1			T1	8		T47	12		T95	4
auto[StDisabled]	auto[1]	8	1			T146	1		T67	1		T74	2
auto[StInvalid]	auto[0]	49	1			T37	1		T43	1		T96	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenId]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T54	1		T51	1		T52	1
auto[StReset]	auto[OpGenId]	1	1			T149	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	22	1			T26	1		T209	1		T32	1
auto[StInit]	auto[OpGenId]	6	1			T1	1		T205	1		T210	1
auto[StInit]	auto[OpGenSwOut]	12	1			T27	1		T207	1		T148	1
auto[StInit]	auto[OpGenHwOut]	7	1			T5	1		T211	1		T73	1
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T208	1		T212	1		T213	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T60	1		T214	1		T8	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T7	1		T215	1		T216	1
auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T48	1		T40	1		T18	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T206	1		T214	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T103	1		T217	1		T218	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T211	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T3	1		T36	1		T47	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T118	1		T219	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T6	1		T220	1		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T146	1		T67	1		T74	2
auto[StDisabled]	auto[OpGenHwOut]	1	1			T221	1		-	-		-	-