Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4945

1

T1

36

T2

13

T3

2

auto[1]

562

1

T1

6

T4

1

T13

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4945

1

T1

36

T2

13

T3

2

auto[1]

562

1

T1

6

T4

1

T13

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4964

1

T1

39

T2

13

T3

2

auto[1]

543

1

T1

3

T12

4

T13

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4964

1

T1

39

T2

13

T3

2

auto[1]

543

1

T1

3

T12

4

T13

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T1	3		T3	1		T14	3
auto[OpGenId]	1182	1			T1	13		T3	1		T4	5
auto[OpGenSwOut]	1177	1			T1	12		T4	4		T13	1
auto[OpGenHwOut]	2638	1			T1	14		T2	13		T12	8
auto[OpDisable]	94	1			T47	1		T65	1		T125	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T1	3		T3	1		T14	3
auto[OpGenId]	1182	1			T1	13		T3	1		T4	5
auto[OpGenSwOut]	1177	1			T1	12		T4	4		T13	1
auto[OpGenHwOut]	2638	1			T1	14		T2	13		T12	8
auto[OpDisable]	94	1			T47	1		T65	1		T125	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4933

1

T1

40

T2

9

T3

1

auto[1]

574

1

T1

2

T2

4

T3

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4933

1

T1

40

T2

9

T3

1

auto[1]

574

1

T1

2

T2

4

T3

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5184

1

T1

42

T2

13

T3

2

auto[1]

323

1

T4

3

T14

4

T16

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1926	1			T1	13		T2	3		T3	1
auto[1]	732	1			T1	4		T2	1		T3	1
auto[2]	699	1			T1	7		T2	1		T12	1
auto[3]	727	1			T1	3		T2	2		T12	1
auto[4]	371	1			T1	5		T12	1		T4	1
auto[5]	360	1			T1	3		T2	3		T12	1
auto[6]	345	1			T1	4		T2	2		T4	2
auto[7]	347	1			T1	3		T2	1		T14	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1423	1			T1	15		T2	6		T12	2
clear_one[1]	732	1			T1	4		T2	1		T3	1
clear_one[2]	699	1			T1	7		T2	1		T12	1
clear_one[3]	727	1			T1	3		T2	2		T12	1
clear_none	1926	1			T1	13		T2	3		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1040	1			T1	8		T2	5		T4	2
auto[StInit]	675	1			T1	5		T2	1		T3	1
auto[StCreatorRootKey]	594	1			T1	4		T2	1		T12	1
auto[StOwnerIntKey]	533	1			T1	5		T2	1		T12	1
auto[StOwnerKey]	456	1			T1	4		T2	1		T3	1
auto[StDisabled]	1939	1			T1	16		T2	4		T12	4
auto[StInvalid]	270	1			T37	4		T38	5		T43	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1040	1			T1	8		T2	5		T4	2
auto[StInit]	675	1			T1	5		T2	1		T3	1
auto[StCreatorRootKey]	594	1			T1	4		T2	1		T12	1
auto[StOwnerIntKey]	533	1			T1	5		T2	1		T12	1
auto[StOwnerKey]	456	1			T1	4		T2	1		T3	1
auto[StDisabled]	1939	1			T1	16		T2	4		T12	4
auto[StInvalid]	270	1			T37	4		T38	5		T43	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T228	1		T229	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	185	1			T1	3		T4	1		T37	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	147	1			T1	2		T77	1		T187	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	264	1			T1	1		T2	1		T106	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T1	1		T3	1		T14	1
auto[0]	auto[StInit]	auto[OpGenId]	100	1			T23	1		T196	1		T144	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	92	1			T1	2		T230	1		T231	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	179	1			T12	1		T15	1		T106	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T144	1		T232	1		T136	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T1	1		T188	1		T195	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T23	1		T47	2		T65	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	84	1			T1	1		T2	1		T16	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T47	1		T194	1		T233	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	30	1			T13	1		T16	1		T144	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	40	1			T1	1		T47	1		T60	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T1	1		T12	1		T202	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	18	1			T144	1		T52	1		T86	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T234	1		T123	1		T103	2
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T4	1		T194	1		T65	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	54	1			T15	1		T203	1		T132	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	22	1			T47	1		T130	1		T145	1
auto[0]	auto[StDisabled]	auto[OpGenId]	71	1			T4	1		T94	1		T191	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T4	1		T14	1		T188	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	179	1			T2	1		T12	1		T13	1
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T235	1		T62	1		T52	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T97	1		T81	1		T236	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T38	1		T50	1		T96	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	21	1			T37	1		T38	1		T97	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T50	1		T97	1		T237	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T1	1		T97	1		T60	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T38	1		T47	1		T185	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	61	1			T107	2		T200	1		T145	1
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T238	1		T226	1		T239	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T60	1		T240	1		T80	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T222	3		T241	1		T242	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	24	1			T197	1		T138	1		T243	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T217	1		T244	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T95	1		T18	1		T52	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T4	2		T47	1		T122	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T106	1		T47	1		T131	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T128	3		T136	1		T246	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T95	1		T247	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T47	1		T197	1		T52	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T132	1		T48	1		T249	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T128	1		T136	1		T250	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	7	1			T3	1		T47	1		T207	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T1	1		T77	1		T125	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T251	1		T252	1		T253	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T1	1		T134	1		T254	1
auto[1]	auto[StDisabled]	auto[OpGenId]	62	1			T94	1		T77	1		T128	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T1	1		T13	1		T189	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T2	1		T12	1		T16	2
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T65	1		T255	1		T256	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T96	1		T257	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T259	1		T260	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T82	1		T262	1		T83	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T37	1		T96	1		T263	1
auto[2]	auto[StReset]	auto[OpGenId]	10	1			T38	1		T47	1		T264	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T47	1		T265	1		T244	2
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T203	1		T200	1		T121	2
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T14	1		T103	1		T266	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T267	1		T268	1		T213	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T23	1		T131	1		T269	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T1	1		T200	1		T48	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T52	1		T270	1		T271	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T1	1		T14	1		T47	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T125	1		T211	1		T217	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T204	1		T134	1		T272	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T265	1		T211	2		T227	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T60	1		T51	1		T52	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T64	1		T273	1		T207	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T203	1		T274	1		T275	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T89	1		T276	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T47	2		T134	1		T197	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T122	1		T60	1		T207	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T2	1		T106	1		T107	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	28	1			T145	1		T277	2		T185	1
auto[2]	auto[StDisabled]	auto[OpGenId]	66	1			T1	3		T4	1		T16	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T196	1		T189	1		T128	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T1	2		T12	1		T4	1
auto[2]	auto[StDisabled]	auto[OpDisable]	15	1			T68	1		T52	1		T207	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T278	1		T263	1		T261	2
auto[2]	auto[StInvalid]	auto[OpGenId]	13	1			T43	1		T56	1		T63	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T78	1		T279	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T50	1		T237	1		T281	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T97	1		T48	1		T78	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T201	1		T130	1		T54	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T2	1		T200	1		T282	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T250	1		T283	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T201	1		T284	1		T52	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	17	1			T24	1		T43	1		T217	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T203	1		T187	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T128	2		T240	1		T19	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T276	1		T286	1		T74	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T47	1		T52	1		T276	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T43	1		T132	1		T287	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T144	1		T128	1		T135	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T47	1		T197	1		T179	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T47	1		T179	1		T288	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T15	1		T47	1		T18	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T289	2		T290	1		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T135	1		T52	1		T277	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T198	1		T60	1		T197	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T1	1		T144	1		T272	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	14	1			T144	1		T47	2		T136	1
auto[3]	auto[StDisabled]	auto[OpGenId]	65	1			T94	1		T144	1		T47	4
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T191	1		T144	1		T122	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T1	2		T2	1		T12	1
auto[3]	auto[StDisabled]	auto[OpDisable]	19	1			T47	1		T71	1		T72	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T96	1		T291	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T43	1		T81	1		T56	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T262	1		T293	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T97	1		T56	1		T63	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T295	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T138	1		T259	1		T98	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T1	1		T179	1		T100	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T296	1		T297	1		T298	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T299	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T23	1		T48	1		T300	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	2	1			T76	1		T301	1		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	16	1			T121	1		T302	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T304	1		T146	1		T305	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T207	1		T306	1		T307	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T308	1		T309	1		T310	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T12	1		T107	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T73	1		T312	1		T241	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T228	1		T67	1		T87	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T130	1		T313	1		T185	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T1	1		T107	1		T131	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T52	1		T305	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T95	1		T60	1		T228	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T202	1		T228	3		T179	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T311	1		T314	1		T315	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T14	1		T316	1		T317	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T4	1		T130	1		T197	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T1	2		T14	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T1	1		T14	1		T203	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T179	1		T214	1		T318	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T319	1		T320	1		T321	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T38	1		T43	1		T50	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T97	1		T260	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T43	1		T95	1		T211	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T60	1		T100	1		T322	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T2	1		T282	1		T323	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T254	1		T70	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T1	1		T63	1		T324	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T137	2		T325	1		T326	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T2	1		T47	1		T25	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T197	1		T228	1		T53	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T196	1		T327	1		T328	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T179	1		T105	1		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T15	1		T203	1		T251	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T316	2		T330	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T47	1		T19	1		T331	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T65	1		T332	1		T333	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T1	2		T2	1		T95	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T301	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T316	2		T105	1		T334	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T207	1		T270	1		T335	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T12	1		T200	1		T204	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T191	1		T47	1		T70	1
auto[5]	auto[StDisabled]	auto[OpGenId]	24	1			T47	2		T313	1		T254	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T94	1		T60	1		T197	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T106	1		T203	1		T204	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T125	1		T241	1		T182	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T37	1		T78	2		T336	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T237	1		T337	1		T338	2
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T82	1		T339	1		T340	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T96	1		T278	1		T262	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T136	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T4	1		T281	1		T341	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T145	1		T52	1		T185	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T2	1		T125	1		T303	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T24	1		T270	1		T289	2
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T197	1		T297	1		T342	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	10	1			T24	1		T25	1		T136	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T4	1		T314	1		T343	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T136	1		T316	2		T227	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T47	1		T231	1		T100	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T190	1		T74	1		T271	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T60	1		T253	1		T288	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T52	1		T316	1		T103	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T47	1		T344	1		T73	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T47	2		T232	1		T179	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	9	1			T106	1		T200	1		T121	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T47	1		T309	1		T345	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T1	1		T131	1		T178	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T273	1		T346	1		T307	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T1	1		T70	1		T347	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T1	1		T128	2		T135	1
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T123	1		T348	1		T349	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T1	1		T187	1		T128	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T2	1		T106	2		T200	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T322	1		T218	1		T271	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T84	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T293	1		T350	1		T351	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T83	1		T281	1		T352	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T37	1		T353	1		T354	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T48	1		T125	1		T60	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T144	1		T222	1		T147	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	31	1			T2	1		T287	1		T273	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T355	1		T356	1		T357	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T52	1		T225	1		T358	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T130	1		T359	1		T332	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T47	1		T80	1		T179	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T297	1		T360	1		T361	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T1	1		T74	1		T213	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T49	1		T207	1		T70	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T47	1		T60	1		T362	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T180	1		T363	2		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T277	1		T268	1		T360	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T69	1		T73	1		T364	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T14	1		T204	1		T52	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T325	1		T365	1		T363	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T360	1		T210	1		T366	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T16	1		T48	1		T214	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T130	1		T121	1		T60	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T47	1		T231	1		T228	1
auto[7]	auto[StDisabled]	auto[OpGenId]	27	1			T1	1		T69	1		T136	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T1	1		T202	1		T131	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T196	1		T251	1		T47	1
auto[7]	auto[StDisabled]	auto[OpDisable]	8	1			T207	1		T100	1		T217	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T338	1		T367	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T82	1		T368	1		T369	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T38	2		T78	1		T236	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T43	1		T81	1		T353	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1423

1

T1

15

T2

6

T12

2

clear_one[1]

auto[0]

auto[0]

auto[0]

433

1

T1

4

T4

2

T94

1

clear_one[1]

auto[0]

auto[0]

auto[1]

138

1

T2

1

T3

1

T107

1

clear_one[1]

auto[0]

auto[1]

auto[0]

126

1

T12

1

T13

1

T16

1

clear_one[1]

auto[0]

auto[1]

auto[1]

35

1

T16

1

T249

1

T370

1

clear_one[2]

auto[0]

auto[0]

auto[0]

416

1

T1

3

T12

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

120

1

T2

1

T16

1

T107

4

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T1

2

T4

1

T106

1

clear_one[2]

auto[1]

auto[0]

auto[1]

34

1

T1

2

T16

1

T134

1

clear_one[3]

auto[0]

auto[0]

auto[0]

442

1

T2

2

T203

1

T24

1

clear_one[3]

auto[0]

auto[1]

auto[0]

116

1

T1

1

T12

1

T15

3

clear_one[3]

auto[1]

auto[0]

auto[0]

129

1

T1

1

T94

1

T47

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T1

1

T144

6

T233

1

clear_none

auto[0]

auto[0]

auto[0]

1373

1

T1

12

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

162

1

T2

2

T4

1

T202

1

clear_none

auto[0]

auto[1]

auto[0]

132

1

T1

1

T12

2

T13

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T188

1

T123

1

T60

1

clear_none

auto[1]

auto[0]

auto[0]

130

1

T16

1

T203

1

T200

1

clear_none

auto[1]

auto[0]

auto[1]

35

1

T47

1

T138

1

T86

2

clear_none

auto[1]

auto[1]

auto[0]

44

1

T13

1

T94

1

T144

4

clear_none

auto[1]

auto[1]

auto[1]

21

1

T349

1

T99

1

T214

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1326	1			T1	15		T2	6		T12	2
clear_all	auto[1]	97	1			T14	2		T128	2		T135	1
clear_one[1]	auto[0]	690	1			T1	4		T2	1		T3	1
clear_one[1]	auto[1]	42	1			T4	1		T16	1		T128	7
clear_one[2]	auto[0]	669	1			T1	7		T2	1		T12	1
clear_one[2]	auto[1]	30	1			T4	1		T14	1		T16	1
clear_one[3]	auto[0]	673	1			T1	3		T2	2		T12	1
clear_one[3]	auto[1]	54	1			T144	3		T128	2		T135	2
clear_none	auto[0]	1826	1			T1	13		T2	3		T3	1
clear_none	auto[1]	100	1			T4	1		T14	1		T16	2