Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34546

1

T1

299

T2

29

T3

10

auto[1]

290

1

T4

3

T14

4

T16

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34549	1			T1	299		T2	29		T3	10
auto[134217728:268435455]	11	1			T136	1		T138	1		T295	1
auto[268435456:402653183]	12	1			T128	1		T134	1		T138	1
auto[402653184:536870911]	6	1			T317	1		T270	1		T395	1
auto[536870912:671088639]	8	1			T135	3		T295	1		T379	1
auto[671088640:805306367]	11	1			T4	1		T144	2		T145	1
auto[805306368:939524095]	8	1			T136	1		T316	1		T138	2
auto[939524096:1073741823]	7	1			T136	1		T138	1		T254	1
auto[1073741824:1207959551]	11	1			T128	1		T145	1		T137	1
auto[1207959552:1342177279]	11	1			T14	1		T144	1		T128	2
auto[1342177280:1476395007]	3	1			T16	1		T134	1		T290	1
auto[1476395008:1610612735]	13	1			T128	1		T136	2		T316	1
auto[1610612736:1744830463]	7	1			T246	1		T396	1		T397	1
auto[1744830464:1879048191]	4	1			T128	1		T295	1		T335	1
auto[1879048192:2013265919]	9	1			T4	1		T145	1		T136	1
auto[2013265920:2147483647]	12	1			T16	1		T295	1		T270	1
auto[2147483648:2281701375]	3	1			T254	1		T379	1		T398	1
auto[2281701376:2415919103]	7	1			T128	1		T136	1		T137	1
auto[2415919104:2550136831]	11	1			T14	1		T228	1		T317	1
auto[2550136832:2684354559]	15	1			T228	2		T276	1		T297	2
auto[2684354560:2818572287]	5	1			T16	1		T317	1		T330	1
auto[2818572288:2952790015]	11	1			T295	1		T270	1		T335	1
auto[2952790016:3087007743]	13	1			T16	1		T135	1		T307	2
auto[3087007744:3221225471]	13	1			T134	1		T297	1		T330	1
auto[3221225472:3355443199]	9	1			T134	1		T360	2		T399	1
auto[3355443200:3489660927]	15	1			T135	1		T295	1		T246	1
auto[3489660928:3623878655]	8	1			T128	1		T134	1		T135	1
auto[3623878656:3758096383]	9	1			T134	2		T136	1		T297	1
auto[3758096384:3892314111]	8	1			T14	1		T134	1		T136	1
auto[3892314112:4026531839]	9	1			T134	1		T135	1		T228	1
auto[4026531840:4160749567]	11	1			T4	1		T14	1		T16	1
auto[4160749568:4294967295]	7	1			T317	1		T398	1		T395	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34546	1			T1	299		T2	29		T3	10
auto[0:134217727]	auto[1]	3	1			T400	1		T289	1		T290	1
auto[134217728:268435455]	auto[1]	11	1			T136	1		T138	1		T295	1
auto[268435456:402653183]	auto[1]	12	1			T128	1		T134	1		T138	1
auto[402653184:536870911]	auto[1]	6	1			T317	1		T270	1		T395	1
auto[536870912:671088639]	auto[1]	8	1			T135	3		T295	1		T379	1
auto[671088640:805306367]	auto[1]	11	1			T4	1		T144	2		T145	1
auto[805306368:939524095]	auto[1]	8	1			T136	1		T316	1		T138	2
auto[939524096:1073741823]	auto[1]	7	1			T136	1		T138	1		T254	1
auto[1073741824:1207959551]	auto[1]	11	1			T128	1		T145	1		T137	1
auto[1207959552:1342177279]	auto[1]	11	1			T14	1		T144	1		T128	2
auto[1342177280:1476395007]	auto[1]	3	1			T16	1		T134	1		T290	1
auto[1476395008:1610612735]	auto[1]	13	1			T128	1		T136	2		T316	1
auto[1610612736:1744830463]	auto[1]	7	1			T246	1		T396	1		T397	1
auto[1744830464:1879048191]	auto[1]	4	1			T128	1		T295	1		T335	1
auto[1879048192:2013265919]	auto[1]	9	1			T4	1		T145	1		T136	1
auto[2013265920:2147483647]	auto[1]	12	1			T16	1		T295	1		T270	1
auto[2147483648:2281701375]	auto[1]	3	1			T254	1		T379	1		T398	1
auto[2281701376:2415919103]	auto[1]	7	1			T128	1		T136	1		T137	1
auto[2415919104:2550136831]	auto[1]	11	1			T14	1		T228	1		T317	1
auto[2550136832:2684354559]	auto[1]	15	1			T228	2		T276	1		T297	2
auto[2684354560:2818572287]	auto[1]	5	1			T16	1		T317	1		T330	1
auto[2818572288:2952790015]	auto[1]	11	1			T295	1		T270	1		T335	1
auto[2952790016:3087007743]	auto[1]	13	1			T16	1		T135	1		T307	2
auto[3087007744:3221225471]	auto[1]	13	1			T134	1		T297	1		T330	1
auto[3221225472:3355443199]	auto[1]	9	1			T134	1		T360	2		T399	1
auto[3355443200:3489660927]	auto[1]	15	1			T135	1		T295	1		T246	1
auto[3489660928:3623878655]	auto[1]	8	1			T128	1		T134	1		T135	1
auto[3623878656:3758096383]	auto[1]	9	1			T134	2		T136	1		T297	1
auto[3758096384:3892314111]	auto[1]	8	1			T14	1		T134	1		T136	1
auto[3892314112:4026531839]	auto[1]	9	1			T134	1		T135	1		T228	1
auto[4026531840:4160749567]	auto[1]	11	1			T4	1		T14	1		T16	1
auto[4160749568:4294967295]	auto[1]	7	1			T317	1		T398	1		T395	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T1

21

T3

2

T4

1

auto[1]

1913

1

T1

23

T3

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T16	1		T94	1		T37	2
auto[134217728:268435455]	126	1			T1	1		T13	1		T14	1
auto[268435456:402653183]	85	1			T1	1		T23	1		T47	2
auto[402653184:536870911]	109	1			T1	2		T14	1		T36	1
auto[536870912:671088639]	113	1			T1	1		T14	1		T23	1
auto[671088640:805306367]	103	1			T1	5		T4	1		T50	1
auto[805306368:939524095]	111	1			T1	3		T14	1		T23	1
auto[939524096:1073741823]	109	1			T1	1		T191	1		T43	1
auto[1073741824:1207959551]	120	1			T3	1		T23	1		T37	1
auto[1207959552:1342177279]	91	1			T190	1		T134	1		T125	1
auto[1342177280:1476395007]	117	1			T1	4		T4	1		T13	1
auto[1476395008:1610612735]	125	1			T1	2		T16	1		T24	2
auto[1610612736:1744830463]	107	1			T201	1		T47	4		T145	1
auto[1744830464:1879048191]	102	1			T1	1		T37	1		T24	1
auto[1879048192:2013265919]	105	1			T1	2		T3	1		T191	1
auto[2013265920:2147483647]	93	1			T47	2		T97	1		T122	1
auto[2147483648:2281701375]	119	1			T1	1		T3	1		T94	1
auto[2281701376:2415919103]	117	1			T47	1		T232	1		T145	2
auto[2415919104:2550136831]	115	1			T1	1		T201	1		T128	2
auto[2550136832:2684354559]	110	1			T1	3		T3	1		T94	1
auto[2684354560:2818572287]	93	1			T47	3		T82	2		T60	1
auto[2818572288:2952790015]	116	1			T1	2		T38	1		T47	5
auto[2952790016:3087007743]	111	1			T1	1		T188	1		T50	1
auto[3087007744:3221225471]	121	1			T1	3		T13	1		T191	1
auto[3221225472:3355443199]	97	1			T191	1		T144	3		T50	1
auto[3355443200:3489660927]	121	1			T1	1		T4	1		T16	1
auto[3489660928:3623878655]	108	1			T1	2		T3	1		T16	1
auto[3623878656:3758096383]	122	1			T1	1		T14	1		T23	1
auto[3758096384:3892314111]	119	1			T1	1		T16	1		T37	1
auto[3892314112:4026531839]	124	1			T1	3		T144	1		T201	1
auto[4026531840:4160749567]	103	1			T1	1		T24	1		T38	1
auto[4160749568:4294967295]	87	1			T1	1		T36	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T94	1		T37	2		T43	1
auto[0:134217727]	auto[1]	62	1			T16	1		T24	1		T144	1
auto[134217728:268435455]	auto[0]	58	1			T1	1		T13	1		T37	1
auto[134217728:268435455]	auto[1]	68	1			T14	1		T16	1		T37	1
auto[268435456:402653183]	auto[0]	42	1			T47	1		T97	1		T60	1
auto[268435456:402653183]	auto[1]	43	1			T1	1		T23	1		T47	1
auto[402653184:536870911]	auto[0]	50	1			T50	1		T47	1		T29	1
auto[402653184:536870911]	auto[1]	59	1			T1	2		T14	1		T36	1
auto[536870912:671088639]	auto[0]	53	1			T1	1		T201	1		T47	1
auto[536870912:671088639]	auto[1]	60	1			T14	1		T23	1		T47	1
auto[671088640:805306367]	auto[0]	49	1			T1	2		T4	1		T50	1
auto[671088640:805306367]	auto[1]	54	1			T1	3		T145	1		T65	1
auto[805306368:939524095]	auto[0]	52	1			T1	2		T128	1		T47	1
auto[805306368:939524095]	auto[1]	59	1			T1	1		T14	1		T23	1
auto[939524096:1073741823]	auto[0]	45	1			T1	1		T43	1		T145	1
auto[939524096:1073741823]	auto[1]	64	1			T191	1		T194	1		T125	1
auto[1073741824:1207959551]	auto[0]	63	1			T23	1		T37	1		T36	1
auto[1073741824:1207959551]	auto[1]	57	1			T3	1		T191	1		T36	1
auto[1207959552:1342177279]	auto[0]	46	1			T190	1		T134	1		T125	1
auto[1207959552:1342177279]	auto[1]	45	1			T284	1		T25	1		T62	1
auto[1342177280:1476395007]	auto[0]	59	1			T1	2		T47	1		T97	1
auto[1342177280:1476395007]	auto[1]	58	1			T1	2		T4	1		T13	1
auto[1476395008:1610612735]	auto[0]	42	1			T24	2		T199	1		T135	1
auto[1476395008:1610612735]	auto[1]	83	1			T1	2		T16	1		T47	1
auto[1610612736:1744830463]	auto[0]	52	1			T47	3		T145	1		T63	1
auto[1610612736:1744830463]	auto[1]	55	1			T201	1		T47	1		T63	1
auto[1744830464:1879048191]	auto[0]	50	1			T37	1		T24	1		T47	1
auto[1744830464:1879048191]	auto[1]	52	1			T1	1		T47	2		T133	1
auto[1879048192:2013265919]	auto[0]	40	1			T1	2		T3	1		T60	1
auto[1879048192:2013265919]	auto[1]	65	1			T191	1		T49	1		T65	1
auto[2013265920:2147483647]	auto[0]	44	1			T47	2		T97	1		T25	1
auto[2013265920:2147483647]	auto[1]	49	1			T122	1		T60	1		T18	1
auto[2147483648:2281701375]	auto[0]	56	1			T1	1		T3	1		T38	1
auto[2147483648:2281701375]	auto[1]	63	1			T94	1		T51	1		T52	1
auto[2281701376:2415919103]	auto[0]	42	1			T60	1		T209	1		T85	1
auto[2281701376:2415919103]	auto[1]	75	1			T47	1		T232	1		T145	2
auto[2415919104:2550136831]	auto[0]	44	1			T1	1		T145	1		T52	2
auto[2415919104:2550136831]	auto[1]	71	1			T201	1		T128	2		T47	1
auto[2550136832:2684354559]	auto[0]	43	1			T1	1		T94	1		T54	1
auto[2550136832:2684354559]	auto[1]	67	1			T1	2		T3	1		T188	1
auto[2684354560:2818572287]	auto[0]	47	1			T47	3		T63	1		T51	1
auto[2684354560:2818572287]	auto[1]	46	1			T82	2		T60	1		T401	1
auto[2818572288:2952790015]	auto[0]	55	1			T1	2		T47	4		T60	1
auto[2818572288:2952790015]	auto[1]	61	1			T38	1		T47	1		T194	1
auto[2952790016:3087007743]	auto[0]	59	1			T1	1		T188	1		T50	1
auto[2952790016:3087007743]	auto[1]	52	1			T233	1		T209	1		T52	2
auto[3087007744:3221225471]	auto[0]	50	1			T1	1		T43	1		T47	1
auto[3087007744:3221225471]	auto[1]	71	1			T1	2		T13	1		T191	1
auto[3221225472:3355443199]	auto[0]	38	1			T191	1		T50	1		T48	1
auto[3221225472:3355443199]	auto[1]	59	1			T144	3		T47	2		T130	1
auto[3355443200:3489660927]	auto[0]	57	1			T5	1		T402	1		T138	1
auto[3355443200:3489660927]	auto[1]	64	1			T1	1		T4	1		T16	1
auto[3489660928:3623878655]	auto[0]	51	1			T38	1		T47	1		T278	1
auto[3489660928:3623878655]	auto[1]	57	1			T1	2		T3	1		T16	1
auto[3623878656:3758096383]	auto[0]	54	1			T1	1		T14	1		T47	1
auto[3623878656:3758096383]	auto[1]	68	1			T23	1		T38	1		T96	1
auto[3758096384:3892314111]	auto[0]	53	1			T1	1		T37	1		T97	1
auto[3758096384:3892314111]	auto[1]	66	1			T16	1		T190	1		T47	1
auto[3892314112:4026531839]	auto[0]	61	1			T1	1		T47	1		T96	1
auto[3892314112:4026531839]	auto[1]	63	1			T1	2		T144	1		T201	1
auto[4026531840:4160749567]	auto[0]	58	1			T24	1		T38	1		T144	1
auto[4026531840:4160749567]	auto[1]	45	1			T1	1		T201	1		T47	1
auto[4160749568:4294967295]	auto[0]	35	1			T63	1		T403	1		T240	1
auto[4160749568:4294967295]	auto[1]	52	1			T1	1		T36	1		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T1

21

T3

2

T4

1

auto[1]

1914

1

T1

23

T3

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T1	2		T13	1		T190	1
auto[134217728:268435455]	103	1			T1	2		T4	1		T23	1
auto[268435456:402653183]	115	1			T1	3		T38	1		T201	2
auto[402653184:536870911]	107	1			T190	1		T47	4		T49	1
auto[536870912:671088639]	135	1			T1	1		T43	1		T47	1
auto[671088640:805306367]	108	1			T1	1		T37	1		T144	1
auto[805306368:939524095]	87	1			T190	1		T201	1		T128	1
auto[939524096:1073741823]	109	1			T1	2		T37	2		T47	1
auto[1073741824:1207959551]	116	1			T1	2		T4	1		T13	1
auto[1207959552:1342177279]	103	1			T1	2		T47	3		T231	1
auto[1342177280:1476395007]	98	1			T23	1		T128	2		T47	2
auto[1476395008:1610612735]	108	1			T16	1		T94	1		T24	1
auto[1610612736:1744830463]	107	1			T1	2		T23	1		T50	1
auto[1744830464:1879048191]	116	1			T1	2		T128	1		T47	5
auto[1879048192:2013265919]	112	1			T1	1		T16	1		T24	1
auto[2013265920:2147483647]	110	1			T1	5		T16	1		T144	1
auto[2147483648:2281701375]	118	1			T3	1		T23	1		T24	1
auto[2281701376:2415919103]	117	1			T1	1		T43	1		T47	2
auto[2415919104:2550136831]	114	1			T3	1		T36	1		T43	1
auto[2550136832:2684354559]	109	1			T1	3		T37	1		T47	1
auto[2684354560:2818572287]	120	1			T1	1		T14	1		T94	1
auto[2818572288:2952790015]	125	1			T16	1		T130	1		T96	1
auto[2952790016:3087007743]	130	1			T1	2		T23	1		T201	1
auto[3087007744:3221225471]	95	1			T1	1		T24	1		T97	1
auto[3221225472:3355443199]	111	1			T3	1		T4	1		T16	1
auto[3355443200:3489660927]	102	1			T1	1		T3	1		T14	1
auto[3489660928:3623878655]	104	1			T1	2		T14	1		T188	1
auto[3623878656:3758096383]	124	1			T24	1		T188	1		T191	1
auto[3758096384:3892314111]	112	1			T1	3		T3	1		T14	2
auto[3892314112:4026531839]	97	1			T1	3		T38	1		T191	1
auto[4026531840:4160749567]	109	1			T1	2		T38	1		T191	1
auto[4160749568:4294967295]	101	1			T13	1		T49	1		T145	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T1	2		T190	1		T50	1
auto[0:134217727]	auto[1]	47	1			T13	1		T47	1		T63	1
auto[134217728:268435455]	auto[0]	43	1			T1	1		T23	1		T133	1
auto[134217728:268435455]	auto[1]	60	1			T1	1		T4	1		T201	1
auto[268435456:402653183]	auto[0]	49	1			T201	1		T199	1		T95	1
auto[268435456:402653183]	auto[1]	66	1			T1	3		T38	1		T201	1
auto[402653184:536870911]	auto[0]	42	1			T190	1		T47	2		T96	1
auto[402653184:536870911]	auto[1]	65	1			T47	2		T49	1		T145	1
auto[536870912:671088639]	auto[0]	60	1			T43	1		T97	1		T278	1
auto[536870912:671088639]	auto[1]	75	1			T1	1		T47	1		T130	1
auto[671088640:805306367]	auto[0]	50	1			T37	1		T144	1		T43	1
auto[671088640:805306367]	auto[1]	58	1			T1	1		T47	3		T194	1
auto[805306368:939524095]	auto[0]	37	1			T125	1		T60	1		T78	1
auto[805306368:939524095]	auto[1]	50	1			T190	1		T201	1		T128	1
auto[939524096:1073741823]	auto[0]	55	1			T37	2		T97	1		T209	1
auto[939524096:1073741823]	auto[1]	54	1			T1	2		T47	1		T122	1
auto[1073741824:1207959551]	auto[0]	50	1			T1	2		T4	1		T13	1
auto[1073741824:1207959551]	auto[1]	66	1			T128	1		T47	3		T130	1
auto[1207959552:1342177279]	auto[0]	44	1			T1	1		T47	2		T52	1
auto[1207959552:1342177279]	auto[1]	59	1			T1	1		T47	1		T231	1
auto[1342177280:1476395007]	auto[0]	48	1			T128	2		T47	1		T145	1
auto[1342177280:1476395007]	auto[1]	50	1			T23	1		T47	1		T55	1
auto[1476395008:1610612735]	auto[0]	47	1			T94	1		T24	1		T54	1
auto[1476395008:1610612735]	auto[1]	61	1			T16	1		T38	1		T188	1
auto[1610612736:1744830463]	auto[0]	52	1			T1	2		T50	1		T5	1
auto[1610612736:1744830463]	auto[1]	55	1			T23	1		T97	1		T65	1
auto[1744830464:1879048191]	auto[0]	51	1			T47	1		T54	2		T52	1
auto[1744830464:1879048191]	auto[1]	65	1			T1	2		T128	1		T47	4
auto[1879048192:2013265919]	auto[0]	53	1			T24	1		T47	4		T48	1
auto[1879048192:2013265919]	auto[1]	59	1			T1	1		T16	1		T194	1
auto[2013265920:2147483647]	auto[0]	40	1			T1	1		T50	1		T47	1
auto[2013265920:2147483647]	auto[1]	70	1			T1	4		T16	1		T144	1
auto[2147483648:2281701375]	auto[0]	56	1			T3	1		T24	1		T55	1
auto[2147483648:2281701375]	auto[1]	62	1			T23	1		T47	1		T130	1
auto[2281701376:2415919103]	auto[0]	54	1			T43	1		T47	1		T145	1
auto[2281701376:2415919103]	auto[1]	63	1			T1	1		T47	1		T96	1
auto[2415919104:2550136831]	auto[0]	53	1			T43	1		T60	1		T56	1
auto[2415919104:2550136831]	auto[1]	61	1			T3	1		T36	1		T198	1
auto[2550136832:2684354559]	auto[0]	48	1			T1	1		T97	1		T199	1
auto[2550136832:2684354559]	auto[1]	61	1			T1	2		T37	1		T47	1
auto[2684354560:2818572287]	auto[0]	55	1			T1	1		T37	2		T38	1
auto[2684354560:2818572287]	auto[1]	65	1			T14	1		T94	1		T191	1
auto[2818572288:2952790015]	auto[0]	52	1			T16	1		T96	1		T63	1
auto[2818572288:2952790015]	auto[1]	73	1			T130	1		T54	1		T65	1
auto[2952790016:3087007743]	auto[0]	65	1			T1	1		T47	3		T54	1
auto[2952790016:3087007743]	auto[1]	65	1			T1	1		T23	1		T201	1
auto[3087007744:3221225471]	auto[0]	49	1			T24	1		T51	1		T207	1
auto[3087007744:3221225471]	auto[1]	46	1			T1	1		T97	1		T122	1
auto[3221225472:3355443199]	auto[0]	51	1			T3	1		T37	1		T199	1
auto[3221225472:3355443199]	auto[1]	60	1			T4	1		T16	1		T47	1
auto[3355443200:3489660927]	auto[0]	46	1			T14	1		T36	1		T97	1
auto[3355443200:3489660927]	auto[1]	56	1			T1	1		T3	1		T16	1
auto[3489660928:3623878655]	auto[0]	52	1			T1	2		T14	1		T188	1
auto[3489660928:3623878655]	auto[1]	52	1			T144	2		T60	2		T18	1
auto[3623878656:3758096383]	auto[0]	63	1			T191	1		T47	3		T198	1
auto[3623878656:3758096383]	auto[1]	61	1			T24	1		T188	1		T232	1
auto[3758096384:3892314111]	auto[0]	54	1			T1	3		T191	1		T47	3
auto[3758096384:3892314111]	auto[1]	58	1			T3	1		T14	2		T94	1
auto[3892314112:4026531839]	auto[0]	46	1			T1	2		T38	1		T47	1
auto[3892314112:4026531839]	auto[1]	51	1			T1	1		T191	1		T128	1
auto[4026531840:4160749567]	auto[0]	46	1			T1	2		T38	1		T47	1
auto[4026531840:4160749567]	auto[1]	63	1			T191	1		T144	1		T36	1
auto[4160749568:4294967295]	auto[0]	44	1			T49	1		T145	1		T228	1
auto[4160749568:4294967295]	auto[1]	57	1			T13	1		T82	1		T63	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T1

21

T3

2

T4

1

auto[1]

1905

1

T1

23

T3

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T1	3		T16	1		T36	1
auto[134217728:268435455]	102	1			T1	2		T16	1		T201	1
auto[268435456:402653183]	97	1			T1	1		T23	1		T37	1
auto[402653184:536870911]	121	1			T1	3		T38	1		T201	2
auto[536870912:671088639]	97	1			T1	2		T144	1		T47	4
auto[671088640:805306367]	107	1			T1	2		T94	1		T47	1
auto[805306368:939524095]	106	1			T191	1		T144	1		T190	1
auto[939524096:1073741823]	97	1			T1	2		T3	1		T4	1
auto[1073741824:1207959551]	94	1			T14	1		T47	1		T60	1
auto[1207959552:1342177279]	114	1			T1	3		T3	1		T16	1
auto[1342177280:1476395007]	99	1			T1	1		T16	1		T38	1
auto[1476395008:1610612735]	115	1			T1	1		T37	1		T128	1
auto[1610612736:1744830463]	98	1			T1	3		T23	2		T188	1
auto[1744830464:1879048191]	111	1			T1	1		T191	1		T144	1
auto[1879048192:2013265919]	104	1			T24	1		T38	1		T198	1
auto[2013265920:2147483647]	101	1			T1	3		T16	1		T94	1
auto[2147483648:2281701375]	114	1			T1	4		T37	1		T128	1
auto[2281701376:2415919103]	135	1			T1	1		T128	1		T47	5
auto[2415919104:2550136831]	106	1			T1	2		T14	1		T24	1
auto[2550136832:2684354559]	101	1			T4	1		T36	1		T201	1
auto[2684354560:2818572287]	122	1			T13	1		T16	1		T190	1
auto[2818572288:2952790015]	121	1			T13	1		T23	1		T188	1
auto[2952790016:3087007743]	121	1			T1	2		T23	1		T191	1
auto[3087007744:3221225471]	107	1			T13	1		T14	1		T43	1
auto[3221225472:3355443199]	122	1			T1	1		T3	1		T14	1
auto[3355443200:3489660927]	94	1			T14	1		T24	1		T201	1
auto[3489660928:3623878655]	123	1			T1	2		T3	2		T94	1
auto[3623878656:3758096383]	115	1			T144	1		T47	3		T97	1
auto[3758096384:3892314111]	99	1			T37	1		T144	1		T36	1
auto[3892314112:4026531839]	115	1			T4	1		T38	1		T188	1
auto[4026531840:4160749567]	122	1			T1	2		T47	4		T96	1
auto[4160749568:4294967295]	110	1			T1	3		T37	1		T43	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T1	1		T36	1		T47	1
auto[0:134217727]	auto[1]	63	1			T1	2		T16	1		T201	1
auto[134217728:268435455]	auto[0]	45	1			T201	1		T47	1		T97	1
auto[134217728:268435455]	auto[1]	57	1			T1	2		T16	1		T47	1
auto[268435456:402653183]	auto[0]	35	1			T37	1		T128	1		T47	1
auto[268435456:402653183]	auto[1]	62	1			T1	1		T23	1		T82	1
auto[402653184:536870911]	auto[0]	52	1			T1	1		T38	1		T47	1
auto[402653184:536870911]	auto[1]	69	1			T1	2		T201	2		T197	1
auto[536870912:671088639]	auto[0]	51	1			T1	1		T144	1		T47	2
auto[536870912:671088639]	auto[1]	46	1			T1	1		T47	2		T130	1
auto[671088640:805306367]	auto[0]	49	1			T1	2		T52	3		T89	1
auto[671088640:805306367]	auto[1]	58	1			T94	1		T47	1		T130	1
auto[805306368:939524095]	auto[0]	40	1			T47	1		T55	1		T54	1
auto[805306368:939524095]	auto[1]	66	1			T191	1		T144	1		T190	1
auto[939524096:1073741823]	auto[0]	48	1			T1	1		T97	1		T199	1
auto[939524096:1073741823]	auto[1]	49	1			T1	1		T3	1		T4	1
auto[1073741824:1207959551]	auto[0]	41	1			T56	1		T136	1		T250	1
auto[1073741824:1207959551]	auto[1]	53	1			T14	1		T47	1		T60	1
auto[1207959552:1342177279]	auto[0]	53	1			T1	1		T3	1		T37	1
auto[1207959552:1342177279]	auto[1]	61	1			T1	2		T16	1		T43	1
auto[1342177280:1476395007]	auto[0]	45	1			T1	1		T16	1		T43	1
auto[1342177280:1476395007]	auto[1]	54	1			T38	1		T47	1		T51	2
auto[1476395008:1610612735]	auto[0]	53	1			T199	1		T125	1		T52	1
auto[1476395008:1610612735]	auto[1]	62	1			T1	1		T37	1		T128	1
auto[1610612736:1744830463]	auto[0]	45	1			T1	3		T23	1		T233	1
auto[1610612736:1744830463]	auto[1]	53	1			T23	1		T188	1		T191	1
auto[1744830464:1879048191]	auto[0]	55	1			T1	1		T47	1		T96	1
auto[1744830464:1879048191]	auto[1]	56	1			T191	1		T144	1		T47	2
auto[1879048192:2013265919]	auto[0]	47	1			T24	1		T38	1		T97	1
auto[1879048192:2013265919]	auto[1]	57	1			T198	1		T199	1		T95	1
auto[2013265920:2147483647]	auto[0]	43	1			T1	2		T94	1		T24	1
auto[2013265920:2147483647]	auto[1]	58	1			T1	1		T16	1		T24	1
auto[2147483648:2281701375]	auto[0]	51	1			T1	2		T37	1		T47	1
auto[2147483648:2281701375]	auto[1]	63	1			T1	2		T128	1		T233	1
auto[2281701376:2415919103]	auto[0]	67	1			T128	1		T47	3		T199	1
auto[2281701376:2415919103]	auto[1]	68	1			T1	1		T47	2		T194	1
auto[2415919104:2550136831]	auto[0]	55	1			T1	1		T14	1		T24	1
auto[2415919104:2550136831]	auto[1]	51	1			T1	1		T43	1		T194	1
auto[2550136832:2684354559]	auto[0]	53	1			T4	1		T278	1		T78	1
auto[2550136832:2684354559]	auto[1]	48	1			T36	1		T201	1		T65	1
auto[2684354560:2818572287]	auto[0]	56	1			T47	1		T60	1		T5	1
auto[2684354560:2818572287]	auto[1]	66	1			T13	1		T16	1		T190	1
auto[2818572288:2952790015]	auto[0]	50	1			T23	1		T144	1		T47	2
auto[2818572288:2952790015]	auto[1]	71	1			T13	1		T188	1		T128	1
auto[2952790016:3087007743]	auto[0]	49	1			T191	1		T36	1		T60	1
auto[2952790016:3087007743]	auto[1]	72	1			T1	2		T23	1		T47	2
auto[3087007744:3221225471]	auto[0]	54	1			T13	1		T14	1		T43	1
auto[3087007744:3221225471]	auto[1]	53	1			T130	1		T60	1		T228	1
auto[3221225472:3355443199]	auto[0]	50	1			T1	1		T190	1		T96	1
auto[3221225472:3355443199]	auto[1]	72	1			T3	1		T14	1		T191	1
auto[3355443200:3489660927]	auto[0]	48	1			T24	1		T60	1		T56	1
auto[3355443200:3489660927]	auto[1]	46	1			T14	1		T201	1		T47	1
auto[3489660928:3623878655]	auto[0]	58	1			T1	1		T3	1		T94	1
auto[3489660928:3623878655]	auto[1]	65	1			T1	1		T3	1		T65	1
auto[3623878656:3758096383]	auto[0]	51	1			T47	2		T134	1		T63	1
auto[3623878656:3758096383]	auto[1]	64	1			T144	1		T47	1		T97	1
auto[3758096384:3892314111]	auto[0]	43	1			T37	1		T50	1		T47	2
auto[3758096384:3892314111]	auto[1]	56	1			T144	1		T36	1		T47	1
auto[3892314112:4026531839]	auto[0]	61	1			T38	1		T50	2		T145	1
auto[3892314112:4026531839]	auto[1]	54	1			T4	1		T188	1		T145	1
auto[4026531840:4160749567]	auto[0]	49	1			T1	1		T47	2		T198	1
auto[4026531840:4160749567]	auto[1]	73	1			T1	1		T47	2		T96	1
auto[4160749568:4294967295]	auto[0]	51	1			T1	1		T37	1		T43	1
auto[4160749568:4294967295]	auto[1]	59	1			T1	2		T43	1		T47	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T1

21

T3

2

T4

1

auto[1]

1905

1

T1

23

T3

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T1	1		T14	2		T188	1
auto[134217728:268435455]	102	1			T1	2		T94	1		T23	1
auto[268435456:402653183]	112	1			T1	1		T201	2		T128	1
auto[402653184:536870911]	106	1			T1	1		T13	1		T37	1
auto[536870912:671088639]	131	1			T3	1		T16	1		T23	1
auto[671088640:805306367]	125	1			T1	1		T37	2		T144	1
auto[805306368:939524095]	108	1			T1	1		T23	1		T38	1
auto[939524096:1073741823]	122	1			T37	1		T188	1		T47	3
auto[1073741824:1207959551]	83	1			T1	1		T16	1		T24	1
auto[1207959552:1342177279]	108	1			T1	1		T13	1		T38	1
auto[1342177280:1476395007]	94	1			T24	1		T47	1		T60	1
auto[1476395008:1610612735]	97	1			T1	2		T38	1		T191	1
auto[1610612736:1744830463]	115	1			T1	2		T3	1		T4	1
auto[1744830464:1879048191]	96	1			T199	1		T60	2		T197	2
auto[1879048192:2013265919]	136	1			T1	3		T37	1		T36	1
auto[2013265920:2147483647]	126	1			T1	1		T190	1		T128	1
auto[2147483648:2281701375]	96	1			T24	1		T191	1		T47	2
auto[2281701376:2415919103]	115	1			T1	2		T4	1		T37	1
auto[2415919104:2550136831]	87	1			T1	3		T47	2		T49	1
auto[2550136832:2684354559]	97	1			T1	1		T3	1		T128	1
auto[2684354560:2818572287]	97	1			T1	1		T94	1		T23	1
auto[2818572288:2952790015]	107	1			T1	2		T16	1		T94	1
auto[2952790016:3087007743]	111	1			T1	3		T201	1		T47	2
auto[3087007744:3221225471]	110	1			T1	2		T3	1		T191	1
auto[3221225472:3355443199]	114	1			T1	3		T3	1		T13	1
auto[3355443200:3489660927]	88	1			T201	1		T47	1		T130	1
auto[3489660928:3623878655]	131	1			T1	4		T4	1		T24	1
auto[3623878656:3758096383]	108	1			T1	1		T16	1		T43	2
auto[3758096384:3892314111]	105	1			T1	1		T38	1		T144	1
auto[3892314112:4026531839]	136	1			T1	1		T14	1		T37	1
auto[4026531840:4160749567]	126	1			T1	1		T16	1		T191	1
auto[4160749568:4294967295]	108	1			T1	2		T16	1		T47	1