Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3111

1

T1

37

T3

2

T4

3

auto[1]

299

1

T4

1

T14

2

T16

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T38	1		T201	1		T47	2
auto[134217728:268435455]	119	1			T1	1		T14	1		T144	1
auto[268435456:402653183]	99	1			T3	1		T14	1		T37	1
auto[402653184:536870911]	99	1			T1	1		T16	1		T37	1
auto[536870912:671088639]	110	1			T16	2		T144	1		T190	1
auto[671088640:805306367]	113	1			T1	2		T4	1		T43	1
auto[805306368:939524095]	114	1			T1	2		T144	2		T36	1
auto[939524096:1073741823]	91	1			T1	1		T4	1		T37	1
auto[1073741824:1207959551]	106	1			T1	2		T13	1		T16	1
auto[1207959552:1342177279]	119	1			T1	1		T4	1		T14	1
auto[1342177280:1476395007]	97	1			T1	1		T16	1		T94	1
auto[1476395008:1610612735]	90	1			T128	1		T47	2		T194	1
auto[1610612736:1744830463]	106	1			T1	2		T13	1		T128	1
auto[1744830464:1879048191]	110	1			T1	2		T23	1		T201	2
auto[1879048192:2013265919]	103	1			T1	3		T37	1		T191	1
auto[2013265920:2147483647]	105	1			T1	3		T191	1		T144	1
auto[2147483648:2281701375]	98	1			T1	2		T14	1		T16	1
auto[2281701376:2415919103]	116	1			T1	1		T4	1		T16	1
auto[2415919104:2550136831]	105	1			T14	1		T16	1		T37	1
auto[2550136832:2684354559]	105	1			T1	1		T144	1		T43	1
auto[2684354560:2818572287]	119	1			T1	1		T16	1		T23	1
auto[2818572288:2952790015]	118	1			T1	3		T14	1		T16	1
auto[2952790016:3087007743]	115	1			T24	1		T128	1		T47	2
auto[3087007744:3221225471]	106	1			T190	1		T47	1		T82	1
auto[3221225472:3355443199]	96	1			T1	2		T198	1		T145	1
auto[3355443200:3489660927]	95	1			T1	1		T94	1		T134	1
auto[3489660928:3623878655]	103	1			T23	1		T128	1		T47	1
auto[3623878656:3758096383]	101	1			T1	1		T188	1		T145	1
auto[3758096384:3892314111]	107	1			T1	2		T94	1		T37	1
auto[3892314112:4026531839]	118	1			T13	1		T14	1		T38	1
auto[4026531840:4160749567]	121	1			T1	1		T3	1		T23	1
auto[4160749568:4294967295]	106	1			T1	1		T38	1		T128	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	93	1			T38	1		T201	1		T47	2
auto[0:134217727]	auto[1]	7	1			T297	1		T379	1		T398	1
auto[134217728:268435455]	auto[0]	111	1			T1	1		T14	1		T144	1
auto[134217728:268435455]	auto[1]	8	1			T330	1		T398	1		T395	1
auto[268435456:402653183]	auto[0]	93	1			T3	1		T14	1		T37	1
auto[268435456:402653183]	auto[1]	6	1			T136	1		T297	1		T377	1
auto[402653184:536870911]	auto[0]	89	1			T1	1		T16	1		T37	1
auto[402653184:536870911]	auto[1]	10	1			T135	1		T276	1		T297	1
auto[536870912:671088639]	auto[0]	103	1			T16	2		T190	1		T47	1
auto[536870912:671088639]	auto[1]	7	1			T144	1		T228	1		T316	1
auto[671088640:805306367]	auto[0]	104	1			T1	2		T4	1		T43	1
auto[671088640:805306367]	auto[1]	9	1			T135	2		T317	1		T379	1
auto[805306368:939524095]	auto[0]	105	1			T1	2		T36	1		T47	3
auto[805306368:939524095]	auto[1]	9	1			T144	2		T254	1		T335	1
auto[939524096:1073741823]	auto[0]	85	1			T1	1		T4	1		T37	1
auto[939524096:1073741823]	auto[1]	6	1			T145	1		T295	1		T305	1
auto[1073741824:1207959551]	auto[0]	97	1			T1	2		T13	1		T16	1
auto[1073741824:1207959551]	auto[1]	9	1			T128	1		T134	1		T295	1
auto[1207959552:1342177279]	auto[0]	102	1			T1	1		T4	1		T16	1
auto[1207959552:1342177279]	auto[1]	17	1			T14	1		T136	1		T317	2
auto[1342177280:1476395007]	auto[0]	86	1			T1	1		T94	1		T47	3
auto[1342177280:1476395007]	auto[1]	11	1			T16	1		T144	1		T228	1
auto[1476395008:1610612735]	auto[0]	79	1			T47	2		T194	1		T97	2
auto[1476395008:1610612735]	auto[1]	11	1			T128	1		T276	1		T295	1
auto[1610612736:1744830463]	auto[0]	94	1			T1	2		T13	1		T128	1
auto[1610612736:1744830463]	auto[1]	12	1			T135	1		T254	2		T276	1
auto[1744830464:1879048191]	auto[0]	102	1			T1	2		T23	1		T201	2
auto[1744830464:1879048191]	auto[1]	8	1			T138	1		T297	1		T330	1
auto[1879048192:2013265919]	auto[0]	95	1			T1	3		T37	1		T191	1
auto[1879048192:2013265919]	auto[1]	8	1			T144	1		T316	1		T270	1
auto[2013265920:2147483647]	auto[0]	92	1			T1	3		T191	1		T144	1
auto[2013265920:2147483647]	auto[1]	13	1			T128	1		T136	1		T137	1
auto[2147483648:2281701375]	auto[0]	90	1			T1	2		T14	1		T24	1
auto[2147483648:2281701375]	auto[1]	8	1			T16	1		T128	1		T379	1
auto[2281701376:2415919103]	auto[0]	105	1			T1	1		T23	1		T188	1
auto[2281701376:2415919103]	auto[1]	11	1			T4	1		T16	1		T144	1
auto[2415919104:2550136831]	auto[0]	97	1			T14	1		T37	1		T144	1
auto[2415919104:2550136831]	auto[1]	8	1			T16	1		T135	1		T138	1
auto[2550136832:2684354559]	auto[0]	91	1			T1	1		T144	1		T43	1
auto[2550136832:2684354559]	auto[1]	14	1			T136	1		T295	1		T246	2
auto[2684354560:2818572287]	auto[0]	108	1			T1	1		T23	1		T37	1
auto[2684354560:2818572287]	auto[1]	11	1			T16	1		T228	1		T136	1
auto[2818572288:2952790015]	auto[0]	111	1			T1	3		T14	1		T16	1
auto[2818572288:2952790015]	auto[1]	7	1			T145	1		T138	1		T307	1
auto[2952790016:3087007743]	auto[0]	101	1			T24	1		T47	2		T232	1
auto[2952790016:3087007743]	auto[1]	14	1			T128	1		T136	1		T317	1
auto[3087007744:3221225471]	auto[0]	100	1			T190	1		T47	1		T82	1
auto[3087007744:3221225471]	auto[1]	6	1			T297	1		T379	2		T397	1
auto[3221225472:3355443199]	auto[0]	84	1			T1	2		T198	1		T145	1
auto[3221225472:3355443199]	auto[1]	12	1			T228	1		T317	2		T297	1
auto[3355443200:3489660927]	auto[0]	87	1			T1	1		T94	1		T199	1
auto[3355443200:3489660927]	auto[1]	8	1			T134	1		T138	1		T379	1
auto[3489660928:3623878655]	auto[0]	97	1			T23	1		T47	1		T49	1
auto[3489660928:3623878655]	auto[1]	6	1			T128	1		T295	1		T378	1
auto[3623878656:3758096383]	auto[0]	96	1			T1	1		T188	1		T145	1
auto[3623878656:3758096383]	auto[1]	5	1			T295	1		T360	1		T305	1
auto[3758096384:3892314111]	auto[0]	99	1			T1	2		T94	1		T37	1
auto[3758096384:3892314111]	auto[1]	8	1			T145	1		T228	1		T137	1
auto[3892314112:4026531839]	auto[0]	106	1			T13	1		T38	1		T128	1
auto[3892314112:4026531839]	auto[1]	12	1			T14	1		T135	1		T228	1
auto[4026531840:4160749567]	auto[0]	108	1			T1	1		T3	1		T23	1
auto[4026531840:4160749567]	auto[1]	13	1			T137	2		T138	1		T346	1
auto[4160749568:4294967295]	auto[0]	101	1			T1	1		T38	1		T128	1
auto[4160749568:4294967295]	auto[1]	5	1			T136	1		T316	1		T360	1