Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3110

1

T1

37

T3

2

T4

3

auto[1]

346

1

T4

2

T14

5

T16

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T1	2		T4	1		T14	2
auto[134217728:268435455]	113	1			T1	3		T3	1		T13	1
auto[268435456:402653183]	102	1			T1	3		T16	1		T191	1
auto[402653184:536870911]	104	1			T133	1		T96	1		T145	1
auto[536870912:671088639]	113	1			T24	1		T144	2		T47	3
auto[671088640:805306367]	103	1			T16	1		T201	1		T43	1
auto[805306368:939524095]	111	1			T1	4		T16	1		T191	1
auto[939524096:1073741823]	102	1			T1	2		T14	1		T16	1
auto[1073741824:1207959551]	105	1			T1	2		T4	1		T37	1
auto[1207959552:1342177279]	120	1			T23	1		T36	1		T50	2
auto[1342177280:1476395007]	107	1			T24	1		T43	1		T128	1
auto[1476395008:1610612735]	105	1			T47	1		T199	1		T82	1
auto[1610612736:1744830463]	100	1			T1	1		T3	1		T37	1
auto[1744830464:1879048191]	127	1			T14	1		T16	1		T188	1
auto[1879048192:2013265919]	84	1			T1	1		T16	1		T23	1
auto[2013265920:2147483647]	118	1			T1	2		T24	1		T190	1
auto[2147483648:2281701375]	92	1			T14	1		T128	1		T47	1
auto[2281701376:2415919103]	120	1			T128	2		T47	1		T198	1
auto[2415919104:2550136831]	106	1			T1	2		T16	1		T191	1
auto[2550136832:2684354559]	100	1			T1	2		T4	1		T14	1
auto[2684354560:2818572287]	98	1			T1	1		T14	1		T24	1
auto[2818572288:2952790015]	134	1			T1	1		T4	1		T190	1
auto[2952790016:3087007743]	109	1			T1	1		T14	1		T16	1
auto[3087007744:3221225471]	92	1			T1	2		T13	1		T38	1
auto[3221225472:3355443199]	98	1			T37	2		T24	1		T43	1
auto[3355443200:3489660927]	121	1			T13	1		T14	1		T94	1
auto[3489660928:3623878655]	102	1			T1	4		T4	1		T16	1
auto[3623878656:3758096383]	131	1			T1	1		T16	1		T188	1
auto[3758096384:3892314111]	97	1			T23	2		T144	1		T201	1
auto[3892314112:4026531839]	120	1			T1	2		T14	1		T94	1
auto[4026531840:4160749567]	109	1			T1	1		T38	1		T144	1
auto[4160749568:4294967295]	103	1			T16	1		T37	2		T191	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	105	1			T1	2		T14	1		T190	1
auto[0:134217727]	auto[1]	5	1			T4	1		T14	1		T297	1
auto[134217728:268435455]	auto[0]	101	1			T1	3		T3	1		T13	1
auto[134217728:268435455]	auto[1]	12	1			T135	1		T136	1		T138	2
auto[268435456:402653183]	auto[0]	94	1			T1	3		T191	1		T144	1
auto[268435456:402653183]	auto[1]	8	1			T16	1		T254	1		T295	1
auto[402653184:536870911]	auto[0]	91	1			T133	1		T96	1		T145	1
auto[402653184:536870911]	auto[1]	13	1			T316	1		T138	1		T254	1
auto[536870912:671088639]	auto[0]	96	1			T24	1		T144	1		T47	3
auto[536870912:671088639]	auto[1]	17	1			T144	1		T145	1		T135	1
auto[671088640:805306367]	auto[0]	98	1			T16	1		T201	1		T43	1
auto[671088640:805306367]	auto[1]	5	1			T398	1		T395	1		T399	1
auto[805306368:939524095]	auto[0]	101	1			T1	4		T191	1		T36	1
auto[805306368:939524095]	auto[1]	10	1			T16	1		T295	1		T270	1
auto[939524096:1073741823]	auto[0]	89	1			T1	2		T16	1		T47	1
auto[939524096:1073741823]	auto[1]	13	1			T14	1		T228	1		T136	2
auto[1073741824:1207959551]	auto[0]	95	1			T1	2		T4	1		T37	1
auto[1073741824:1207959551]	auto[1]	10	1			T145	1		T134	1		T270	1
auto[1207959552:1342177279]	auto[0]	115	1			T23	1		T36	1		T50	2
auto[1207959552:1342177279]	auto[1]	5	1			T134	1		T136	1		T317	1
auto[1342177280:1476395007]	auto[0]	96	1			T24	1		T43	1		T47	1
auto[1342177280:1476395007]	auto[1]	11	1			T128	1		T136	1		T317	1
auto[1476395008:1610612735]	auto[0]	97	1			T47	1		T199	1		T82	1
auto[1476395008:1610612735]	auto[1]	8	1			T137	1		T297	1		T295	1
auto[1610612736:1744830463]	auto[0]	92	1			T1	1		T3	1		T37	1
auto[1610612736:1744830463]	auto[1]	8	1			T136	1		T270	1		T246	1
auto[1744830464:1879048191]	auto[0]	109	1			T188	1		T50	1		T47	1
auto[1744830464:1879048191]	auto[1]	18	1			T14	1		T16	1		T135	1
auto[1879048192:2013265919]	auto[0]	77	1			T1	1		T23	1		T128	1
auto[1879048192:2013265919]	auto[1]	7	1			T16	1		T135	1		T138	1
auto[2013265920:2147483647]	auto[0]	105	1			T1	2		T24	1		T190	1
auto[2013265920:2147483647]	auto[1]	13	1			T145	1		T136	2		T317	1
auto[2147483648:2281701375]	auto[0]	86	1			T14	1		T47	1		T130	1
auto[2147483648:2281701375]	auto[1]	6	1			T128	1		T295	1		T379	1
auto[2281701376:2415919103]	auto[0]	103	1			T47	1		T198	1		T278	1
auto[2281701376:2415919103]	auto[1]	17	1			T128	2		T135	2		T228	1
auto[2415919104:2550136831]	auto[0]	97	1			T1	2		T191	1		T47	4
auto[2415919104:2550136831]	auto[1]	9	1			T16	1		T379	1		T398	2
auto[2550136832:2684354559]	auto[0]	92	1			T1	2		T4	1		T16	1
auto[2550136832:2684354559]	auto[1]	8	1			T14	1		T135	1		T317	1
auto[2684354560:2818572287]	auto[0]	82	1			T1	1		T14	1		T24	1
auto[2684354560:2818572287]	auto[1]	16	1			T128	1		T317	1		T138	1
auto[2818572288:2952790015]	auto[0]	123	1			T1	1		T190	1		T128	1
auto[2818572288:2952790015]	auto[1]	11	1			T4	1		T228	1		T136	2
auto[2952790016:3087007743]	auto[0]	98	1			T1	1		T14	1		T201	1
auto[2952790016:3087007743]	auto[1]	11	1			T16	1		T134	1		T135	1
auto[3087007744:3221225471]	auto[0]	81	1			T1	2		T13	1		T38	1
auto[3087007744:3221225471]	auto[1]	11	1			T128	1		T136	2		T297	1
auto[3221225472:3355443199]	auto[0]	89	1			T37	2		T24	1		T43	1
auto[3221225472:3355443199]	auto[1]	9	1			T135	2		T228	1		T330	1
auto[3355443200:3489660927]	auto[0]	108	1			T13	1		T94	1		T130	1
auto[3355443200:3489660927]	auto[1]	13	1			T14	1		T134	1		T138	1
auto[3489660928:3623878655]	auto[0]	96	1			T1	4		T4	1		T16	1
auto[3489660928:3623878655]	auto[1]	6	1			T134	1		T254	1		T295	1
auto[3623878656:3758096383]	auto[0]	115	1			T1	1		T16	1		T188	1
auto[3623878656:3758096383]	auto[1]	16	1			T128	1		T228	1		T316	1
auto[3758096384:3892314111]	auto[0]	83	1			T23	2		T201	1		T50	1
auto[3758096384:3892314111]	auto[1]	14	1			T144	1		T135	1		T136	1
auto[3892314112:4026531839]	auto[0]	107	1			T1	2		T14	1		T94	1
auto[3892314112:4026531839]	auto[1]	13	1			T144	1		T135	1		T137	1
auto[4026531840:4160749567]	auto[0]	95	1			T1	1		T38	1		T43	1
auto[4026531840:4160749567]	auto[1]	14	1			T144	1		T128	1		T135	2
auto[4160749568:4294967295]	auto[0]	94	1			T37	2		T191	1		T47	3
auto[4160749568:4294967295]	auto[1]	9	1			T16	1		T134	1		T246	1