Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T1

17

T3

1

T4

1

auto[1]

1907

1

T1

27

T3

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T1	4		T38	1		T43	1
auto[134217728:268435455]	112	1			T128	1		T47	2		T54	1
auto[268435456:402653183]	114	1			T1	2		T36	1		T47	1
auto[402653184:536870911]	109	1			T1	2		T13	1		T191	1
auto[536870912:671088639]	103	1			T1	1		T3	1		T47	4
auto[671088640:805306367]	97	1			T1	3		T47	3		T54	1
auto[805306368:939524095]	121	1			T4	1		T37	1		T36	1
auto[939524096:1073741823]	115	1			T1	1		T16	1		T24	1
auto[1073741824:1207959551]	114	1			T1	1		T3	1		T14	1
auto[1207959552:1342177279]	106	1			T1	2		T3	1		T201	1
auto[1342177280:1476395007]	119	1			T1	2		T14	1		T94	1
auto[1476395008:1610612735]	112	1			T1	1		T14	1		T37	1
auto[1610612736:1744830463]	109	1			T37	1		T188	1		T201	1
auto[1744830464:1879048191]	109	1			T1	2		T24	1		T47	1
auto[1879048192:2013265919]	105	1			T188	1		T144	1		T201	1
auto[2013265920:2147483647]	106	1			T1	2		T16	1		T23	1
auto[2147483648:2281701375]	106	1			T13	1		T16	1		T23	1
auto[2281701376:2415919103]	109	1			T47	4		T130	1		T145	1
auto[2415919104:2550136831]	114	1			T1	2		T13	1		T16	1
auto[2550136832:2684354559]	106	1			T1	2		T4	1		T16	1
auto[2684354560:2818572287]	121	1			T1	1		T24	1		T47	1
auto[2818572288:2952790015]	110	1			T1	2		T14	1		T16	1
auto[2952790016:3087007743]	105	1			T23	1		T201	1		T43	2
auto[3087007744:3221225471]	110	1			T1	2		T3	1		T24	1
auto[3221225472:3355443199]	120	1			T1	1		T38	1		T144	1
auto[3355443200:3489660927]	123	1			T1	1		T4	1		T94	1
auto[3489660928:3623878655]	86	1			T1	3		T47	1		T96	1
auto[3623878656:3758096383]	105	1			T1	1		T201	1		T47	2
auto[3758096384:3892314111]	111	1			T1	1		T14	1		T194	2
auto[3892314112:4026531839]	118	1			T1	3		T94	1		T37	1
auto[4026531840:4160749567]	98	1			T1	1		T3	1		T23	1
auto[4160749568:4294967295]	108	1			T1	1		T144	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T1	1		T43	1		T50	1
auto[0:134217727]	auto[1]	60	1			T1	3		T38	1		T27	1
auto[134217728:268435455]	auto[0]	58	1			T128	1		T47	1		T54	1
auto[134217728:268435455]	auto[1]	54	1			T47	1		T65	1		T122	1
auto[268435456:402653183]	auto[0]	54	1			T36	1		T47	1		T97	1
auto[268435456:402653183]	auto[1]	60	1			T1	2		T40	1		T123	1
auto[402653184:536870911]	auto[0]	56	1			T1	1		T13	1		T201	1
auto[402653184:536870911]	auto[1]	53	1			T1	1		T191	1		T144	1
auto[536870912:671088639]	auto[0]	41	1			T1	1		T47	1		T97	1
auto[536870912:671088639]	auto[1]	62	1			T3	1		T47	3		T135	1
auto[671088640:805306367]	auto[0]	40	1			T1	1		T47	1		T32	1
auto[671088640:805306367]	auto[1]	57	1			T1	2		T47	2		T54	1
auto[805306368:939524095]	auto[0]	57	1			T4	1		T133	1		T145	1
auto[805306368:939524095]	auto[1]	64	1			T37	1		T36	1		T130	1
auto[939524096:1073741823]	auto[0]	53	1			T1	1		T24	1		T38	1
auto[939524096:1073741823]	auto[1]	62	1			T16	1		T191	1		T43	1
auto[1073741824:1207959551]	auto[0]	50	1			T1	1		T37	1		T144	1
auto[1073741824:1207959551]	auto[1]	64	1			T3	1		T14	1		T190	1
auto[1207959552:1342177279]	auto[0]	40	1			T1	1		T47	1		T55	1
auto[1207959552:1342177279]	auto[1]	66	1			T1	1		T3	1		T201	1
auto[1342177280:1476395007]	auto[0]	64	1			T1	2		T94	1		T190	1
auto[1342177280:1476395007]	auto[1]	55	1			T14	1		T47	1		T81	1
auto[1476395008:1610612735]	auto[0]	48	1			T14	1		T191	1		T52	1
auto[1476395008:1610612735]	auto[1]	64	1			T1	1		T37	1		T43	1
auto[1610612736:1744830463]	auto[0]	59	1			T37	1		T47	2		T56	1
auto[1610612736:1744830463]	auto[1]	50	1			T188	1		T201	1		T199	1
auto[1744830464:1879048191]	auto[0]	53	1			T1	1		T47	1		T199	1
auto[1744830464:1879048191]	auto[1]	56	1			T1	1		T24	1		T60	1
auto[1879048192:2013265919]	auto[0]	48	1			T47	1		T209	1		T52	1
auto[1879048192:2013265919]	auto[1]	57	1			T188	1		T144	1		T201	1
auto[2013265920:2147483647]	auto[0]	41	1			T128	1		T47	1		T125	1
auto[2013265920:2147483647]	auto[1]	65	1			T1	2		T16	1		T23	1
auto[2147483648:2281701375]	auto[0]	49	1			T37	1		T96	1		T60	1
auto[2147483648:2281701375]	auto[1]	57	1			T13	1		T16	1		T23	1
auto[2281701376:2415919103]	auto[0]	49	1			T47	2		T197	1		T233	1
auto[2281701376:2415919103]	auto[1]	60	1			T47	2		T130	1		T145	1
auto[2415919104:2550136831]	auto[0]	49	1			T50	1		T47	1		T78	1
auto[2415919104:2550136831]	auto[1]	65	1			T1	2		T13	1		T16	1
auto[2550136832:2684354559]	auto[0]	40	1			T1	1		T24	1		T145	2
auto[2550136832:2684354559]	auto[1]	66	1			T1	1		T4	1		T16	1
auto[2684354560:2818572287]	auto[0]	57	1			T24	1		T47	1		T97	1
auto[2684354560:2818572287]	auto[1]	64	1			T1	1		T198	1		T82	1
auto[2818572288:2952790015]	auto[0]	54	1			T1	1		T16	1		T188	1
auto[2818572288:2952790015]	auto[1]	56	1			T1	1		T14	1		T47	1
auto[2952790016:3087007743]	auto[0]	53	1			T201	1		T43	2		T47	1
auto[2952790016:3087007743]	auto[1]	52	1			T23	1		T128	1		T49	1
auto[3087007744:3221225471]	auto[0]	45	1			T50	1		T47	2		T134	1
auto[3087007744:3221225471]	auto[1]	65	1			T1	2		T3	1		T24	1
auto[3221225472:3355443199]	auto[0]	51	1			T1	1		T38	1		T144	1
auto[3221225472:3355443199]	auto[1]	69	1			T47	1		T96	1		T134	1
auto[3355443200:3489660927]	auto[0]	50	1			T94	1		T47	1		T54	1
auto[3355443200:3489660927]	auto[1]	73	1			T1	1		T4	1		T191	1
auto[3489660928:3623878655]	auto[0]	42	1			T96	1		T145	1		T54	1
auto[3489660928:3623878655]	auto[1]	44	1			T1	3		T47	1		T135	1
auto[3623878656:3758096383]	auto[0]	50	1			T1	1		T47	1		T54	1
auto[3623878656:3758096383]	auto[1]	55	1			T201	1		T47	1		T232	1
auto[3758096384:3892314111]	auto[0]	49	1			T194	1		T60	1		T278	1
auto[3758096384:3892314111]	auto[1]	62	1			T1	1		T14	1		T194	1
auto[3892314112:4026531839]	auto[0]	60	1			T1	2		T37	1		T38	1
auto[3892314112:4026531839]	auto[1]	58	1			T1	1		T94	1		T47	2
auto[4026531840:4160749567]	auto[0]	44	1			T3	1		T37	1		T198	1
auto[4026531840:4160749567]	auto[1]	54	1			T1	1		T23	1		T36	1
auto[4160749568:4294967295]	auto[0]	50	1			T1	1		T50	1		T47	1
auto[4160749568:4294967295]	auto[1]	58	1			T144	1		T47	1		T232	1