Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 98.11 98.60 100.00 99.02 98.41 91.14


Total test records in report: 1081
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T1007 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.118281836 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:11 PM PDT 24 75222454 ps
T158 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1945013314 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:14 PM PDT 24 234546846 ps
T1008 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3501083333 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:09 PM PDT 24 46339541 ps
T1009 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2701374824 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:08 PM PDT 24 125503191 ps
T1010 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2101105017 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:06 PM PDT 24 25941857 ps
T1011 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1821674373 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:51 PM PDT 24 131259700 ps
T1012 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3387771378 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:15 PM PDT 24 329444270 ps
T1013 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2072277514 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:08 PM PDT 24 190628371 ps
T1014 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3217956097 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:05 PM PDT 24 8895027 ps
T1015 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1503458760 Jul 25 04:43:34 PM PDT 24 Jul 25 04:43:39 PM PDT 24 98981719 ps
T167 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1862447718 Jul 25 04:43:02 PM PDT 24 Jul 25 04:43:07 PM PDT 24 143456719 ps
T1016 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4270479254 Jul 25 04:43:51 PM PDT 24 Jul 25 04:43:52 PM PDT 24 55291269 ps
T1017 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2024641710 Jul 25 04:42:58 PM PDT 24 Jul 25 04:43:04 PM PDT 24 3057084220 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2203985746 Jul 25 04:42:59 PM PDT 24 Jul 25 04:43:00 PM PDT 24 15459380 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2573336639 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:21 PM PDT 24 858785547 ps
T1020 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1474231337 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:05 PM PDT 24 51718377 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2870633959 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:10 PM PDT 24 189950470 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3701961683 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:10 PM PDT 24 22566717 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1091340275 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:04 PM PDT 24 40288258 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4139878841 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:07 PM PDT 24 44132881 ps
T1025 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4226267772 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:07 PM PDT 24 15447896 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.505419390 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:13 PM PDT 24 140969719 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.423063257 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:06 PM PDT 24 176974111 ps
T177 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3676141588 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:52 PM PDT 24 54668448 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1001775211 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:06 PM PDT 24 159962409 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2054309492 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:11 PM PDT 24 65810058 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.856264553 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:14 PM PDT 24 378826100 ps
T1031 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2647082435 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:06 PM PDT 24 173280790 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.635606987 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:08 PM PDT 24 136521509 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.288457938 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:09 PM PDT 24 150925645 ps
T171 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1857524615 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:05 PM PDT 24 758252160 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1058388909 Jul 25 04:42:57 PM PDT 24 Jul 25 04:43:02 PM PDT 24 717505698 ps
T1035 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2429366214 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:13 PM PDT 24 1347996080 ps
T1036 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.43091706 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:06 PM PDT 24 63390030 ps
T1037 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3888686677 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:10 PM PDT 24 23313118 ps
T1038 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.769795100 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:48 PM PDT 24 47288579 ps
T1039 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2001642807 Jul 25 04:43:15 PM PDT 24 Jul 25 04:43:26 PM PDT 24 18517954 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2084415777 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:12 PM PDT 24 426034583 ps
T1041 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1514810357 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:09 PM PDT 24 45018355 ps
T1042 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2355710289 Jul 25 04:43:29 PM PDT 24 Jul 25 04:43:32 PM PDT 24 273666102 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.980123129 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:08 PM PDT 24 300945098 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3740124526 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:17 PM PDT 24 180793440 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2226986847 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:55 PM PDT 24 25058567 ps
T1046 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3751538540 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:09 PM PDT 24 19915098 ps
T1047 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2805552608 Jul 25 04:43:40 PM PDT 24 Jul 25 04:43:41 PM PDT 24 12380493 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.106300715 Jul 25 04:43:17 PM PDT 24 Jul 25 04:43:19 PM PDT 24 61640558 ps
T1049 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4277970522 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:07 PM PDT 24 43683000 ps
T1050 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4213846428 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 204788536 ps
T1051 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.290017133 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:02 PM PDT 24 97649810 ps
T1052 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1008389262 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:07 PM PDT 24 41139250 ps
T1053 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.999862455 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 39410423 ps
T156 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2949793592 Jul 25 04:43:02 PM PDT 24 Jul 25 04:43:12 PM PDT 24 544560962 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2200526081 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:05 PM PDT 24 170777905 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.44726188 Jul 25 04:42:55 PM PDT 24 Jul 25 04:42:56 PM PDT 24 32122350 ps
T1056 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3737596417 Jul 25 04:43:07 PM PDT 24 Jul 25 04:43:08 PM PDT 24 18808476 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4116767575 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:07 PM PDT 24 76486599 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1113094085 Jul 25 04:42:59 PM PDT 24 Jul 25 04:43:01 PM PDT 24 69988066 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3530868578 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:08 PM PDT 24 55833853 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1865913433 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:07 PM PDT 24 50094392 ps
T1061 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.904146343 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:09 PM PDT 24 247872411 ps
T1062 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3128215024 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:52 PM PDT 24 54742179 ps
T1063 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.950407338 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:10 PM PDT 24 77388159 ps
T1064 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3956401699 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:04 PM PDT 24 99370707 ps
T166 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.240569885 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:16 PM PDT 24 1139061529 ps
T1065 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2957721593 Jul 25 04:43:32 PM PDT 24 Jul 25 04:43:32 PM PDT 24 10881504 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.882428845 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:03 PM PDT 24 21770304 ps
T1067 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3695523218 Jul 25 04:43:04 PM PDT 24 Jul 25 04:43:05 PM PDT 24 11282663 ps
T1068 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3317834266 Jul 25 04:43:14 PM PDT 24 Jul 25 04:43:16 PM PDT 24 73384992 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.817150275 Jul 25 04:42:59 PM PDT 24 Jul 25 04:43:00 PM PDT 24 23100925 ps
T1070 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.958798104 Jul 25 04:43:06 PM PDT 24 Jul 25 04:43:10 PM PDT 24 311526956 ps
T1071 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2068511541 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:08 PM PDT 24 182668430 ps
T1072 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3938739367 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:05 PM PDT 24 62285989 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.422762288 Jul 25 04:42:56 PM PDT 24 Jul 25 04:42:58 PM PDT 24 130894296 ps
T1074 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.896396532 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:17 PM PDT 24 206851469 ps
T1075 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.783810293 Jul 25 04:43:31 PM PDT 24 Jul 25 04:43:33 PM PDT 24 220344356 ps
T1076 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3819726536 Jul 25 04:43:08 PM PDT 24 Jul 25 04:43:12 PM PDT 24 128200816 ps
T1077 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.543338144 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:05 PM PDT 24 64050734 ps
T1078 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3869220549 Jul 25 04:43:09 PM PDT 24 Jul 25 04:43:14 PM PDT 24 113001374 ps
T1079 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1549936992 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:06 PM PDT 24 12789409 ps
T1080 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4031645667 Jul 25 04:43:46 PM PDT 24 Jul 25 04:43:47 PM PDT 24 25098691 ps
T1081 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1957175202 Jul 25 04:43:12 PM PDT 24 Jul 25 04:43:14 PM PDT 24 67428283 ps

Test location /workspace/coverage/default/35.keymgr_stress_all.1524399755
Short name T1
Test name
Test status
Simulation time 4461831041 ps
CPU time 42.74 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 215124 kb
Host smart-c352a885-1a2f-4f0e-8905-ededce7fa18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524399755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1524399755
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4284407113
Short name T52
Test name
Test status
Simulation time 1356679778 ps
CPU time 46.94 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 216036 kb
Host smart-681b2b03-333c-4174-b5b1-6ae8fd324264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284407113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4284407113
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.325958470
Short name T95
Test name
Test status
Simulation time 1274891211 ps
CPU time 13.28 seconds
Started Jul 25 04:46:00 PM PDT 24
Finished Jul 25 04:46:13 PM PDT 24
Peak memory 222260 kb
Host smart-c60a1770-03ec-4e59-adf4-1f8e7a590825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325958470 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.325958470
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1667135096
Short name T11
Test name
Test status
Simulation time 560640467 ps
CPU time 6.86 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 233328 kb
Host smart-2a4d6f13-30ee-4d73-b97d-0c2aa8ac843b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667135096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1667135096
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.107872978
Short name T23
Test name
Test status
Simulation time 289634370 ps
CPU time 4.85 seconds
Started Jul 25 04:45:08 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 214020 kb
Host smart-490ff4dd-b9e0-4938-b63d-ed7c79381b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107872978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.107872978
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3765979503
Short name T47
Test name
Test status
Simulation time 4384447335 ps
CPU time 43.44 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:47:02 PM PDT 24
Peak memory 221672 kb
Host smart-7da6d945-67cc-44d8-916c-941a7c0742d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765979503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3765979503
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.860539422
Short name T136
Test name
Test status
Simulation time 1037786877 ps
CPU time 51.87 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:51:12 PM PDT 24
Peak memory 215084 kb
Host smart-eca99b86-a586-4a1e-86d6-1bff5667f815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860539422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.860539422
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3509999586
Short name T111
Test name
Test status
Simulation time 650728284 ps
CPU time 6.64 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 222208 kb
Host smart-b6a77fb2-9afd-4985-b76a-db25d54be1af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509999586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3509999586
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.856194536
Short name T211
Test name
Test status
Simulation time 1784688340 ps
CPU time 44.03 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 216064 kb
Host smart-a6080076-603b-4c0c-adfb-fa6e27b25433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856194536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.856194536
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1659684215
Short name T8
Test name
Test status
Simulation time 72139288 ps
CPU time 3.25 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 210084 kb
Host smart-efd5cabc-5cfe-4d5b-b794-4b8284a1ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659684215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1659684215
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2989313550
Short name T138
Test name
Test status
Simulation time 402956921 ps
CPU time 20.53 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 215252 kb
Host smart-fec849fa-d263-4fa9-ba1d-eab763d8ad1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989313550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2989313550
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2943388949
Short name T305
Test name
Test status
Simulation time 7916416696 ps
CPU time 84.61 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 215576 kb
Host smart-8a0bf20e-9af9-4b36-b7a2-d885cc0f07d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943388949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2943388949
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3370266480
Short name T39
Test name
Test status
Simulation time 245719073 ps
CPU time 2.96 seconds
Started Jul 25 04:45:31 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 209952 kb
Host smart-af0137fa-e319-44c3-9e37-65aad9aed5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370266480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3370266480
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.810318981
Short name T48
Test name
Test status
Simulation time 202953169 ps
CPU time 12.22 seconds
Started Jul 25 04:45:32 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 222228 kb
Host smart-dbc67c08-c520-4d75-a817-1ce4ef34e255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810318981 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.810318981
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1437523211
Short name T360
Test name
Test status
Simulation time 281817150 ps
CPU time 7.05 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 214008 kb
Host smart-7285372a-eb10-4a6e-b449-736435e151d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437523211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1437523211
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.146051688
Short name T63
Test name
Test status
Simulation time 284765370 ps
CPU time 7.63 seconds
Started Jul 25 04:45:42 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 221372 kb
Host smart-864c66a6-220a-40f1-9eb0-4fda38bebd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146051688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.146051688
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1974580798
Short name T207
Test name
Test status
Simulation time 8936178189 ps
CPU time 80.83 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:46:56 PM PDT 24
Peak memory 216352 kb
Host smart-97d199b1-a564-4883-8529-8c14593e9448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974580798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1974580798
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3658911969
Short name T18
Test name
Test status
Simulation time 308079615 ps
CPU time 4.07 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 209532 kb
Host smart-3ad98a22-d4e1-4a5f-8cd8-1782baa068f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658911969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3658911969
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2486641246
Short name T144
Test name
Test status
Simulation time 205356494 ps
CPU time 4.02 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 214972 kb
Host smart-10dd8fde-3046-4a7c-b518-a009b30233ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486641246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2486641246
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2470568204
Short name T109
Test name
Test status
Simulation time 115875484 ps
CPU time 1.6 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 214012 kb
Host smart-20500cbf-d038-4b68-b284-45603e74269b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470568204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2470568204
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.155198690
Short name T38
Test name
Test status
Simulation time 84322518 ps
CPU time 3.87 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 215724 kb
Host smart-6ea18043-a281-43fb-81c5-ef68808792db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155198690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.155198690
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1765627753
Short name T827
Test name
Test status
Simulation time 706681850 ps
CPU time 38.59 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 214520 kb
Host smart-e7705b35-8625-4784-9eca-d67998211748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765627753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1765627753
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1139329112
Short name T100
Test name
Test status
Simulation time 11237777146 ps
CPU time 36.94 seconds
Started Jul 25 04:44:57 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 222372 kb
Host smart-046c9413-c88e-4f93-be81-a05884ab3609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139329112 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1139329112
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1471322646
Short name T36
Test name
Test status
Simulation time 276705062 ps
CPU time 4.79 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 217936 kb
Host smart-1c325077-10c8-4c89-8e77-492d5e1c8674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471322646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1471322646
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3936529822
Short name T335
Test name
Test status
Simulation time 303513971 ps
CPU time 4.59 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 215256 kb
Host smart-180b11d6-5063-4983-8815-6afad012bf4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936529822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3936529822
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1666280916
Short name T42
Test name
Test status
Simulation time 66571455 ps
CPU time 2.32 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 213988 kb
Host smart-774c9a23-e245-41a5-a325-86584f872803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666280916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1666280916
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2826354168
Short name T226
Test name
Test status
Simulation time 145611186 ps
CPU time 2.81 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208876 kb
Host smart-ad36feac-1297-43e4-b206-539e5dab64a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826354168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2826354168
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.243689893
Short name T29
Test name
Test status
Simulation time 71130049 ps
CPU time 1.69 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 214052 kb
Host smart-af98b0c8-471b-4e82-b366-38fe355e2689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243689893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.243689893
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3275792036
Short name T21
Test name
Test status
Simulation time 55313938 ps
CPU time 2.35 seconds
Started Jul 25 04:46:02 PM PDT 24
Finished Jul 25 04:46:04 PM PDT 24
Peak memory 215776 kb
Host smart-17a4db94-8b37-4b43-afce-ad69b79ba320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275792036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3275792036
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.4040800950
Short name T135
Test name
Test status
Simulation time 641022439 ps
CPU time 34.05 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 222092 kb
Host smart-86eca175-bd9d-4226-a60b-3298918a217c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040800950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4040800950
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3520589833
Short name T103
Test name
Test status
Simulation time 1034448132 ps
CPU time 29.13 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 215368 kb
Host smart-b1548836-326a-463c-ad54-ca6396fa81be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520589833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3520589833
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2581082205
Short name T90
Test name
Test status
Simulation time 79352007 ps
CPU time 3.64 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 209088 kb
Host smart-814aba70-cebd-4231-898b-515a33a3b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581082205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2581082205
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3113755226
Short name T16
Test name
Test status
Simulation time 112085028 ps
CPU time 3.81 seconds
Started Jul 25 04:46:05 PM PDT 24
Finished Jul 25 04:46:09 PM PDT 24
Peak memory 214076 kb
Host smart-24fe5ac5-2718-4580-94ff-fcd32312db32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113755226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3113755226
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3996589968
Short name T124
Test name
Test status
Simulation time 29699117 ps
CPU time 0.72 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:01 PM PDT 24
Peak memory 205772 kb
Host smart-2a7e6234-a8f7-4a74-976d-e3cc088afedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996589968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3996589968
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3597641514
Short name T214
Test name
Test status
Simulation time 37151920800 ps
CPU time 232.77 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 222256 kb
Host smart-adde56b9-d4b5-49c9-8090-db640b6897ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597641514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3597641514
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2949793592
Short name T156
Test name
Test status
Simulation time 544560962 ps
CPU time 9.01 seconds
Started Jul 25 04:43:02 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 205516 kb
Host smart-ad532af1-9bfd-440e-bea9-bd4354d1ae1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949793592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2949793592
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3414748364
Short name T70
Test name
Test status
Simulation time 19988556464 ps
CPU time 416.55 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:52:00 PM PDT 24
Peak memory 222352 kb
Host smart-6dd804c5-41ba-4257-b1c6-1280acb48dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414748364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3414748364
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3446486712
Short name T245
Test name
Test status
Simulation time 319980697 ps
CPU time 5.54 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 215124 kb
Host smart-0df1f20f-786d-4eb8-b142-2132f944595a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446486712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3446486712
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2450532223
Short name T221
Test name
Test status
Simulation time 10315278777 ps
CPU time 294.61 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 222256 kb
Host smart-91828f75-d7d5-4ad2-b9f3-240cc178a4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450532223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2450532223
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1272933260
Short name T398
Test name
Test status
Simulation time 2634673658 ps
CPU time 69.77 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 214648 kb
Host smart-1f284456-02a9-4023-be6f-c352b739bdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272933260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1272933260
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2612913253
Short name T60
Test name
Test status
Simulation time 5285714465 ps
CPU time 53.11 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 222044 kb
Host smart-8a2f0a04-d647-4036-83f3-5b4247d14b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612913253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2612913253
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3427777496
Short name T65
Test name
Test status
Simulation time 1220704378 ps
CPU time 10.83 seconds
Started Jul 25 04:45:55 PM PDT 24
Finished Jul 25 04:46:06 PM PDT 24
Peak memory 207340 kb
Host smart-86350165-aaab-4d25-8449-cedd46ddfabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427777496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3427777496
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.191142363
Short name T97
Test name
Test status
Simulation time 466844431 ps
CPU time 3.3 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 222084 kb
Host smart-f4a43557-9222-4bbe-900c-c01b5be6fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191142363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.191142363
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3057798708
Short name T163
Test name
Test status
Simulation time 314021322 ps
CPU time 10.66 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:15 PM PDT 24
Peak memory 213808 kb
Host smart-43eef925-8c62-44be-8581-c6242c6ef532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057798708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3057798708
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.586500743
Short name T319
Test name
Test status
Simulation time 131110232 ps
CPU time 3.83 seconds
Started Jul 25 04:46:08 PM PDT 24
Finished Jul 25 04:46:12 PM PDT 24
Peak memory 214200 kb
Host smart-fd32d99a-1dc5-448b-b386-1bf593097525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586500743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.586500743
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3033694249
Short name T150
Test name
Test status
Simulation time 76663537 ps
CPU time 3.86 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 222448 kb
Host smart-1859092b-ae92-419e-9e0f-ee1556c9a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033694249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3033694249
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.581427297
Short name T149
Test name
Test status
Simulation time 159814997 ps
CPU time 4.53 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 216988 kb
Host smart-8c79772f-5ee2-4a54-8ee4-722288a8c38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581427297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.581427297
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.212432848
Short name T289
Test name
Test status
Simulation time 171656969 ps
CPU time 9.21 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 214664 kb
Host smart-1f016ddd-22c8-4ddc-9c2c-2f430cf2c7c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212432848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.212432848
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.240569885
Short name T166
Test name
Test status
Simulation time 1139061529 ps
CPU time 9.32 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:16 PM PDT 24
Peak memory 213780 kb
Host smart-3dc0f4f1-e664-46b7-8e32-ba83fd1945d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240569885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.240569885
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4175467688
Short name T391
Test name
Test status
Simulation time 155741099 ps
CPU time 2.4 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 210136 kb
Host smart-99a91aad-908e-4587-9249-c9c079c9ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175467688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4175467688
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3277495118
Short name T973
Test name
Test status
Simulation time 254422050 ps
CPU time 3.82 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 214008 kb
Host smart-8fde20e5-92ee-4c85-aae9-05bd93b59bc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277495118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3277495118
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1616298436
Short name T178
Test name
Test status
Simulation time 461470398 ps
CPU time 21.12 seconds
Started Jul 25 04:46:01 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 222244 kb
Host smart-0430d912-4c83-4a70-8c78-25bc3b8b0d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616298436 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1616298436
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1781619916
Short name T96
Test name
Test status
Simulation time 31044447 ps
CPU time 2.07 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 213972 kb
Host smart-7ab02dc8-5a8e-4ee6-afea-1134712354f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781619916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1781619916
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.673977129
Short name T301
Test name
Test status
Simulation time 118494201 ps
CPU time 6.3 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 215056 kb
Host smart-37ff8237-f61a-4daf-8513-874df4ebf6a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673977129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.673977129
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1779672481
Short name T162
Test name
Test status
Simulation time 695213509 ps
CPU time 4.28 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 213732 kb
Host smart-a3285e6c-d434-4200-96ba-7d8c32787094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779672481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1779672481
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1862447718
Short name T167
Test name
Test status
Simulation time 143456719 ps
CPU time 5.15 seconds
Started Jul 25 04:43:02 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 214816 kb
Host smart-19f093fa-da76-42bc-832e-c16278424a05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862447718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1862447718
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.768933044
Short name T165
Test name
Test status
Simulation time 586419621 ps
CPU time 4.71 seconds
Started Jul 25 04:43:20 PM PDT 24
Finished Jul 25 04:43:25 PM PDT 24
Peak memory 213992 kb
Host smart-c4ee9bac-8c09-4e3c-9f9a-d549a3fad46f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768933044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
768933044
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3677154035
Short name T146
Test name
Test status
Simulation time 306962104 ps
CPU time 3.97 seconds
Started Jul 25 04:44:39 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 218008 kb
Host smart-528d65e3-8444-4f98-9f4a-cf0725df607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677154035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3677154035
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3630831931
Short name T312
Test name
Test status
Simulation time 745926076 ps
CPU time 4.19 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 222164 kb
Host smart-857be4eb-c5c8-4227-b1ec-b5c9a8121c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630831931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3630831931
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2527183570
Short name T610
Test name
Test status
Simulation time 93847904 ps
CPU time 3.7 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 214064 kb
Host smart-4790a86b-842b-462d-b558-7b400a59a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527183570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2527183570
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.130048007
Short name T340
Test name
Test status
Simulation time 71567392 ps
CPU time 2.62 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 214140 kb
Host smart-73559f8a-75c2-4028-a428-dd8dcc6fb3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130048007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.130048007
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1599146073
Short name T159
Test name
Test status
Simulation time 218767482 ps
CPU time 2.69 seconds
Started Jul 25 04:44:34 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 210576 kb
Host smart-e3faab48-b41e-40ff-941d-7fdc53983d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599146073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1599146073
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3652041806
Short name T148
Test name
Test status
Simulation time 82281405 ps
CPU time 1.84 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 217336 kb
Host smart-71774bfc-d679-4d1f-a6d9-2ef18da7bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652041806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3652041806
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3988286802
Short name T147
Test name
Test status
Simulation time 121755381 ps
CPU time 5.23 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 218104 kb
Host smart-3a6bd602-a807-4e8c-a9cd-d8a4ca7923ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988286802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3988286802
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2508217122
Short name T152
Test name
Test status
Simulation time 452800064 ps
CPU time 3.25 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 222324 kb
Host smart-f5fe4ed1-57fd-4c82-8e79-040ef06288fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508217122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2508217122
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1371977663
Short name T151
Test name
Test status
Simulation time 143787231 ps
CPU time 2.88 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 222284 kb
Host smart-61da303a-ecb4-4438-a74f-074200b4e6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371977663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1371977663
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3603760720
Short name T338
Test name
Test status
Simulation time 204816673 ps
CPU time 4.61 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 205776 kb
Host smart-8adb4980-0f8e-4493-92b4-685c241c491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603760720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3603760720
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1860085037
Short name T350
Test name
Test status
Simulation time 329473311 ps
CPU time 2.33 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 214056 kb
Host smart-95645866-ccf4-4507-b5ae-effc84e368aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860085037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1860085037
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3382212649
Short name T271
Test name
Test status
Simulation time 9404993943 ps
CPU time 193.36 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 217780 kb
Host smart-79d829df-ed83-4a5f-a6ba-57dbac206c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382212649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3382212649
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3541760473
Short name T12
Test name
Test status
Simulation time 120577872 ps
CPU time 4.01 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 206544 kb
Host smart-6bc1dc31-a3dd-4842-bfe5-d52ed399be9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541760473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3541760473
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_random.2195359027
Short name T130
Test name
Test status
Simulation time 203603665 ps
CPU time 6.17 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 218020 kb
Host smart-2622cdaf-3c64-4e0e-b911-d080787c6f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195359027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2195359027
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.233950615
Short name T363
Test name
Test status
Simulation time 4983248449 ps
CPU time 69.12 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 215080 kb
Host smart-8c6db7c4-c86d-4532-a03c-da322065c7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233950615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.233950615
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1945013314
Short name T158
Test name
Test status
Simulation time 234546846 ps
CPU time 5.8 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 213992 kb
Host smart-34512086-a62b-40e1-9c78-296c841858d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945013314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1945013314
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2763958436
Short name T157
Test name
Test status
Simulation time 424220282 ps
CPU time 4.34 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 214920 kb
Host smart-41c3fd6b-3a6d-4a65-a9b1-e1a6930e6120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763958436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2763958436
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.906773483
Short name T154
Test name
Test status
Simulation time 293844582 ps
CPU time 6.78 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 213760 kb
Host smart-63fcef4c-f455-4780-9d3d-f7b64b6fd55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906773483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
906773483
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1912422018
Short name T46
Test name
Test status
Simulation time 1633464112 ps
CPU time 40.58 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:42 PM PDT 24
Peak memory 231048 kb
Host smart-89a734f0-98ff-4c5d-b67f-e1148ac0e01e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912422018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1912422018
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1314277814
Short name T55
Test name
Test status
Simulation time 337664707 ps
CPU time 3.1 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 222440 kb
Host smart-c5d9b7d7-7e2c-4b3c-beed-bb80bc2e83d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314277814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1314277814
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2021488587
Short name T797
Test name
Test status
Simulation time 188260407 ps
CPU time 4.77 seconds
Started Jul 25 04:44:05 PM PDT 24
Finished Jul 25 04:44:09 PM PDT 24
Peak memory 208788 kb
Host smart-c3c04357-1862-4562-8b6f-14f00160d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021488587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2021488587
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2291755732
Short name T611
Test name
Test status
Simulation time 943855965 ps
CPU time 24.74 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 222240 kb
Host smart-448145b0-a510-4542-85f9-50b4104986de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291755732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2291755732
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3313838924
Short name T164
Test name
Test status
Simulation time 90110181 ps
CPU time 2.02 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 209608 kb
Host smart-268cdc98-5e0e-4ab8-9111-80b9e9db80e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313838924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3313838924
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2113673097
Short name T223
Test name
Test status
Simulation time 3320507041 ps
CPU time 7.67 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 209488 kb
Host smart-43b3e3ae-20dc-455c-b616-1690c3b1236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113673097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2113673097
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1727241391
Short name T225
Test name
Test status
Simulation time 1037556380 ps
CPU time 7.79 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 222180 kb
Host smart-56456bff-6ed5-4cf6-a59d-7319fc8e0f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727241391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1727241391
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sideload.992654947
Short name T196
Test name
Test status
Simulation time 186015157 ps
CPU time 2.62 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 206776 kb
Host smart-46290adb-1644-4c62-9efb-2bbff5192f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992654947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.992654947
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3231200445
Short name T310
Test name
Test status
Simulation time 49814323 ps
CPU time 2.69 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 208504 kb
Host smart-92c3b7b5-2367-41dd-8109-7bd40585c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231200445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3231200445
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3533654763
Short name T873
Test name
Test status
Simulation time 478246600 ps
CPU time 23.38 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 220736 kb
Host smart-b2b43f11-c432-4772-9ced-db480a3918c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533654763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3533654763
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.679310489
Short name T316
Test name
Test status
Simulation time 192755775 ps
CPU time 2.88 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 214056 kb
Host smart-e088af96-3e52-4b44-ab59-3eb89f149e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679310489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.679310489
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.489909883
Short name T341
Test name
Test status
Simulation time 16287177714 ps
CPU time 56.13 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 214168 kb
Host smart-75408e7b-5f9f-432f-882e-e225c494689f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489909883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.489909883
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1108843332
Short name T83
Test name
Test status
Simulation time 338584909 ps
CPU time 2.99 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 214036 kb
Host smart-6d68cdf3-1a70-4e60-b539-f4d10e946543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108843332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1108843332
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1512208926
Short name T229
Test name
Test status
Simulation time 109091374 ps
CPU time 2.63 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 214820 kb
Host smart-fb38cf34-e7e0-4a11-8b7b-939ee6e21775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512208926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1512208926
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.90756063
Short name T6
Test name
Test status
Simulation time 120856758 ps
CPU time 5.13 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 220016 kb
Host smart-0945701a-5236-4838-9300-833093f122c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90756063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.90756063
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2849218307
Short name T368
Test name
Test status
Simulation time 335382500 ps
CPU time 3.76 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 214044 kb
Host smart-08eb5a57-b932-4f7b-b0f1-5c5280faf824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849218307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2849218307
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3960666339
Short name T283
Test name
Test status
Simulation time 15819145857 ps
CPU time 107 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 218892 kb
Host smart-a546aba3-80d9-4931-b7de-b053775e8704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960666339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3960666339
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1397720941
Short name T78
Test name
Test status
Simulation time 220288078 ps
CPU time 4.7 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 215680 kb
Host smart-4e80fce9-2d72-45ed-af2b-672a104012c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397720941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1397720941
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2610251827
Short name T118
Test name
Test status
Simulation time 302625978 ps
CPU time 11.46 seconds
Started Jul 25 04:45:42 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 220448 kb
Host smart-f0624208-3c7d-488a-b343-842084601fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610251827 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2610251827
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.565753030
Short name T297
Test name
Test status
Simulation time 236621885 ps
CPU time 3.92 seconds
Started Jul 25 04:44:06 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 215584 kb
Host smart-e06cbbb2-4d4f-43cc-8ff1-eb697e941315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565753030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.565753030
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2284966063
Short name T84
Test name
Test status
Simulation time 494099563 ps
CPU time 4.2 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:42 PM PDT 24
Peak memory 214100 kb
Host smart-ea3ae94b-769d-406f-9226-a72f9210e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284966063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2284966063
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3362294416
Short name T295
Test name
Test status
Simulation time 399903960 ps
CPU time 18.86 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:46:09 PM PDT 24
Peak memory 215248 kb
Host smart-488c1ab3-3e33-4ae0-b11a-39a37eaf9421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362294416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3362294416
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2924628121
Short name T299
Test name
Test status
Simulation time 3027060830 ps
CPU time 42.51 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 214212 kb
Host smart-eae27346-b376-4e07-be07-5eb4347dac0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924628121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2924628121
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2562904254
Short name T972
Test name
Test status
Simulation time 299389592 ps
CPU time 4.08 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:42:59 PM PDT 24
Peak memory 205532 kb
Host smart-7aee1067-bafa-401c-aa7c-a825e78f8d1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562904254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
562904254
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3846350762
Short name T153
Test name
Test status
Simulation time 10687736961 ps
CPU time 14.95 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:21 PM PDT 24
Peak memory 205636 kb
Host smart-47a12dfd-8333-4496-950b-9ba70a0cc16b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846350762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
846350762
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2150756252
Short name T967
Test name
Test status
Simulation time 40643813 ps
CPU time 1.27 seconds
Started Jul 25 04:42:51 PM PDT 24
Finished Jul 25 04:42:53 PM PDT 24
Peak memory 205592 kb
Host smart-8f386cbf-1c6e-4b68-aa49-96ba17765977
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150756252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
150756252
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2203985746
Short name T1018
Test name
Test status
Simulation time 15459380 ps
CPU time 1.27 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 213772 kb
Host smart-a719106c-e683-47b4-b587-2a059d161cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203985746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2203985746
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1366787188
Short name T961
Test name
Test status
Simulation time 59263217 ps
CPU time 1.18 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 205632 kb
Host smart-23dee4cd-b17d-446e-b927-2bdc72f8fa67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366787188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1366787188
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.44726188
Short name T1055
Test name
Test status
Simulation time 32122350 ps
CPU time 0.75 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:42:56 PM PDT 24
Peak memory 205276 kb
Host smart-980f7308-865d-4ad4-80a2-b7897ff60029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44726188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.44726188
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1113094085
Short name T1058
Test name
Test status
Simulation time 69988066 ps
CPU time 1.97 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 205608 kb
Host smart-2a7e6e01-3244-4a7c-9e69-f2c5a3cfbacc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113094085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1113094085
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.290017133
Short name T1051
Test name
Test status
Simulation time 97649810 ps
CPU time 2.08 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 213892 kb
Host smart-9ac43d5b-60be-4fd3-9f67-b12bfc634c0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290017133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.290017133
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2024641710
Short name T1017
Test name
Test status
Simulation time 3057084220 ps
CPU time 6.61 seconds
Started Jul 25 04:42:58 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 220424 kb
Host smart-da5401a4-24e7-46fa-b5f4-667f83b93d18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024641710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2024641710
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.543338144
Short name T1077
Test name
Test status
Simulation time 64050734 ps
CPU time 1.75 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 213716 kb
Host smart-e69e2ac5-69ba-418b-ba0b-06c35315fc6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543338144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.543338144
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2196949747
Short name T980
Test name
Test status
Simulation time 476837362 ps
CPU time 4.11 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 213864 kb
Host smart-994b4dfb-c98e-410a-ac13-09e0e76b0df3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196949747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2196949747
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2009593707
Short name T1004
Test name
Test status
Simulation time 737592596 ps
CPU time 6.92 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 205620 kb
Host smart-c3ccaec7-cf55-4786-89b7-589335c1da6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009593707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
009593707
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3593143676
Short name T993
Test name
Test status
Simulation time 3456601507 ps
CPU time 23.85 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 205656 kb
Host smart-41a137e6-90e8-4957-956b-7e8236600cb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593143676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
593143676
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2093321584
Short name T952
Test name
Test status
Simulation time 38742364 ps
CPU time 0.94 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 205408 kb
Host smart-8256bba6-17cc-4865-bd30-43e46d3f78aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093321584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
093321584
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.429650480
Short name T929
Test name
Test status
Simulation time 65630552 ps
CPU time 1.27 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 213876 kb
Host smart-ddea2a66-8f2c-46ca-90d5-6f8753708f7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429650480 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.429650480
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3171167829
Short name T998
Test name
Test status
Simulation time 23129313 ps
CPU time 1.13 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205464 kb
Host smart-f1b45cf3-266b-4946-85ea-505c9254a3b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171167829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3171167829
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4096342570
Short name T948
Test name
Test status
Simulation time 38836642 ps
CPU time 0.76 seconds
Started Jul 25 04:42:56 PM PDT 24
Finished Jul 25 04:42:57 PM PDT 24
Peak memory 205360 kb
Host smart-583b06b5-60f8-4aba-bf85-c4f6437c22c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096342570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4096342570
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2068511541
Short name T1071
Test name
Test status
Simulation time 182668430 ps
CPU time 2.41 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205624 kb
Host smart-48ce4010-38cc-4cae-ac8b-cf69f056028d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068511541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2068511541
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1058388909
Short name T1034
Test name
Test status
Simulation time 717505698 ps
CPU time 5.25 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 214032 kb
Host smart-94907711-9ddf-4928-9de8-754cd237d77f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058388909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1058388909
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3083807047
Short name T927
Test name
Test status
Simulation time 227405631 ps
CPU time 2.98 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 215808 kb
Host smart-bc33d94a-db6c-4891-a769-c83751aab6e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083807047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3083807047
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1857524615
Short name T171
Test name
Test status
Simulation time 758252160 ps
CPU time 4.55 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 213748 kb
Host smart-3ee20079-70da-4aa4-806d-6395061184ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857524615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1857524615
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2991858402
Short name T982
Test name
Test status
Simulation time 80411608 ps
CPU time 1.34 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205532 kb
Host smart-f9f1de71-dcb3-4517-ba03-528c4ed4a8a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991858402 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2991858402
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4116767575
Short name T1057
Test name
Test status
Simulation time 76486599 ps
CPU time 1.05 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205580 kb
Host smart-039ab55a-3052-4a08-89d2-5ef7b10232b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116767575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4116767575
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1474231337
Short name T1020
Test name
Test status
Simulation time 51718377 ps
CPU time 0.69 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205368 kb
Host smart-dc029ac7-75df-4453-8e1e-783c9de2bb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474231337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1474231337
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2200526081
Short name T1054
Test name
Test status
Simulation time 170777905 ps
CPU time 2.34 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205516 kb
Host smart-b97dcb85-9422-4291-b130-53073b3c1a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200526081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2200526081
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3579082543
Short name T985
Test name
Test status
Simulation time 161575251 ps
CPU time 1.85 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 214104 kb
Host smart-36ef51a5-ae56-46a3-8744-f1928c97b347
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579082543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3579082543
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2618466395
Short name T1006
Test name
Test status
Simulation time 1234749837 ps
CPU time 8.23 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:18 PM PDT 24
Peak memory 222232 kb
Host smart-c7327545-c589-4c53-b872-3d1b69379cd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618466395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2618466395
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.106300715
Short name T1048
Test name
Test status
Simulation time 61640558 ps
CPU time 2.01 seconds
Started Jul 25 04:43:17 PM PDT 24
Finished Jul 25 04:43:19 PM PDT 24
Peak memory 221928 kb
Host smart-11981271-c29b-4790-81f1-17ec19fd8f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106300715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.106300715
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.969175481
Short name T939
Test name
Test status
Simulation time 286326753 ps
CPU time 5.68 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 213784 kb
Host smart-1df631e4-2df9-4fce-8dd6-8d43cfad2848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969175481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.969175481
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.904146343
Short name T1061
Test name
Test status
Simulation time 247872411 ps
CPU time 2.12 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 213868 kb
Host smart-c66f3201-ed49-42c3-9049-9fa21e6d5eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904146343 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.904146343
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3052265398
Short name T995
Test name
Test status
Simulation time 109672073 ps
CPU time 1.17 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:42:59 PM PDT 24
Peak memory 205632 kb
Host smart-3e45c08c-7884-4882-927f-57f4efd33c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052265398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3052265398
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3769258427
Short name T918
Test name
Test status
Simulation time 91340461 ps
CPU time 0.85 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205424 kb
Host smart-3ce77779-2269-4862-9d86-653e92cc1f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769258427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3769258427
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2054309492
Short name T1029
Test name
Test status
Simulation time 65810058 ps
CPU time 1.81 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 205512 kb
Host smart-e06957f8-d170-46be-b6df-94d137c01d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054309492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2054309492
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3727919883
Short name T958
Test name
Test status
Simulation time 349303364 ps
CPU time 3.65 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 214052 kb
Host smart-79c7fd8c-dc02-42de-85f2-e266287f37ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727919883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3727919883
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.896396532
Short name T1074
Test name
Test status
Simulation time 206851469 ps
CPU time 7.6 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 220264 kb
Host smart-869a5b16-431c-422d-a1cf-52aaf1fe6948
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896396532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.896396532
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1091340275
Short name T1023
Test name
Test status
Simulation time 40288258 ps
CPU time 2.53 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 215988 kb
Host smart-b9741b5e-8527-4dfd-823f-b02bcc973a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091340275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1091340275
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2244922411
Short name T173
Test name
Test status
Simulation time 349591081 ps
CPU time 4.23 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 213716 kb
Host smart-c5930b71-28b8-4a27-92e2-7f8afb2f2bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244922411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2244922411
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1565170911
Short name T915
Test name
Test status
Simulation time 88621952 ps
CPU time 1.39 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205660 kb
Host smart-614331b9-6484-410d-8499-0599b3e44c15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565170911 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1565170911
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.194972916
Short name T141
Test name
Test status
Simulation time 192659938 ps
CPU time 1.44 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:16 PM PDT 24
Peak memory 205584 kb
Host smart-c6098287-287b-4450-8eed-13381f57c065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194972916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.194972916
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2160058123
Short name T932
Test name
Test status
Simulation time 38795347 ps
CPU time 0.69 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 205368 kb
Host smart-bf9d1361-dc3d-42c0-87f1-5240790aac67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160058123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2160058123
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.882428845
Short name T1066
Test name
Test status
Simulation time 21770304 ps
CPU time 1.61 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 205588 kb
Host smart-4f154d1e-3d68-4237-85ec-36f7040df4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882428845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.882428845
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1821674373
Short name T1011
Test name
Test status
Simulation time 131259700 ps
CPU time 2.05 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 213524 kb
Host smart-7c7743a9-700a-47bf-b4a1-6bf959b9beea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821674373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1821674373
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.950407338
Short name T1063
Test name
Test status
Simulation time 77388159 ps
CPU time 3.58 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 214052 kb
Host smart-7e9c73aa-8278-4a32-8523-075a4516fcc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950407338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.950407338
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1164360723
Short name T986
Test name
Test status
Simulation time 188005693 ps
CPU time 3.2 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 216372 kb
Host smart-40d73887-8b08-4793-a90b-c0b6ba670f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164360723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1164360723
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2084415777
Short name T1040
Test name
Test status
Simulation time 426034583 ps
CPU time 5.15 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 206004 kb
Host smart-a73dea8b-efca-4429-a232-29bf85388766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084415777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2084415777
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4270479254
Short name T1016
Test name
Test status
Simulation time 55291269 ps
CPU time 1.16 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 205596 kb
Host smart-5210dd14-ce63-4225-86ea-032b7478dc5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270479254 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4270479254
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.769795100
Short name T1038
Test name
Test status
Simulation time 47288579 ps
CPU time 1.07 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 205628 kb
Host smart-f9444855-48fb-48cf-b40c-e63db742eef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769795100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.769795100
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3701961683
Short name T1022
Test name
Test status
Simulation time 22566717 ps
CPU time 0.77 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205392 kb
Host smart-b3ce76bf-bdab-4ff1-9e76-b69802571034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701961683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3701961683
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2647082435
Short name T1031
Test name
Test status
Simulation time 173280790 ps
CPU time 2.41 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205524 kb
Host smart-b2fda110-b3ba-4f01-84a7-070ac96133b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647082435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2647082435
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.288457938
Short name T1033
Test name
Test status
Simulation time 150925645 ps
CPU time 1.83 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 214144 kb
Host smart-62667828-b0e3-47d4-9f7e-917d729c2312
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288457938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.288457938
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3875962873
Short name T949
Test name
Test status
Simulation time 81166644 ps
CPU time 2.62 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 213748 kb
Host smart-96f7f142-596a-44aa-a699-c3957bf943f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875962873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3875962873
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.348930740
Short name T170
Test name
Test status
Simulation time 101531878 ps
CPU time 3 seconds
Started Jul 25 04:43:27 PM PDT 24
Finished Jul 25 04:43:30 PM PDT 24
Peak memory 213840 kb
Host smart-55da9556-5282-4e6c-b13c-2e613b470a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348930740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.348930740
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.595207280
Short name T925
Test name
Test status
Simulation time 156647239 ps
CPU time 1.46 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 213856 kb
Host smart-fcd852d2-65e3-4593-a00f-bd43ee89c132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595207280 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.595207280
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3888686677
Short name T1037
Test name
Test status
Simulation time 23313118 ps
CPU time 1.4 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205616 kb
Host smart-a8b63d41-b938-451e-a8d8-57b0ea32df12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888686677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3888686677
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3482273805
Short name T930
Test name
Test status
Simulation time 10213564 ps
CPU time 0.77 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205292 kb
Host smart-0e2e0673-f3de-422f-8b83-8eeba793c7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482273805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3482273805
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3128215024
Short name T1062
Test name
Test status
Simulation time 54742179 ps
CPU time 1.71 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 205500 kb
Host smart-bc577634-cd5c-463b-bf69-f2b2dcc7a0bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128215024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3128215024
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.523647677
Short name T936
Test name
Test status
Simulation time 87399452 ps
CPU time 2.76 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 214044 kb
Host smart-a6d53f25-b791-4d0b-af12-30d7da398f28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523647677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.523647677
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2429366214
Short name T1035
Test name
Test status
Simulation time 1347996080 ps
CPU time 8.43 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 214036 kb
Host smart-20348e6c-81f2-46fa-ae1c-7fe26601ccf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429366214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2429366214
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2170238589
Short name T184
Test name
Test status
Simulation time 248031378 ps
CPU time 1.73 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 213776 kb
Host smart-8be18100-ea61-4201-9132-617f8cdb9c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170238589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2170238589
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3869220549
Short name T1078
Test name
Test status
Simulation time 113001374 ps
CPU time 4.58 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 213676 kb
Host smart-29cc60e0-7b4a-47e0-856f-f7f45a228d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869220549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3869220549
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.314874966
Short name T935
Test name
Test status
Simulation time 343780147 ps
CPU time 1.12 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205612 kb
Host smart-4bd4bdb9-bb2b-4618-a765-8d393c7a11c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314874966 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.314874966
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1514810357
Short name T1041
Test name
Test status
Simulation time 45018355 ps
CPU time 0.86 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205364 kb
Host smart-f8e74582-9565-4bfd-94b9-448dd276e13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514810357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1514810357
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4277970522
Short name T1049
Test name
Test status
Simulation time 43683000 ps
CPU time 0.82 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205372 kb
Host smart-1e9752f7-e582-48a9-9d89-565bcfc1724e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277970522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4277970522
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1001775211
Short name T1028
Test name
Test status
Simulation time 159962409 ps
CPU time 1.84 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205488 kb
Host smart-3c99f30d-ab61-4eb8-8da1-0ba186fa29ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001775211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1001775211
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.780977433
Short name T114
Test name
Test status
Simulation time 925191338 ps
CPU time 5.25 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 214040 kb
Host smart-5a1d805b-3281-45b1-90fe-50be05849c8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780977433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.780977433
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3474029069
Short name T920
Test name
Test status
Simulation time 55142222 ps
CPU time 2.34 seconds
Started Jul 25 04:43:32 PM PDT 24
Finished Jul 25 04:43:35 PM PDT 24
Peak memory 213732 kb
Host smart-d264fa9b-bc46-49b7-8069-6e50f9a37693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474029069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3474029069
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3317834266
Short name T1068
Test name
Test status
Simulation time 73384992 ps
CPU time 1.74 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:16 PM PDT 24
Peak memory 213924 kb
Host smart-056c4fda-ea35-43da-ba93-34d8d211ae1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317834266 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3317834266
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.252767978
Short name T999
Test name
Test status
Simulation time 60234276 ps
CPU time 1.36 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 205620 kb
Host smart-bd32bd46-c6f3-4fe2-b77e-1833e730d33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252767978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.252767978
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1697437083
Short name T990
Test name
Test status
Simulation time 9810018 ps
CPU time 0.69 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:15 PM PDT 24
Peak memory 205292 kb
Host smart-66933778-3b95-47af-bcca-01e79982ac62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697437083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1697437083
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1090648958
Short name T979
Test name
Test status
Simulation time 28257398 ps
CPU time 1.7 seconds
Started Jul 25 04:43:46 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 205520 kb
Host smart-21997759-1fe8-42f0-bd94-e4252ae06a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090648958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1090648958
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.422762288
Short name T1073
Test name
Test status
Simulation time 130894296 ps
CPU time 1.74 seconds
Started Jul 25 04:42:56 PM PDT 24
Finished Jul 25 04:42:58 PM PDT 24
Peak memory 213956 kb
Host smart-61282685-68b0-40c1-857d-a87c625bb573
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422762288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.422762288
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1503458760
Short name T1015
Test name
Test status
Simulation time 98981719 ps
CPU time 4.67 seconds
Started Jul 25 04:43:34 PM PDT 24
Finished Jul 25 04:43:39 PM PDT 24
Peak memory 219936 kb
Host smart-7f02340b-a136-4e53-a246-abd237feca93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503458760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1503458760
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4139878841
Short name T1024
Test name
Test status
Simulation time 44132881 ps
CPU time 2.89 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 213812 kb
Host smart-a04561e5-f804-4f25-bd44-85a1a016f9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139878841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4139878841
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4036713207
Short name T938
Test name
Test status
Simulation time 77447162 ps
CPU time 2.27 seconds
Started Jul 25 04:43:10 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 213876 kb
Host smart-e18dc1b1-021f-46be-93ff-155a0e7380dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036713207 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4036713207
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2072277514
Short name T1013
Test name
Test status
Simulation time 190628371 ps
CPU time 1.5 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205568 kb
Host smart-01674b94-888b-410d-acd7-abf6cb4e5e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072277514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2072277514
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4031645667
Short name T1080
Test name
Test status
Simulation time 25098691 ps
CPU time 0.75 seconds
Started Jul 25 04:43:46 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 205372 kb
Host smart-4fad3e15-f010-4135-9393-7a5a7383696e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031645667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4031645667
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1231046682
Short name T921
Test name
Test status
Simulation time 163219793 ps
CPU time 3.36 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205600 kb
Host smart-405819ae-fc18-4dc1-81d4-201d199fedad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231046682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1231046682
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.49421721
Short name T992
Test name
Test status
Simulation time 150496812 ps
CPU time 4.72 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 214016 kb
Host smart-b8446d78-7fa0-43f4-8aa5-36e3d6a5b154
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49421721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow
_reg_errors.49421721
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.731304226
Short name T117
Test name
Test status
Simulation time 345915309 ps
CPU time 4.07 seconds
Started Jul 25 04:43:15 PM PDT 24
Finished Jul 25 04:43:19 PM PDT 24
Peak memory 214048 kb
Host smart-1f22d032-72c1-4164-b21b-9cfcdd8ea15b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731304226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.731304226
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1731137834
Short name T994
Test name
Test status
Simulation time 46975716 ps
CPU time 2.68 seconds
Started Jul 25 04:43:29 PM PDT 24
Finished Jul 25 04:43:37 PM PDT 24
Peak memory 213712 kb
Host smart-d659bf67-833f-49eb-81c3-8ef6550768a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731137834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1731137834
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3958566478
Short name T1000
Test name
Test status
Simulation time 47409852 ps
CPU time 1.59 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 213944 kb
Host smart-d8ff4340-ae1c-4dd1-9491-b7f5a49cdd25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958566478 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3958566478
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2880850097
Short name T940
Test name
Test status
Simulation time 13029499 ps
CPU time 0.85 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 205440 kb
Host smart-1756e60d-6046-4539-882e-c3e5a2a49450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880850097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2880850097
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2702433119
Short name T937
Test name
Test status
Simulation time 13427431 ps
CPU time 0.75 seconds
Started Jul 25 04:43:16 PM PDT 24
Finished Jul 25 04:43:22 PM PDT 24
Peak memory 205316 kb
Host smart-7d3b6e52-f63d-471a-af56-c9f6a4ce05ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702433119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2702433119
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.140874996
Short name T142
Test name
Test status
Simulation time 84236603 ps
CPU time 2.05 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 205632 kb
Host smart-2379602e-a79c-480d-bc86-099444d506bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140874996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.140874996
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2355710289
Short name T1042
Test name
Test status
Simulation time 273666102 ps
CPU time 3.37 seconds
Started Jul 25 04:43:29 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 214032 kb
Host smart-2e08dab3-0b5f-4393-889a-12d444d6f673
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355710289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2355710289
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.517929837
Short name T116
Test name
Test status
Simulation time 508585336 ps
CPU time 15.27 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:20 PM PDT 24
Peak memory 220184 kb
Host smart-2b0d25e8-cae0-4790-b579-008dade979aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517929837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.517929837
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1171740806
Short name T931
Test name
Test status
Simulation time 268186662 ps
CPU time 2.72 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 216848 kb
Host smart-1a94e070-8d11-41ca-a8cb-bacfce02b82d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171740806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1171740806
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.479365369
Short name T975
Test name
Test status
Simulation time 30857576 ps
CPU time 1.9 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 213820 kb
Host smart-abca5078-6fb3-403d-ab66-5dfd69dff769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479365369 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.479365369
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.118281836
Short name T1007
Test name
Test status
Simulation time 75222454 ps
CPU time 1.15 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 205512 kb
Host smart-bec03c64-3c21-4eb6-b309-5649d8ea18e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118281836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.118281836
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2101105017
Short name T1010
Test name
Test status
Simulation time 25941857 ps
CPU time 0.77 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205332 kb
Host smart-becf7016-ba7f-4a01-b76a-a8980f66d927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101105017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2101105017
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2107160082
Short name T991
Test name
Test status
Simulation time 154272018 ps
CPU time 2.1 seconds
Started Jul 25 04:43:26 PM PDT 24
Finished Jul 25 04:43:28 PM PDT 24
Peak memory 205652 kb
Host smart-cd5a4e0e-5bd2-4d1b-9227-e540bf6a4033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107160082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2107160082
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3956401699
Short name T1064
Test name
Test status
Simulation time 99370707 ps
CPU time 2.52 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 214016 kb
Host smart-cdf95c16-073a-4fb0-af09-58220e49badd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956401699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3956401699
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.505419390
Short name T1026
Test name
Test status
Simulation time 140969719 ps
CPU time 4.15 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 219856 kb
Host smart-dbb64f9b-8c6f-4e24-94df-0dc5d45dd34a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505419390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.505419390
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1238921376
Short name T914
Test name
Test status
Simulation time 112089106 ps
CPU time 1.87 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 213796 kb
Host smart-6e007099-cf1d-48c8-8285-7ca78f953250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238921376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1238921376
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3676141588
Short name T177
Test name
Test status
Simulation time 54668448 ps
CPU time 2.59 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 214516 kb
Host smart-d366ef22-6de0-4084-9502-41a5366fd1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676141588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3676141588
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3433783806
Short name T976
Test name
Test status
Simulation time 1102388192 ps
CPU time 7.22 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 205504 kb
Host smart-0e025b39-fdbc-4687-8e35-c98d018435b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433783806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
433783806
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3301628252
Short name T933
Test name
Test status
Simulation time 289589682 ps
CPU time 11.73 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205632 kb
Host smart-535d7caa-b62c-4094-9e69-6ec1403cecad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301628252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
301628252
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2226986847
Short name T1045
Test name
Test status
Simulation time 25058567 ps
CPU time 1.31 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 205592 kb
Host smart-269b887b-aa57-45c8-8e10-0bb955be63e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226986847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
226986847
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3938739367
Short name T1072
Test name
Test status
Simulation time 62285989 ps
CPU time 1.72 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 213764 kb
Host smart-c687b6d6-fa5f-4cb7-8ac5-e151acc19d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938739367 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3938739367
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.537534822
Short name T989
Test name
Test status
Simulation time 31918438 ps
CPU time 1.6 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:42:59 PM PDT 24
Peak memory 205640 kb
Host smart-68d1b89f-2b84-4280-81d5-988009be637c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537534822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.537534822
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.817150275
Short name T1069
Test name
Test status
Simulation time 23100925 ps
CPU time 0.83 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 205268 kb
Host smart-21dd520f-3608-42ef-82df-02af587967db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817150275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.817150275
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2690242932
Short name T139
Test name
Test status
Simulation time 84532852 ps
CPU time 2.54 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 205548 kb
Host smart-046937df-3cea-4a04-a246-84346e4598ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690242932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2690242932
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.441559652
Short name T943
Test name
Test status
Simulation time 138928765 ps
CPU time 1.83 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 214024 kb
Host smart-6042e0ad-bcdc-407d-b8eb-b75a1ebf99d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441559652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.441559652
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.856264553
Short name T1030
Test name
Test status
Simulation time 378826100 ps
CPU time 8.19 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 220764 kb
Host smart-5ec06b0d-4345-4e79-af77-bfc887625e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856264553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.856264553
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4213846428
Short name T1050
Test name
Test status
Simulation time 204788536 ps
CPU time 1.65 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215836 kb
Host smart-37f75e04-32ab-4f12-9242-6a5b5e950b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213846428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4213846428
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4235135994
Short name T172
Test name
Test status
Simulation time 318916626 ps
CPU time 10.61 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 216376 kb
Host smart-00fb1e30-d623-4bca-ab92-1faf3a666d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235135994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4235135994
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3086814267
Short name T969
Test name
Test status
Simulation time 8547523 ps
CPU time 0.8 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205344 kb
Host smart-8a508ba4-6382-4d2b-b476-bfb0d1bbf378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086814267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3086814267
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1658073162
Short name T981
Test name
Test status
Simulation time 10167161 ps
CPU time 0.77 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 205372 kb
Host smart-9e6a21cf-327c-4f25-bfb2-ccffc041d813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658073162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1658073162
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2001642807
Short name T1039
Test name
Test status
Simulation time 18517954 ps
CPU time 0.66 seconds
Started Jul 25 04:43:15 PM PDT 24
Finished Jul 25 04:43:26 PM PDT 24
Peak memory 205360 kb
Host smart-84d33d57-c4c1-447a-b934-a0bdfc29188c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001642807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2001642807
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1891363283
Short name T964
Test name
Test status
Simulation time 11454028 ps
CPU time 0.68 seconds
Started Jul 25 04:43:11 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 205392 kb
Host smart-78896f81-4169-4af1-9036-7022aa405d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891363283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1891363283
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1211418694
Short name T1003
Test name
Test status
Simulation time 9313946 ps
CPU time 0.78 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 205376 kb
Host smart-dbc4fefa-b984-4a1d-8b1d-6866a29075a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211418694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1211418694
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3737596417
Short name T1056
Test name
Test status
Simulation time 18808476 ps
CPU time 0.76 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205384 kb
Host smart-cac02935-39c4-4c5a-b1ef-70a56d390fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737596417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3737596417
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3112953195
Short name T971
Test name
Test status
Simulation time 13850195 ps
CPU time 0.84 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 205372 kb
Host smart-80e0bf55-28b5-4e0f-a224-064c3f988c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112953195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3112953195
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2187537544
Short name T919
Test name
Test status
Simulation time 11281260 ps
CPU time 0.71 seconds
Started Jul 25 04:43:02 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 205384 kb
Host smart-a8e2eb3a-28a1-4de0-9e1d-a32646fddd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187537544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2187537544
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2805552608
Short name T1047
Test name
Test status
Simulation time 12380493 ps
CPU time 0.86 seconds
Started Jul 25 04:43:40 PM PDT 24
Finished Jul 25 04:43:41 PM PDT 24
Peak memory 205372 kb
Host smart-73ac3119-553f-416d-b47e-f4c3ceae9b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805552608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2805552608
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3695523218
Short name T1067
Test name
Test status
Simulation time 11282663 ps
CPU time 0.84 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205368 kb
Host smart-15a92859-4d6c-4f02-98f4-691c2e2e1f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695523218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3695523218
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1267382840
Short name T143
Test name
Test status
Simulation time 260356025 ps
CPU time 8.78 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 205640 kb
Host smart-27e7ab11-3e52-4604-b659-2e77b787bc07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267382840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
267382840
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2573336639
Short name T1019
Test name
Test status
Simulation time 858785547 ps
CPU time 11.27 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:21 PM PDT 24
Peak memory 205600 kb
Host smart-30b34aca-88ec-4077-8591-8472cd9a3c1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573336639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
573336639
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1545497378
Short name T966
Test name
Test status
Simulation time 228002703 ps
CPU time 1.13 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205500 kb
Host smart-8caa27ef-d5b5-4343-8224-809638c22491
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545497378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
545497378
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3530868578
Short name T1059
Test name
Test status
Simulation time 55833853 ps
CPU time 1.13 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205620 kb
Host smart-b3a1dcb6-9b1b-4348-88f4-3f79b063c41a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530868578 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3530868578
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3135254474
Short name T978
Test name
Test status
Simulation time 51077513 ps
CPU time 0.97 seconds
Started Jul 25 04:43:02 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 205572 kb
Host smart-f65f6a39-df82-44b2-a8c6-efa98d37707f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135254474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3135254474
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3529498518
Short name T922
Test name
Test status
Simulation time 22496931 ps
CPU time 0.72 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205296 kb
Host smart-183d4cbe-c261-40f5-b3ff-8e8090e14e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529498518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3529498518
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3204952143
Short name T988
Test name
Test status
Simulation time 124671604 ps
CPU time 1.86 seconds
Started Jul 25 04:43:18 PM PDT 24
Finished Jul 25 04:43:20 PM PDT 24
Peak memory 205608 kb
Host smart-bd444463-4abb-462b-a34c-e2d6173f7691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204952143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3204952143
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1168991369
Short name T974
Test name
Test status
Simulation time 172927664 ps
CPU time 2.85 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:19 PM PDT 24
Peak memory 213964 kb
Host smart-7a8020fe-270d-4c34-b0bb-7d53a61ed76f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168991369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1168991369
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4186010805
Short name T947
Test name
Test status
Simulation time 803945108 ps
CPU time 5.22 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 213972 kb
Host smart-39831674-5d72-4f56-bdf6-6799fae4bf49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186010805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4186010805
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2201740851
Short name T970
Test name
Test status
Simulation time 492646448 ps
CPU time 4.45 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 213784 kb
Host smart-8ec130bb-de19-4daa-a14d-2d196be8845f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201740851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2201740851
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.454077003
Short name T176
Test name
Test status
Simulation time 100321927 ps
CPU time 2.95 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205808 kb
Host smart-fbc71f86-dc20-4028-8dfc-c423c2d6a35a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454077003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
454077003
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1096315603
Short name T997
Test name
Test status
Simulation time 82157867 ps
CPU time 0.72 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 205296 kb
Host smart-5fdb32a8-5c16-4cff-9374-115dd5148a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096315603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1096315603
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.57334035
Short name T912
Test name
Test status
Simulation time 12947225 ps
CPU time 0.83 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205360 kb
Host smart-e235a5b4-79bc-42f9-b9f4-28c235d8fbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57334035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.57334035
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3501083333
Short name T1008
Test name
Test status
Simulation time 46339541 ps
CPU time 0.84 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205392 kb
Host smart-9d0717e4-8060-4f60-b610-ce8cf3bb82c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501083333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3501083333
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.999862455
Short name T1053
Test name
Test status
Simulation time 39410423 ps
CPU time 0.76 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 205296 kb
Host smart-c7fa8604-aa25-474e-8c68-22e482fff639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999862455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.999862455
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2070393345
Short name T959
Test name
Test status
Simulation time 14489807 ps
CPU time 0.76 seconds
Started Jul 25 04:43:39 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 205372 kb
Host smart-bcdd052b-1b97-43c9-a7a2-3e3c9235c7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070393345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2070393345
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1466055208
Short name T983
Test name
Test status
Simulation time 20713385 ps
CPU time 0.8 seconds
Started Jul 25 04:43:33 PM PDT 24
Finished Jul 25 04:43:34 PM PDT 24
Peak memory 205280 kb
Host smart-88f2b86c-3332-4f34-b4f1-a7ecb2c1f653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466055208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1466055208
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2957721593
Short name T1065
Test name
Test status
Simulation time 10881504 ps
CPU time 0.7 seconds
Started Jul 25 04:43:32 PM PDT 24
Finished Jul 25 04:43:32 PM PDT 24
Peak memory 205280 kb
Host smart-cdfd35e4-ae4e-4622-b48e-840a96e4d4fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957721593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2957721593
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2302620247
Short name T956
Test name
Test status
Simulation time 48052047 ps
CPU time 0.92 seconds
Started Jul 25 04:43:45 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 205536 kb
Host smart-4053df98-760e-487b-93af-ad548f606a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302620247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2302620247
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2701374824
Short name T1009
Test name
Test status
Simulation time 125503191 ps
CPU time 0.84 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205284 kb
Host smart-8a27a0f8-136f-47ea-9636-c7e74ccc983b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701374824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2701374824
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2809008431
Short name T957
Test name
Test status
Simulation time 9273296 ps
CPU time 0.78 seconds
Started Jul 25 04:43:32 PM PDT 24
Finished Jul 25 04:43:34 PM PDT 24
Peak memory 205324 kb
Host smart-26ba35ba-3d94-4fcb-8b5d-d80ef7c8a577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809008431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2809008431
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1739365443
Short name T934
Test name
Test status
Simulation time 5136616783 ps
CPU time 13.7 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 205632 kb
Host smart-81bd49bb-6d8d-448f-b144-959453be9675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739365443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
739365443
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2872944422
Short name T963
Test name
Test status
Simulation time 571943191 ps
CPU time 12.59 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:16 PM PDT 24
Peak memory 205608 kb
Host smart-de082ea7-2cca-4689-a882-21127bc9cbf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872944422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
872944422
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3035468517
Short name T965
Test name
Test status
Simulation time 16651301 ps
CPU time 1.13 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205516 kb
Host smart-a5442ce9-52c5-4128-8108-7b8c779488aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035468517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
035468517
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1856339442
Short name T376
Test name
Test status
Simulation time 99369643 ps
CPU time 1.71 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 213856 kb
Host smart-7d802dbf-ee3f-4f07-b6f5-7e8bf8ed2108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856339442 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1856339442
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1165341373
Short name T960
Test name
Test status
Simulation time 98360809 ps
CPU time 1.07 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205580 kb
Host smart-85e1e512-04d4-4b4f-8e9f-226db1cc3576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165341373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1165341373
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3337691232
Short name T968
Test name
Test status
Simulation time 18525418 ps
CPU time 0.75 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205372 kb
Host smart-bbcb2377-3f55-4642-ad66-0ebbfc5a35b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337691232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3337691232
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1285259879
Short name T987
Test name
Test status
Simulation time 117491391 ps
CPU time 2.49 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205612 kb
Host smart-d233dbd2-f5fa-4517-9d7b-5a9a116237ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285259879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1285259879
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.980123129
Short name T1043
Test name
Test status
Simulation time 300945098 ps
CPU time 1.68 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 214032 kb
Host smart-c7ef7e01-c790-4488-b3cb-07e753ee7983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980123129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.980123129
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2870633959
Short name T1021
Test name
Test status
Simulation time 189950470 ps
CPU time 6.78 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 214132 kb
Host smart-6bbc8ae7-66c1-4c99-a652-b0ac33cc0673
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870633959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2870633959
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3606427521
Short name T910
Test name
Test status
Simulation time 633647280 ps
CPU time 5.43 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 213784 kb
Host smart-651695ad-1202-43f5-8f91-5877010bf555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606427521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3606427521
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2307200365
Short name T1001
Test name
Test status
Simulation time 19012941 ps
CPU time 0.71 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205348 kb
Host smart-8d412c72-ab54-495d-8901-f219e66b0481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307200365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2307200365
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3751538540
Short name T1046
Test name
Test status
Simulation time 19915098 ps
CPU time 0.8 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205388 kb
Host smart-814214fb-a7d8-4f79-8341-a12301509a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751538540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3751538540
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1819683511
Short name T926
Test name
Test status
Simulation time 22942987 ps
CPU time 0.85 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 205384 kb
Host smart-59f4c23d-888d-4fde-81ad-fc9cf2b71bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819683511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1819683511
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2934649837
Short name T923
Test name
Test status
Simulation time 38970777 ps
CPU time 0.68 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205312 kb
Host smart-09f67dfc-4e0c-4ab1-b488-e4d8c1c3aedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934649837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2934649837
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3205546746
Short name T944
Test name
Test status
Simulation time 8881708 ps
CPU time 0.75 seconds
Started Jul 25 04:43:21 PM PDT 24
Finished Jul 25 04:43:27 PM PDT 24
Peak memory 205316 kb
Host smart-b41a8c60-7270-46e9-b642-2f8fc597403a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205546746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3205546746
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.417557642
Short name T917
Test name
Test status
Simulation time 149397642 ps
CPU time 0.83 seconds
Started Jul 25 04:43:16 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 205300 kb
Host smart-2d536074-a1c3-4747-b942-a857e80e4b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417557642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.417557642
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.43091706
Short name T1036
Test name
Test status
Simulation time 63390030 ps
CPU time 0.7 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205396 kb
Host smart-2a0479c5-bb05-4afe-aa3b-6633ec49d6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43091706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.43091706
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2274402805
Short name T909
Test name
Test status
Simulation time 16931673 ps
CPU time 0.91 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205444 kb
Host smart-2fc8080c-b3e1-46bc-9b08-3cff08ca58f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274402805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2274402805
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3422877608
Short name T916
Test name
Test status
Simulation time 51204324 ps
CPU time 0.78 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205292 kb
Host smart-d75fd7a3-75fa-4704-8062-f152a5de0647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422877608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3422877608
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3703729957
Short name T962
Test name
Test status
Simulation time 11546340 ps
CPU time 0.74 seconds
Started Jul 25 04:43:35 PM PDT 24
Finished Jul 25 04:43:36 PM PDT 24
Peak memory 205304 kb
Host smart-fae18f0b-8c02-4c73-9f3e-66e7fdcaf757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703729957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3703729957
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2287052791
Short name T1002
Test name
Test status
Simulation time 215156596 ps
CPU time 1.56 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 213796 kb
Host smart-e7635bfd-e124-4044-ace3-cbd88f528e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287052791 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2287052791
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1865913433
Short name T1060
Test name
Test status
Simulation time 50094392 ps
CPU time 1.1 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205556 kb
Host smart-09d231b6-06eb-46c9-a4c0-1ffd94205fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865913433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1865913433
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3217956097
Short name T1014
Test name
Test status
Simulation time 8895027 ps
CPU time 0.7 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205368 kb
Host smart-c0e134ff-ab19-499b-be7c-51b4c79fcad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217956097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3217956097
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1008389262
Short name T1052
Test name
Test status
Simulation time 41139250 ps
CPU time 1.33 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205568 kb
Host smart-c00bafdf-74a1-47da-acfd-455bb4345a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008389262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1008389262
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1789740169
Short name T110
Test name
Test status
Simulation time 1532829464 ps
CPU time 3.75 seconds
Started Jul 25 04:43:14 PM PDT 24
Finished Jul 25 04:43:18 PM PDT 24
Peak memory 214048 kb
Host smart-8ceff5f9-55d3-4794-8151-728c27c0d76d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789740169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1789740169
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.854737956
Short name T113
Test name
Test status
Simulation time 861735369 ps
CPU time 5.15 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 219896 kb
Host smart-0aa9551f-372f-4fcb-9ceb-11ff63cb83c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854737956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.854737956
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2983615125
Short name T950
Test name
Test status
Simulation time 262747850 ps
CPU time 1.57 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205656 kb
Host smart-6160d7d9-885c-4ea5-9aea-278ad2e182e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983615125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2983615125
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3883165550
Short name T954
Test name
Test status
Simulation time 161148967 ps
CPU time 1.99 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 213744 kb
Host smart-bf918410-af31-4bd4-97a3-34637ed249e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883165550 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3883165550
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1394341947
Short name T942
Test name
Test status
Simulation time 51103276 ps
CPU time 1.06 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205528 kb
Host smart-1a583979-e9d3-4de9-b081-1344af505693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394341947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1394341947
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3296974953
Short name T945
Test name
Test status
Simulation time 46911629 ps
CPU time 0.71 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 205324 kb
Host smart-3e223619-b726-437c-a795-27a8f038fc60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296974953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3296974953
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2316360513
Short name T955
Test name
Test status
Simulation time 37260718 ps
CPU time 1.38 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 213804 kb
Host smart-c9e551f6-95b9-4a99-bae6-45694197aa6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316360513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2316360513
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3387771378
Short name T1012
Test name
Test status
Simulation time 329444270 ps
CPU time 4.92 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:15 PM PDT 24
Peak memory 213964 kb
Host smart-d04c1122-9259-4381-b4b6-f020d71cfc17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387771378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3387771378
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3386660101
Short name T924
Test name
Test status
Simulation time 292590284 ps
CPU time 3.78 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 214084 kb
Host smart-02402639-75a3-49a3-a3cf-2cf4a80cc081
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386660101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3386660101
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.719096080
Short name T928
Test name
Test status
Simulation time 37951389 ps
CPU time 1.34 seconds
Started Jul 25 04:43:09 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 213676 kb
Host smart-8930fd28-b417-49b0-9d9a-aa9492a43ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719096080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.719096080
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3037144066
Short name T1005
Test name
Test status
Simulation time 79412461 ps
CPU time 1.67 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:11 PM PDT 24
Peak memory 214076 kb
Host smart-1f88bd66-6255-4fe5-ab82-56cd582111e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037144066 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3037144066
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.783810293
Short name T1075
Test name
Test status
Simulation time 220344356 ps
CPU time 1.52 seconds
Started Jul 25 04:43:31 PM PDT 24
Finished Jul 25 04:43:33 PM PDT 24
Peak memory 205624 kb
Host smart-b6ca016a-df35-4d02-9cf2-547801c6161f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783810293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.783810293
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1549936992
Short name T1079
Test name
Test status
Simulation time 12789409 ps
CPU time 0.73 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 205348 kb
Host smart-0765c8f2-b0bb-4750-aa14-c07aec94d58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549936992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1549936992
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4101543313
Short name T977
Test name
Test status
Simulation time 161077691 ps
CPU time 1.51 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 205628 kb
Host smart-8f390ea3-e299-4456-9292-6f5f94db254c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101543313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4101543313
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.190985648
Short name T984
Test name
Test status
Simulation time 579132893 ps
CPU time 4.2 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 214016 kb
Host smart-46c1187d-d8d2-4b14-b9b2-1eb645c82401
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190985648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.190985648
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3740124526
Short name T1044
Test name
Test status
Simulation time 180793440 ps
CPU time 8.11 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:17 PM PDT 24
Peak memory 213984 kb
Host smart-3394c7af-3cae-4458-858c-1dab26dd135f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740124526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3740124526
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1380344817
Short name T911
Test name
Test status
Simulation time 287101879 ps
CPU time 2.69 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 213808 kb
Host smart-edbc40a8-6676-4ade-a135-fbe51ecaf9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380344817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1380344817
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1480069677
Short name T155
Test name
Test status
Simulation time 330258916 ps
CPU time 5.11 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 213732 kb
Host smart-0114c86b-8080-4153-b697-e92f5ec2f7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480069677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1480069677
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3785237445
Short name T946
Test name
Test status
Simulation time 29193128 ps
CPU time 1.55 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 213908 kb
Host smart-319d2d8c-d220-4c6e-895e-6b8c8afe94ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785237445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3785237445
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3172039048
Short name T996
Test name
Test status
Simulation time 48318923 ps
CPU time 1.18 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:09 PM PDT 24
Peak memory 205636 kb
Host smart-8f05e2bd-f46f-40bb-ba12-d5f6c7993b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172039048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3172039048
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3793776817
Short name T951
Test name
Test status
Simulation time 11718930 ps
CPU time 0.73 seconds
Started Jul 25 04:43:07 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 205348 kb
Host smart-bd5e59d2-6fe5-4e5a-a0ae-ef75158ed1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793776817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3793776817
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3869773423
Short name T140
Test name
Test status
Simulation time 41973994 ps
CPU time 1.65 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:42:59 PM PDT 24
Peak memory 205556 kb
Host smart-7d3b137e-b673-4592-a9d6-9b92a493c292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869773423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3869773423
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.423063257
Short name T1027
Test name
Test status
Simulation time 176974111 ps
CPU time 1.85 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:06 PM PDT 24
Peak memory 214056 kb
Host smart-f9304cd0-1118-4e18-99e2-bbd0f5610cb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423063257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.423063257
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3369433598
Short name T953
Test name
Test status
Simulation time 1200702837 ps
CPU time 6.1 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:15 PM PDT 24
Peak memory 214040 kb
Host smart-76776c0f-3d97-440f-8fd5-67f67191552a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369433598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3369433598
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3819726536
Short name T1076
Test name
Test status
Simulation time 128200816 ps
CPU time 2.74 seconds
Started Jul 25 04:43:08 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 213728 kb
Host smart-950aa172-e156-4d54-8fdc-9fd9017b9b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819726536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3819726536
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1957175202
Short name T1081
Test name
Test status
Simulation time 67428283 ps
CPU time 1.42 seconds
Started Jul 25 04:43:12 PM PDT 24
Finished Jul 25 04:43:14 PM PDT 24
Peak memory 213752 kb
Host smart-7fac6b99-3dbc-4f7b-8f12-aad9127cb8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957175202 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1957175202
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4226267772
Short name T1025
Test name
Test status
Simulation time 15447896 ps
CPU time 1.06 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205588 kb
Host smart-934d3d33-d09a-41ae-988f-b5bd1818dda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226267772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4226267772
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2352588840
Short name T913
Test name
Test status
Simulation time 11450769 ps
CPU time 0.71 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 205388 kb
Host smart-fdc6083d-07fb-4c91-901f-d782dd80c6e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352588840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2352588840
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2350160496
Short name T941
Test name
Test status
Simulation time 25852143 ps
CPU time 1.61 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:05 PM PDT 24
Peak memory 205588 kb
Host smart-671d6309-a750-46a5-8a4e-69b1e0a66e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350160496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2350160496
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.958798104
Short name T1070
Test name
Test status
Simulation time 311526956 ps
CPU time 2.96 seconds
Started Jul 25 04:43:06 PM PDT 24
Finished Jul 25 04:43:10 PM PDT 24
Peak memory 214004 kb
Host smart-8b5b33a8-68eb-4447-95b7-684f7b099bf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958798104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.958798104
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3354435947
Short name T115
Test name
Test status
Simulation time 606692569 ps
CPU time 14.64 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:23 PM PDT 24
Peak memory 220788 kb
Host smart-c042987f-8784-48a0-a0d4-b2a33361fc14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354435947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3354435947
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.635606987
Short name T1032
Test name
Test status
Simulation time 136521509 ps
CPU time 2.68 seconds
Started Jul 25 04:43:04 PM PDT 24
Finished Jul 25 04:43:08 PM PDT 24
Peak memory 213884 kb
Host smart-1b68f29b-b0f7-4979-a0ed-e3ffc9668ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635606987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.635606987
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3545155042
Short name T695
Test name
Test status
Simulation time 11871232 ps
CPU time 0.7 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 205736 kb
Host smart-d168cf9d-724a-4f9f-9d2a-f90fa8343621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545155042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3545155042
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1897292167
Short name T408
Test name
Test status
Simulation time 110264753 ps
CPU time 6.04 seconds
Started Jul 25 04:44:13 PM PDT 24
Finished Jul 25 04:44:19 PM PDT 24
Peak memory 214052 kb
Host smart-934082c7-35af-4ffa-9a93-2d5c2c0d4a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897292167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1897292167
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2915915654
Short name T288
Test name
Test status
Simulation time 218937574 ps
CPU time 4.37 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:08 PM PDT 24
Peak memory 208840 kb
Host smart-df2b682a-cb17-4633-90e8-52dca86ec7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915915654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2915915654
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1108966708
Short name T258
Test name
Test status
Simulation time 395132691 ps
CPU time 4.72 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 222164 kb
Host smart-7934eead-7dfc-4a99-b905-4f6299741f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108966708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1108966708
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3472828392
Short name T868
Test name
Test status
Simulation time 119802332 ps
CPU time 2.75 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 207756 kb
Host smart-de81e565-4553-4c87-9709-ade7435b8a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472828392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3472828392
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3441177304
Short name T738
Test name
Test status
Simulation time 2485950610 ps
CPU time 8.16 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 219532 kb
Host smart-5a9cf1fc-ef3a-48f5-bac6-c2a1ac9df58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441177304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3441177304
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1257581307
Short name T687
Test name
Test status
Simulation time 116620958 ps
CPU time 4.06 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 206532 kb
Host smart-67d0e418-c384-4a9d-b90f-703a7f175c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257581307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1257581307
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3573049657
Short name T671
Test name
Test status
Simulation time 132992516 ps
CPU time 2.32 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 206528 kb
Host smart-c35212c2-f050-4206-ab3d-ddc0aad1c3f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573049657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3573049657
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1145612149
Short name T657
Test name
Test status
Simulation time 1083112882 ps
CPU time 7.14 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 207716 kb
Host smart-bdb3ec0b-d059-4161-9e59-e10cfb9a1edc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145612149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1145612149
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3705945658
Short name T607
Test name
Test status
Simulation time 253055298 ps
CPU time 4.36 seconds
Started Jul 25 04:44:39 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 208732 kb
Host smart-36a008e6-23ce-4d64-8faf-83fda093388f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705945658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3705945658
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.765267396
Short name T688
Test name
Test status
Simulation time 899029533 ps
CPU time 3.72 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 207752 kb
Host smart-d277ed61-3316-4366-9967-ddc1bd0ecab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765267396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.765267396
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1939766275
Short name T698
Test name
Test status
Simulation time 101104455 ps
CPU time 2.38 seconds
Started Jul 25 04:44:34 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 206556 kb
Host smart-78c73086-edd5-4d66-8043-272e09e0d27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939766275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1939766275
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.706670680
Short name T123
Test name
Test status
Simulation time 122817475 ps
CPU time 4.87 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:08 PM PDT 24
Peak memory 207784 kb
Host smart-1e8de375-6bef-4517-a615-e80105daaeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706670680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.706670680
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2543710495
Short name T751
Test name
Test status
Simulation time 19697648 ps
CPU time 0.88 seconds
Started Jul 25 04:44:22 PM PDT 24
Finished Jul 25 04:44:23 PM PDT 24
Peak memory 205788 kb
Host smart-940dd7e6-8cc1-43ab-8e83-5a02848588c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543710495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2543710495
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4124565809
Short name T377
Test name
Test status
Simulation time 35246740 ps
CPU time 2.75 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 214392 kb
Host smart-45929df4-63dc-4ce9-8fc7-b947dd754594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124565809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4124565809
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2142993628
Short name T30
Test name
Test status
Simulation time 270819145 ps
CPU time 1.85 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 215228 kb
Host smart-b928aa47-1885-4e81-b672-7f8cdb832c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142993628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2142993628
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3117110081
Short name T682
Test name
Test status
Simulation time 291370948 ps
CPU time 3.33 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 208744 kb
Host smart-1c36d12d-6de3-493e-9f73-885cb4cb3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117110081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3117110081
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3245974018
Short name T81
Test name
Test status
Simulation time 65625191 ps
CPU time 3.43 seconds
Started Jul 25 04:44:31 PM PDT 24
Finished Jul 25 04:44:35 PM PDT 24
Peak memory 214020 kb
Host smart-11d93f6a-580a-4200-93ed-432b9cf7b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245974018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3245974018
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_random.2378579457
Short name T824
Test name
Test status
Simulation time 1059341631 ps
CPU time 5.02 seconds
Started Jul 25 04:44:14 PM PDT 24
Finished Jul 25 04:44:19 PM PDT 24
Peak memory 209024 kb
Host smart-e433459f-f5ca-41e4-91ba-fd45a131f4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378579457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2378579457
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2391580105
Short name T9
Test name
Test status
Simulation time 451611767 ps
CPU time 10.99 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 237228 kb
Host smart-087b7481-4d5d-4162-a576-a5f07e461c5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391580105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2391580105
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4084793292
Short name T764
Test name
Test status
Simulation time 801191912 ps
CPU time 3.85 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:25 PM PDT 24
Peak memory 208616 kb
Host smart-e67216aa-3748-4439-89c5-3be6a1246b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084793292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4084793292
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.348499199
Short name T566
Test name
Test status
Simulation time 112507521 ps
CPU time 3.68 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:42 PM PDT 24
Peak memory 208680 kb
Host smart-695dc5e7-bd06-41ca-b42d-5ec7d3d449bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348499199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.348499199
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3737453977
Short name T448
Test name
Test status
Simulation time 151672423 ps
CPU time 2.86 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:44:33 PM PDT 24
Peak memory 206608 kb
Host smart-2e547ba7-67ce-4a78-ad8f-2f8a3805755d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737453977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3737453977
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3287729872
Short name T555
Test name
Test status
Simulation time 571948527 ps
CPU time 6.67 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 208552 kb
Host smart-3b24288b-36f8-4dc2-8dcc-e3939e701a83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287729872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3287729872
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3076072521
Short name T553
Test name
Test status
Simulation time 41050591 ps
CPU time 1.84 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 214056 kb
Host smart-7dd2b233-7a26-4019-9312-759402c8b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076072521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3076072521
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.5033511
Short name T619
Test name
Test status
Simulation time 749286670 ps
CPU time 19.54 seconds
Started Jul 25 04:44:21 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 208184 kb
Host smart-85d093dd-dfb5-417f-84bc-cd6c87ed95ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5033511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.5033511
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.107843761
Short name T244
Test name
Test status
Simulation time 4924710142 ps
CPU time 54.08 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:45:33 PM PDT 24
Peak memory 216132 kb
Host smart-f6deb37b-57f2-4ede-91ef-f5e613ba354e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107843761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.107843761
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2466681910
Short name T406
Test name
Test status
Simulation time 1264416657 ps
CPU time 14.46 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 208340 kb
Host smart-9bfd6305-04c0-424e-8e45-757faa282644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466681910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2466681910
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2657580650
Short name T34
Test name
Test status
Simulation time 58694185 ps
CPU time 1.89 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 209900 kb
Host smart-55bde865-3afb-4442-9b55-44eb6479fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657580650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2657580650
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3489325601
Short name T522
Test name
Test status
Simulation time 39413313 ps
CPU time 0.91 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 205708 kb
Host smart-e380ba84-c83e-483c-9a53-030c8948678d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489325601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3489325601
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.852811889
Short name T409
Test name
Test status
Simulation time 126203165 ps
CPU time 2.58 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 215132 kb
Host smart-63659c97-56a3-45fa-bca0-acf9bc78089e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852811889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.852811889
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2418658635
Short name T540
Test name
Test status
Simulation time 3508123068 ps
CPU time 17.84 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 209428 kb
Host smart-049d61e7-084b-4c97-b79a-d849f0941f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418658635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2418658635
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1607759913
Short name T736
Test name
Test status
Simulation time 642980229 ps
CPU time 2.41 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 208488 kb
Host smart-92765934-e304-4be1-b625-92ff31a9cd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607759913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1607759913
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1325668651
Short name T875
Test name
Test status
Simulation time 334002034 ps
CPU time 2.7 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 214024 kb
Host smart-69d69ad9-df90-44e0-a3fa-fab5ae011709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325668651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1325668651
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4168402917
Short name T66
Test name
Test status
Simulation time 89155630 ps
CPU time 4.28 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 219584 kb
Host smart-bbb33de5-ca7d-493b-bb92-ac0c53210931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168402917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4168402917
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3272171611
Short name T556
Test name
Test status
Simulation time 704436012 ps
CPU time 17.4 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 214056 kb
Host smart-8e308e77-39eb-4410-af1f-580428bab300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272171611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3272171611
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3199065458
Short name T331
Test name
Test status
Simulation time 241169198 ps
CPU time 3.6 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 208392 kb
Host smart-b4cccdeb-8bde-4aa6-8270-e16e7a3737d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199065458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3199065458
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2875603384
Short name T422
Test name
Test status
Simulation time 567297652 ps
CPU time 4.48 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 206808 kb
Host smart-47157876-50a7-4091-85b3-edcdcb4adcae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875603384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2875603384
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2471350704
Short name T835
Test name
Test status
Simulation time 82334135 ps
CPU time 3.75 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 208320 kb
Host smart-06b1927d-9614-4880-a4d7-bafe9fafe670
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471350704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2471350704
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3754808644
Short name T683
Test name
Test status
Simulation time 127161899 ps
CPU time 2.31 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 208764 kb
Host smart-9b42669e-56e4-46cb-924f-56f38d21d30c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754808644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3754808644
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2545345806
Short name T623
Test name
Test status
Simulation time 229385121 ps
CPU time 5.5 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208548 kb
Host smart-65b48471-407b-4cbb-bf4f-d2a96edffa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545345806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2545345806
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1767625513
Short name T524
Test name
Test status
Simulation time 292598963 ps
CPU time 5.55 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:01 PM PDT 24
Peak memory 208300 kb
Host smart-5090606c-5737-4191-aa77-5f332727b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767625513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1767625513
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1375146052
Short name T871
Test name
Test status
Simulation time 443226160 ps
CPU time 2.42 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 214024 kb
Host smart-ac6f0d28-84f9-4d9a-b325-c528130c3789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375146052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1375146052
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.162152280
Short name T479
Test name
Test status
Simulation time 133441531 ps
CPU time 2.78 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 210216 kb
Host smart-79da745e-c423-4eb1-92ea-d344191bc181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162152280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.162152280
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4247823143
Short name T270
Test name
Test status
Simulation time 234038389 ps
CPU time 12.52 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 215680 kb
Host smart-01a85289-899f-4d85-9819-1e3e1d94a65b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247823143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4247823143
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2253410299
Short name T892
Test name
Test status
Simulation time 201865839 ps
CPU time 1.78 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:19 PM PDT 24
Peak memory 207232 kb
Host smart-32054e52-10ca-45f6-baac-24b4e3034d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253410299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2253410299
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.855401004
Short name T547
Test name
Test status
Simulation time 268285176 ps
CPU time 2.93 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 222248 kb
Host smart-669fcc7f-ca15-4a1f-819d-c65d27ffb0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855401004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.855401004
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.509591701
Short name T541
Test name
Test status
Simulation time 319045118 ps
CPU time 6.49 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 219516 kb
Host smart-c3a41bde-5af1-4602-90ab-20c49eaf7396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509591701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.509591701
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3991622900
Short name T599
Test name
Test status
Simulation time 774765601 ps
CPU time 15.72 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 208928 kb
Host smart-b163df8e-a2c8-435f-ae6e-d90f6a9601d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991622900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3991622900
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.190454386
Short name T77
Test name
Test status
Simulation time 103537048 ps
CPU time 1.98 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 208560 kb
Host smart-e867f28d-696b-42a9-b56e-7fe6aaf185f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190454386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.190454386
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.620147177
Short name T525
Test name
Test status
Simulation time 3280994661 ps
CPU time 8.79 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 206732 kb
Host smart-f67eb82f-55cd-4f8f-9e5e-6bc276547a9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620147177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.620147177
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.834896201
Short name T315
Test name
Test status
Simulation time 1602922524 ps
CPU time 41.15 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 208016 kb
Host smart-87f73a7b-64ac-4ae4-b27a-08688b60f8e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834896201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.834896201
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3538309601
Short name T806
Test name
Test status
Simulation time 3081658342 ps
CPU time 55.3 seconds
Started Jul 25 04:44:42 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 208204 kb
Host smart-858f070e-77ad-4883-a144-c953b48046bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538309601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3538309601
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3535750386
Short name T662
Test name
Test status
Simulation time 70238692 ps
CPU time 1.85 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 208604 kb
Host smart-597de336-94fc-4d86-aba0-2e708209548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535750386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3535750386
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.458045876
Short name T384
Test name
Test status
Simulation time 284799277 ps
CPU time 3.82 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 206660 kb
Host smart-82c961d6-ed78-49c9-9637-f8b0be67f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458045876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.458045876
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1074524751
Short name T322
Test name
Test status
Simulation time 916643191 ps
CPU time 32.82 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 221840 kb
Host smart-a34a9c8d-8907-4344-aa37-073fd195e7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074524751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1074524751
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1525807297
Short name T441
Test name
Test status
Simulation time 57332351 ps
CPU time 2.62 seconds
Started Jul 25 04:45:12 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 216172 kb
Host smart-01b413fc-f69c-4861-9736-b7c6bd44cedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525807297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1525807297
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2032096622
Short name T35
Test name
Test status
Simulation time 208100084 ps
CPU time 3.47 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 210156 kb
Host smart-5db53afb-892b-4ec5-9bd7-d65279b6acbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032096622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2032096622
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1251764653
Short name T842
Test name
Test status
Simulation time 12734135 ps
CPU time 0.69 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 205756 kb
Host smart-ea05f500-a81c-4e11-a771-60bff31dc5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251764653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1251764653
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4241763773
Short name T307
Test name
Test status
Simulation time 56342581 ps
CPU time 4.09 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 213940 kb
Host smart-b6577c59-1478-4e25-a7d5-2edeb889d377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241763773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4241763773
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2109910247
Short name T731
Test name
Test status
Simulation time 757021313 ps
CPU time 4.67 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 214036 kb
Host smart-3058f3f7-abb3-4b88-89eb-4e22481fbb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109910247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2109910247
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3089754661
Short name T549
Test name
Test status
Simulation time 248149219 ps
CPU time 3.74 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 220644 kb
Host smart-108933e1-7f10-4cba-8dd6-dac1270f8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089754661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3089754661
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2392798001
Short name T462
Test name
Test status
Simulation time 38059743 ps
CPU time 2.63 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 222304 kb
Host smart-69cdf06b-b199-4dac-90f9-64845f4c0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392798001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2392798001
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.4209073596
Short name T634
Test name
Test status
Simulation time 9634648451 ps
CPU time 47.86 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 209788 kb
Host smart-34803702-9458-4f85-9e17-5715efe74d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209073596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4209073596
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2880159271
Short name T451
Test name
Test status
Simulation time 66263494 ps
CPU time 2.99 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 207804 kb
Host smart-df380b72-05e9-4fa1-b918-7d7e2c206098
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880159271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2880159271
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2976999777
Short name T311
Test name
Test status
Simulation time 119002802 ps
CPU time 3.91 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 207880 kb
Host smart-50f1018b-ad31-4604-888c-52b683cffdc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976999777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2976999777
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3536339199
Short name T833
Test name
Test status
Simulation time 384852735 ps
CPU time 7.57 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:45:01 PM PDT 24
Peak memory 208404 kb
Host smart-a8f88469-8fb3-44a6-a90a-db127df3120b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536339199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3536339199
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1816874757
Short name T583
Test name
Test status
Simulation time 90619133 ps
CPU time 2.73 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 209000 kb
Host smart-47be43c4-576c-4302-a069-7cd65bc57729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816874757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1816874757
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1132186234
Short name T724
Test name
Test status
Simulation time 193529872 ps
CPU time 2.41 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 206476 kb
Host smart-bb410370-a584-417f-8927-feac715a4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132186234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1132186234
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3295675581
Short name T185
Test name
Test status
Simulation time 1432947806 ps
CPU time 22.78 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:45:16 PM PDT 24
Peak memory 222192 kb
Host smart-b1a65cf9-abb9-4c0e-b9dc-3753decf9772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295675581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3295675581
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.308043667
Short name T562
Test name
Test status
Simulation time 42769434 ps
CPU time 2.72 seconds
Started Jul 25 04:45:02 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 214044 kb
Host smart-8bd320b0-6711-4bb8-a956-08d4853e5d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308043667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.308043667
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4162524238
Short name T373
Test name
Test status
Simulation time 109858694 ps
CPU time 2.45 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 210112 kb
Host smart-d32a5f04-71b9-4d51-ad40-4136a3f5571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162524238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4162524238
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.65089746
Short name T104
Test name
Test status
Simulation time 57929355 ps
CPU time 1.15 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 205828 kb
Host smart-9d5a06c9-5504-41a4-9a1c-bc01f146f446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65089746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.65089746
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1354160605
Short name T399
Test name
Test status
Simulation time 213349168 ps
CPU time 3.4 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 214004 kb
Host smart-477bd252-c41c-45df-a8a8-65f1af78bf78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354160605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1354160605
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2787752821
Short name T681
Test name
Test status
Simulation time 68127335 ps
CPU time 1.44 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 205812 kb
Host smart-fe5b7865-1956-4c2f-88cc-2a799fc7d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787752821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2787752821
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.164596825
Short name T72
Test name
Test status
Simulation time 55876588 ps
CPU time 1.78 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 207728 kb
Host smart-4ba6e9dd-9bfb-4e2f-a6cf-af689b630728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164596825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.164596825
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1376802926
Short name T904
Test name
Test status
Simulation time 217876581 ps
CPU time 2.16 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 213976 kb
Host smart-d9d29457-6ead-4ee4-9b6f-e8a842d1728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376802926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1376802926
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.580341936
Short name T747
Test name
Test status
Simulation time 283243829 ps
CPU time 3.13 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 209352 kb
Host smart-57ba16f8-5f4d-41e8-ad59-84b2172fe0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580341936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.580341936
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3989938705
Short name T344
Test name
Test status
Simulation time 508135102 ps
CPU time 5.81 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 207240 kb
Host smart-0d0b511b-58de-4362-96f2-f388cdcbe228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989938705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3989938705
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1272629276
Short name T189
Test name
Test status
Simulation time 547914399 ps
CPU time 12.36 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 207972 kb
Host smart-27029a89-23d0-417f-a079-dd060dc93629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272629276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1272629276
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1006529082
Short name T455
Test name
Test status
Simulation time 292121383 ps
CPU time 2.73 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 208620 kb
Host smart-24dfe8d6-cc80-47e2-9758-ec95f5ceb222
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006529082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1006529082
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1099515988
Short name T759
Test name
Test status
Simulation time 362866233 ps
CPU time 3.92 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 208584 kb
Host smart-db35951f-2c3d-4107-86a9-42ec31971d7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099515988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1099515988
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4007231492
Short name T419
Test name
Test status
Simulation time 2220205640 ps
CPU time 5.24 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 207876 kb
Host smart-09607880-bccc-4190-a6c2-b2d46b016dcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007231492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4007231492
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2707860867
Short name T247
Test name
Test status
Simulation time 202779259 ps
CPU time 2.83 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 215708 kb
Host smart-46b954c4-585e-4128-b14f-5ff01e182ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707860867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2707860867
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.644080481
Short name T819
Test name
Test status
Simulation time 490511551 ps
CPU time 3.15 seconds
Started Jul 25 04:44:57 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 208452 kb
Host smart-11b443b3-19e7-48c6-88ce-349b7bdee0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644080481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.644080481
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4081661382
Short name T74
Test name
Test status
Simulation time 7974008246 ps
CPU time 33.83 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 222284 kb
Host smart-6f49bfd0-dfc8-42b5-8dcd-8986f9b04de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081661382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4081661382
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1811460554
Short name T669
Test name
Test status
Simulation time 208095896 ps
CPU time 10.09 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 222156 kb
Host smart-2489d231-e10d-48b8-85ae-cade25a9cbce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811460554 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1811460554
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.311960203
Short name T240
Test name
Test status
Simulation time 646233065 ps
CPU time 6.68 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 219440 kb
Host smart-73599901-a09f-4fe2-b4b1-2b3e79f4c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311960203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.311960203
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2202417697
Short name T161
Test name
Test status
Simulation time 140929870 ps
CPU time 4.6 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:18 PM PDT 24
Peak memory 210136 kb
Host smart-259624e6-ae3a-44a7-a9a2-d41abb64a720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202417697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2202417697
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1990006136
Short name T727
Test name
Test status
Simulation time 44810870 ps
CPU time 0.84 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 205740 kb
Host smart-149c9ece-f6a0-4710-8aea-39fda7e3e945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990006136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1990006136
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1485672042
Short name T395
Test name
Test status
Simulation time 210376195 ps
CPU time 10.55 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 215112 kb
Host smart-ae2d895b-c8bf-4ef4-839b-39bf3ec761bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485672042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1485672042
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2816741814
Short name T888
Test name
Test status
Simulation time 222483321 ps
CPU time 3.54 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 209904 kb
Host smart-5c898bf5-3647-4d73-a953-52a5b13fd548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816741814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2816741814
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3118986995
Short name T79
Test name
Test status
Simulation time 681862078 ps
CPU time 2.66 seconds
Started Jul 25 04:45:01 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 208880 kb
Host smart-84f5f753-66cd-4bad-8155-8efb7400d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118986995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3118986995
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1528220509
Short name T56
Test name
Test status
Simulation time 224714330 ps
CPU time 5.05 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 214000 kb
Host smart-bfef30f1-bea8-4fbf-98a0-599a359c5e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528220509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1528220509
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3594004735
Short name T430
Test name
Test status
Simulation time 59666860 ps
CPU time 2.48 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 218160 kb
Host smart-3d0fd825-d07a-4075-8600-f3edb428ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594004735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3594004735
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2819371340
Short name T231
Test name
Test status
Simulation time 88475924 ps
CPU time 4.19 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 209100 kb
Host smart-c0fea7da-db48-417a-bc22-303fbb77e240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819371340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2819371340
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1150380979
Short name T242
Test name
Test status
Simulation time 272512462 ps
CPU time 3.13 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208468 kb
Host smart-e2355b99-83ef-4180-8e33-718bc9a9e8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150380979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1150380979
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3178750707
Short name T571
Test name
Test status
Simulation time 2063034352 ps
CPU time 24.49 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:45:11 PM PDT 24
Peak memory 208180 kb
Host smart-ade4802b-abd8-4557-8856-0d8a6de04fcd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178750707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3178750707
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2321590446
Short name T510
Test name
Test status
Simulation time 97763435 ps
CPU time 2.92 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 206700 kb
Host smart-08ca58b8-9d10-4be2-a115-8b848eb6b221
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321590446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2321590446
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2954920372
Short name T440
Test name
Test status
Simulation time 543406593 ps
CPU time 6.39 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 207688 kb
Host smart-414d00cc-094e-448e-9442-5ee0cd2d0c31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954920372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2954920372
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3930510471
Short name T469
Test name
Test status
Simulation time 3296789031 ps
CPU time 7.35 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 214076 kb
Host smart-97586d71-a9bb-4f3a-ac6d-be74375d45d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930510471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3930510471
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1917037521
Short name T192
Test name
Test status
Simulation time 407302312 ps
CPU time 5.68 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 206392 kb
Host smart-9eb0fdf8-1bd9-4086-93f2-9f0834fb8a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917037521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1917037521
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1221646040
Short name T180
Test name
Test status
Simulation time 336229226 ps
CPU time 12.76 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 222212 kb
Host smart-282d3694-f0b2-458d-b880-b17ff7514e44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221646040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1221646040
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.95121411
Short name T589
Test name
Test status
Simulation time 1711707382 ps
CPU time 50.46 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:46 PM PDT 24
Peak memory 214024 kb
Host smart-cde9f7fa-8ca6-4175-9db6-0cd81d41056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95121411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.95121411
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1808568832
Short name T126
Test name
Test status
Simulation time 133837361 ps
CPU time 2.37 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 209748 kb
Host smart-cccf548d-adc5-4345-ae19-4be3404bf70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808568832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1808568832
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2617390593
Short name T901
Test name
Test status
Simulation time 12014753 ps
CPU time 0.72 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 205756 kb
Host smart-64d9031a-0712-4038-a54e-86511a5a3e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617390593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2617390593
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2672133694
Short name T31
Test name
Test status
Simulation time 211947252 ps
CPU time 1.64 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 213988 kb
Host smart-7adb8b9c-411d-472f-9529-8279371bef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672133694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2672133694
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1071512931
Short name T496
Test name
Test status
Simulation time 1318811997 ps
CPU time 8.23 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 218080 kb
Host smart-c03ea8c1-3400-4928-aeab-bfe6320eedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071512931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1071512931
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.798092537
Short name T630
Test name
Test status
Simulation time 118488003 ps
CPU time 2.75 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 214152 kb
Host smart-91d79aca-a89e-4f15-9046-9144c4f21920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798092537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.798092537
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2614678441
Short name T291
Test name
Test status
Simulation time 87732739 ps
CPU time 3.36 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 214172 kb
Host smart-2678ce5f-2476-4608-ab70-59d58c90c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614678441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2614678441
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.3852897450
Short name T348
Test name
Test status
Simulation time 302326927 ps
CPU time 4.12 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 209308 kb
Host smart-62a59bf6-8c0c-4fe3-8409-2c27455f707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852897450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3852897450
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1498146717
Short name T131
Test name
Test status
Simulation time 64982869 ps
CPU time 2.41 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208396 kb
Host smart-bccdea2c-afd8-49f6-ab1b-c7e8a38f61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498146717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1498146717
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1534692275
Short name T692
Test name
Test status
Simulation time 208037190 ps
CPU time 5.81 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 208136 kb
Host smart-b3893ac7-f483-4660-af5e-d469828a6bac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534692275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1534692275
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3001027054
Short name T628
Test name
Test status
Simulation time 107922758 ps
CPU time 2.7 seconds
Started Jul 25 04:44:57 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 206704 kb
Host smart-670f7caa-558a-4663-a0b1-cd239b632887
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001027054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3001027054
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3715407319
Short name T864
Test name
Test status
Simulation time 106929567 ps
CPU time 3.73 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 208404 kb
Host smart-2a17ed82-b32a-413c-aa66-9b224f47ec82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715407319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3715407319
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3581294069
Short name T407
Test name
Test status
Simulation time 489392495 ps
CPU time 5.51 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 208936 kb
Host smart-f2b669a5-8a92-44da-a69a-e6bc0bf084ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581294069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3581294069
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.392885825
Short name T855
Test name
Test status
Simulation time 154318799 ps
CPU time 2.43 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 206712 kb
Host smart-bcedef9a-65db-4ccb-bc3e-51fa9202f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392885825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.392885825
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.177269016
Short name T837
Test name
Test status
Simulation time 2074211032 ps
CPU time 11.24 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 219836 kb
Host smart-5847c9a0-32cb-433d-adf2-989e2ae6c7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177269016 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.177269016
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1597071472
Short name T585
Test name
Test status
Simulation time 195573124 ps
CPU time 3.7 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 208780 kb
Host smart-6c19cd03-1f41-48e1-b14b-aff288f69d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597071472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1597071472
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1364153782
Short name T639
Test name
Test status
Simulation time 66913378 ps
CPU time 2.81 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 210176 kb
Host smart-4017fea6-4726-4db5-96c2-a9661c5db352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364153782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1364153782
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1810825561
Short name T91
Test name
Test status
Simulation time 52218674 ps
CPU time 0.76 seconds
Started Jul 25 04:44:58 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 205696 kb
Host smart-6d0c94e0-f031-4302-9929-c6b612273359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810825561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1810825561
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.773876840
Short name T290
Test name
Test status
Simulation time 985992610 ps
CPU time 46.01 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 222124 kb
Host smart-a9e35ec4-d1e3-44d4-b430-05d945e9178e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773876840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.773876840
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3487449545
Short name T646
Test name
Test status
Simulation time 179892766 ps
CPU time 2.69 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 218756 kb
Host smart-957dbe30-f68c-416c-a398-87a8989e886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487449545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3487449545
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3821734696
Short name T899
Test name
Test status
Simulation time 82998695 ps
CPU time 2.19 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:21 PM PDT 24
Peak memory 214024 kb
Host smart-2433cf90-8bc2-4e8a-84a7-0924abb958f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821734696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3821734696
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1435769316
Short name T616
Test name
Test status
Simulation time 101550547 ps
CPU time 2.25 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 213968 kb
Host smart-2f796992-388f-4738-add5-8b705ccb071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435769316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1435769316
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4031139651
Short name T205
Test name
Test status
Simulation time 243076879 ps
CPU time 2.99 seconds
Started Jul 25 04:45:02 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 222304 kb
Host smart-9377a283-e622-447b-be4d-da026989b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031139651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4031139651
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.448459458
Short name T94
Test name
Test status
Simulation time 286201773 ps
CPU time 9.8 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 208076 kb
Host smart-4520c658-d932-4474-9859-38897cc3af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448459458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.448459458
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.179904574
Short name T450
Test name
Test status
Simulation time 351872535 ps
CPU time 10.58 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 207828 kb
Host smart-8a046585-9f25-48ed-b7ec-997ab720bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179904574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.179904574
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.997610816
Short name T744
Test name
Test status
Simulation time 503505474 ps
CPU time 5.92 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208360 kb
Host smart-ae75f4f9-d949-4a4c-a566-eeb498f96796
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997610816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.997610816
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.295059792
Short name T121
Test name
Test status
Simulation time 59618735 ps
CPU time 2.95 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208496 kb
Host smart-743da90d-291d-4e0e-aff0-3bdbf28dbedf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295059792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.295059792
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.942994722
Short name T452
Test name
Test status
Simulation time 2235768029 ps
CPU time 44.69 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 207808 kb
Host smart-4fc67f1f-2361-49b8-9beb-e66e9cdf0883
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942994722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.942994722
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2020712984
Short name T656
Test name
Test status
Simulation time 98662456 ps
CPU time 1.62 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 207320 kb
Host smart-2249529f-cde0-470d-b4fe-78690bdce43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020712984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2020712984
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2248008104
Short name T464
Test name
Test status
Simulation time 480503719 ps
CPU time 7.91 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 207604 kb
Host smart-b8e9566a-fd27-4c58-96c6-678ddb7e0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248008104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2248008104
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3002071479
Short name T210
Test name
Test status
Simulation time 24205623722 ps
CPU time 230.93 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:49:03 PM PDT 24
Peak memory 218008 kb
Host smart-72a6595d-ada9-4c09-8d85-4c48d13aea54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002071479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3002071479
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.871236590
Short name T13
Test name
Test status
Simulation time 527045714 ps
CPU time 6.32 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 207540 kb
Host smart-f7535659-438a-4c38-80fc-e3ca72c59da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871236590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.871236590
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2639580636
Short name T497
Test name
Test status
Simulation time 51806071 ps
CPU time 2.23 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 209540 kb
Host smart-6bdc80f8-b1cf-4786-bbf0-0699700a4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639580636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2639580636
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3387841651
Short name T768
Test name
Test status
Simulation time 17202658 ps
CPU time 0.82 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 205760 kb
Host smart-cd5233fa-f94a-43dd-bd2b-77ae0c7d8ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387841651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3387841651
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1925339092
Short name T396
Test name
Test status
Simulation time 1171786543 ps
CPU time 15.8 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 222220 kb
Host smart-5818edf6-7602-4513-ae33-8ea8f363ee6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925339092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1925339092
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3873875927
Short name T235
Test name
Test status
Simulation time 106480743 ps
CPU time 2.36 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 207124 kb
Host smart-bd3d0bf0-87cf-43ef-8a01-38e2607f27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873875927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3873875927
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2439218012
Short name T359
Test name
Test status
Simulation time 118806382 ps
CPU time 4.58 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 214032 kb
Host smart-93b20d10-11d6-447f-90c8-7bd8064728e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439218012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2439218012
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1539180581
Short name T771
Test name
Test status
Simulation time 49324500 ps
CPU time 2.68 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 214056 kb
Host smart-727efad2-2793-49db-854d-65f86ede19a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539180581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1539180581
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3565118578
Short name T592
Test name
Test status
Simulation time 486254243 ps
CPU time 6.77 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 220000 kb
Host smart-13b53f24-46dd-4a9d-85ab-7ee09f992a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565118578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3565118578
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.4125808424
Short name T324
Test name
Test status
Simulation time 422802552 ps
CPU time 4.5 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 217988 kb
Host smart-8ae85921-003a-4544-a022-107d55f4044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125808424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4125808424
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2773069523
Short name T543
Test name
Test status
Simulation time 970007258 ps
CPU time 10.7 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 206584 kb
Host smart-a3dc831f-04c9-4dcc-a289-e942a464dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773069523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2773069523
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.984970630
Short name T505
Test name
Test status
Simulation time 776245695 ps
CPU time 3.65 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 206692 kb
Host smart-a221fdce-3aa9-4eee-bcfc-a4d0a8b7ed8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984970630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.984970630
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1874042423
Short name T494
Test name
Test status
Simulation time 101842790 ps
CPU time 4.09 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:11 PM PDT 24
Peak memory 206700 kb
Host smart-c0966f0a-6712-465f-ac9d-e3d2726f14f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874042423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1874042423
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1152504737
Short name T421
Test name
Test status
Simulation time 50669100 ps
CPU time 2.48 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 207952 kb
Host smart-da1793c2-13e8-4be6-825f-f82d3ae52319
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152504737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1152504737
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.153707154
Short name T512
Test name
Test status
Simulation time 347759770 ps
CPU time 3.94 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208716 kb
Host smart-62f20989-37fa-45dc-b726-f52abb6c8fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153707154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.153707154
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4230755114
Short name T877
Test name
Test status
Simulation time 201792666 ps
CPU time 3.98 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 208352 kb
Host smart-270195e3-6026-490d-8181-eac90d93c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230755114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4230755114
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2890208148
Short name T563
Test name
Test status
Simulation time 118861606 ps
CPU time 5.25 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 209476 kb
Host smart-f233e067-bdd0-4abe-8d45-38d4f305e0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890208148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2890208148
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2075071917
Short name T112
Test name
Test status
Simulation time 176158593 ps
CPU time 2.26 seconds
Started Jul 25 04:45:01 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 209820 kb
Host smart-96471486-b6e1-4173-988f-7a040999f192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075071917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2075071917
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1932141662
Short name T411
Test name
Test status
Simulation time 9434864 ps
CPU time 0.78 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 205676 kb
Host smart-424b6d78-d1a7-4966-bf4a-2939809f7581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932141662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1932141662
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3394982845
Short name T715
Test name
Test status
Simulation time 384291089 ps
CPU time 3.01 seconds
Started Jul 25 04:45:17 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 219932 kb
Host smart-bf195469-e85b-4589-a356-af06967b89e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394982845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3394982845
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.542228488
Short name T256
Test name
Test status
Simulation time 101624960 ps
CPU time 1.55 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 207088 kb
Host smart-4720768b-9749-41d5-9ab6-74fe0ec32cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542228488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.542228488
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1425820346
Short name T85
Test name
Test status
Simulation time 59815513 ps
CPU time 3.8 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 214032 kb
Host smart-903d1d36-cc62-46b5-ab1a-da5567f7c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425820346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1425820346
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2149034513
Short name T257
Test name
Test status
Simulation time 120463711 ps
CPU time 3.21 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 214752 kb
Host smart-ce684012-79c8-40db-9069-d9f59d19487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149034513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2149034513
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3214607510
Short name T212
Test name
Test status
Simulation time 143036568 ps
CPU time 2.88 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 219976 kb
Host smart-0e0d7cbd-7b9c-4d7f-8537-3fd5f70e0498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214607510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3214607510
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2160644542
Short name T617
Test name
Test status
Simulation time 278488654 ps
CPU time 5.58 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 208856 kb
Host smart-db92688f-5308-45f8-a078-bdac0254396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160644542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2160644542
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2520354876
Short name T857
Test name
Test status
Simulation time 120894915 ps
CPU time 3.9 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 208748 kb
Host smart-6de2beec-0401-4f3c-acb0-02e7f095dfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520354876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2520354876
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.272448395
Short name T874
Test name
Test status
Simulation time 512901897 ps
CPU time 2.88 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 208832 kb
Host smart-f6754500-ebb2-4dde-89b7-994832d0cebe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272448395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.272448395
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1075633491
Short name T565
Test name
Test status
Simulation time 143060965 ps
CPU time 2.03 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 206740 kb
Host smart-f4ead646-b0a3-4d06-8e3d-644a4cb6ab0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075633491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1075633491
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.172583646
Short name T754
Test name
Test status
Simulation time 92270015 ps
CPU time 3.2 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 208704 kb
Host smart-22fe9259-3ac7-466d-b3a5-1eb09ac69a35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172583646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.172583646
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4029930854
Short name T329
Test name
Test status
Simulation time 53229804 ps
CPU time 2.54 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 209624 kb
Host smart-038c0b2a-b42b-4c28-820e-6a4b886014e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029930854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4029930854
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.254231121
Short name T567
Test name
Test status
Simulation time 149186676 ps
CPU time 4.46 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:44:59 PM PDT 24
Peak memory 206408 kb
Host smart-4baba81d-9002-4f91-8836-69a7cac05c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254231121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.254231121
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.214931989
Short name T76
Test name
Test status
Simulation time 481295439 ps
CPU time 9.03 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 222204 kb
Host smart-0a50b6f8-632e-4398-b601-4dd40d819ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214931989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.214931989
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.430875563
Short name T838
Test name
Test status
Simulation time 667140182 ps
CPU time 18.43 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 221468 kb
Host smart-cdc3c850-14b3-4ff4-8c2b-cb288d8a6e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430875563 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.430875563
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2072752199
Short name T523
Test name
Test status
Simulation time 2845988403 ps
CPU time 12.76 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 214244 kb
Host smart-20d9f5cd-97b8-4a2c-871b-06221992d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072752199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2072752199
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2779797272
Short name T584
Test name
Test status
Simulation time 167429949 ps
CPU time 2.11 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:21 PM PDT 24
Peak memory 209784 kb
Host smart-d3dab62f-c6be-4c06-9a94-a3dee83828e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779797272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2779797272
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1801757352
Short name T439
Test name
Test status
Simulation time 37633280 ps
CPU time 0.75 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 205924 kb
Host smart-3edba47f-99c0-4d82-86f2-1cf3ebbf46ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801757352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1801757352
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3512187270
Short name T228
Test name
Test status
Simulation time 7124340640 ps
CPU time 70.98 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 214472 kb
Host smart-d8cc8537-7d33-4575-9c03-5089cec0fa56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512187270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3512187270
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3010957615
Short name T528
Test name
Test status
Simulation time 120896618 ps
CPU time 4.58 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 221176 kb
Host smart-849a0c4f-3389-4fd7-91c3-6863d4bbb569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010957615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3010957615
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2323139689
Short name T404
Test name
Test status
Simulation time 116844551 ps
CPU time 2.43 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 207624 kb
Host smart-d2e42031-591b-4a80-8f32-f02161d292b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323139689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2323139689
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2189187738
Short name T86
Test name
Test status
Simulation time 1260145777 ps
CPU time 21.23 seconds
Started Jul 25 04:44:58 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 214036 kb
Host smart-34d7a7e9-4e41-4e23-9daf-3f9cf1901751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189187738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2189187738
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.378534624
Short name T708
Test name
Test status
Simulation time 120075741 ps
CPU time 2.45 seconds
Started Jul 25 04:44:58 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 221004 kb
Host smart-fd4cea48-8486-43b8-975c-c341c1f69a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378534624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.378534624
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2687493850
Short name T908
Test name
Test status
Simulation time 235924391 ps
CPU time 3.18 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 210008 kb
Host smart-3b2033fe-554e-4dfb-9927-c30d8222822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687493850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2687493850
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.454372611
Short name T722
Test name
Test status
Simulation time 1847417553 ps
CPU time 10.78 seconds
Started Jul 25 04:45:15 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 207344 kb
Host smart-339d8238-b582-46bc-9f22-dfcc73c15a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454372611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.454372611
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4071044993
Short name T640
Test name
Test status
Simulation time 209592620 ps
CPU time 5.26 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 207700 kb
Host smart-d578b640-5f52-4548-bfee-8b859bf2ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071044993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4071044993
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2038873748
Short name T820
Test name
Test status
Simulation time 91906968 ps
CPU time 3.52 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 208556 kb
Host smart-8449bdde-c9c9-4bf2-9a20-ea75e874c10f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038873748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2038873748
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3064837465
Short name T846
Test name
Test status
Simulation time 662226279 ps
CPU time 14.81 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:21 PM PDT 24
Peak memory 208692 kb
Host smart-a85e940c-2ca9-4e43-8fcb-02a9bbf3836b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064837465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3064837465
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1058462114
Short name T383
Test name
Test status
Simulation time 143499518 ps
CPU time 2.49 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 206552 kb
Host smart-4b16db02-2ec0-4c64-b93f-06f00a6c14f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058462114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1058462114
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1898234804
Short name T637
Test name
Test status
Simulation time 599720401 ps
CPU time 4.27 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 213980 kb
Host smart-134b8b2f-1025-4280-b2d0-9ec54b7377cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898234804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1898234804
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.441815411
Short name T788
Test name
Test status
Simulation time 60673263 ps
CPU time 2.18 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:45:38 PM PDT 24
Peak memory 206632 kb
Host smart-4cd6f774-8e83-4ce7-8bfd-33b31ffa1b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441815411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.441815411
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2760864331
Short name T333
Test name
Test status
Simulation time 3107174963 ps
CPU time 19.22 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 222404 kb
Host smart-592b550e-2a84-4069-8cad-dd610c7663a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760864331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2760864331
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1666361380
Short name T51
Test name
Test status
Simulation time 782266181 ps
CPU time 7.59 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 222340 kb
Host smart-fcde9e38-91e5-4333-a651-a76014ce40f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666361380 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1666361380
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2181570191
Short name T342
Test name
Test status
Simulation time 107823651 ps
CPU time 3.39 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 214116 kb
Host smart-00cff1eb-50ca-4378-953c-cb1896aa69c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181570191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2181570191
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1810296403
Short name T168
Test name
Test status
Simulation time 349460105 ps
CPU time 2.7 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 210324 kb
Host smart-db361b91-30d9-432b-a37f-e3b07bf383c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810296403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1810296403
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1480427994
Short name T414
Test name
Test status
Simulation time 12149312 ps
CPU time 0.71 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 205672 kb
Host smart-ef2c33c9-dd17-42a7-9f74-bae6299ea544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480427994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1480427994
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2183589257
Short name T895
Test name
Test status
Simulation time 112386094 ps
CPU time 1.72 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:47 PM PDT 24
Peak memory 216528 kb
Host smart-89e693cc-8ba3-4e24-8a72-9179f2a0aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183589257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2183589257
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3091919970
Short name T737
Test name
Test status
Simulation time 320964680 ps
CPU time 3.08 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 217880 kb
Host smart-b9049a3c-6e22-47eb-bf7d-2d0fac3048e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091919970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3091919970
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1348926454
Short name T509
Test name
Test status
Simulation time 178778422 ps
CPU time 5.7 seconds
Started Jul 25 04:44:19 PM PDT 24
Finished Jul 25 04:44:25 PM PDT 24
Peak memory 208520 kb
Host smart-ecd912f3-abf0-4cbd-ba81-bee4a07f0a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348926454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1348926454
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3055946168
Short name T281
Test name
Test status
Simulation time 85214922 ps
CPU time 2.99 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 214032 kb
Host smart-3d086cdd-e1b3-4e7d-ace3-758f7f1db9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055946168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3055946168
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2447171608
Short name T752
Test name
Test status
Simulation time 505642263 ps
CPU time 7.18 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:12 PM PDT 24
Peak memory 207980 kb
Host smart-438433c3-bb25-44c5-8dff-b0a981fc1eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447171608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2447171608
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2681419755
Short name T10
Test name
Test status
Simulation time 1819781355 ps
CPU time 13.45 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 239000 kb
Host smart-5fb2ac61-32eb-4b8e-8843-a8490515548c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681419755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2681419755
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1027447706
Short name T392
Test name
Test status
Simulation time 181260046 ps
CPU time 2.41 seconds
Started Jul 25 04:44:11 PM PDT 24
Finished Jul 25 04:44:13 PM PDT 24
Peak memory 206632 kb
Host smart-4d25ec7d-fe70-4112-a948-b6122fbc95e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027447706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1027447706
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.73937851
Short name T577
Test name
Test status
Simulation time 132448097 ps
CPU time 2.26 seconds
Started Jul 25 04:44:28 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 206640 kb
Host smart-a8a71ded-7f75-4286-b7b7-e2ca183a5331
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73937851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.73937851
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.574342400
Short name T763
Test name
Test status
Simulation time 759390502 ps
CPU time 6.95 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:42 PM PDT 24
Peak memory 207908 kb
Host smart-2ad23bb6-e410-4b31-9e98-e3341254cd41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574342400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.574342400
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3194015618
Short name T274
Test name
Test status
Simulation time 21936916 ps
CPU time 1.84 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:47 PM PDT 24
Peak memory 206636 kb
Host smart-7ca97760-d871-4b17-9ea6-bbdbbd88e775
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194015618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3194015618
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2054952305
Short name T823
Test name
Test status
Simulation time 106312389 ps
CPU time 1.9 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 217940 kb
Host smart-8f0366d1-f4a7-4f24-86b3-ae128cb55508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054952305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2054952305
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.730077465
Short name T437
Test name
Test status
Simulation time 154380338 ps
CPU time 3.16 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 208076 kb
Host smart-5b6ab44b-bd55-40a1-8a22-21148e0d4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730077465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.730077465
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3267814138
Short name T241
Test name
Test status
Simulation time 666157325 ps
CPU time 22.19 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 221616 kb
Host smart-008fbfd3-b6fd-4700-9250-9e3ca7d3e555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267814138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3267814138
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2878208047
Short name T182
Test name
Test status
Simulation time 2517494873 ps
CPU time 23.24 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:25 PM PDT 24
Peak memory 222272 kb
Host smart-9b5b2a12-4243-446c-8fe9-97adfd6a02f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878208047 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2878208047
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2988283596
Short name T201
Test name
Test status
Simulation time 730471264 ps
CPU time 9.96 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 218068 kb
Host smart-7dd985c4-4a67-4089-9e7f-265f9063dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988283596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2988283596
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4159903842
Short name T818
Test name
Test status
Simulation time 1067967389 ps
CPU time 2.56 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 209732 kb
Host smart-39ec3637-4b02-4a1c-b3ee-ac9334dcd4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159903842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4159903842
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3657180726
Short name T92
Test name
Test status
Simulation time 17453432 ps
CPU time 0.81 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 205696 kb
Host smart-7713a417-3be8-4a5c-bf5f-507cf0cdb2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657180726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3657180726
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2955366750
Short name T403
Test name
Test status
Simulation time 784949589 ps
CPU time 3.72 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 209400 kb
Host smart-25445783-e9b6-4e21-be58-9a467896e390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955366750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2955366750
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2694425125
Short name T263
Test name
Test status
Simulation time 77077036 ps
CPU time 3.62 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:03 PM PDT 24
Peak memory 214004 kb
Host smart-db8202c3-9197-4600-afe7-72933df585bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694425125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2694425125
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2116247828
Short name T613
Test name
Test status
Simulation time 120725558 ps
CPU time 2.18 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 215712 kb
Host smart-624f1ec6-6252-4d47-9f3d-500896e3beb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116247828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2116247828
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.868072322
Short name T526
Test name
Test status
Simulation time 431931529 ps
CPU time 2.72 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 218104 kb
Host smart-7a26c5b0-155f-42df-8773-63e70e5e9896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868072322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.868072322
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3553839647
Short name T794
Test name
Test status
Simulation time 858760705 ps
CPU time 6.14 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 207796 kb
Host smart-cf12952e-8a45-49cd-b384-b2391a42d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553839647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3553839647
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2951074960
Short name T362
Test name
Test status
Simulation time 148836325 ps
CPU time 4.14 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 206336 kb
Host smart-e2be6f01-2059-4f99-bb80-6783d73f659b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951074960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2951074960
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2822442322
Short name T667
Test name
Test status
Simulation time 290441045 ps
CPU time 4.34 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 208028 kb
Host smart-3bc73a1a-e525-4cb9-820f-0c43eb8f3c2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822442322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2822442322
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.772097633
Short name T673
Test name
Test status
Simulation time 486779797 ps
CPU time 4.93 seconds
Started Jul 25 04:45:08 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 206752 kb
Host smart-9059540e-c6ec-4068-85ea-ae085f40e6f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772097633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.772097633
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2604098342
Short name T133
Test name
Test status
Simulation time 96717249 ps
CPU time 3.08 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 208844 kb
Host smart-50ea6596-dad1-475f-82d8-1a87828c8a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604098342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2604098342
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3851979656
Short name T418
Test name
Test status
Simulation time 90616063 ps
CPU time 2.07 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 206628 kb
Host smart-2acccf4a-8ba0-4ae8-8e7b-317caacc25ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851979656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3851979656
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4191147726
Short name T402
Test name
Test status
Simulation time 164107436 ps
CPU time 2.97 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 207284 kb
Host smart-5c31c2e4-4926-42a9-8674-21042772f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191147726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4191147726
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.637697607
Short name T810
Test name
Test status
Simulation time 36785503 ps
CPU time 0.75 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 205800 kb
Host smart-56a47c3e-a3d1-4dbf-ba62-332ede7a3ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637697607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.637697607
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1845554540
Short name T400
Test name
Test status
Simulation time 242715741 ps
CPU time 12.59 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 214060 kb
Host smart-f0d38768-1f16-4a16-90bf-d541c78146c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845554540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1845554540
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3540646411
Short name T615
Test name
Test status
Simulation time 444626116 ps
CPU time 1.48 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 209452 kb
Host smart-73999f9d-a805-4558-ac35-9662bf515cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540646411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3540646411
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4213064706
Short name T125
Test name
Test status
Simulation time 700828780 ps
CPU time 5.83 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 219440 kb
Host smart-c07cf7fd-44d6-4bb3-ab06-dfc5eb0eea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213064706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4213064706
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1887829292
Short name T492
Test name
Test status
Simulation time 563612837 ps
CPU time 8.93 seconds
Started Jul 25 04:45:12 PM PDT 24
Finished Jul 25 04:45:21 PM PDT 24
Peak memory 214156 kb
Host smart-a0b6bb20-2fb2-4517-8c24-a7998df1d5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887829292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1887829292
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2789668078
Short name T629
Test name
Test status
Simulation time 56649252 ps
CPU time 1.99 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:24 PM PDT 24
Peak memory 222016 kb
Host smart-9f367476-7a21-486f-8422-06fc46ff8b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789668078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2789668078
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.347373849
Short name T64
Test name
Test status
Simulation time 227501651 ps
CPU time 6.23 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 210496 kb
Host smart-3f5dfaf5-094f-4303-9ded-47cfbe2d3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347373849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.347373849
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2246868606
Short name T328
Test name
Test status
Simulation time 469417245 ps
CPU time 5.87 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 218008 kb
Host smart-e22c2773-ac34-407f-84a2-b4665165b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246868606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2246868606
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1022721780
Short name T766
Test name
Test status
Simulation time 194659113 ps
CPU time 2.72 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 208244 kb
Host smart-534e02f1-ffa5-4c0c-8916-4fcd61cab020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022721780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1022721780
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.216306141
Short name T456
Test name
Test status
Simulation time 741689992 ps
CPU time 5.22 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 207964 kb
Host smart-e5699fa8-2179-4e4b-ba8e-7ddd80b26a41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216306141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.216306141
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.885491073
Short name T817
Test name
Test status
Simulation time 362504430 ps
CPU time 8.3 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 207696 kb
Host smart-894c48ed-ffb1-41b4-8b8d-897ac4d589b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885491073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.885491073
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3147877215
Short name T649
Test name
Test status
Simulation time 284631158 ps
CPU time 3.83 seconds
Started Jul 25 04:44:58 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 206788 kb
Host smart-090df822-a588-4bb3-8c9d-11967e22c9b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147877215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3147877215
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3719091001
Short name T370
Test name
Test status
Simulation time 1189801151 ps
CPU time 12.35 seconds
Started Jul 25 04:45:03 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 208432 kb
Host smart-395dc52f-6fe1-439f-9de3-2179d6bf28b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719091001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3719091001
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2784330199
Short name T783
Test name
Test status
Simulation time 267228837 ps
CPU time 3.68 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 207504 kb
Host smart-5f58ffbd-b46c-47e3-bfe5-6822de70b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784330199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2784330199
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2536062434
Short name T587
Test name
Test status
Simulation time 4446621497 ps
CPU time 36.73 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 220040 kb
Host smart-4b354da0-d600-457a-88c6-f0a695cda6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536062434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2536062434
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1666224686
Short name T772
Test name
Test status
Simulation time 208234558 ps
CPU time 6.25 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 214024 kb
Host smart-7fad1c85-3130-4354-a1c0-426e65b35824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666224686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1666224686
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1690273249
Short name T604
Test name
Test status
Simulation time 294390571 ps
CPU time 2.61 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:38 PM PDT 24
Peak memory 209944 kb
Host smart-285f2b09-2d26-47b0-bc4c-98611195a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690273249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1690273249
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3283737812
Short name T423
Test name
Test status
Simulation time 38805973 ps
CPU time 0.81 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 205764 kb
Host smart-a50df4aa-7643-44b9-beb1-0235db91388e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283737812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3283737812
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2813057797
Short name T478
Test name
Test status
Simulation time 25505038 ps
CPU time 1.76 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 207320 kb
Host smart-dc7f3658-fe16-4788-8e33-6fef9b5977cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813057797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2813057797
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2672730854
Short name T259
Test name
Test status
Simulation time 33718001 ps
CPU time 2.11 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:06 PM PDT 24
Peak memory 214060 kb
Host smart-2671724f-b897-4e12-912c-6e1bc9073ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672730854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2672730854
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1535730809
Short name T339
Test name
Test status
Simulation time 175996956 ps
CPU time 1.57 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 213928 kb
Host smart-7f356627-7c5f-4da5-8d96-dee7b1eb91e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535730809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1535730809
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.4164525243
Short name T498
Test name
Test status
Simulation time 140728236 ps
CPU time 2.44 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 209284 kb
Host smart-b2ab9da3-716d-4491-875a-30131402215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164525243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4164525243
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3946233042
Short name T725
Test name
Test status
Simulation time 491065592 ps
CPU time 5.42 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 214000 kb
Host smart-08229100-3b73-44ac-9f16-b52062c717b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946233042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3946233042
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3944338827
Short name T486
Test name
Test status
Simulation time 686195254 ps
CPU time 18.54 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 208540 kb
Host smart-8a77560d-ac7d-400d-8e9c-52d1d72476dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944338827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3944338827
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1629082258
Short name T389
Test name
Test status
Simulation time 121979511 ps
CPU time 4.89 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 206696 kb
Host smart-35941fec-448d-42e3-9fee-6c66c6394b8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629082258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1629082258
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3058566657
Short name T287
Test name
Test status
Simulation time 657641705 ps
CPU time 3.64 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 208540 kb
Host smart-0621c7ac-fbd5-41f4-8ae9-66fb020f5250
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058566657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3058566657
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4108420496
Short name T467
Test name
Test status
Simulation time 576308491 ps
CPU time 13.35 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 207616 kb
Host smart-1e8fcdb0-0e05-4b7b-aac2-063281f45e5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108420496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4108420496
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1947475337
Short name T709
Test name
Test status
Simulation time 510605924 ps
CPU time 3.26 seconds
Started Jul 25 04:45:05 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 213912 kb
Host smart-a18b1d06-0135-41dc-8b1f-3656c20323bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947475337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1947475337
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1551600894
Short name T554
Test name
Test status
Simulation time 269172098 ps
CPU time 2.18 seconds
Started Jul 25 04:45:05 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 208252 kb
Host smart-52311b68-8a33-4ed4-9924-cc07cebad4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551600894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1551600894
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1225323677
Short name T197
Test name
Test status
Simulation time 1372999727 ps
CPU time 10.43 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 220336 kb
Host smart-cdfc6135-dcbc-4e93-8da0-95040120be3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225323677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1225323677
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3766409916
Short name T603
Test name
Test status
Simulation time 835221379 ps
CPU time 17.84 seconds
Started Jul 25 04:44:54 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 222312 kb
Host smart-f0487f4d-9df5-4df0-9794-97552b2f5b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766409916 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3766409916
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3772238438
Short name T745
Test name
Test status
Simulation time 66968979 ps
CPU time 3.47 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 207320 kb
Host smart-e5263d70-f019-46cf-b777-5f844a53f130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772238438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3772238438
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1444054048
Short name T633
Test name
Test status
Simulation time 161876288 ps
CPU time 1.72 seconds
Started Jul 25 04:45:26 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 209736 kb
Host smart-0ac08cc7-fa5f-4cb2-83d8-e076789bc5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444054048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1444054048
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2432696475
Short name T672
Test name
Test status
Simulation time 60888683 ps
CPU time 0.91 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 205828 kb
Host smart-34a4d7c0-ae63-47a1-a4c7-407900f10bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432696475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2432696475
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1892811633
Short name T27
Test name
Test status
Simulation time 2245856016 ps
CPU time 5.45 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 216280 kb
Host smart-1bfff32f-0d13-49a6-96a9-fbbd2bd89676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892811633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1892811633
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1174172880
Short name T890
Test name
Test status
Simulation time 151113911 ps
CPU time 2.08 seconds
Started Jul 25 04:45:12 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 208840 kb
Host smart-19e171c4-f771-4ca8-ba47-5f7e61fead8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174172880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1174172880
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2913078060
Short name T840
Test name
Test status
Simulation time 42297151 ps
CPU time 2.3 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 214192 kb
Host smart-7a86bed2-04d2-4e60-a384-2e0f7dcf29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913078060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2913078060
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1566368277
Short name T278
Test name
Test status
Simulation time 297211673 ps
CPU time 2.63 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 214232 kb
Host smart-f66bd81d-0ddb-4c6a-b115-4648189a0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566368277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1566368277
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.984760050
Short name T495
Test name
Test status
Simulation time 33039973 ps
CPU time 2.1 seconds
Started Jul 25 04:45:10 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 215456 kb
Host smart-36eccbb2-55ed-4d32-b36e-d6a3b7fb5a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984760050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.984760050
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3231176183
Short name T814
Test name
Test status
Simulation time 390641426 ps
CPU time 4.34 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 207236 kb
Host smart-f525d680-d65f-48c7-b781-d3617e73335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231176183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3231176183
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1520526769
Short name T653
Test name
Test status
Simulation time 43104682 ps
CPU time 1.94 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 208504 kb
Host smart-fb05acc7-2480-48b6-92b3-8f8624edbecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520526769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1520526769
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1019067014
Short name T739
Test name
Test status
Simulation time 60736940 ps
CPU time 3.1 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 208592 kb
Host smart-918383bb-928f-429e-9fbc-ce01c5c52aee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019067014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1019067014
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3430658814
Short name T550
Test name
Test status
Simulation time 2998370808 ps
CPU time 30.37 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 208080 kb
Host smart-58aba31d-088b-40a0-b7d3-ded17034e265
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430658814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3430658814
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.534999423
Short name T428
Test name
Test status
Simulation time 56920629 ps
CPU time 2.94 seconds
Started Jul 25 04:45:05 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 208292 kb
Host smart-b540c991-c2cc-4ca0-947d-fa5cae46fce4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534999423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.534999423
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.60308913
Short name T521
Test name
Test status
Simulation time 335028287 ps
CPU time 8.18 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 207916 kb
Host smart-7f527aa0-9133-4a52-8473-0f5077b99dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60308913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.60308913
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1237962903
Short name T770
Test name
Test status
Simulation time 768212695 ps
CPU time 15.33 seconds
Started Jul 25 04:45:12 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 207580 kb
Host smart-32fa4ebe-7f2f-4ec0-9e5e-e7f70f2dcb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237962903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1237962903
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3318928545
Short name T808
Test name
Test status
Simulation time 1192667382 ps
CPU time 10.17 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 220692 kb
Host smart-2b3dd92d-b3c1-4659-946d-38285d76f508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318928545 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3318928545
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2594875212
Short name T481
Test name
Test status
Simulation time 388981692 ps
CPU time 3.5 seconds
Started Jul 25 04:45:10 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 214128 kb
Host smart-01b203bd-0fc3-4ba2-bbf2-a59bdf5ecb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594875212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2594875212
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.284738356
Short name T557
Test name
Test status
Simulation time 401909107 ps
CPU time 3.5 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 210264 kb
Host smart-9f7b2269-7794-410a-b87d-490f4300aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284738356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.284738356
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.643291438
Short name T775
Test name
Test status
Simulation time 14481712 ps
CPU time 0.76 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 205704 kb
Host smart-87ea0113-9744-4909-b7fc-ea482f85fb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643291438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.643291438
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1515932275
Short name T397
Test name
Test status
Simulation time 84402906 ps
CPU time 4.87 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:16 PM PDT 24
Peak memory 214004 kb
Host smart-28aba223-2e15-4b8f-b00e-8a4170ca4379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515932275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1515932275
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2891002485
Short name T784
Test name
Test status
Simulation time 163768866 ps
CPU time 3.23 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 216412 kb
Host smart-db06695a-2b6c-406f-9950-6b5ff8e4f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891002485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2891002485
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.440552306
Short name T636
Test name
Test status
Simulation time 543268671 ps
CPU time 4.7 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:05 PM PDT 24
Peak memory 207132 kb
Host smart-5f56baf0-01d0-470a-8b61-7a934402b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440552306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.440552306
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3105197455
Short name T294
Test name
Test status
Simulation time 508995786 ps
CPU time 5.25 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:18 PM PDT 24
Peak memory 214160 kb
Host smart-153150d6-d570-4656-bb44-ba9319a9a213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105197455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3105197455
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1548590919
Short name T7
Test name
Test status
Simulation time 250776047 ps
CPU time 3.19 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 219176 kb
Host smart-50a2cc4a-ceea-43c0-835c-8836aca6fee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548590919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1548590919
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.785800758
Short name T355
Test name
Test status
Simulation time 98400529 ps
CPU time 3.8 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 214108 kb
Host smart-afe414fd-eabd-4043-92fc-c3bcec6b61bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785800758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.785800758
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1437965454
Short name T234
Test name
Test status
Simulation time 83489812 ps
CPU time 2.85 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 207712 kb
Host smart-d6ee3296-cded-4936-92d9-c833c12b8763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437965454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1437965454
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3545876406
Short name T314
Test name
Test status
Simulation time 1585302049 ps
CPU time 7.64 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 208352 kb
Host smart-49953229-7591-4720-9f06-d64c7134b19b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545876406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3545876406
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3098185246
Short name T723
Test name
Test status
Simulation time 652540034 ps
CPU time 5.12 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 208684 kb
Host smart-020ff072-a293-402b-8e26-9e1189bb67a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098185246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3098185246
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1352535804
Short name T488
Test name
Test status
Simulation time 42166012 ps
CPU time 2.69 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 208672 kb
Host smart-78631d4e-b469-4745-810b-aa4a7bba6eb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352535804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1352535804
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.53735415
Short name T719
Test name
Test status
Simulation time 119592154 ps
CPU time 2.48 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 222208 kb
Host smart-ef5857cf-ca20-4065-9335-bf001a635d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53735415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.53735415
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3253498174
Short name T675
Test name
Test status
Simulation time 454679452 ps
CPU time 3.6 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:24 PM PDT 24
Peak memory 208256 kb
Host smart-d82da841-4650-48a7-946e-1209836ab572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253498174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3253498174
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3386445818
Short name T743
Test name
Test status
Simulation time 2114044221 ps
CPU time 9.69 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 222276 kb
Host smart-f0178fba-349b-42ec-827b-08574a5a22b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386445818 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3386445818
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.485538735
Short name T861
Test name
Test status
Simulation time 63484522 ps
CPU time 2.98 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 207896 kb
Host smart-2e83c303-bdd0-483c-9938-3ffae3c25ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485538735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.485538735
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.757304766
Short name T44
Test name
Test status
Simulation time 869404148 ps
CPU time 8.33 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 210632 kb
Host smart-b545e529-3865-4178-9a4b-bbcb922a59c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757304766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.757304766
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.752423837
Short name T789
Test name
Test status
Simulation time 17752707 ps
CPU time 0.78 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 205744 kb
Host smart-b9b5b73a-000e-47fd-937e-6dd6da3fc2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752423837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.752423837
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1687817388
Short name T605
Test name
Test status
Simulation time 131368951 ps
CPU time 2.65 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 214308 kb
Host smart-d20818a3-e5b8-46bc-9b32-e1ebf1a5e184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687817388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1687817388
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1086042083
Short name T20
Test name
Test status
Simulation time 210880346 ps
CPU time 8.66 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 222412 kb
Host smart-2c433b58-0ce6-4085-a81b-97373dba673c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086042083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1086042083
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.746959436
Short name T749
Test name
Test status
Simulation time 119712999 ps
CPU time 3.51 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 207856 kb
Host smart-aa93645e-afc1-4642-9d04-901d94ce8ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746959436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.746959436
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3602155524
Short name T624
Test name
Test status
Simulation time 48572306 ps
CPU time 3.45 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 207264 kb
Host smart-9cce6623-489a-4072-8a06-660f1dc20e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602155524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3602155524
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3411615220
Short name T804
Test name
Test status
Simulation time 2704719439 ps
CPU time 29.28 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 208976 kb
Host smart-8ae6ed4a-44f1-4951-8cbc-9043e9da5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411615220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3411615220
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.788634865
Short name T443
Test name
Test status
Simulation time 993578760 ps
CPU time 5.99 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 208228 kb
Host smart-532103ea-4ad9-4a00-a5a5-24f07fce57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788634865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.788634865
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2226892062
Short name T663
Test name
Test status
Simulation time 350747507 ps
CPU time 7.91 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 208172 kb
Host smart-98ad9928-1bb9-4db6-9028-e78387bb4db2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226892062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2226892062
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2486812122
Short name T638
Test name
Test status
Simulation time 883135011 ps
CPU time 8.75 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 207564 kb
Host smart-3cc36e07-99be-4ced-bd20-39d37f35fc9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486812122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2486812122
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1823893179
Short name T282
Test name
Test status
Simulation time 84445933 ps
CPU time 3.72 seconds
Started Jul 25 04:45:06 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 208632 kb
Host smart-1cbc794f-bd15-4de6-b7b7-d49164079af6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823893179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1823893179
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1468492567
Short name T447
Test name
Test status
Simulation time 685174944 ps
CPU time 11.71 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 208732 kb
Host smart-72cb2544-7224-4831-905e-0743f938317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468492567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1468492567
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3134370624
Short name T795
Test name
Test status
Simulation time 370803186 ps
CPU time 4.16 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 207076 kb
Host smart-36f6a507-08cb-4582-9dc5-5cca01de33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134370624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3134370624
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2112134251
Short name T560
Test name
Test status
Simulation time 119151333 ps
CPU time 2.39 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 208596 kb
Host smart-c586fb46-0c3a-41bb-a893-8c936a623b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112134251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2112134251
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.814079542
Short name T862
Test name
Test status
Simulation time 91807841 ps
CPU time 2.01 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:20 PM PDT 24
Peak memory 209748 kb
Host smart-4625cc78-ca03-4b77-afe8-4b8cf6b38999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814079542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.814079542
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1850704775
Short name T425
Test name
Test status
Simulation time 14830290 ps
CPU time 0.91 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 205804 kb
Host smart-5926be79-a42b-4756-b9e8-fd8476e4d18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850704775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1850704775
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1555380105
Short name T778
Test name
Test status
Simulation time 1532153082 ps
CPU time 4.52 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 221568 kb
Host smart-9b64370c-17c0-458f-ae6f-c4495c1036dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555380105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1555380105
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2806151808
Short name T545
Test name
Test status
Simulation time 55138529 ps
CPU time 2.26 seconds
Started Jul 25 04:45:31 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 209652 kb
Host smart-4ccd4174-62e5-481c-8eef-2fad6b441e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806151808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2806151808
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2983039520
Short name T260
Test name
Test status
Simulation time 45059686 ps
CPU time 2.38 seconds
Started Jul 25 04:45:40 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 222116 kb
Host smart-183e4ae4-0a12-4319-af9d-0b4e516da78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983039520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2983039520
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.695265626
Short name T538
Test name
Test status
Simulation time 109544140 ps
CPU time 3.88 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 208204 kb
Host smart-c6a063ea-ca1e-4ddf-a9db-33c63c71e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695265626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.695265626
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1626487208
Short name T487
Test name
Test status
Simulation time 59101712 ps
CPU time 2.25 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 206620 kb
Host smart-772fe471-a20e-4fbc-aa3b-cf0a235f9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626487208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1626487208
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2647817886
Short name T581
Test name
Test status
Simulation time 1495674582 ps
CPU time 32.85 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:46:11 PM PDT 24
Peak memory 208408 kb
Host smart-9bf3baae-b33f-4992-9c2d-5adff5fc0f96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647817886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2647817886
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.932120752
Short name T449
Test name
Test status
Simulation time 108650034 ps
CPU time 3.26 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:10 PM PDT 24
Peak memory 208384 kb
Host smart-3bb84f58-bb4e-49f2-8cbe-0037101f22fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932120752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.932120752
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3102661279
Short name T477
Test name
Test status
Simulation time 527849737 ps
CPU time 3.71 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 206648 kb
Host smart-6c2e53e4-543f-4379-b291-44899e9d9ab5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102661279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3102661279
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1196829863
Short name T602
Test name
Test status
Simulation time 82488931 ps
CPU time 2.85 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 217976 kb
Host smart-06d89957-1791-4029-aefc-e4c68222f253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196829863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1196829863
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3691499988
Short name T193
Test name
Test status
Simulation time 50581344 ps
CPU time 2.39 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:13 PM PDT 24
Peak memory 207852 kb
Host smart-9c487839-9b33-4819-aa1a-0dbc8cdb1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691499988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3691499988
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4141576784
Short name T907
Test name
Test status
Simulation time 254686728 ps
CPU time 13.95 seconds
Started Jul 25 04:45:17 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 215852 kb
Host smart-2848aa80-842d-420c-bbf1-b75b535fdc8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141576784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4141576784
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1408090444
Short name T489
Test name
Test status
Simulation time 102736351 ps
CPU time 3.41 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 209496 kb
Host smart-35dc87e2-ea0d-4213-9f2d-f420d73a914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408090444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1408090444
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3065474135
Short name T805
Test name
Test status
Simulation time 389909610 ps
CPU time 2.65 seconds
Started Jul 25 04:45:32 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 210272 kb
Host smart-29513e3b-c130-4476-8629-68872923dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065474135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3065474135
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3142467052
Short name T786
Test name
Test status
Simulation time 10053868 ps
CPU time 0.81 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 205792 kb
Host smart-7e1cbb72-7b03-4327-ae37-b522581f74c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142467052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3142467052
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1735595501
Short name T246
Test name
Test status
Simulation time 203018366 ps
CPU time 10.13 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 214040 kb
Host smart-1bb397af-f278-44d3-80c7-592cc06495e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735595501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1735595501
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4115414185
Short name T590
Test name
Test status
Simulation time 96817744 ps
CPU time 3.84 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:38 PM PDT 24
Peak memory 207976 kb
Host smart-3fc48002-1f4c-4d49-ab33-8da7debd3f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115414185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4115414185
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1367032733
Short name T255
Test name
Test status
Simulation time 90862195 ps
CPU time 2.92 seconds
Started Jul 25 04:45:12 PM PDT 24
Finished Jul 25 04:45:15 PM PDT 24
Peak memory 209932 kb
Host smart-aff4d240-445b-46cb-9832-870f9e5ac809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367032733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1367032733
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2597958251
Short name T767
Test name
Test status
Simulation time 45702564 ps
CPU time 2.83 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 208964 kb
Host smart-69bd1f86-1647-4249-a7bb-0c5869949683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597958251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2597958251
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1772303443
Short name T704
Test name
Test status
Simulation time 64031578 ps
CPU time 2.54 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:36 PM PDT 24
Peak memory 221536 kb
Host smart-af708731-48f5-47f1-9e65-1f514f742665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772303443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1772303443
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3065902856
Short name T220
Test name
Test status
Simulation time 1202608123 ps
CPU time 4.35 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 218320 kb
Host smart-ae9e06d2-e6d3-420b-a306-7c0e0692b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065902856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3065902856
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.373849090
Short name T684
Test name
Test status
Simulation time 50987523 ps
CPU time 3.28 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 207304 kb
Host smart-7f269d40-ffe1-4570-9119-a938b9544f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373849090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.373849090
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3593271429
Short name T612
Test name
Test status
Simulation time 48545748 ps
CPU time 2.69 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:27 PM PDT 24
Peak memory 206608 kb
Host smart-eb2efe74-740c-42d6-9cf7-79645e22817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593271429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3593271429
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1846266254
Short name T393
Test name
Test status
Simulation time 48239433 ps
CPU time 2.37 seconds
Started Jul 25 04:45:16 PM PDT 24
Finished Jul 25 04:45:19 PM PDT 24
Peak memory 206540 kb
Host smart-8c0dd8a6-c954-4c1a-8cde-2e31d78acc9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846266254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1846266254
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2772638514
Short name T518
Test name
Test status
Simulation time 166313340 ps
CPU time 6.36 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 208540 kb
Host smart-b35e0f31-ae43-4ba9-bb85-7b29dcd023b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772638514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2772638514
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3868480175
Short name T608
Test name
Test status
Simulation time 64524684 ps
CPU time 3.32 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 206704 kb
Host smart-17892c28-e027-4c09-8c4d-b256ef158ddc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868480175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3868480175
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1562361232
Short name T544
Test name
Test status
Simulation time 57044590 ps
CPU time 2.44 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:17 PM PDT 24
Peak memory 208548 kb
Host smart-7ad443ba-e9ef-4073-baa2-2f0a9d4007b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562361232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1562361232
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.190084340
Short name T129
Test name
Test status
Simulation time 321053451 ps
CPU time 3.29 seconds
Started Jul 25 04:44:57 PM PDT 24
Finished Jul 25 04:45:01 PM PDT 24
Peak memory 208092 kb
Host smart-e1f5b8b8-e50d-42f8-af97-660fad396add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190084340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.190084340
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1484612558
Short name T218
Test name
Test status
Simulation time 853127470 ps
CPU time 31.07 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 215176 kb
Host smart-27e7202c-e074-416d-a9df-9ee925dbd140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484612558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1484612558
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3588043272
Short name T69
Test name
Test status
Simulation time 580889682 ps
CPU time 7.44 seconds
Started Jul 25 04:45:17 PM PDT 24
Finished Jul 25 04:45:24 PM PDT 24
Peak memory 219844 kb
Host smart-fb552218-9011-4d99-bcff-354978ec4c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588043272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3588043272
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3123390221
Short name T105
Test name
Test status
Simulation time 94690265 ps
CPU time 4.23 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 207436 kb
Host smart-8122ea87-a4ac-4206-9ee3-0a775b411805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123390221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3123390221
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2957832634
Short name T711
Test name
Test status
Simulation time 51621110 ps
CPU time 2.08 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 209892 kb
Host smart-045119dd-b155-476d-baef-6f513b336f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957832634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2957832634
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3634358999
Short name T651
Test name
Test status
Simulation time 21659957 ps
CPU time 0.78 seconds
Started Jul 25 04:45:34 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 205860 kb
Host smart-412390fe-0e95-4712-904d-bf403324ec7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634358999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3634358999
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1486004467
Short name T900
Test name
Test status
Simulation time 140558240 ps
CPU time 3.39 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 216148 kb
Host smart-4bcbcb1d-93f1-49cc-95ab-26a66efd7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486004467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1486004467
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2160442668
Short name T834
Test name
Test status
Simulation time 98029337 ps
CPU time 2.42 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:24 PM PDT 24
Peak memory 207136 kb
Host smart-dd8c2771-1cff-4d15-9102-88b4e02945d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160442668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2160442668
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1197524170
Short name T236
Test name
Test status
Simulation time 88730109 ps
CPU time 3.23 seconds
Started Jul 25 04:45:32 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 214068 kb
Host smart-546ddf31-e1e1-4699-80a9-27926e2e7cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197524170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1197524170
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.269071639
Short name T660
Test name
Test status
Simulation time 451583842 ps
CPU time 7.54 seconds
Started Jul 25 04:44:59 PM PDT 24
Finished Jul 25 04:45:07 PM PDT 24
Peak memory 220760 kb
Host smart-99c026b8-93e1-4dfb-9f00-ea8d2818a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269071639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.269071639
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2553417601
Short name T579
Test name
Test status
Simulation time 244421073 ps
CPU time 2.45 seconds
Started Jul 25 04:45:34 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 214044 kb
Host smart-8fc40afb-9004-49fb-a034-6977b056d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553417601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2553417601
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.669931036
Short name T99
Test name
Test status
Simulation time 135069717 ps
CPU time 2.52 seconds
Started Jul 25 04:45:00 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 207160 kb
Host smart-2b65b240-5217-4b86-ad1f-a9788020c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669931036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.669931036
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1569845492
Short name T300
Test name
Test status
Simulation time 320593065 ps
CPU time 5.04 seconds
Started Jul 25 04:45:04 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 208416 kb
Host smart-492d2b11-4e08-4f49-a694-650e082a735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569845492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1569845492
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2004753266
Short name T506
Test name
Test status
Simulation time 2683947467 ps
CPU time 17.36 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 208844 kb
Host smart-5c458abb-b4ed-4018-b48a-4e30b4f7f3e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004753266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2004753266
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1391353911
Short name T204
Test name
Test status
Simulation time 65162887 ps
CPU time 2.8 seconds
Started Jul 25 04:44:58 PM PDT 24
Finished Jul 25 04:45:01 PM PDT 24
Peak memory 207996 kb
Host smart-37172e77-245a-4487-bc7a-6d7ef49c93a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391353911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1391353911
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1383687985
Short name T658
Test name
Test status
Simulation time 151339757 ps
CPU time 3.03 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 207872 kb
Host smart-10a2ebb2-f740-4d0a-a194-843415d951f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383687985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1383687985
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1829759692
Short name T306
Test name
Test status
Simulation time 33352075 ps
CPU time 2.12 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 215596 kb
Host smart-ee8b3f2f-8b8e-416e-8f32-1f11a1dd4a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829759692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1829759692
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1736812516
Short name T433
Test name
Test status
Simulation time 58683215 ps
CPU time 2.43 seconds
Started Jul 25 04:45:34 PM PDT 24
Finished Jul 25 04:45:36 PM PDT 24
Peak memory 205848 kb
Host smart-e15f750b-9f12-4c05-8976-312ddefeff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736812516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1736812516
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1447295742
Short name T216
Test name
Test status
Simulation time 105304370 ps
CPU time 3.31 seconds
Started Jul 25 04:44:56 PM PDT 24
Finished Jul 25 04:45:04 PM PDT 24
Peak memory 219688 kb
Host smart-66e81eb8-bca5-40e2-86e5-f5d5a919d67c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447295742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1447295742
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.173438947
Short name T357
Test name
Test status
Simulation time 496209178 ps
CPU time 6.63 seconds
Started Jul 25 04:45:32 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 209464 kb
Host smart-814593cd-3f56-4274-85e7-cb99d8352925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173438947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.173438947
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1019041395
Short name T779
Test name
Test status
Simulation time 298998917 ps
CPU time 3.44 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:42 PM PDT 24
Peak memory 210260 kb
Host smart-617884db-9d6e-48e3-b58e-627376afd7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019041395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1019041395
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2453233966
Short name T601
Test name
Test status
Simulation time 55356909 ps
CPU time 0.79 seconds
Started Jul 25 04:45:40 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 205764 kb
Host smart-eea4b88d-1f7e-4362-8a09-c49df3e360dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453233966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2453233966
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4087474775
Short name T410
Test name
Test status
Simulation time 323830260 ps
CPU time 3.2 seconds
Started Jul 25 04:45:25 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 214048 kb
Host smart-47237aa4-063b-4efe-b4fc-17af1650a0d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087474775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4087474775
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.547546864
Short name T720
Test name
Test status
Simulation time 178483842 ps
CPU time 2.93 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 207036 kb
Host smart-5c7880a8-38e4-44bd-bd84-3303903e6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547546864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.547546864
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3079292189
Short name T516
Test name
Test status
Simulation time 376259962 ps
CPU time 4.3 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 207896 kb
Host smart-be417cca-1e1f-4b1e-8607-94e629d3ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079292189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3079292189
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.593703878
Short name T796
Test name
Test status
Simulation time 56655255 ps
CPU time 2.03 seconds
Started Jul 25 04:45:11 PM PDT 24
Finished Jul 25 04:45:14 PM PDT 24
Peak memory 214080 kb
Host smart-6a4bca83-2caa-492d-b686-01e9f30073da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593703878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.593703878
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.319407148
Short name T879
Test name
Test status
Simulation time 64464919 ps
CPU time 3.89 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 220228 kb
Host smart-95542719-4c4d-489b-b9f0-84dfd202c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319407148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.319407148
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1496253660
Short name T188
Test name
Test status
Simulation time 29700705 ps
CPU time 2.17 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:42 PM PDT 24
Peak memory 207512 kb
Host smart-f6285566-cc29-4c6b-865f-70ea4b83da59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496253660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1496253660
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1490930142
Short name T896
Test name
Test status
Simulation time 70906095 ps
CPU time 3.18 seconds
Started Jul 25 04:45:20 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 208604 kb
Host smart-b79ee92f-b9d6-4a32-ae66-c60dc06eb05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490930142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1490930142
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2564298179
Short name T551
Test name
Test status
Simulation time 291160245 ps
CPU time 2.21 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 207156 kb
Host smart-c9665f15-36c0-47eb-b6f8-bb9f3a14ff39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564298179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2564298179
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3239288125
Short name T132
Test name
Test status
Simulation time 4858614665 ps
CPU time 14.99 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 207644 kb
Host smart-590990b5-2c56-4eb1-817f-5488dc8ca904
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239288125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3239288125
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1846865587
Short name T107
Test name
Test status
Simulation time 127074309 ps
CPU time 4.55 seconds
Started Jul 25 04:45:26 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 208688 kb
Host smart-0b274859-37b0-416c-ae29-b138b485c0cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846865587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1846865587
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.483863710
Short name T380
Test name
Test status
Simulation time 26611618 ps
CPU time 1.78 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 208368 kb
Host smart-35a16575-ca79-448c-a88b-370360a2df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483863710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.483863710
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3244529984
Short name T700
Test name
Test status
Simulation time 122721561 ps
CPU time 2.79 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 208424 kb
Host smart-cbf89717-e726-4182-8f8a-8de0a13bff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244529984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3244529984
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2298561311
Short name T326
Test name
Test status
Simulation time 12441257227 ps
CPU time 43.16 seconds
Started Jul 25 04:45:18 PM PDT 24
Finished Jul 25 04:46:07 PM PDT 24
Peak memory 215696 kb
Host smart-df6f53b2-cdf8-4a87-9769-e56c2988aba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298561311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2298561311
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3159743466
Short name T250
Test name
Test status
Simulation time 124444915 ps
CPU time 5.61 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:19 PM PDT 24
Peak memory 218356 kb
Host smart-73446b12-9c98-4453-900b-9702af36bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159743466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3159743466
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1047661558
Short name T175
Test name
Test status
Simulation time 206169815 ps
CPU time 2.21 seconds
Started Jul 25 04:45:07 PM PDT 24
Finished Jul 25 04:45:09 PM PDT 24
Peak memory 209580 kb
Host smart-7feb0192-9db2-49bd-9189-4e169d8d1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047661558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1047661558
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3352744007
Short name T533
Test name
Test status
Simulation time 13402486 ps
CPU time 0.75 seconds
Started Jul 25 04:44:19 PM PDT 24
Finished Jul 25 04:44:20 PM PDT 24
Peak memory 205776 kb
Host smart-213e4060-c372-4b70-af0c-18f1b4f3d31f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352744007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3352744007
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.114662259
Short name T532
Test name
Test status
Simulation time 108424258 ps
CPU time 3.52 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:42 PM PDT 24
Peak memory 208144 kb
Host smart-5997446a-0a53-42e2-a565-baf592fafdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114662259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.114662259
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1173428103
Short name T485
Test name
Test status
Simulation time 192632206 ps
CPU time 2.18 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:27 PM PDT 24
Peak memory 207212 kb
Host smart-ef0387aa-a5fa-431b-8a51-502420153e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173428103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1173428103
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3367577245
Short name T718
Test name
Test status
Simulation time 157721204 ps
CPU time 3.95 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 214020 kb
Host smart-c02e4f94-db20-47fc-9d3d-0fa176c56742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367577245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3367577245
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1665599525
Short name T37
Test name
Test status
Simulation time 139890464 ps
CPU time 2.58 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 205760 kb
Host smart-3368dad0-f87b-4343-a3c0-be6011d98476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665599525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1665599525
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2264680321
Short name T515
Test name
Test status
Simulation time 220182767 ps
CPU time 3.93 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 209564 kb
Host smart-aa2e5308-74e5-4431-99fe-78575fb05dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264680321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2264680321
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1124134919
Short name T273
Test name
Test status
Simulation time 85920709 ps
CPU time 4.71 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:14 PM PDT 24
Peak memory 217980 kb
Host smart-ff84e774-bc11-40eb-a54b-a01fc9f9c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124134919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1124134919
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2581946376
Short name T678
Test name
Test status
Simulation time 745663050 ps
CPU time 4.87 seconds
Started Jul 25 04:44:07 PM PDT 24
Finished Jul 25 04:44:12 PM PDT 24
Peak memory 207780 kb
Host smart-da509a27-aa50-4581-8ff9-11b19d2d9ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581946376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2581946376
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.180305898
Short name T860
Test name
Test status
Simulation time 91764879 ps
CPU time 2.07 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 208304 kb
Host smart-1a9391db-adf4-46eb-9a2a-2061cd51f6a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180305898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.180305898
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4001756747
Short name T473
Test name
Test status
Simulation time 140376492 ps
CPU time 4.98 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 207880 kb
Host smart-6b18794c-04f3-4c61-8906-21bc39937518
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001756747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4001756747
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.448902444
Short name T304
Test name
Test status
Simulation time 168023884 ps
CPU time 3.18 seconds
Started Jul 25 04:44:18 PM PDT 24
Finished Jul 25 04:44:22 PM PDT 24
Peak memory 207700 kb
Host smart-6cd95ce0-4c2e-4c5f-ab93-67c4144459df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448902444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.448902444
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.372039357
Short name T17
Test name
Test status
Simulation time 364713690 ps
CPU time 4.58 seconds
Started Jul 25 04:44:34 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 206560 kb
Host smart-d633d0bd-3404-44e3-a163-c6cc7c04c976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372039357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.372039357
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1162212554
Short name T286
Test name
Test status
Simulation time 2396890250 ps
CPU time 14.6 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:14 PM PDT 24
Peak memory 214872 kb
Host smart-9b59eb67-8c92-479c-b12b-7ca33a50a59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162212554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1162212554
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2272537525
Short name T741
Test name
Test status
Simulation time 258725201 ps
CPU time 3.47 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 207356 kb
Host smart-e6410f32-c502-4717-9b37-0e2426718377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272537525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2272537525
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1098018895
Short name T815
Test name
Test status
Simulation time 48337350 ps
CPU time 1.69 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 209584 kb
Host smart-ae85a467-372e-43fc-ab15-c3e4c6e44a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098018895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1098018895
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1858383772
Short name T412
Test name
Test status
Simulation time 104560620 ps
CPU time 0.92 seconds
Started Jul 25 04:45:17 PM PDT 24
Finished Jul 25 04:45:18 PM PDT 24
Peak memory 205824 kb
Host smart-48d6ea30-dc6e-42df-8a9b-1ce9a3f720ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858383772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1858383772
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.282858308
Short name T317
Test name
Test status
Simulation time 688450867 ps
CPU time 13.83 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 214816 kb
Host smart-3e052bf9-c460-4352-876a-c2eaa5acbcf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282858308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.282858308
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.597890931
Short name T705
Test name
Test status
Simulation time 1240168255 ps
CPU time 4.65 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:19 PM PDT 24
Peak memory 221236 kb
Host smart-7efd8585-1911-4187-b6e5-da5042b16952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597890931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.597890931
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.90880035
Short name T503
Test name
Test status
Simulation time 328742564 ps
CPU time 4.47 seconds
Started Jul 25 04:45:32 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 210208 kb
Host smart-33880fbe-9c0d-4512-9f9d-4aae087d5475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90880035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.90880035
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1723609356
Short name T552
Test name
Test status
Simulation time 103008674 ps
CPU time 2.14 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:29 PM PDT 24
Peak memory 214036 kb
Host smart-05aac16f-b7a0-4dbd-8def-2a08c52b93fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723609356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1723609356
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2165426973
Short name T261
Test name
Test status
Simulation time 107834471 ps
CPU time 2.21 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 220760 kb
Host smart-4fd15cf3-70aa-4632-a2ed-8346b2e137b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165426973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2165426973
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2060338388
Short name T829
Test name
Test status
Simulation time 76587803 ps
CPU time 3.09 seconds
Started Jul 25 04:45:30 PM PDT 24
Finished Jul 25 04:45:33 PM PDT 24
Peak memory 214020 kb
Host smart-5021163a-da12-4f4a-85ca-49b7c4ad4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060338388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2060338388
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3549783168
Short name T872
Test name
Test status
Simulation time 897200137 ps
CPU time 20.71 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 209996 kb
Host smart-691d9d5d-af5d-4006-8742-e7e5e8e471a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549783168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3549783168
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3732882629
Short name T537
Test name
Test status
Simulation time 346352155 ps
CPU time 4.31 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 206596 kb
Host smart-a27a62e9-8ed0-4aed-b892-88db9dd62ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732882629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3732882629
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.989356661
Short name T828
Test name
Test status
Simulation time 644997169 ps
CPU time 5.03 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 208412 kb
Host smart-18a1ae0c-6750-4f37-adf7-7146609a9eeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989356661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.989356661
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1096314832
Short name T251
Test name
Test status
Simulation time 175112927 ps
CPU time 2.42 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 206728 kb
Host smart-792b279d-75c7-49c4-a36e-143f7bda20c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096314832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1096314832
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3074317569
Short name T644
Test name
Test status
Simulation time 940630552 ps
CPU time 17.71 seconds
Started Jul 25 04:45:19 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 207796 kb
Host smart-ccc23ce5-291a-4d5b-8c58-25983ac10f3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074317569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3074317569
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.147789049
Short name T268
Test name
Test status
Simulation time 98510275 ps
CPU time 3.61 seconds
Started Jul 25 04:45:22 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 214032 kb
Host smart-bb4ad778-c498-44d1-b8e3-5f35bf023af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147789049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.147789049
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1192422934
Short name T707
Test name
Test status
Simulation time 243183148 ps
CPU time 2.83 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 207916 kb
Host smart-0580d5b8-4534-4bbd-9290-6b6bd57d861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192422934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1192422934
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2300192922
Short name T471
Test name
Test status
Simulation time 98107585 ps
CPU time 2.98 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 215776 kb
Host smart-a2c8d61b-d9d4-4dc9-ae02-d5bb17b1affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300192922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2300192922
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1837943987
Short name T58
Test name
Test status
Simulation time 88766638 ps
CPU time 1.78 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 209864 kb
Host smart-0a27f829-d8a2-46a6-b3e1-b124a1cf83a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837943987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1837943987
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1637440600
Short name T415
Test name
Test status
Simulation time 17544054 ps
CPU time 0.73 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 205768 kb
Host smart-ede85b8f-d35c-4a60-a48c-dadd1f709acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637440600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1637440600
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1505949932
Short name T803
Test name
Test status
Simulation time 34487090 ps
CPU time 2.73 seconds
Started Jul 25 04:45:31 PM PDT 24
Finished Jul 25 04:45:34 PM PDT 24
Peak memory 215268 kb
Host smart-403fa320-c933-4dfc-b47f-dfc574237ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505949932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1505949932
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.567338201
Short name T432
Test name
Test status
Simulation time 116810048 ps
CPU time 3.55 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:28 PM PDT 24
Peak memory 209876 kb
Host smart-35843f1a-9006-410a-9e51-ce0c69ce5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567338201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.567338201
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1043077564
Short name T826
Test name
Test status
Simulation time 427960371 ps
CPU time 2 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:23 PM PDT 24
Peak memory 208332 kb
Host smart-7eac68bd-e536-4aa7-b603-2fc6bfba2d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043077564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1043077564
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4089638449
Short name T80
Test name
Test status
Simulation time 373768435 ps
CPU time 4.59 seconds
Started Jul 25 04:45:31 PM PDT 24
Finished Jul 25 04:45:36 PM PDT 24
Peak memory 214028 kb
Host smart-b68eb62f-e35e-43a5-8a32-697d2d6d166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089638449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4089638449
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.4267955907
Short name T655
Test name
Test status
Simulation time 142221243 ps
CPU time 3.82 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:22 PM PDT 24
Peak memory 213980 kb
Host smart-017ae8b3-cbc0-4e10-ae64-116bd7de44d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267955907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4267955907
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1424443071
Short name T748
Test name
Test status
Simulation time 69971985 ps
CPU time 3.43 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:25 PM PDT 24
Peak memory 214236 kb
Host smart-c8fa1ba4-a21c-43fd-9489-7705700ef5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424443071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1424443071
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2453371510
Short name T753
Test name
Test status
Simulation time 319024795 ps
CPU time 5.69 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 214088 kb
Host smart-210a52f3-baee-43e4-a7e0-c4ea2c520e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453371510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2453371510
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.13266018
Short name T323
Test name
Test status
Simulation time 69642188 ps
CPU time 2.51 seconds
Started Jul 25 04:45:13 PM PDT 24
Finished Jul 25 04:45:16 PM PDT 24
Peak memory 208440 kb
Host smart-90e5c292-edcc-4dcf-b285-d50119fc3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13266018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.13266018
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1694462460
Short name T458
Test name
Test status
Simulation time 263044428 ps
CPU time 3.28 seconds
Started Jul 25 04:45:14 PM PDT 24
Finished Jul 25 04:45:18 PM PDT 24
Peak memory 208776 kb
Host smart-ed556eb3-2b3e-4953-bc06-c8653ad5beb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694462460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1694462460
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1002009430
Short name T812
Test name
Test status
Simulation time 392209592 ps
CPU time 3.3 seconds
Started Jul 25 04:45:54 PM PDT 24
Finished Jul 25 04:45:57 PM PDT 24
Peak memory 208212 kb
Host smart-a6edf694-e27a-4e3b-b5e5-9f210db3801c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002009430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1002009430
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.235438925
Short name T275
Test name
Test status
Simulation time 34035494 ps
CPU time 1.65 seconds
Started Jul 25 04:45:24 PM PDT 24
Finished Jul 25 04:45:26 PM PDT 24
Peak memory 206544 kb
Host smart-367fd81d-6867-4019-b740-19b755495b04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235438925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.235438925
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1636530784
Short name T401
Test name
Test status
Simulation time 172289443 ps
CPU time 2.97 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:46:01 PM PDT 24
Peak memory 214108 kb
Host smart-14ad98a7-376d-4e70-b728-09b99c202513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636530784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1636530784
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.645221729
Short name T511
Test name
Test status
Simulation time 44666373 ps
CPU time 2.31 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 208104 kb
Host smart-bc76d338-d16e-4ce4-9b1a-637e51b995c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645221729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.645221729
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.378632331
Short name T213
Test name
Test status
Simulation time 1479878362 ps
CPU time 27.67 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:57 PM PDT 24
Peak memory 214872 kb
Host smart-92780801-4b07-41c3-b54c-06f6d9e046b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378632331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.378632331
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2603501115
Short name T836
Test name
Test status
Simulation time 40172497 ps
CPU time 2.5 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 214028 kb
Host smart-a6564879-5e7b-40b2-a84f-308c10a60dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603501115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2603501115
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1436982916
Short name T413
Test name
Test status
Simulation time 33117153 ps
CPU time 0.79 seconds
Started Jul 25 04:45:34 PM PDT 24
Finished Jul 25 04:45:35 PM PDT 24
Peak memory 205752 kb
Host smart-964fc6db-4af9-4f8a-9575-9b6215278e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436982916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1436982916
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2116923334
Short name T19
Test name
Test status
Simulation time 196296498 ps
CPU time 3.93 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 210352 kb
Host smart-2f847823-c406-41b8-93f9-f228d476a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116923334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2116923334
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2849764721
Short name T716
Test name
Test status
Simulation time 2150203061 ps
CPU time 15.8 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 214108 kb
Host smart-b96db3fa-f529-4058-bbee-c9463fe79d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849764721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2849764721
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1461095413
Short name T237
Test name
Test status
Simulation time 75134522 ps
CPU time 3.81 seconds
Started Jul 25 04:45:35 PM PDT 24
Finished Jul 25 04:45:39 PM PDT 24
Peak memory 214048 kb
Host smart-dab4e456-eae8-4817-a1b4-a9e7ed32be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461095413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1461095413
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1548249758
Short name T292
Test name
Test status
Simulation time 149460603 ps
CPU time 2.74 seconds
Started Jul 25 04:45:27 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 214088 kb
Host smart-6c651252-2079-450a-922e-190fd7408ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548249758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1548249758
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.537091992
Short name T729
Test name
Test status
Simulation time 205424863 ps
CPU time 3.51 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 219992 kb
Host smart-be91b2fe-380f-45fb-b5de-340235eddd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537091992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.537091992
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2156351280
Short name T470
Test name
Test status
Simulation time 75653495 ps
CPU time 1.7 seconds
Started Jul 25 04:45:23 PM PDT 24
Finished Jul 25 04:45:24 PM PDT 24
Peak memory 206812 kb
Host smart-f63dcf45-ac4d-4e0f-8220-a5f12c56f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156351280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2156351280
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.623018926
Short name T856
Test name
Test status
Simulation time 1246037208 ps
CPU time 37.27 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 208396 kb
Host smart-6a9d7541-c78a-49da-922c-d0a546a48bd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623018926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.623018926
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3630304232
Short name T676
Test name
Test status
Simulation time 1256743166 ps
CPU time 15.21 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 208228 kb
Host smart-cd4a71a7-42b7-47fd-a614-5b89c29eec1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630304232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3630304232
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3496943902
Short name T597
Test name
Test status
Simulation time 204129954 ps
CPU time 2.66 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 206712 kb
Host smart-e8f4d462-e903-4a1e-8336-35fb055b60b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496943902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3496943902
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1347047144
Short name T782
Test name
Test status
Simulation time 380778561 ps
CPU time 3.91 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 207644 kb
Host smart-8ee51248-2a04-4895-865f-d900f7619a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347047144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1347047144
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2325956719
Short name T381
Test name
Test status
Simulation time 387242036 ps
CPU time 8.21 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 208032 kb
Host smart-455bc34e-7a93-4437-a5df-64fe1a128938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325956719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2325956719
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1882731016
Short name T194
Test name
Test status
Simulation time 274669345 ps
CPU time 3.89 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:32 PM PDT 24
Peak memory 207348 kb
Host smart-3953e488-f92e-4b7b-9608-e3bd8db63547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882731016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1882731016
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.249530515
Short name T891
Test name
Test status
Simulation time 131503621 ps
CPU time 1.83 seconds
Started Jul 25 04:45:31 PM PDT 24
Finished Jul 25 04:45:33 PM PDT 24
Peak memory 209640 kb
Host smart-8135672d-48ac-418a-84a8-e596c7da44fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249530515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.249530515
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1215240296
Short name T717
Test name
Test status
Simulation time 61737599 ps
CPU time 0.91 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 205840 kb
Host smart-bb529349-2e75-4c0f-9992-b24b74ba3e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215240296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1215240296
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3595481639
Short name T254
Test name
Test status
Simulation time 408694682 ps
CPU time 6.58 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 214600 kb
Host smart-87249ab6-3e06-4b6a-9664-52ed32e4910f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595481639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3595481639
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3300930594
Short name T632
Test name
Test status
Simulation time 91784548 ps
CPU time 1.97 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 207404 kb
Host smart-919b28ba-e60b-4be5-a949-735ae6d0be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300930594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3300930594
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4057976813
Short name T321
Test name
Test status
Simulation time 68799966 ps
CPU time 2.86 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 214024 kb
Host smart-70d91a57-f112-4bd1-a1a5-6b543b85c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057976813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4057976813
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1664964180
Short name T689
Test name
Test status
Simulation time 110773050 ps
CPU time 3.66 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 220332 kb
Host smart-927b8f21-3494-4a0a-b50b-dff9ad573cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664964180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1664964180
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1902597134
Short name T54
Test name
Test status
Simulation time 133927025 ps
CPU time 2.91 seconds
Started Jul 25 04:45:28 PM PDT 24
Finished Jul 25 04:45:31 PM PDT 24
Peak memory 206888 kb
Host smart-2f59d1b3-31cc-4c05-82dc-7f37b6bd6f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902597134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1902597134
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3175778638
Short name T641
Test name
Test status
Simulation time 50011777 ps
CPU time 3.18 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:36 PM PDT 24
Peak memory 207080 kb
Host smart-30879b3a-f3e5-4d2f-9d6d-125d08af285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175778638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3175778638
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1513630603
Short name T364
Test name
Test status
Simulation time 60474542 ps
CPU time 3 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 208008 kb
Host smart-e73e519f-b4e8-40fb-9979-a6122bc0f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513630603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1513630603
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4092066558
Short name T635
Test name
Test status
Simulation time 243725216 ps
CPU time 3 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:42 PM PDT 24
Peak memory 208292 kb
Host smart-7381d914-e768-4f7a-899c-ae96dd0d950e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092066558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4092066558
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3202197819
Short name T444
Test name
Test status
Simulation time 35001420 ps
CPU time 2.29 seconds
Started Jul 25 04:45:21 PM PDT 24
Finished Jul 25 04:45:24 PM PDT 24
Peak memory 206588 kb
Host smart-190c7102-461f-434b-822c-746108749ae4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202197819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3202197819
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1216279988
Short name T614
Test name
Test status
Simulation time 73816663 ps
CPU time 3.6 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 208552 kb
Host smart-992e3adf-7a96-474f-befd-689eafc8ecc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216279988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1216279988
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3425857928
Short name T825
Test name
Test status
Simulation time 365194666 ps
CPU time 8.74 seconds
Started Jul 25 04:46:08 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 214068 kb
Host smart-e180bd79-8fbb-4a53-93d3-000eadabdf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425857928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3425857928
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1247816456
Short name T802
Test name
Test status
Simulation time 91527220 ps
CPU time 2.62 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 206564 kb
Host smart-7587598f-60ea-4a5b-a191-273413d3eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247816456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1247816456
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2363904853
Short name T746
Test name
Test status
Simulation time 419285904 ps
CPU time 15.99 seconds
Started Jul 25 04:45:29 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 221656 kb
Host smart-b4431b3c-98a4-452d-93c5-78ebcf8bf94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363904853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2363904853
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1233206147
Short name T721
Test name
Test status
Simulation time 1230527216 ps
CPU time 32.3 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 209324 kb
Host smart-4ec54140-c5fb-4021-afa9-e1cafac08b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233206147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1233206147
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3625724171
Short name T869
Test name
Test status
Simulation time 319630031 ps
CPU time 7.28 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 210756 kb
Host smart-4ecc665b-3a06-4353-b7fd-00289ee6f185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625724171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3625724171
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.238558490
Short name T887
Test name
Test status
Simulation time 124418867 ps
CPU time 0.7 seconds
Started Jul 25 04:45:42 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 205752 kb
Host smart-88720422-02c7-4272-8acf-ae733e340ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238558490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.238558490
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4252766107
Short name T757
Test name
Test status
Simulation time 2283548880 ps
CPU time 13.19 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:46:14 PM PDT 24
Peak memory 214100 kb
Host smart-178af91c-5f89-4a65-91fc-85edc8ad72d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252766107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4252766107
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1782278258
Short name T648
Test name
Test status
Simulation time 17758210401 ps
CPU time 21.15 seconds
Started Jul 25 04:46:03 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 210308 kb
Host smart-5648d269-9ffd-4a4d-80cc-58a750887a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782278258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1782278258
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1372222682
Short name T694
Test name
Test status
Simulation time 113778992 ps
CPU time 3.3 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 222064 kb
Host smart-a5ee0062-9515-43a1-b112-936639f41377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372222682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1372222682
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.352836534
Short name T61
Test name
Test status
Simulation time 260602851 ps
CPU time 3.02 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 209420 kb
Host smart-8f24bec3-39f8-4732-9f47-642749ac96a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352836534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.352836534
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2923941497
Short name T191
Test name
Test status
Simulation time 63687030 ps
CPU time 2.45 seconds
Started Jul 25 04:45:40 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 207240 kb
Host smart-ee45ba03-123b-44be-b5d9-33c1c6d59503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923941497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2923941497
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3943908722
Short name T531
Test name
Test status
Simulation time 153081564 ps
CPU time 2.34 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 206736 kb
Host smart-d32117a8-8d9f-411f-bbac-02c6c652a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943908722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3943908722
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2315685844
Short name T468
Test name
Test status
Simulation time 919820569 ps
CPU time 3.93 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:38 PM PDT 24
Peak memory 208224 kb
Host smart-443e6ede-08ea-46d9-97be-f330aa7b2bf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315685844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2315685844
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2372948307
Short name T594
Test name
Test status
Simulation time 646356049 ps
CPU time 7.85 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 206828 kb
Host smart-849f5e5c-0994-49fc-aaed-b42b16443617
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372948307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2372948307
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2872600681
Short name T755
Test name
Test status
Simulation time 66402564 ps
CPU time 2.42 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 206976 kb
Host smart-cb341f97-f171-4fe1-b4fa-67a127480070
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872600681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2872600681
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3184967172
Short name T852
Test name
Test status
Simulation time 42365253 ps
CPU time 2.31 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:41 PM PDT 24
Peak memory 215624 kb
Host smart-f6c36289-c278-47fd-900d-cba6e188ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184967172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3184967172
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.503978335
Short name T742
Test name
Test status
Simulation time 109076087 ps
CPU time 1.87 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 208456 kb
Host smart-8f6663ea-e03c-4eeb-9f44-6e6ced0a7097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503978335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.503978335
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3479165967
Short name T264
Test name
Test status
Simulation time 701208845 ps
CPU time 19.66 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 222208 kb
Host smart-4a7b7d4e-288d-421e-a28e-07a71ecda950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479165967 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3479165967
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3735202736
Short name T446
Test name
Test status
Simulation time 338482348 ps
CPU time 4.24 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 207196 kb
Host smart-13bd1a69-0080-40d7-a034-0c445d5dfb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735202736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3735202736
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.109280451
Short name T457
Test name
Test status
Simulation time 148805939 ps
CPU time 2.31 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 210100 kb
Host smart-46c0b4f6-90d6-4364-b930-aa7d3f35ab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109280451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.109280451
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2649522376
Short name T519
Test name
Test status
Simulation time 21074434 ps
CPU time 0.85 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 205744 kb
Host smart-bb11b637-001d-4e7c-ad7a-ff700d84c737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649522376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2649522376
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3104342107
Short name T134
Test name
Test status
Simulation time 112172072 ps
CPU time 3.63 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 214008 kb
Host smart-6cb3d910-5387-4888-a500-9b268fabd214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104342107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3104342107
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3981313424
Short name T267
Test name
Test status
Simulation time 119973927 ps
CPU time 3.05 seconds
Started Jul 25 04:45:33 PM PDT 24
Finished Jul 25 04:45:37 PM PDT 24
Peak memory 218068 kb
Host smart-0726cf75-251f-4b08-8b41-6a87a1786f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981313424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3981313424
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1317852554
Short name T224
Test name
Test status
Simulation time 229121314 ps
CPU time 4.89 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 208856 kb
Host smart-fb28cfea-67f3-4e80-a128-d1e8b441585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317852554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1317852554
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2364660724
Short name T463
Test name
Test status
Simulation time 171112778 ps
CPU time 5.84 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 214032 kb
Host smart-52de3b99-f9fa-41b9-b573-7f121a1beef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364660724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2364660724
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2061745593
Short name T233
Test name
Test status
Simulation time 389075431 ps
CPU time 12.15 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:08 PM PDT 24
Peak memory 214116 kb
Host smart-101b451f-5826-42c0-a48e-09e77daa01a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061745593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2061745593
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2956633734
Short name T202
Test name
Test status
Simulation time 287939867 ps
CPU time 3.4 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 208524 kb
Host smart-9f6e68ba-b7cf-4dad-b8c5-2a12bdb4ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956633734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2956633734
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2477631997
Short name T776
Test name
Test status
Simulation time 82510937 ps
CPU time 1.76 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 207304 kb
Host smart-717f0166-2f29-4e58-aa58-2e4bfdd87015
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477631997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2477631997
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3709118066
Short name T431
Test name
Test status
Simulation time 37011987 ps
CPU time 2.27 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 206688 kb
Host smart-15d1aac2-1ebb-4a75-b0d8-51e3900f26ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709118066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3709118066
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3055906535
Short name T813
Test name
Test status
Simulation time 118941297 ps
CPU time 3.06 seconds
Started Jul 25 04:45:40 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 208400 kb
Host smart-f908434b-4816-49da-baff-c646e1bb358b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055906535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3055906535
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1519418141
Short name T866
Test name
Test status
Simulation time 128330287 ps
CPU time 1.88 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 208708 kb
Host smart-d22e25d3-d4a6-4fe8-ae8e-eb53987bb1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519418141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1519418141
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1732448470
Short name T674
Test name
Test status
Simulation time 391225354 ps
CPU time 2.84 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:42 PM PDT 24
Peak memory 207144 kb
Host smart-c5e6240b-8350-49eb-8c83-ff478d971a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732448470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1732448470
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1357467435
Short name T434
Test name
Test status
Simulation time 593172088 ps
CPU time 7.09 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:12 PM PDT 24
Peak memory 209552 kb
Host smart-6305681c-97a1-4b36-8b16-e90016cf34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357467435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1357467435
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3445074252
Short name T564
Test name
Test status
Simulation time 364947931 ps
CPU time 2.81 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 210060 kb
Host smart-2e08345c-33d1-4ef5-8995-921796f159fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445074252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3445074252
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3557893465
Short name T93
Test name
Test status
Simulation time 25147386 ps
CPU time 0.82 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 205784 kb
Host smart-81d263e6-bde5-43e2-af61-5ce0e5dcbf55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557893465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3557893465
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2592460769
Short name T137
Test name
Test status
Simulation time 445640082 ps
CPU time 3.88 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 214280 kb
Host smart-2be444b4-5f28-4a78-ad16-757423df654a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592460769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2592460769
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1284078069
Short name T863
Test name
Test status
Simulation time 183002216 ps
CPU time 4.36 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 210384 kb
Host smart-0c1e1532-b787-4de8-986a-d100f30a5d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284078069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1284078069
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.191943454
Short name T800
Test name
Test status
Simulation time 175864153 ps
CPU time 3.58 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 218260 kb
Host smart-1664489f-3511-4c17-9e9e-d62b96e8d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191943454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.191943454
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1970613700
Short name T337
Test name
Test status
Simulation time 158951768 ps
CPU time 3.57 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 215124 kb
Host smart-5e656eaa-89aa-4b06-9cc2-bf98f1e7feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970613700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1970613700
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1416663900
Short name T280
Test name
Test status
Simulation time 512375453 ps
CPU time 3.23 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:08 PM PDT 24
Peak memory 222228 kb
Host smart-433415b9-b651-432a-b7d6-c9b3fe68a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416663900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1416663900
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4205566049
Short name T595
Test name
Test status
Simulation time 270322152 ps
CPU time 3.2 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 209456 kb
Host smart-9459eacf-cf78-41d3-b7cc-cc6a42eebaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205566049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4205566049
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3398353647
Short name T349
Test name
Test status
Simulation time 322607761 ps
CPU time 3.99 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 207052 kb
Host smart-c38d1926-e0a2-4422-95d6-95345f92413c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398353647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3398353647
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.523681709
Short name T865
Test name
Test status
Simulation time 323487973 ps
CPU time 3.58 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 208316 kb
Host smart-aa434ebc-350f-4ef4-b473-710a23e33dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523681709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.523681709
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2174649167
Short name T435
Test name
Test status
Simulation time 77460973 ps
CPU time 3.39 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 206680 kb
Host smart-3cbdbfde-e652-454b-b281-3c7deaf17130
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174649167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2174649167
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1700899790
Short name T536
Test name
Test status
Simulation time 347117827 ps
CPU time 3.21 seconds
Started Jul 25 04:45:36 PM PDT 24
Finished Jul 25 04:45:45 PM PDT 24
Peak memory 208464 kb
Host smart-023fd8ea-1938-4dad-8eb6-ac7e15c2a4df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700899790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1700899790
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2635146041
Short name T876
Test name
Test status
Simulation time 50545375 ps
CPU time 2.69 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 206532 kb
Host smart-79b37f1b-b141-4547-8678-5cf3ff3c8890
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635146041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2635146041
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3102277813
Short name T761
Test name
Test status
Simulation time 73384862 ps
CPU time 2.29 seconds
Started Jul 25 04:45:40 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 208536 kb
Host smart-802069f3-c41e-434a-96d7-fca061ffbccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102277813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3102277813
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.200260406
Short name T542
Test name
Test status
Simulation time 46456712 ps
CPU time 1.81 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 206872 kb
Host smart-8b4a8b57-ba3a-4827-b45f-39e88bf70ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200260406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.200260406
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2344425225
Short name T332
Test name
Test status
Simulation time 3009067796 ps
CPU time 54.18 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 216112 kb
Host smart-03815c9b-12b9-4435-b9e9-6dd9ccdf780c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344425225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2344425225
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.839645593
Short name T880
Test name
Test status
Simulation time 1579169069 ps
CPU time 17.82 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:46:07 PM PDT 24
Peak memory 222164 kb
Host smart-5fb08c19-1594-4b20-95ba-f7a22b6360fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839645593 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.839645593
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1134938199
Short name T568
Test name
Test status
Simulation time 1673050575 ps
CPU time 5.99 seconds
Started Jul 25 04:46:11 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 214104 kb
Host smart-112b319e-bb3d-4cca-a871-b0032b42517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134938199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1134938199
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1365655310
Short name T706
Test name
Test status
Simulation time 263328029 ps
CPU time 2.73 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 209816 kb
Host smart-63d4d24b-28f0-4a7f-9579-d130d21b8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365655310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1365655310
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4068323689
Short name T773
Test name
Test status
Simulation time 51378877 ps
CPU time 0.91 seconds
Started Jul 25 04:45:57 PM PDT 24
Finished Jul 25 04:46:03 PM PDT 24
Peak memory 205756 kb
Host smart-6de859fd-26da-4b72-9951-c1234436184f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068323689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4068323689
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2669873207
Short name T14
Test name
Test status
Simulation time 703859908 ps
CPU time 6.41 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 214084 kb
Host smart-4a1b428d-ecc1-4af7-a341-56efa8b96a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669873207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2669873207
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1276821438
Short name T33
Test name
Test status
Simulation time 374580387 ps
CPU time 4.24 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 221072 kb
Host smart-fbcd9625-1d0e-4cb8-8440-7fabd91e9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276821438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1276821438
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1062040777
Short name T387
Test name
Test status
Simulation time 118506565 ps
CPU time 4.34 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 214016 kb
Host smart-52bb5258-6797-46cc-9715-b23a4cae4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062040777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1062040777
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2777335464
Short name T89
Test name
Test status
Simulation time 475413667 ps
CPU time 4.88 seconds
Started Jul 25 04:45:53 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 220932 kb
Host smart-bf9d9404-2837-4ce9-acca-894909af4717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777335464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2777335464
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2754299324
Short name T482
Test name
Test status
Simulation time 28509468 ps
CPU time 1.74 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 206932 kb
Host smart-c74d94e6-c1b0-4b25-b633-121c749979d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754299324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2754299324
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1449709790
Short name T394
Test name
Test status
Simulation time 88526914 ps
CPU time 3.7 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 208948 kb
Host smart-b807cf63-7050-437f-b538-3f6ae9c5bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449709790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1449709790
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.685287351
Short name T574
Test name
Test status
Simulation time 1079030003 ps
CPU time 31.3 seconds
Started Jul 25 04:45:38 PM PDT 24
Finished Jul 25 04:46:10 PM PDT 24
Peak memory 208036 kb
Host smart-4360c559-3935-48fc-9e3c-c2331679ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685287351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.685287351
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3051446990
Short name T203
Test name
Test status
Simulation time 5496335436 ps
CPU time 59.75 seconds
Started Jul 25 04:46:01 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 208476 kb
Host smart-6c39f8d9-5010-48c3-9979-71e0c59d34af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051446990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3051446990
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3765553058
Short name T298
Test name
Test status
Simulation time 402415387 ps
CPU time 4.81 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:44 PM PDT 24
Peak memory 208384 kb
Host smart-b549d52c-fcd9-43b8-a069-1020aa5bca1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765553058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3765553058
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.82199458
Short name T303
Test name
Test status
Simulation time 216799435 ps
CPU time 2.59 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 208296 kb
Host smart-c8ce4094-e60a-4e2b-95a5-34144fd44cc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82199458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.82199458
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.611509230
Short name T843
Test name
Test status
Simulation time 48893686 ps
CPU time 1.52 seconds
Started Jul 25 04:45:42 PM PDT 24
Finished Jul 25 04:45:43 PM PDT 24
Peak memory 209684 kb
Host smart-ce8cf514-26c7-4711-b1cc-6fe8a9eba7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611509230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.611509230
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2848483563
Short name T484
Test name
Test status
Simulation time 31239155 ps
CPU time 2.1 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 206544 kb
Host smart-21779826-0357-4778-b054-189facb0185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848483563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2848483563
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1505814273
Short name T845
Test name
Test status
Simulation time 8434574513 ps
CPU time 64.52 seconds
Started Jul 25 04:46:13 PM PDT 24
Finished Jul 25 04:47:18 PM PDT 24
Peak memory 215016 kb
Host smart-7983ae68-4922-44c3-88fa-8c6b73d07155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505814273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1505814273
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.875858070
Short name T219
Test name
Test status
Simulation time 231682414 ps
CPU time 13.44 seconds
Started Jul 25 04:46:03 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 222376 kb
Host smart-9138445d-4bfa-4a6f-b0b4-5ac29bc25235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875858070 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.875858070
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2915660309
Short name T546
Test name
Test status
Simulation time 2618969317 ps
CPU time 27.87 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 214084 kb
Host smart-b8f3e64f-1513-4bf0-b65c-d1bfa95c4a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915660309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2915660309
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1328650460
Short name T57
Test name
Test status
Simulation time 120937617 ps
CPU time 2.06 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 210080 kb
Host smart-8e72c126-6f5a-41a7-b9b7-7e5b05b7685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328650460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1328650460
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3526345996
Short name T539
Test name
Test status
Simulation time 32093602 ps
CPU time 0.72 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 205776 kb
Host smart-53c61f65-9da1-4dc9-ba29-0382f425e4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526345996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3526345996
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3511750745
Short name T670
Test name
Test status
Simulation time 208884208 ps
CPU time 2.73 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 214104 kb
Host smart-4202d211-1614-4446-9e52-f8d586a09f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511750745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3511750745
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2104118597
Short name T343
Test name
Test status
Simulation time 255889183 ps
CPU time 1.97 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 209856 kb
Host smart-2bcc2113-3e43-48dd-961e-720991130adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104118597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2104118597
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3548831143
Short name T351
Test name
Test status
Simulation time 69876196 ps
CPU time 3.39 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 214204 kb
Host smart-1f2c0e9c-73a9-4e94-b8fa-5ba033b152e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548831143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3548831143
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3747034171
Short name T336
Test name
Test status
Simulation time 392585312 ps
CPU time 2.39 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 214012 kb
Host smart-6b925fa8-7679-4062-baf1-5e4a6c92eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747034171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3747034171
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.639899989
Short name T3
Test name
Test status
Simulation time 84034064 ps
CPU time 3.83 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 219720 kb
Host smart-ce927bbe-5dfa-4fc2-846c-ce38f0b1f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639899989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.639899989
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1189300099
Short name T248
Test name
Test status
Simulation time 365475770 ps
CPU time 5.61 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 209060 kb
Host smart-6877677b-9b87-4cdf-b257-afa2175469b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189300099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1189300099
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3505300628
Short name T530
Test name
Test status
Simulation time 1601438571 ps
CPU time 10.61 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:46:01 PM PDT 24
Peak memory 207856 kb
Host smart-f92b53fc-e63a-4b6e-8713-b3be5f0be6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505300628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3505300628
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2728924399
Short name T200
Test name
Test status
Simulation time 51234940 ps
CPU time 2.71 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 208216 kb
Host smart-737adaff-bec1-4454-991e-0edcb913fe9f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728924399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2728924399
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4186075818
Short name T272
Test name
Test status
Simulation time 2382551564 ps
CPU time 30.38 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 208024 kb
Host smart-0cb872d2-07cc-45aa-81bb-4dd724b011e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186075818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4186075818
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.155904306
Short name T618
Test name
Test status
Simulation time 180347289 ps
CPU time 4.75 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 207716 kb
Host smart-f01487a2-e936-4637-beaf-4b89f12e5fa8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155904306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.155904306
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2510219407
Short name T445
Test name
Test status
Simulation time 3160330045 ps
CPU time 14.55 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 209236 kb
Host smart-03bb8ed2-499a-48a8-a0a0-51302f2a1785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510219407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2510219407
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3579014458
Short name T699
Test name
Test status
Simulation time 139266125 ps
CPU time 3.48 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 207868 kb
Host smart-ac961a35-576f-4dc5-bd82-f087cb346fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579014458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3579014458
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2123845590
Short name T849
Test name
Test status
Simulation time 648488922 ps
CPU time 16.35 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 222196 kb
Host smart-e929707b-69e5-4de8-812f-2fc2d4a3a8e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123845590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2123845590
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1163686833
Short name T358
Test name
Test status
Simulation time 8170608852 ps
CPU time 48.16 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 217956 kb
Host smart-aead8219-4e93-444e-ae11-34e50b42ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163686833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1163686833
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2939862044
Short name T889
Test name
Test status
Simulation time 98046668 ps
CPU time 1.9 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 210308 kb
Host smart-613e63a4-17ea-4e9a-87df-11241d9c6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939862044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2939862044
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2942904505
Short name T859
Test name
Test status
Simulation time 55874069 ps
CPU time 0.9 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 205812 kb
Host smart-b51a3da4-0bdd-420f-99a9-fa2fc9b1e56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942904505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2942904505
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.769756313
Short name T128
Test name
Test status
Simulation time 2346430945 ps
CPU time 31.27 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 214716 kb
Host smart-616a7172-329f-4464-85a4-5b03414ade3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769756313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.769756313
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2850695321
Short name T894
Test name
Test status
Simulation time 9532841583 ps
CPU time 46.66 seconds
Started Jul 25 04:45:41 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 222436 kb
Host smart-fe4d98e2-561b-4234-875d-1eede4dd684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850695321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2850695321
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1516926287
Short name T493
Test name
Test status
Simulation time 2774632948 ps
CPU time 40.02 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 208284 kb
Host smart-a7bcd6bd-8523-47f7-a7b7-1fff1609d70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516926287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1516926287
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2925444770
Short name T769
Test name
Test status
Simulation time 155195042 ps
CPU time 4.35 seconds
Started Jul 25 04:45:54 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 220336 kb
Host smart-40ae76df-64b9-4043-ac85-9326af98c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925444770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2925444770
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2449180146
Short name T122
Test name
Test status
Simulation time 40117232 ps
CPU time 2.83 seconds
Started Jul 25 04:46:01 PM PDT 24
Finished Jul 25 04:46:04 PM PDT 24
Peak memory 207992 kb
Host smart-7bcc0c5e-ed01-46d3-941d-c274325c934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449180146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2449180146
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.742590981
Short name T713
Test name
Test status
Simulation time 968520433 ps
CPU time 9.88 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:46:00 PM PDT 24
Peak memory 208540 kb
Host smart-da2f5484-c12a-4274-b2ec-262a4e9447c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742590981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.742590981
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2489663155
Short name T472
Test name
Test status
Simulation time 25970933 ps
CPU time 2.08 seconds
Started Jul 25 04:46:23 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 208524 kb
Host smart-664cc183-fea8-47ea-a30c-9c34eb80be63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489663155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2489663155
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1478637886
Short name T807
Test name
Test status
Simulation time 123247659 ps
CPU time 1.77 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:46 PM PDT 24
Peak memory 206692 kb
Host smart-a3bedae5-15ae-4ad6-82a0-d115589d812f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478637886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1478637886
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3006839013
Short name T243
Test name
Test status
Simulation time 347789658 ps
CPU time 5.51 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 208736 kb
Host smart-dc21ead9-5c62-48d2-bb6b-33cda1d99508
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006839013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3006839013
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3487631553
Short name T284
Test name
Test status
Simulation time 592869176 ps
CPU time 4.39 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 217956 kb
Host smart-94142e9b-c8e9-48e3-8c18-df4cceddf138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487631553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3487631553
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2937536405
Short name T454
Test name
Test status
Simulation time 435060149 ps
CPU time 7.96 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 208140 kb
Host smart-6d62dd05-5bd9-439a-a41d-76abf1dc300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937536405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2937536405
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3328875963
Short name T365
Test name
Test status
Simulation time 290928451 ps
CPU time 9.03 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:57 PM PDT 24
Peak memory 222172 kb
Host smart-799b8c76-fc4f-48bd-bab5-5b78b3db1c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328875963 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3328875963
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.219402724
Short name T884
Test name
Test status
Simulation time 546812182 ps
CPU time 8.13 seconds
Started Jul 25 04:45:59 PM PDT 24
Finished Jul 25 04:46:08 PM PDT 24
Peak memory 207656 kb
Host smart-487cabd5-887b-4624-95a0-d49fab5a8c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219402724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.219402724
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3331791840
Short name T501
Test name
Test status
Simulation time 55728719 ps
CPU time 1.9 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 209700 kb
Host smart-c31ffc1d-822a-411f-87b2-3c7b661268f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331791840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3331791840
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2747313350
Short name T858
Test name
Test status
Simulation time 37917193 ps
CPU time 0.91 seconds
Started Jul 25 04:44:44 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 205736 kb
Host smart-5da38957-f2ca-4acc-b90c-04c4946537b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747313350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2747313350
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3529268472
Short name T405
Test name
Test status
Simulation time 64227448 ps
CPU time 3.36 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:28 PM PDT 24
Peak memory 214144 kb
Host smart-50816158-12bf-48e6-94d3-8e0d2404d91a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529268472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3529268472
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1053142248
Short name T436
Test name
Test status
Simulation time 105943199 ps
CPU time 1.52 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 208488 kb
Host smart-62a8bd4a-e5da-490c-81b4-736f507b3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053142248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1053142248
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1590209041
Short name T222
Test name
Test status
Simulation time 545579973 ps
CPU time 4.8 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 214048 kb
Host smart-22d70c13-aa02-462c-8683-fa65868f473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590209041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1590209041
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1656164519
Short name T262
Test name
Test status
Simulation time 191664155 ps
CPU time 6.43 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 222308 kb
Host smart-8a56ae3d-5e67-4423-bd78-8cc6cb893965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656164519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1656164519
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3524507574
Short name T893
Test name
Test status
Simulation time 1171902533 ps
CPU time 4.64 seconds
Started Jul 25 04:44:13 PM PDT 24
Finished Jul 25 04:44:18 PM PDT 24
Peak memory 222152 kb
Host smart-fae086ff-9cfe-4e00-83da-d8b60984dfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524507574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3524507574
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2044827983
Short name T620
Test name
Test status
Simulation time 35948631 ps
CPU time 2.45 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:06 PM PDT 24
Peak memory 207096 kb
Host smart-fcc387ec-fa88-41ee-995f-6df40f35842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044827983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2044827983
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3622441618
Short name T45
Test name
Test status
Simulation time 618302281 ps
CPU time 6.74 seconds
Started Jul 25 04:44:31 PM PDT 24
Finished Jul 25 04:44:38 PM PDT 24
Peak memory 229656 kb
Host smart-d6ce1525-718d-4e82-a98b-5fd89c1d6d42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622441618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3622441618
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3381641382
Short name T558
Test name
Test status
Simulation time 582823263 ps
CPU time 3.63 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 208316 kb
Host smart-646bb026-cf08-4401-9442-5ebe59afbf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381641382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3381641382
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3167238479
Short name T777
Test name
Test status
Simulation time 85681351 ps
CPU time 3.55 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:19 PM PDT 24
Peak memory 208452 kb
Host smart-ebe5c23d-c10d-4565-b497-e8c363454e1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167238479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3167238479
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2430440891
Short name T714
Test name
Test status
Simulation time 160942981 ps
CPU time 3.57 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:33 PM PDT 24
Peak memory 208468 kb
Host smart-03d99f0c-3cd6-435f-b48d-1cac5a87e608
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430440891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2430440891
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1132287716
Short name T598
Test name
Test status
Simulation time 161985693 ps
CPU time 3.73 seconds
Started Jul 25 04:44:14 PM PDT 24
Finished Jul 25 04:44:18 PM PDT 24
Peak memory 208492 kb
Host smart-56964cba-daf1-4ae1-a9a2-7bb59177028f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132287716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1132287716
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2293215106
Short name T559
Test name
Test status
Simulation time 159405506 ps
CPU time 3.34 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 208304 kb
Host smart-9ae33ecc-51a3-46bc-9198-d3d391fce838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293215106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2293215106
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3796922934
Short name T844
Test name
Test status
Simulation time 506314552 ps
CPU time 3.08 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 208044 kb
Host smart-4a9fa769-9a88-4bd1-9075-844500914217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796922934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3796922934
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1517936475
Short name T652
Test name
Test status
Simulation time 106195909 ps
CPU time 4.2 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 218452 kb
Host smart-6ec043a9-26cb-450a-b729-3f1b2da2ced4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517936475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1517936475
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.563869933
Short name T265
Test name
Test status
Simulation time 847671117 ps
CPU time 6 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:33 PM PDT 24
Peak memory 218028 kb
Host smart-da22fd25-baa5-4cff-ba07-513af1aec1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563869933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.563869933
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3125043048
Short name T740
Test name
Test status
Simulation time 34424388 ps
CPU time 0.78 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 205764 kb
Host smart-18d8e847-14fd-49e0-abb3-a48ec34a8036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125043048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3125043048
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3508668076
Short name T576
Test name
Test status
Simulation time 89770922 ps
CPU time 2.86 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:31 PM PDT 24
Peak memory 208840 kb
Host smart-771f932a-ea53-490b-9637-b40d94727bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508668076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3508668076
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2201823837
Short name T429
Test name
Test status
Simulation time 1564303445 ps
CPU time 8.63 seconds
Started Jul 25 04:45:55 PM PDT 24
Finished Jul 25 04:46:09 PM PDT 24
Peak memory 208468 kb
Host smart-86081ae7-e264-494a-8958-414b1ee9bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201823837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2201823837
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2954458494
Short name T227
Test name
Test status
Simulation time 3199148870 ps
CPU time 9.65 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 214144 kb
Host smart-6ed8d2cc-8d53-4ad1-9c07-95d5a3dae4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954458494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2954458494
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3162481467
Short name T354
Test name
Test status
Simulation time 42074710 ps
CPU time 2.25 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 220480 kb
Host smart-f3d42dd5-aa76-465f-8e8c-6f91c748c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162481467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3162481467
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.387490990
Short name T781
Test name
Test status
Simulation time 35367137 ps
CPU time 2.58 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 209660 kb
Host smart-d3bdbfe6-3cfe-47a1-bb43-55680aa4dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387490990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.387490990
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1153423740
Short name T809
Test name
Test status
Simulation time 53472496 ps
CPU time 3.64 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 210120 kb
Host smart-a023e161-3a3a-4155-b014-0f8013e05a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153423740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1153423740
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.977183278
Short name T102
Test name
Test status
Simulation time 22549430465 ps
CPU time 45.77 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 208192 kb
Host smart-c27203bb-5a35-4001-b228-290a4c21cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977183278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.977183278
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.292203579
Short name T735
Test name
Test status
Simulation time 850642149 ps
CPU time 11.43 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:12 PM PDT 24
Peak memory 208240 kb
Host smart-039aa9ec-8ba7-4d1f-8aaa-4642b5fd23c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292203579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.292203579
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3725039549
Short name T631
Test name
Test status
Simulation time 106127886 ps
CPU time 2.17 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 206744 kb
Host smart-d2662507-f59c-41c8-9378-69cf47bee649
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725039549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3725039549
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3465208564
Short name T851
Test name
Test status
Simulation time 393936943 ps
CPU time 6.02 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 207768 kb
Host smart-f60a6763-ec07-49bb-910e-dea20b93089f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465208564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3465208564
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3727906967
Short name T702
Test name
Test status
Simulation time 1946642812 ps
CPU time 12.97 seconds
Started Jul 25 04:46:13 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 218260 kb
Host smart-95214197-903d-4e9c-9dd5-a21967e6a8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727906967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3727906967
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.785512770
Short name T881
Test name
Test status
Simulation time 179812921 ps
CPU time 3.72 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 206536 kb
Host smart-04a328c6-a6af-4337-97d4-fd2ae9d6655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785512770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.785512770
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1852664707
Short name T73
Test name
Test status
Simulation time 119714867989 ps
CPU time 220.58 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 222284 kb
Host smart-b834b30b-6b18-4392-9303-302e5f7bb2b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852664707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1852664707
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3810027202
Short name T664
Test name
Test status
Simulation time 606007872 ps
CPU time 18.94 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:46:06 PM PDT 24
Peak memory 222328 kb
Host smart-2ba5e5e8-ba1c-43ae-b13a-9d09efb18782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810027202 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3810027202
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.742043139
Short name T426
Test name
Test status
Simulation time 451435311 ps
CPU time 4.5 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 208112 kb
Host smart-bf3423a1-14d5-4ee1-9230-a06ceb45f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742043139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.742043139
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1373078715
Short name T561
Test name
Test status
Simulation time 102339443 ps
CPU time 3.4 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 210216 kb
Host smart-3b6a3fb6-3497-4850-82e8-4bfc5f35eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373078715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1373078715
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3263368423
Short name T476
Test name
Test status
Simulation time 11093065 ps
CPU time 0.83 seconds
Started Jul 25 04:46:17 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 205756 kb
Host smart-e79b6dbf-614a-4f56-b838-8452d3c52714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263368423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3263368423
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1567863977
Short name T369
Test name
Test status
Simulation time 84230149 ps
CPU time 2.53 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 214044 kb
Host smart-10250d37-2d87-40a6-88be-c4202833071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567863977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1567863977
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3627694594
Short name T320
Test name
Test status
Simulation time 547613755 ps
CPU time 5.1 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 213980 kb
Host smart-a617d233-3238-4b5b-b7ed-8de60f842497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627694594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3627694594
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2492128155
Short name T206
Test name
Test status
Simulation time 93858931 ps
CPU time 3.43 seconds
Started Jul 25 04:46:09 PM PDT 24
Finished Jul 25 04:46:13 PM PDT 24
Peak memory 209336 kb
Host smart-2a31de30-c6cb-4cfd-8389-706cc74f21fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492128155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2492128155
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1696181257
Short name T850
Test name
Test status
Simulation time 945096747 ps
CPU time 26.2 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:46:14 PM PDT 24
Peak memory 209328 kb
Host smart-1b357340-bcb5-44a3-8b50-fb02da85d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696181257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1696181257
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2727992777
Short name T905
Test name
Test status
Simulation time 131709178 ps
CPU time 2.5 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 208400 kb
Host smart-7ef55fb8-9602-4807-a743-5938ee370275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727992777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2727992777
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1425407851
Short name T491
Test name
Test status
Simulation time 237394258 ps
CPU time 2.6 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 206736 kb
Host smart-36505e58-389c-4800-ad91-95335ff2f491
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425407851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1425407851
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.877478819
Short name T811
Test name
Test status
Simulation time 11137063724 ps
CPU time 40.79 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 208928 kb
Host smart-9ef21f17-c445-4444-94ca-6ab6026e6def
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877478819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.877478819
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3353332421
Short name T252
Test name
Test status
Simulation time 386100610 ps
CPU time 2.74 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 206984 kb
Host smart-65a04fa7-b3f2-4f18-b031-79ff62977ccf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353332421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3353332421
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2327961583
Short name T480
Test name
Test status
Simulation time 37927659 ps
CPU time 2.39 seconds
Started Jul 25 04:46:17 PM PDT 24
Finished Jul 25 04:46:19 PM PDT 24
Peak memory 207324 kb
Host smart-228ebfe1-7a0d-4eee-be63-35c24580e290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327961583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2327961583
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2832066204
Short name T906
Test name
Test status
Simulation time 826389346 ps
CPU time 18.84 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 208428 kb
Host smart-b81cac4a-327b-42fc-991e-01ca5017a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832066204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2832066204
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3134651719
Short name T119
Test name
Test status
Simulation time 173385338 ps
CPU time 6.38 seconds
Started Jul 25 04:46:08 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 222204 kb
Host smart-a0a309c9-8d56-48cb-9028-a8be301fe055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134651719 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3134651719
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.390810904
Short name T774
Test name
Test status
Simulation time 146911497 ps
CPU time 5.21 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 210084 kb
Host smart-47cc93f2-96f4-4953-ab19-ac2768d4a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390810904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.390810904
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3130997904
Short name T762
Test name
Test status
Simulation time 599885102 ps
CPU time 3.97 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 209760 kb
Host smart-b7c08eca-6aab-4168-8001-0f3273139734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130997904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3130997904
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4294086826
Short name T885
Test name
Test status
Simulation time 44406632 ps
CPU time 0.7 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 205736 kb
Host smart-4794ad9f-7f32-48e1-a89d-5cdaa3acd09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294086826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4294086826
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2845531533
Short name T346
Test name
Test status
Simulation time 78074702 ps
CPU time 1.93 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:46 PM PDT 24
Peak memory 214040 kb
Host smart-fbbfd529-1db1-472f-ab09-e5c01c7e1e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845531533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2845531533
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3751831447
Short name T32
Test name
Test status
Simulation time 6504447987 ps
CPU time 64.82 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:46:52 PM PDT 24
Peak memory 222456 kb
Host smart-acf2cefd-1407-411f-ab82-c7208310626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751831447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3751831447
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2710992996
Short name T49
Test name
Test status
Simulation time 99906594 ps
CPU time 1.87 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 214052 kb
Host smart-2f0cc463-7126-4d1c-9cf1-5c3edf77fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710992996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2710992996
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2112790708
Short name T279
Test name
Test status
Simulation time 217124108 ps
CPU time 2.1 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 220764 kb
Host smart-380d9a13-f635-40b8-b544-86f40422cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112790708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2112790708
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.901324960
Short name T215
Test name
Test status
Simulation time 174484540 ps
CPU time 3.87 seconds
Started Jul 25 04:46:16 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 222168 kb
Host smart-2e79c1b7-5706-426b-8a09-11af97ec5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901324960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.901324960
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2843489399
Short name T327
Test name
Test status
Simulation time 238229281 ps
CPU time 5.5 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 214200 kb
Host smart-0d3306df-c6c7-41ed-91b0-44086b2499a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843489399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2843489399
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3726353138
Short name T195
Test name
Test status
Simulation time 83164401 ps
CPU time 3.22 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 206580 kb
Host smart-bfb07edd-b811-4a1d-90ed-e2b6779e04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726353138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3726353138
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.981967053
Short name T596
Test name
Test status
Simulation time 2467531678 ps
CPU time 3.98 seconds
Started Jul 25 04:45:46 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 208464 kb
Host smart-4145f071-8f0b-484e-8f8a-6e43e59ef6d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981967053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.981967053
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.87196738
Short name T578
Test name
Test status
Simulation time 6443485092 ps
CPU time 58.07 seconds
Started Jul 25 04:46:23 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 207620 kb
Host smart-6d63292c-fa4f-462b-96b2-795968ed8ef2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87196738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.87196738
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1384780812
Short name T442
Test name
Test status
Simulation time 493947134 ps
CPU time 2.46 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 206496 kb
Host smart-49a41f2f-ba50-423d-a4a6-89351165f5eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384780812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1384780812
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1071713526
Short name T609
Test name
Test status
Simulation time 36918305 ps
CPU time 2.12 seconds
Started Jul 25 04:45:55 PM PDT 24
Finished Jul 25 04:46:03 PM PDT 24
Peak memory 220220 kb
Host smart-9eb094fa-3dfe-4fda-8da2-5b11dcd11d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071713526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1071713526
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3653571628
Short name T654
Test name
Test status
Simulation time 406006986 ps
CPU time 3.53 seconds
Started Jul 25 04:45:53 PM PDT 24
Finished Jul 25 04:45:57 PM PDT 24
Peak memory 208616 kb
Host smart-add2baaf-2980-4515-b65a-e0e8bdd3e77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653571628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3653571628
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1371245274
Short name T325
Test name
Test status
Simulation time 15615411282 ps
CPU time 67.15 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 216988 kb
Host smart-f914310e-f80e-4df1-9f64-d280c79d19a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371245274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1371245274
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3267637448
Short name T787
Test name
Test status
Simulation time 503848201 ps
CPU time 18.63 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:46:02 PM PDT 24
Peak memory 222152 kb
Host smart-5b3f2f5c-c65b-4e92-be70-bb28acee5c0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267637448 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3267637448
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1935919523
Short name T504
Test name
Test status
Simulation time 94566421 ps
CPU time 3.98 seconds
Started Jul 25 04:45:54 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 217992 kb
Host smart-b08086b9-5129-4428-a5bd-96f4f8a48750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935919523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1935919523
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2927680808
Short name T160
Test name
Test status
Simulation time 176054566 ps
CPU time 2.81 seconds
Started Jul 25 04:46:12 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 209988 kb
Host smart-7d049c83-7d7e-44a6-ae06-e9830c0c64c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927680808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2927680808
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1335986507
Short name T520
Test name
Test status
Simulation time 31875726 ps
CPU time 0.77 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:48 PM PDT 24
Peak memory 205712 kb
Host smart-c46a0d56-934d-45d2-95ce-cae6c884aaf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335986507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1335986507
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2826534681
Short name T378
Test name
Test status
Simulation time 189654874 ps
CPU time 3.6 seconds
Started Jul 25 04:46:16 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 215128 kb
Host smart-7ae481cd-c8a7-440a-9531-81900fb2384d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826534681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2826534681
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.158208806
Short name T318
Test name
Test status
Simulation time 25276518 ps
CPU time 1.73 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 217368 kb
Host smart-a51287dc-c4ae-4957-97e4-8836e84b9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158208806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.158208806
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3241167975
Short name T367
Test name
Test status
Simulation time 35574262 ps
CPU time 1.85 seconds
Started Jul 25 04:45:57 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 214104 kb
Host smart-beb22eeb-5008-425c-aa80-0c70952e067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241167975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3241167975
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1849250124
Short name T902
Test name
Test status
Simulation time 242350968 ps
CPU time 3.52 seconds
Started Jul 25 04:45:56 PM PDT 24
Finished Jul 25 04:46:00 PM PDT 24
Peak memory 214160 kb
Host smart-fc6f542e-c1e9-490e-ad87-7915070e6680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849250124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1849250124
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.259922015
Short name T659
Test name
Test status
Simulation time 199604996 ps
CPU time 4.16 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 209696 kb
Host smart-30428d4e-66b0-46bf-a40e-333aab37fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259922015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.259922015
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1508638536
Short name T308
Test name
Test status
Simulation time 1250637003 ps
CPU time 37.68 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 214036 kb
Host smart-1ffd246c-3387-4a2d-a9c3-f22c0f4be8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508638536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1508638536
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.619289499
Short name T668
Test name
Test status
Simulation time 3435608325 ps
CPU time 5.19 seconds
Started Jul 25 04:46:00 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 208348 kb
Host smart-facb8262-f3a6-4fc3-8fb2-25b2971d22f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619289499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.619289499
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.208338912
Short name T106
Test name
Test status
Simulation time 44099415 ps
CPU time 2.4 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 206968 kb
Host smart-6d445408-8409-49c7-8dd7-2f7b0689f625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208338912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.208338912
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4240119444
Short name T438
Test name
Test status
Simulation time 38069677 ps
CPU time 2.16 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 206688 kb
Host smart-8b16f1b9-282f-4193-9e72-c8b77c3a7dd5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240119444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4240119444
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1852669216
Short name T417
Test name
Test status
Simulation time 795363471 ps
CPU time 2.42 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 206724 kb
Host smart-03a595cd-9973-4c3f-81bc-3aa74631bac2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852669216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1852669216
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1343863803
Short name T385
Test name
Test status
Simulation time 27190810 ps
CPU time 1.73 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:46:00 PM PDT 24
Peak memory 207412 kb
Host smart-3a561302-922a-4e9a-b3cf-77352c3c02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343863803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1343863803
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3096790079
Short name T186
Test name
Test status
Simulation time 709770435 ps
CPU time 4.37 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:55 PM PDT 24
Peak memory 208328 kb
Host smart-d5a01c1c-958a-4a18-bdc6-7ed42f304570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096790079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3096790079
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.859774489
Short name T67
Test name
Test status
Simulation time 2047906413 ps
CPU time 15.62 seconds
Started Jul 25 04:46:06 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 220840 kb
Host smart-74835065-a574-433c-af31-7ccd080be3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859774489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.859774489
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3178284102
Short name T53
Test name
Test status
Simulation time 327098787 ps
CPU time 11.37 seconds
Started Jul 25 04:46:06 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 222280 kb
Host smart-36a21780-af38-43f9-b8ad-d6512a02263c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178284102 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3178284102
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1953269157
Short name T347
Test name
Test status
Simulation time 466486169 ps
CPU time 3.84 seconds
Started Jul 25 04:46:17 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 207088 kb
Host smart-71040e96-2479-415c-9f11-b3a724824bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953269157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1953269157
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.233176349
Short name T127
Test name
Test status
Simulation time 701701144 ps
CPU time 4.44 seconds
Started Jul 25 04:46:13 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 210100 kb
Host smart-66f2a9d6-c1e3-4e81-b499-c4bf4c19047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233176349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.233176349
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.871282761
Short name T507
Test name
Test status
Simulation time 9870217 ps
CPU time 0.81 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 205740 kb
Host smart-92e2b436-c204-42cc-8304-4846bb621be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871282761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.871282761
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2997799257
Short name T379
Test name
Test status
Simulation time 390222858 ps
CPU time 5.99 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 214076 kb
Host smart-d4aea563-b7c4-404a-b7a0-c7838efbee64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997799257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2997799257
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1122939465
Short name T666
Test name
Test status
Simulation time 1878530415 ps
CPU time 17.75 seconds
Started Jul 25 04:45:51 PM PDT 24
Finished Jul 25 04:46:09 PM PDT 24
Peak memory 209376 kb
Host smart-5614306e-6d19-40b3-a74d-ec51f16f5226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122939465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1122939465
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4217883835
Short name T483
Test name
Test status
Simulation time 33818801 ps
CPU time 1.95 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 214004 kb
Host smart-35ca2909-4399-4468-98b4-d44c89822a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217883835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4217883835
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3488799580
Short name T853
Test name
Test status
Simulation time 247699203 ps
CPU time 3.12 seconds
Started Jul 25 04:46:03 PM PDT 24
Finished Jul 25 04:46:06 PM PDT 24
Peak memory 215072 kb
Host smart-ca32ac5c-0c3c-47d2-b9ef-ed4e7510495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488799580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3488799580
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.353750390
Short name T642
Test name
Test status
Simulation time 432014269 ps
CPU time 8.65 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:53 PM PDT 24
Peak memory 208844 kb
Host smart-8b204a63-b205-4107-bfac-014ec5c9330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353750390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.353750390
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1371169959
Short name T230
Test name
Test status
Simulation time 190544101 ps
CPU time 2.7 seconds
Started Jul 25 04:45:53 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 206516 kb
Host smart-e2cd3d86-416e-4b47-a000-605bf856075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371169959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1371169959
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1784735864
Short name T390
Test name
Test status
Simulation time 127700105 ps
CPU time 3.08 seconds
Started Jul 25 04:45:44 PM PDT 24
Finished Jul 25 04:45:47 PM PDT 24
Peak memory 207976 kb
Host smart-8f609716-e528-4f18-a38d-5015d9805d1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784735864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1784735864
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3760072573
Short name T388
Test name
Test status
Simulation time 180781746 ps
CPU time 2.75 seconds
Started Jul 25 04:46:17 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 206708 kb
Host smart-b37de6b4-7c24-46ca-8b48-9d06cb7653d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760072573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3760072573
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4190131311
Short name T780
Test name
Test status
Simulation time 126340124 ps
CPU time 4.44 seconds
Started Jul 25 04:46:08 PM PDT 24
Finished Jul 25 04:46:13 PM PDT 24
Peak memory 208208 kb
Host smart-6c46b755-bbb5-41e5-86a1-cba21eaf49e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190131311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4190131311
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1436651786
Short name T514
Test name
Test status
Simulation time 52154962 ps
CPU time 2.44 seconds
Started Jul 25 04:45:59 PM PDT 24
Finished Jul 25 04:46:01 PM PDT 24
Peak memory 209028 kb
Host smart-cd9aaa2d-e0bc-4f29-8f78-05f7e5989e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436651786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1436651786
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3485217611
Short name T883
Test name
Test status
Simulation time 275012864 ps
CPU time 3.07 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 208240 kb
Host smart-2995c6e1-2188-413c-ae15-24de43ef5bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485217611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3485217611
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2992731443
Short name T345
Test name
Test status
Simulation time 1918353313 ps
CPU time 35.2 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 222192 kb
Host smart-dfdcb749-d3b4-49f8-b708-ca1e42cd7b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992731443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2992731443
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4284675252
Short name T665
Test name
Test status
Simulation time 130309248 ps
CPU time 5.25 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 214048 kb
Host smart-0c245857-ab5b-42f7-b4c9-3b82c0aacddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284675252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4284675252
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1078454300
Short name T372
Test name
Test status
Simulation time 169345272 ps
CPU time 2.45 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 209836 kb
Host smart-56caedc6-4ef5-4670-a060-e002ab25e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078454300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1078454300
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2020000686
Short name T626
Test name
Test status
Simulation time 11244571 ps
CPU time 0.79 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 205740 kb
Host smart-8d0ec62d-3398-47e0-bd9e-3c5814d4d908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020000686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2020000686
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.92327817
Short name T68
Test name
Test status
Simulation time 52252175 ps
CPU time 2.14 seconds
Started Jul 25 04:46:03 PM PDT 24
Finished Jul 25 04:46:06 PM PDT 24
Peak memory 208380 kb
Host smart-6c5ed0d2-5026-444b-9516-e47d0b13e30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92327817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.92327817
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2045555253
Short name T50
Test name
Test status
Simulation time 107869769 ps
CPU time 1.95 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 214048 kb
Host smart-3e9ce4c7-d1c0-4147-affe-21cd912559c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045555253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2045555253
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1740800324
Short name T239
Test name
Test status
Simulation time 453129574 ps
CPU time 4.89 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 214084 kb
Host smart-8d6efb9d-4d3b-46b0-933a-bf999a7c5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740800324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1740800324
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1095677495
Short name T499
Test name
Test status
Simulation time 302430432 ps
CPU time 3.57 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 208544 kb
Host smart-67b1a617-fc3b-4c21-ae3e-451ed07a52e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095677495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1095677495
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3205465968
Short name T822
Test name
Test status
Simulation time 878446142 ps
CPU time 10.31 seconds
Started Jul 25 04:46:08 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 207504 kb
Host smart-601da53c-09c1-466d-aa8b-48601deec6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205465968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3205465968
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1629346052
Short name T570
Test name
Test status
Simulation time 74381007 ps
CPU time 3.06 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 208256 kb
Host smart-94126581-60e8-48c1-895e-f1cfc1f3b9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629346052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1629346052
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3705247725
Short name T685
Test name
Test status
Simulation time 8212602378 ps
CPU time 22.03 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 208720 kb
Host smart-d4a2db44-e092-4b5d-8dd3-74fd856c6b5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705247725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3705247725
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.451274678
Short name T420
Test name
Test status
Simulation time 88995558 ps
CPU time 3.24 seconds
Started Jul 25 04:46:00 PM PDT 24
Finished Jul 25 04:46:03 PM PDT 24
Peak memory 206504 kb
Host smart-81c3837a-026e-4317-beee-a3b25d1b41d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451274678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.451274678
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.99367981
Short name T765
Test name
Test status
Simulation time 387180724 ps
CPU time 2.72 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 206700 kb
Host smart-c5833a91-61e9-4bfc-bf56-b9a1aab083da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99367981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.99367981
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3418518879
Short name T190
Test name
Test status
Simulation time 635924515 ps
CPU time 15.58 seconds
Started Jul 25 04:46:07 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 218016 kb
Host smart-3c286cf5-3f34-4e9e-92f1-25ca1e61ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418518879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3418518879
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2782330241
Short name T572
Test name
Test status
Simulation time 86368064 ps
CPU time 1.67 seconds
Started Jul 25 04:45:58 PM PDT 24
Finished Jul 25 04:46:00 PM PDT 24
Peak memory 206484 kb
Host smart-5769f27f-f484-4c8f-91a0-6bb5825b856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782330241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2782330241
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2105097922
Short name T217
Test name
Test status
Simulation time 1763864297 ps
CPU time 49.53 seconds
Started Jul 25 04:45:59 PM PDT 24
Finished Jul 25 04:46:49 PM PDT 24
Peak memory 215928 kb
Host smart-45a253e6-3cc8-42ed-b91e-b85829d8c767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105097922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2105097922
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3888221141
Short name T71
Test name
Test status
Simulation time 606190068 ps
CPU time 25.5 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 222104 kb
Host smart-d59665ef-0c5c-4bf8-93c5-78b1f7b47f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888221141 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3888221141
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4162643842
Short name T878
Test name
Test status
Simulation time 2535864764 ps
CPU time 29.71 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 209380 kb
Host smart-195dee46-5798-4ea7-b01a-2dcdb50d437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162643842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4162643842
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3158435265
Short name T59
Test name
Test status
Simulation time 916232777 ps
CPU time 4.6 seconds
Started Jul 25 04:46:13 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 209984 kb
Host smart-d3e302c8-cb5d-4ed3-a680-96a6a9d88f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158435265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3158435265
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.650416480
Short name T728
Test name
Test status
Simulation time 66781505 ps
CPU time 0.8 seconds
Started Jul 25 04:45:49 PM PDT 24
Finished Jul 25 04:45:50 PM PDT 24
Peak memory 205744 kb
Host smart-f077bfa7-1389-41e9-b26b-c607aa9a6731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650416480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.650416480
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3586489905
Short name T145
Test name
Test status
Simulation time 111866467 ps
CPU time 4.23 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 222292 kb
Host smart-6686b225-b413-49ea-96b6-611071a4146b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586489905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3586489905
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2742590275
Short name T26
Test name
Test status
Simulation time 243030742 ps
CPU time 3.61 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:51 PM PDT 24
Peak memory 217292 kb
Host smart-0045b961-9cf2-44d9-8b4f-a09e1a0530ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742590275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2742590275
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3262223964
Short name T730
Test name
Test status
Simulation time 1333876672 ps
CPU time 4.46 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 209956 kb
Host smart-1c1e1064-3597-45a3-86ff-74ddc5a8f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262223964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3262223964
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.339750813
Short name T24
Test name
Test status
Simulation time 1267380517 ps
CPU time 26.92 seconds
Started Jul 25 04:45:57 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 214032 kb
Host smart-e0294a68-c17b-46af-84ba-643b617a28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339750813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.339750813
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1149005652
Short name T625
Test name
Test status
Simulation time 75579774 ps
CPU time 1.45 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 213976 kb
Host smart-e2140202-6f71-4797-9b72-b792e6689e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149005652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1149005652
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3024478182
Short name T209
Test name
Test status
Simulation time 362018987 ps
CPU time 2.65 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:07 PM PDT 24
Peak memory 209356 kb
Host smart-051fa01b-8ac9-4935-8965-22ad3fac9f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024478182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3024478182
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2296519985
Short name T199
Test name
Test status
Simulation time 493245588 ps
CPU time 11.19 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 208672 kb
Host smart-0339cb83-6cf1-49e7-b89a-c6cdcf2d815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296519985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2296519985
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3010034305
Short name T313
Test name
Test status
Simulation time 52646902 ps
CPU time 2.87 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 208472 kb
Host smart-55371026-23b1-47a4-bcf4-23bb2262c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010034305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3010034305
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2265296158
Short name T466
Test name
Test status
Simulation time 77468523 ps
CPU time 1.7 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:19 PM PDT 24
Peak memory 206644 kb
Host smart-beefc468-7211-4ca1-bd39-c9f31cd91728
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265296158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2265296158
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3777234024
Short name T701
Test name
Test status
Simulation time 125585607 ps
CPU time 3.36 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 208652 kb
Host smart-eed9b3d8-99c2-4fd2-b1c9-daf4cfd7a824
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777234024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3777234024
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1498269177
Short name T848
Test name
Test status
Simulation time 25620874 ps
CPU time 2.04 seconds
Started Jul 25 04:46:12 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 208408 kb
Host smart-b13e3866-d5fe-4e43-b6dc-7920e2851f28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498269177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1498269177
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2786251105
Short name T760
Test name
Test status
Simulation time 520659481 ps
CPU time 9.71 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 214040 kb
Host smart-d8c17a32-17b4-42ec-a7e9-a110d8336a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786251105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2786251105
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.835527802
Short name T593
Test name
Test status
Simulation time 52489733 ps
CPU time 2.53 seconds
Started Jul 25 04:46:02 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 208120 kb
Host smart-e71a0d23-a352-478a-9a75-a8f68f147b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835527802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.835527802
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2171386559
Short name T266
Test name
Test status
Simulation time 2025994344 ps
CPU time 19.07 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 216284 kb
Host smart-20d82041-5252-4982-b250-68f816effd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171386559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2171386559
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4151863583
Short name T238
Test name
Test status
Simulation time 110161518 ps
CPU time 5.14 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 209760 kb
Host smart-4688c4ae-e3d6-4b73-9332-c3a8e94d264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151863583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4151863583
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1672308929
Short name T169
Test name
Test status
Simulation time 71934051 ps
CPU time 2.11 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 209564 kb
Host smart-5a3866fa-dfb8-4877-9973-643bd619d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672308929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1672308929
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4044975920
Short name T465
Test name
Test status
Simulation time 95580072 ps
CPU time 0.75 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 205764 kb
Host smart-a26ec27c-ad37-42e7-88fb-d6b9305dd363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044975920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4044975920
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2448128472
Short name T586
Test name
Test status
Simulation time 122437592 ps
CPU time 3.03 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:08 PM PDT 24
Peak memory 220448 kb
Host smart-9483f4c1-27fb-4446-b73d-b37a3903581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448128472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2448128472
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1943760589
Short name T898
Test name
Test status
Simulation time 664721326 ps
CPU time 1.99 seconds
Started Jul 25 04:45:57 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 208024 kb
Host smart-5ce95d6c-4b7e-4b8d-babe-1bf9f43d1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943760589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1943760589
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.98080760
Short name T25
Test name
Test status
Simulation time 208768613 ps
CPU time 5.52 seconds
Started Jul 25 04:46:05 PM PDT 24
Finished Jul 25 04:46:10 PM PDT 24
Peak memory 209480 kb
Host smart-a45651eb-818b-468d-880d-0cdecc91f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98080760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.98080760
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2049997557
Short name T353
Test name
Test status
Simulation time 94474192 ps
CPU time 3.18 seconds
Started Jul 25 04:46:02 PM PDT 24
Finished Jul 25 04:46:11 PM PDT 24
Peak memory 222072 kb
Host smart-f79ce423-37eb-40f1-843b-6d39d5e1f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049997557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2049997557
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.121943257
Short name T208
Test name
Test status
Simulation time 140142837 ps
CPU time 3.99 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 208332 kb
Host smart-79ccb7ca-8c62-4937-9c7c-a0ce598cdf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121943257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.121943257
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3752780361
Short name T854
Test name
Test status
Simulation time 43331674 ps
CPU time 3.28 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 214124 kb
Host smart-98faba5b-4a58-40ff-bf99-a1c072edd2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752780361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3752780361
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3499401404
Short name T693
Test name
Test status
Simulation time 20183696 ps
CPU time 1.71 seconds
Started Jul 25 04:45:52 PM PDT 24
Finished Jul 25 04:45:54 PM PDT 24
Peak memory 206916 kb
Host smart-55d09624-77e9-458d-99d7-3c9e0f808fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499401404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3499401404
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3028616185
Short name T903
Test name
Test status
Simulation time 158973893 ps
CPU time 2.25 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 206656 kb
Host smart-bf39bc2c-ccdf-430d-8c05-dd277123ed4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028616185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3028616185
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2336996130
Short name T15
Test name
Test status
Simulation time 156113990 ps
CPU time 1.72 seconds
Started Jul 25 04:46:00 PM PDT 24
Finished Jul 25 04:46:02 PM PDT 24
Peak memory 206688 kb
Host smart-a53cc45c-ee20-4b2b-b858-1d9a368796d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336996130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2336996130
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3714895296
Short name T690
Test name
Test status
Simulation time 185951407 ps
CPU time 6.48 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 208640 kb
Host smart-82176adf-8d1b-4f27-9707-88ea40186507
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714895296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3714895296
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3214860138
Short name T269
Test name
Test status
Simulation time 99033139 ps
CPU time 3.95 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 209608 kb
Host smart-ea9c8349-805d-4abf-ac85-e1cb749bb483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214860138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3214860138
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4207494341
Short name T785
Test name
Test status
Simulation time 144242558 ps
CPU time 3.07 seconds
Started Jul 25 04:46:11 PM PDT 24
Finished Jul 25 04:46:14 PM PDT 24
Peak memory 207620 kb
Host smart-70953b5a-5433-43dc-9445-c6f61d96e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207494341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4207494341
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1189594927
Short name T179
Test name
Test status
Simulation time 829185754 ps
CPU time 30.5 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 222204 kb
Host smart-e3c81792-37a1-467a-875f-302c7b056b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189594927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1189594927
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2737664765
Short name T249
Test name
Test status
Simulation time 609988734 ps
CPU time 4.41 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 208636 kb
Host smart-acd9e6c3-0a4a-4580-821a-b5b59fbcd386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737664765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2737664765
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3665719341
Short name T726
Test name
Test status
Simulation time 101573519 ps
CPU time 2.31 seconds
Started Jul 25 04:46:11 PM PDT 24
Finished Jul 25 04:46:14 PM PDT 24
Peak memory 210416 kb
Host smart-c21bb3e7-32d6-47d8-aa88-80599dc443c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665719341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3665719341
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4227473298
Short name T588
Test name
Test status
Simulation time 24951862 ps
CPU time 0.93 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 205876 kb
Host smart-3399aae0-2929-4fee-afc4-e5bff20c878c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227473298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4227473298
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2957380143
Short name T330
Test name
Test status
Simulation time 502431665 ps
CPU time 13.04 seconds
Started Jul 25 04:46:01 PM PDT 24
Finished Jul 25 04:46:14 PM PDT 24
Peak memory 214052 kb
Host smart-3aa8bd82-a207-4ff5-b227-917a0b351e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957380143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2957380143
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3069005400
Short name T28
Test name
Test status
Simulation time 936951518 ps
CPU time 11.44 seconds
Started Jul 25 04:45:47 PM PDT 24
Finished Jul 25 04:45:58 PM PDT 24
Peak memory 209164 kb
Host smart-83134d20-2178-41d8-a634-e2148b4667da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069005400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3069005400
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4237108817
Short name T296
Test name
Test status
Simulation time 394009445 ps
CPU time 2.21 seconds
Started Jul 25 04:45:53 PM PDT 24
Finished Jul 25 04:46:01 PM PDT 24
Peak memory 218076 kb
Host smart-a43f6e21-0525-41b6-8603-8a5a394c5781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237108817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4237108817
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.216426193
Short name T87
Test name
Test status
Simulation time 277725741 ps
CPU time 5.88 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 209076 kb
Host smart-2a1791f6-8e4c-4505-adae-8883d6adba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216426193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.216426193
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.785785575
Short name T293
Test name
Test status
Simulation time 1214475274 ps
CPU time 3.89 seconds
Started Jul 25 04:46:00 PM PDT 24
Finished Jul 25 04:46:04 PM PDT 24
Peak memory 222088 kb
Host smart-d92e0526-e599-4f24-8cc9-82e3228bc9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785785575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.785785575
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4009561379
Short name T5
Test name
Test status
Simulation time 39413214 ps
CPU time 2.47 seconds
Started Jul 25 04:46:16 PM PDT 24
Finished Jul 25 04:46:18 PM PDT 24
Peak memory 208732 kb
Host smart-9273da98-9911-4f9b-8a19-e2514266681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009561379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4009561379
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.240793178
Short name T697
Test name
Test status
Simulation time 288887986 ps
CPU time 5.68 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 210112 kb
Host smart-81bc460c-bb26-4e39-b1dc-5b7b4b88e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240793178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.240793178
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2134046175
Short name T461
Test name
Test status
Simulation time 30632711 ps
CPU time 2.31 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 208404 kb
Host smart-96590356-f53b-4eb6-8906-7aae3cc14d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134046175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2134046175
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3299596226
Short name T650
Test name
Test status
Simulation time 982173188 ps
CPU time 7.01 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 208420 kb
Host smart-4e72513a-d5be-4d31-ae88-fa7b6cd01298
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299596226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3299596226
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.391606172
Short name T591
Test name
Test status
Simulation time 44764847 ps
CPU time 2.52 seconds
Started Jul 25 04:45:50 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 206596 kb
Host smart-6ce2ae31-61b2-4337-a76a-33e49b19ef1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391606172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.391606172
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1332494178
Short name T253
Test name
Test status
Simulation time 70858396 ps
CPU time 2.98 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 206512 kb
Host smart-87d378f5-d5c0-4e95-8d50-5971b2a030be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332494178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1332494178
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2131566653
Short name T548
Test name
Test status
Simulation time 299041133 ps
CPU time 1.88 seconds
Started Jul 25 04:45:57 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 215504 kb
Host smart-b6a0a479-3e69-4850-8b66-6dd7ee2f2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131566653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2131566653
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1832942428
Short name T647
Test name
Test status
Simulation time 88161375 ps
CPU time 3.3 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 208188 kb
Host smart-334b1b39-c968-45c5-bec7-bbe3e571217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832942428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1832942428
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3134428592
Short name T334
Test name
Test status
Simulation time 204751062 ps
CPU time 3.28 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 209632 kb
Host smart-1a982a08-4a00-4d11-9474-8ba736f05e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134428592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3134428592
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.858334595
Short name T798
Test name
Test status
Simulation time 44147971 ps
CPU time 2.57 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 210132 kb
Host smart-7747d2e6-945e-42e0-a159-b5aa51525fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858334595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.858334595
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1480544678
Short name T416
Test name
Test status
Simulation time 29112672 ps
CPU time 0.72 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 205764 kb
Host smart-3a9d6c31-2547-412e-b841-5394a690c20c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480544678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1480544678
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1756086363
Short name T4
Test name
Test status
Simulation time 145088872 ps
CPU time 2.91 seconds
Started Jul 25 04:46:09 PM PDT 24
Finished Jul 25 04:46:12 PM PDT 24
Peak memory 214708 kb
Host smart-146f0798-14fd-45ab-b425-0c25bc82da8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756086363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1756086363
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.924405859
Short name T22
Test name
Test status
Simulation time 224148591 ps
CPU time 3.52 seconds
Started Jul 25 04:45:48 PM PDT 24
Finished Jul 25 04:45:52 PM PDT 24
Peak memory 217296 kb
Host smart-a69961d1-b1d0-4fef-9acb-c3f775752dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924405859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.924405859
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2792695008
Short name T502
Test name
Test status
Simulation time 54639332 ps
CPU time 2.58 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 208552 kb
Host smart-9a034bb9-1636-4690-80bf-be6f577e8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792695008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2792695008
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3666926647
Short name T82
Test name
Test status
Simulation time 153633279 ps
CPU time 2.71 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 215096 kb
Host smart-afc9590e-ae00-4555-b1b2-c1caf093cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666926647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3666926647
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4098268160
Short name T645
Test name
Test status
Simulation time 136456259 ps
CPU time 2.51 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:25 PM PDT 24
Peak memory 213980 kb
Host smart-980c8375-ccdc-4b3e-bac9-83ec89aa5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098268160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4098268160
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3413048680
Short name T710
Test name
Test status
Simulation time 112102415 ps
CPU time 4.04 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:25 PM PDT 24
Peak memory 214232 kb
Host smart-ba8a026c-deb5-4adc-8869-a2ec1b3190b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413048680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3413048680
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1961926799
Short name T703
Test name
Test status
Simulation time 324397650 ps
CPU time 11.34 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 218128 kb
Host smart-6f2c7c8f-5a6c-4b87-9d3b-7bedb303943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961926799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1961926799
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3338726270
Short name T816
Test name
Test status
Simulation time 75636629 ps
CPU time 3.11 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 207064 kb
Host smart-158595d8-d2a6-47de-9a4b-4eb0f74bcaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338726270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3338726270
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.472443121
Short name T534
Test name
Test status
Simulation time 284605219 ps
CPU time 4.85 seconds
Started Jul 25 04:46:11 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 206636 kb
Host smart-d8620be3-ceb3-40ba-8c00-976db7f90c14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472443121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.472443121
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4178215406
Short name T622
Test name
Test status
Simulation time 142743462 ps
CPU time 2.26 seconds
Started Jul 25 04:45:59 PM PDT 24
Finished Jul 25 04:46:01 PM PDT 24
Peak memory 206836 kb
Host smart-e8a0231a-0bf2-49ff-8fcc-1a417a3be739
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178215406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4178215406
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3317852461
Short name T680
Test name
Test status
Simulation time 1124396930 ps
CPU time 22.45 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:55 PM PDT 24
Peak memory 208652 kb
Host smart-9047a52c-99c5-4c04-98f4-8dba92f0f698
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317852461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3317852461
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3903339874
Short name T459
Test name
Test status
Simulation time 191029210 ps
CPU time 2.07 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 207756 kb
Host smart-305256fb-8435-43c7-a968-58df3789cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903339874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3903339874
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.310346419
Short name T424
Test name
Test status
Simulation time 343070043 ps
CPU time 6.39 seconds
Started Jul 25 04:45:53 PM PDT 24
Finished Jul 25 04:45:59 PM PDT 24
Peak memory 206796 kb
Host smart-35ee65c5-2718-4bc8-b5a1-774c5bd41d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310346419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.310346419
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1031845945
Short name T183
Test name
Test status
Simulation time 554250210 ps
CPU time 19.33 seconds
Started Jul 25 04:46:05 PM PDT 24
Finished Jul 25 04:46:25 PM PDT 24
Peak memory 222212 kb
Host smart-76880a1d-9816-40ba-97de-1cfabfdbb0d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031845945 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1031845945
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2332919724
Short name T606
Test name
Test status
Simulation time 123989794 ps
CPU time 5.23 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 214048 kb
Host smart-e2324d8c-66b2-4547-89de-54d19f916c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332919724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2332919724
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3746454802
Short name T375
Test name
Test status
Simulation time 82957014 ps
CPU time 3.15 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 210320 kb
Host smart-a4724c2c-e7b1-46aa-9c67-5413a5f56e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746454802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3746454802
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2151159125
Short name T600
Test name
Test status
Simulation time 14558102 ps
CPU time 0.74 seconds
Started Jul 25 04:44:21 PM PDT 24
Finished Jul 25 04:44:22 PM PDT 24
Peak memory 205832 kb
Host smart-b1b736d4-6f88-4528-a341-0db7c174b15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151159125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2151159125
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3235941839
Short name T517
Test name
Test status
Simulation time 56566611 ps
CPU time 2.07 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:35 PM PDT 24
Peak memory 222352 kb
Host smart-3a5984ea-f1a8-4036-b3ac-9ea7bef13044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235941839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3235941839
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1472833197
Short name T62
Test name
Test status
Simulation time 125899005 ps
CPU time 2.74 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 207940 kb
Host smart-9e846b6b-c6a2-4a22-9a13-fb1a7932be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472833197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1472833197
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.341110708
Short name T88
Test name
Test status
Simulation time 181389972 ps
CPU time 4.23 seconds
Started Jul 25 04:44:28 PM PDT 24
Finished Jul 25 04:44:33 PM PDT 24
Peak memory 214044 kb
Host smart-a010ffb8-aabf-446b-a42a-a6a23f21bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341110708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.341110708
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.908417044
Short name T43
Test name
Test status
Simulation time 116786762 ps
CPU time 5.06 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 222144 kb
Host smart-d418a9cb-5004-481a-947e-c264c459fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908417044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.908417044
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1292824920
Short name T733
Test name
Test status
Simulation time 307875739 ps
CPU time 3.02 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 207388 kb
Host smart-b84443c2-3316-4655-93d7-d3fa03103274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292824920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1292824920
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2760693610
Short name T309
Test name
Test status
Simulation time 127789471 ps
CPU time 5.73 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 209896 kb
Host smart-452b690d-1917-46a4-a45b-35a0ff374d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760693610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2760693610
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2049672823
Short name T832
Test name
Test status
Simulation time 543872276 ps
CPU time 18.63 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:57 PM PDT 24
Peak memory 207804 kb
Host smart-dd1c13ac-1940-4b47-bc24-c43c3fadca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049672823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2049672823
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2951369406
Short name T302
Test name
Test status
Simulation time 635439933 ps
CPU time 3.26 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 208444 kb
Host smart-62449f23-8ed7-483b-8077-048157396139
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951369406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2951369406
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2289561439
Short name T758
Test name
Test status
Simulation time 99258651 ps
CPU time 3.33 seconds
Started Jul 25 04:44:23 PM PDT 24
Finished Jul 25 04:44:27 PM PDT 24
Peak memory 208440 kb
Host smart-b09663fd-5d68-4503-9644-3f7fc2dfabc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289561439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2289561439
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3220297821
Short name T427
Test name
Test status
Simulation time 8154801007 ps
CPU time 17.05 seconds
Started Jul 25 04:44:26 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 208508 kb
Host smart-15d055d0-5782-40d4-b281-51a34979fe36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220297821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3220297821
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3236012457
Short name T98
Test name
Test status
Simulation time 136715885 ps
CPU time 2.68 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 214064 kb
Host smart-df3ba3c9-c824-46f1-bc15-93dc612b8743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236012457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3236012457
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3026287812
Short name T386
Test name
Test status
Simulation time 69354172 ps
CPU time 1.63 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 206612 kb
Host smart-641e6b27-dc3f-401d-8be8-9f7a73de9814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026287812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3026287812
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1459680132
Short name T821
Test name
Test status
Simulation time 257819025 ps
CPU time 10.66 seconds
Started Jul 25 04:44:13 PM PDT 24
Finished Jul 25 04:44:24 PM PDT 24
Peak memory 219988 kb
Host smart-835fb6db-ac49-4edd-84ec-9931046ddb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459680132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1459680132
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1647008002
Short name T120
Test name
Test status
Simulation time 307583176 ps
CPU time 8.82 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 222264 kb
Host smart-c46ec02a-c164-47b9-947c-c76e298663b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647008002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1647008002
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2535601174
Short name T232
Test name
Test status
Simulation time 588218455 ps
CPU time 5.81 seconds
Started Jul 25 04:44:39 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 209428 kb
Host smart-cba41616-870b-430c-b7ac-49d5b0a709e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535601174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2535601174
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4288938556
Short name T374
Test name
Test status
Simulation time 70960374 ps
CPU time 2.73 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 209792 kb
Host smart-fd61a3dc-6f56-4b7c-91e0-2336495a3c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288938556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4288938556
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4110692163
Short name T513
Test name
Test status
Simulation time 26547505 ps
CPU time 0.74 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 205776 kb
Host smart-7272fed0-5607-49fb-893c-e5869ec4f692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110692163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4110692163
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1742169056
Short name T41
Test name
Test status
Simulation time 604964281 ps
CPU time 6.57 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 218772 kb
Host smart-26d37da0-c38c-43eb-8eba-cdef3264848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742169056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1742169056
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2117555494
Short name T569
Test name
Test status
Simulation time 185906881 ps
CPU time 5.34 seconds
Started Jul 25 04:44:24 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 207488 kb
Host smart-84b6bd73-29bf-4795-b5f2-13c41b64cc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117555494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2117555494
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2027197891
Short name T679
Test name
Test status
Simulation time 713229144 ps
CPU time 5.77 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:38 PM PDT 24
Peak memory 208812 kb
Host smart-cd2c656e-96cd-4a7d-bfa2-77506ff68c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027197891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2027197891
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3308264110
Short name T356
Test name
Test status
Simulation time 1868793365 ps
CPU time 7.16 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 222148 kb
Host smart-d9411b16-b050-498a-879b-8691e515f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308264110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3308264110
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4283391686
Short name T756
Test name
Test status
Simulation time 164665775 ps
CPU time 3.4 seconds
Started Jul 25 04:44:44 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 208888 kb
Host smart-af662520-1dd1-49dd-be00-7db79511922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283391686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4283391686
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2458830868
Short name T750
Test name
Test status
Simulation time 79806976 ps
CPU time 3.8 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 209996 kb
Host smart-53646711-7917-4391-b6e3-d3b933989ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458830868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2458830868
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1857115171
Short name T527
Test name
Test status
Simulation time 99142964 ps
CPU time 2.17 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:24 PM PDT 24
Peak memory 208388 kb
Host smart-65fe8343-91d3-4aa4-afd1-2133708b8b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857115171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1857115171
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1531634454
Short name T500
Test name
Test status
Simulation time 206219183 ps
CPU time 4.26 seconds
Started Jul 25 04:44:12 PM PDT 24
Finished Jul 25 04:44:16 PM PDT 24
Peak memory 207932 kb
Host smart-b3e64472-3567-4d78-8464-7d3e97e1471c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531634454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1531634454
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3528688804
Short name T582
Test name
Test status
Simulation time 345219201 ps
CPU time 2.62 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 206556 kb
Host smart-f200c51b-2ba2-4635-8b40-4335567147f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528688804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3528688804
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3022863767
Short name T627
Test name
Test status
Simulation time 53958156 ps
CPU time 2.68 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 206680 kb
Host smart-36d101ed-6577-4606-8fbc-327ca1f4fd15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022863767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3022863767
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2316012620
Short name T882
Test name
Test status
Simulation time 558439478 ps
CPU time 3.28 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:18 PM PDT 24
Peak memory 207572 kb
Host smart-92927b89-f6f8-4cdd-8d55-ce378313ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316012620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2316012620
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2429297035
Short name T382
Test name
Test status
Simulation time 1317962351 ps
CPU time 4.21 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 208168 kb
Host smart-4f419a81-a542-455b-a33b-20e52e4440f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429297035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2429297035
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1725689835
Short name T830
Test name
Test status
Simulation time 2764102508 ps
CPU time 28.74 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:45:02 PM PDT 24
Peak memory 219632 kb
Host smart-b7ed5c4c-0d58-468e-8ad2-f0d04c034760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725689835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1725689835
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2553459545
Short name T75
Test name
Test status
Simulation time 398272959 ps
CPU time 12.56 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:45:00 PM PDT 24
Peak memory 222244 kb
Host smart-304be8d6-7884-467b-8d9b-606ba58187c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553459545 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2553459545
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2189321237
Short name T792
Test name
Test status
Simulation time 198668158 ps
CPU time 3.52 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 207436 kb
Host smart-4c7a460a-35bb-4853-88d9-f073648015e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189321237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2189321237
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.61617281
Short name T475
Test name
Test status
Simulation time 120824899 ps
CPU time 3.5 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 210088 kb
Host smart-baf5c518-1135-4c29-a358-ba9383023af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61617281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.61617281
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.821918740
Short name T508
Test name
Test status
Simulation time 32878286 ps
CPU time 0.71 seconds
Started Jul 25 04:44:42 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 205732 kb
Host smart-30e6ea0b-9347-4f64-acba-f409ff08e445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821918740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.821918740
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1806769786
Short name T40
Test name
Test status
Simulation time 536254988 ps
CPU time 4.85 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 216696 kb
Host smart-e1aefcd0-9f02-48f6-869f-b1d4f3811a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806769786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1806769786
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2987749886
Short name T696
Test name
Test status
Simulation time 71066451 ps
CPU time 1.61 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 207400 kb
Host smart-3337149b-fd8e-4b4d-b588-d1da78e53e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987749886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2987749886
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2761757108
Short name T839
Test name
Test status
Simulation time 128531645 ps
CPU time 3.5 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 214548 kb
Host smart-969b8926-bfa1-4bd0-b207-34b99d093c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761757108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2761757108
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3292011495
Short name T886
Test name
Test status
Simulation time 404158264 ps
CPU time 3.42 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 214136 kb
Host smart-9c2a800a-d6db-4839-a26b-ef2c0725eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292011495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3292011495
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.61957490
Short name T453
Test name
Test status
Simulation time 117905015 ps
CPU time 5.12 seconds
Started Jul 25 04:44:25 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 222152 kb
Host smart-bc681c43-e243-42a3-a592-2ccad54ea213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61957490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.61957490
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1275893171
Short name T535
Test name
Test status
Simulation time 167481147 ps
CPU time 3.4 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 208532 kb
Host smart-9a519465-693a-49d0-9cde-7ea6a6728c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275893171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1275893171
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4132526534
Short name T897
Test name
Test status
Simulation time 60919325 ps
CPU time 2.95 seconds
Started Jul 25 04:44:31 PM PDT 24
Finished Jul 25 04:44:34 PM PDT 24
Peak memory 208316 kb
Host smart-210f9557-f462-4385-8268-01f0fd02874c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132526534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4132526534
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1432854517
Short name T791
Test name
Test status
Simulation time 813470266 ps
CPU time 2.69 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 206644 kb
Host smart-a5a3d79b-a8cb-4a3e-83fb-a686ad73d9e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432854517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1432854517
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.113340419
Short name T734
Test name
Test status
Simulation time 783216175 ps
CPU time 6.82 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 208120 kb
Host smart-3dc42c6e-499f-46a5-b5d0-8a0ee0077f46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113340419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.113340419
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3095910832
Short name T361
Test name
Test status
Simulation time 83704977 ps
CPU time 2.65 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 215000 kb
Host smart-7d35e1b3-cdc4-499b-ae88-2c900f0b9027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095910832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3095910832
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1095602522
Short name T732
Test name
Test status
Simulation time 511152442 ps
CPU time 2.6 seconds
Started Jul 25 04:44:42 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 207996 kb
Host smart-ec77d30c-c7d0-4d62-bca3-196db71d5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095602522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1095602522
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3537340362
Short name T793
Test name
Test status
Simulation time 4087193497 ps
CPU time 37.97 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:45:08 PM PDT 24
Peak memory 215916 kb
Host smart-07d554a1-d55b-4396-9e1a-d16b7904514f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537340362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3537340362
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1177857802
Short name T661
Test name
Test status
Simulation time 208588559 ps
CPU time 9.56 seconds
Started Jul 25 04:45:39 PM PDT 24
Finished Jul 25 04:45:49 PM PDT 24
Peak memory 222240 kb
Host smart-b25faa5e-cbdc-4d57-a4e3-3b2edb12fe08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177857802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1177857802
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2846068094
Short name T277
Test name
Test status
Simulation time 174528174 ps
CPU time 4.39 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 207800 kb
Host smart-61c74f3c-4e7a-463b-bf1c-01055dd737ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846068094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2846068094
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2637332651
Short name T174
Test name
Test status
Simulation time 546197687 ps
CPU time 1.89 seconds
Started Jul 25 04:44:51 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 209900 kb
Host smart-247eb31d-85ed-4c11-9be2-edf05c334237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637332651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2637332651
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2498983966
Short name T799
Test name
Test status
Simulation time 100722920 ps
CPU time 0.92 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 205860 kb
Host smart-64145a9b-2df7-4fbc-aa80-66b0ea945723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498983966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2498983966
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2639566346
Short name T276
Test name
Test status
Simulation time 110078338 ps
CPU time 3.86 seconds
Started Jul 25 04:44:50 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 214844 kb
Host smart-dbd2023d-ba7e-4745-9344-5d6760d0193c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639566346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2639566346
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1408301425
Short name T371
Test name
Test status
Simulation time 61909879 ps
CPU time 2.68 seconds
Started Jul 25 04:45:37 PM PDT 24
Finished Jul 25 04:45:40 PM PDT 24
Peak memory 209480 kb
Host smart-410a29e9-49c5-41fc-80d2-e314a7a14d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408301425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1408301425
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2117166385
Short name T285
Test name
Test status
Simulation time 168609359 ps
CPU time 2.66 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 214044 kb
Host smart-06880205-2027-4f43-87a7-0eba4b58e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117166385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2117166385
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2683619038
Short name T580
Test name
Test status
Simulation time 220334268 ps
CPU time 7.24 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 208760 kb
Host smart-638356d8-8e1c-46a7-9fc3-184b1a3ce5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683619038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2683619038
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2050750168
Short name T352
Test name
Test status
Simulation time 354480184 ps
CPU time 4.8 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 221120 kb
Host smart-a7719c56-a853-43e6-bca7-75f9649b24e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050750168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2050750168
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1433211267
Short name T841
Test name
Test status
Simulation time 674111078 ps
CPU time 18.42 seconds
Started Jul 25 04:45:45 PM PDT 24
Finished Jul 25 04:46:03 PM PDT 24
Peak memory 208964 kb
Host smart-912a3f97-befb-4c08-9955-23c8cc84bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433211267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1433211267
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1823236319
Short name T573
Test name
Test status
Simulation time 519126207 ps
CPU time 4.01 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 207240 kb
Host smart-0da313c7-9c56-42f1-94a2-02a02ad54834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823236319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1823236319
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3823098479
Short name T187
Test name
Test status
Simulation time 254373548 ps
CPU time 3.03 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 208376 kb
Host smart-98e3115a-7b3c-4efc-8d46-2af32a182c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823098479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3823098479
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.978034083
Short name T712
Test name
Test status
Simulation time 473394748 ps
CPU time 3.32 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:35 PM PDT 24
Peak memory 207108 kb
Host smart-ddd58257-306d-4675-874a-634c84f785fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978034083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.978034083
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.830720465
Short name T621
Test name
Test status
Simulation time 357661673 ps
CPU time 4.52 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 208464 kb
Host smart-0ef20fce-61ef-4ffc-a68a-4be722409369
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830720465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.830720465
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3581501695
Short name T2
Test name
Test status
Simulation time 287007098 ps
CPU time 3.16 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 208672 kb
Host smart-302d32c5-3b0a-4bef-b035-f1ec8fb4fd35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581501695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3581501695
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2576794459
Short name T790
Test name
Test status
Simulation time 105482059 ps
CPU time 2.73 seconds
Started Jul 25 04:45:09 PM PDT 24
Finished Jul 25 04:45:12 PM PDT 24
Peak memory 208532 kb
Host smart-f86ba3ea-2fb6-4ef5-97e8-383d74ccbdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576794459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2576794459
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1886700778
Short name T490
Test name
Test status
Simulation time 89969497 ps
CPU time 3.31 seconds
Started Jul 25 04:44:34 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 208364 kb
Host smart-8b56b328-bd46-4438-914f-2dbe1d83341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886700778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1886700778
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3110226443
Short name T686
Test name
Test status
Simulation time 738420081 ps
CPU time 18.04 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:56 PM PDT 24
Peak memory 216412 kb
Host smart-c02f5e2d-7986-4d66-b8e0-c8b398def1bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110226443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3110226443
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2700204930
Short name T474
Test name
Test status
Simulation time 543721060 ps
CPU time 13.53 seconds
Started Jul 25 04:45:43 PM PDT 24
Finished Jul 25 04:45:56 PM PDT 24
Peak memory 208164 kb
Host smart-2fdeb161-7226-44ba-988c-75a26223b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700204930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2700204930
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3381993990
Short name T108
Test name
Test status
Simulation time 337578011 ps
CPU time 6.05 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:51 PM PDT 24
Peak memory 210644 kb
Host smart-6e84caee-9bf4-4ffe-8656-813f4e0f64fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381993990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3381993990
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.35830749
Short name T691
Test name
Test status
Simulation time 126670386 ps
CPU time 0.71 seconds
Started Jul 25 04:44:52 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 205824 kb
Host smart-45a8ba30-6fbb-4306-8499-661e66d52080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35830749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.35830749
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3662986972
Short name T643
Test name
Test status
Simulation time 103702164 ps
CPU time 2.85 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 216628 kb
Host smart-74726ff0-04ee-4277-a3e3-60707e8797db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662986972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3662986972
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2236902097
Short name T801
Test name
Test status
Simulation time 270075317 ps
CPU time 3.95 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:47 PM PDT 24
Peak memory 214116 kb
Host smart-48cef82c-34a2-460c-bc47-0670e7126091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236902097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2236902097
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3522959050
Short name T867
Test name
Test status
Simulation time 62773585 ps
CPU time 2.44 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 213956 kb
Host smart-717f97f5-d823-409a-b896-81de8a7e0402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522959050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3522959050
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2431774441
Short name T831
Test name
Test status
Simulation time 368629378 ps
CPU time 5.75 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 209256 kb
Host smart-0b3c9adc-3e5b-41ae-85c4-1317bb4417ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431774441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2431774441
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3800549951
Short name T575
Test name
Test status
Simulation time 111781522 ps
CPU time 2.1 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 208580 kb
Host smart-4d4f3889-c0d2-41b7-af29-0fdf551020af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800549951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3800549951
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.387299621
Short name T870
Test name
Test status
Simulation time 38808972 ps
CPU time 2.24 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 206588 kb
Host smart-8408b67c-6d92-4f22-8b42-051fc9472883
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387299621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.387299621
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3003206459
Short name T529
Test name
Test status
Simulation time 79501923 ps
CPU time 3.64 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 206664 kb
Host smart-29bb27dc-d276-425c-9a5c-47737237ef32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003206459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3003206459
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3468587318
Short name T847
Test name
Test status
Simulation time 614611591 ps
CPU time 6.72 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:52 PM PDT 24
Peak memory 208172 kb
Host smart-238c0cfa-94ad-4113-b1a8-5383e4056e30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468587318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3468587318
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1447169146
Short name T101
Test name
Test status
Simulation time 135930450 ps
CPU time 4.68 seconds
Started Jul 25 04:44:44 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 214128 kb
Host smart-b40cb53a-b5fb-4679-b91b-45bb4e934dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447169146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1447169146
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1376849773
Short name T460
Test name
Test status
Simulation time 122249929 ps
CPU time 2.14 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 206900 kb
Host smart-66ce7024-7bcc-4b64-aa91-c31ea1a1d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376849773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1376849773
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.610369346
Short name T366
Test name
Test status
Simulation time 1871198598 ps
CPU time 34.47 seconds
Started Jul 25 04:44:55 PM PDT 24
Finished Jul 25 04:45:30 PM PDT 24
Peak memory 215476 kb
Host smart-09d5264b-1e4f-4e6c-b653-f3030a5d0cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610369346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.610369346
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2644233502
Short name T181
Test name
Test status
Simulation time 2064682129 ps
CPU time 8.81 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 221400 kb
Host smart-a356bd1b-827b-4cbf-ad25-95380e5c2f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644233502 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2644233502
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2533400856
Short name T198
Test name
Test status
Simulation time 746251196 ps
CPU time 4.31 seconds
Started Jul 25 04:44:49 PM PDT 24
Finished Jul 25 04:44:53 PM PDT 24
Peak memory 207248 kb
Host smart-447d73f0-d4fc-4553-8e65-17a645267ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533400856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2533400856
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.449392992
Short name T677
Test name
Test status
Simulation time 1061010290 ps
CPU time 4.73 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:50 PM PDT 24
Peak memory 210164 kb
Host smart-f9aa0c77-bf6e-4d5b-8935-a87d403634c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449392992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.449392992
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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