Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

25

T2

4

T3

3

auto[1]

534

1

T1

3

T11

3

T23

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

25

T2

4

T3

3

auto[1]

534

1

T1

3

T11

3

T23

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701

1

T1

28

T2

4

T3

3

auto[1]

555

1

T11

1

T13

2

T84

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701

1

T1

28

T2

4

T3

3

auto[1]

555

1

T11

1

T13

2

T84

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	388	1			T1	3		T11	3		T12	2
auto[OpGenId]	1125	1			T1	6		T2	3		T3	3
auto[OpGenSwOut]	1138	1			T1	11		T2	1		T11	1
auto[OpGenHwOut]	2546	1			T1	8		T11	3		T13	9
auto[OpDisable]	59	1			T54	1		T58	1		T209	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	388	1			T1	3		T11	3		T12	2
auto[OpGenId]	1125	1			T1	6		T2	3		T3	3
auto[OpGenSwOut]	1138	1			T1	11		T2	1		T11	1
auto[OpGenHwOut]	2546	1			T1	8		T11	3		T13	9
auto[OpDisable]	59	1			T54	1		T58	1		T209	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4729

1

T1

23

T2

4

T3

3

auto[1]

527

1

T1

5

T11

1

T15

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4729

1

T1

23

T2

4

T3

3

auto[1]

527

1

T1

5

T11

1

T15

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5018

1

T1

28

T2

4

T3

3

auto[1]

238

1

T11

3

T117

7

T79

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1815	1			T1	11		T2	1		T3	1
auto[1]	723	1			T1	4		T11	3		T13	1
auto[2]	675	1			T1	6		T2	1		T11	1
auto[3]	669	1			T1	1		T11	2		T12	1
auto[4]	342	1			T2	1		T12	1		T16	2
auto[5]	372	1			T1	1		T13	2		T85	1
auto[6]	314	1			T1	2		T2	1		T3	1
auto[7]	346	1			T1	3		T3	1		T12	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1374	1			T1	6		T2	2		T3	2
clear_one[1]	723	1			T1	4		T11	3		T13	1
clear_one[2]	675	1			T1	6		T2	1		T11	1
clear_one[3]	669	1			T1	1		T11	2		T12	1
clear_none	1815	1			T1	11		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1014	1			T1	6		T2	3		T13	1
auto[StInit]	669	1			T1	3		T2	1		T3	1
auto[StCreatorRootKey]	550	1			T1	5		T3	1		T11	1
auto[StOwnerIntKey]	511	1			T1	3		T3	1		T11	1
auto[StOwnerKey]	448	1			T1	1		T13	1		T16	1
auto[StDisabled]	1804	1			T1	10		T11	4		T13	4
auto[StInvalid]	260	1			T12	5		T36	3		T37	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1014	1			T1	6		T2	3		T13	1
auto[StInit]	669	1			T1	3		T2	1		T3	1
auto[StCreatorRootKey]	550	1			T1	5		T3	1		T11	1
auto[StOwnerIntKey]	511	1			T1	3		T3	1		T11	1
auto[StOwnerKey]	448	1			T1	1		T13	1		T16	1
auto[StDisabled]	1804	1			T1	10		T11	4		T13	4
auto[StInvalid]	260	1			T12	5		T36	3		T37	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T239	1		T240	1		T241	1
auto[0]	auto[StReset]	auto[OpGenId]	163	1			T1	1		T2	1		T15	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	164	1			T1	3		T24	1		T26	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	271	1			T1	2		T13	1		T14	1
auto[0]	auto[StInit]	auto[OpAdvance]	37	1			T204	1		T25	1		T51	1
auto[0]	auto[StInit]	auto[OpGenId]	97	1			T3	1		T207	1		T43	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	87	1			T1	1		T129	1		T53	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	204	1			T11	1		T13	1		T85	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T1	1		T117	1		T51	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T1	1		T23	1		T38	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	44	1			T117	1		T53	1		T58	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	52	1			T1	1		T110	1		T20	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	21	1			T11	1		T117	1		T213	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T1	1		T113	1		T79	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	35	1			T43	1		T44	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T84	1		T86	1		T51	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T202	1		T242	1		T243	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T79	1		T140	1		T149	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T51	1		T209	1		T211	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T110	1		T58	1		T209	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T80	1		T244	1		T149	1
auto[0]	auto[StDisabled]	auto[OpGenId]	57	1			T84	1		T117	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T87	1		T117	1		T43	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T13	1		T86	1		T87	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T140	1		T64	1		T69	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T47	1		T245	1		T246	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T47	1		T91	1		T247	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T12	1		T36	1		T37	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T203	1		T91	1		T88	2
auto[1]	auto[StReset]	auto[OpGenId]	26	1			T203	1		T58	2		T63	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T51	1		T160	1		T248	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T53	1		T249	1		T250	2
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T251	1		T100	1		T102	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T21	1		T140	1		T252	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	16	1			T1	1		T117	1		T22	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	31	1			T15	1		T132	1		T21	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T253	1		T254	1		T48	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T43	2		T51	1		T58	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T15	1		T196	1		T198	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T85	1		T209	1		T6	2
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T25	1		T254	2		T234	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T1	1		T46	1		T51	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T207	1		T62	1		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T1	1		T132	1		T81	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T144	1		T255	1		T227	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T51	1		T140	1		T256	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T43	2		T205	1		T140	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T53	1		T257	1		T249	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T11	1		T65	1		T209	1
auto[1]	auto[StDisabled]	auto[OpGenId]	49	1			T53	1		T58	1		T201	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T1	1		T11	1		T25	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T11	1		T13	1		T132	1
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T258	1		T199	1		T228	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T259	1		T260	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T89	2		T262	1		T245	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T91	1		T262	1		T245	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T263	1		T264	1		T265	1
auto[2]	auto[StReset]	auto[OpGenId]	26	1			T2	1		T203	1		T53	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	15	1			T266	1		T267	1		T268	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T33	1		T132	2		T110	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T209	1		T269	1		T270	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T6	1		T196	1		T271	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T79	1		T272	1		T273	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T130	1		T274	1		T275	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T5	1		T140	1		T276	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	20	1			T43	1		T209	2		T201	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T1	1		T39	1		T253	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T132	1		T112	1		T82	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T276	1		T127	1		T277	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T58	1		T55	1		T208	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T278	1		T126	1		T279	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T280	1		T209	1		T281	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T202	1		T282	1		T283	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T1	1		T44	1		T145	2
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T202	1		T64	1		T124	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T213	1		T284	1		T143	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	19	1			T1	1		T209	1		T140	1
auto[2]	auto[StDisabled]	auto[OpGenId]	53	1			T1	1		T11	1		T23	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T1	2		T44	1		T211	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	141	1			T13	2		T23	1		T132	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T59	1		T285	1		T286	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	2	1			T287	1		T288	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T37	1		T47	1		T289	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T263	1		T290	1		T291	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T36	1		T88	1		T292	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T203	1		T6	1		T247	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T160	1		T58	1		T293	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T33	1		T58	1		T249	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T11	1		T294	1		T295	1
auto[3]	auto[StInit]	auto[OpGenId]	5	1			T6	1		T146	1		T232	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T1	1		T43	1		T146	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T21	1		T54	1		T22	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T296	1		T297	1		T124	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T209	1		T266	1		T63	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T54	1		T55	1		T258	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T11	1		T43	1		T81	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T298	1		T299	1		-	-
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T44	1		T58	1		T300	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T296	1		T217	1		T271	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T85	1		T39	1		T51	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T44	1		T266	1		T269	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T65	1		T196	1		T198	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T204	1		T207	1		T124	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T16	1		T85	1		T112	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T43	1		T54	1		T135	1
auto[3]	auto[StDisabled]	auto[OpGenId]	42	1			T207	1		T43	1		T44	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T111	1		T204	2		T43	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T16	1		T85	1		T86	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T140	1		T71	1		T301	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T12	1		T260	1		T302	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T89	1		T303	1		T304	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T37	1		T289	1		T291	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T36	1		T47	1		T91	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T305	1		T140	1		T306	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T51	1		T5	1		T232	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T132	1		T110	1		T112	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T90	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T2	1		T209	1		T198	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T55	1		T98	1		T276	2
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T16	1		T142	1		T100	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T53	1		T198	1		T307	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T140	1		T308	2		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T24	1		T195	1		T310	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T202	1		T146	1		T215	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T311	1		T31	1		T71	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T198	1		T28	1		T126	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T105	1		T312	1		T313	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T314	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T113	1		T315	1		T48	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T44	1		T201	1		T140	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T87	1		T132	1		T81	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T160	1		T140	1		T146	2
auto[4]	auto[StDisabled]	auto[OpGenId]	31	1			T43	1		T58	1		T209	3
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T43	1		T205	1		T139	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	65	1			T16	1		T86	1		T43	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T209	1		T72	1		T316	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T292	1		T289	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T203	1		T318	1		T260	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T12	1		T319	1		T320	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T321	1		T322	1		T320	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T113	1		T117	1		T4	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T53	1		T140	1		T267	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	11	1			T112	1		T58	1		T140	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T113	1		T140	1		T100	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T51	1		T295	1		T301	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T323	1		T232	1		T324	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T110	1		T53	1		T58	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T1	1		T278	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T111	1		T326	1		T232	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T53	1		T149	1		T327	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T13	1		T130	1		T202	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T276	1		T241	1		T232	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T251	1		T122	1		T228	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T6	1		T248	1		T228	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T257	1		T328	1		T138	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T140	1		T122	1		T323	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T59	1		T253	1		T329	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T149	1		T330	1		T331	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T13	1		T86	1		T280	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T117	2		T53	1		T209	1
auto[5]	auto[StDisabled]	auto[OpGenId]	37	1			T25	1		T79	1		T58	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T204	1		T43	1		T65	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T85	1		T112	1		T130	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T73	1		T76	1		T332	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T333	1		T334	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T88	2		T264	1		T289	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T91	1		T264	1		T335	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T262	1		T290	1		T336	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T330	1		T337	1		T232	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T2	1		T338	1		T151	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T112	1		T203	1		T249	1
auto[6]	auto[StInit]	auto[OpAdvance]	7	1			T63	1		T202	1		T223	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T71	1		T339	1		T340	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T39	1		T198	1		T341	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T140	1		T198	1		T312	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T44	1		T342	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T3	1		T58	1		T140	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T71	1		T343	1		T344	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T16	1		T86	1		T87	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T345	1		T151	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T70	1		T295	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T249	1		T347	1		T348	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T69	1		T349	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T350	1		T351	1		T352	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T101	1		T127	1		T232	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T353	1		T220	1		T354	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T151	1		T355	1		T71	1
auto[6]	auto[StDisabled]	auto[OpGenId]	24	1			T356	1		T300	1		T6	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T1	1		T43	1		T356	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T1	1		T16	2		T86	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T54	1		T58	1		T357	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T246	1		T358	1		T359	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T12	1		T247	1		T322	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T360	1		T361	1		T362	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T363	1		T364	1		T362	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T123	1		T147	1		T297	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T44	1		T55	1		T293	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T132	1		T110	1		T117	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T160	1		T6	1		T225	1
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T33	1		T22	1		T90	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T306	1		T123	1		T102	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T112	1		T20	1		T365	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T33	1		T160	1		T366	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T46	1		T356	1		T269	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T140	1		T150	1		T124	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T328	1		T281	1		T285	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T232	1		T367	1		T368	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T3	1		T94	1		T369	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T150	1		T370	1		T48	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T13	1		T16	1		T110	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T25	1		T151	1		T371	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T90	1		T372	1		T103	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T373	1		T325	1		T374	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T24	1		T375	1		T376	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T43	1		T79	1		T251	1
auto[7]	auto[StDisabled]	auto[OpGenId]	21	1			T58	1		T6	1		T140	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T209	1		T377	1		T217	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T1	3		T85	2		T44	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T69	1		T123	1		T228	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T12	1		T261	1		T378	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T262	1		T319	1		T379	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T245	1		T320	1		T380	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T381	1		-	-		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1374

1

T1

6

T2

2

T3

2

clear_one[1]

auto[0]

auto[0]

auto[0]

414

1

T1

3

T11

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

130

1

T1

1

T15

1

T132

2

clear_one[1]

auto[0]

auto[1]

auto[0]

136

1

T13

1

T85

1

T46

1

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T11

1

T113

1

T25

1

clear_one[2]

auto[0]

auto[0]

auto[0]

384

1

T1

2

T2

1

T13

2

clear_one[2]

auto[0]

auto[0]

auto[1]

114

1

T1

2

T23

1

T132

2

clear_one[2]

auto[1]

auto[0]

auto[0]

138

1

T1

2

T11

1

T112

2

clear_one[2]

auto[1]

auto[0]

auto[1]

39

1

T23

1

T145

6

T98

1

clear_one[3]

auto[0]

auto[0]

auto[0]

375

1

T1

1

T11

1

T12

1

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T85

3

T24

1

T207

1

clear_one[3]

auto[1]

auto[0]

auto[0]

128

1

T11

1

T111

1

T112

2

clear_one[3]

auto[1]

auto[1]

auto[0]

36

1

T204

3

T58

1

T6

1

clear_none

auto[0]

auto[0]

auto[0]

1326

1

T1

8

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

132

1

T1

2

T86

2

T132

2

clear_none

auto[0]

auto[1]

auto[0]

132

1

T13

1

T110

2

T207

1

clear_none

auto[0]

auto[1]

auto[1]

32

1

T113

1

T20

1

T44

2

clear_none

auto[1]

auto[0]

auto[0]

127

1

T1

1

T11

1

T87

2

clear_none

auto[1]

auto[0]

auto[1]

20

1

T79

2

T63

1

T242

1

clear_none

auto[1]

auto[1]

auto[0]

29

1

T84

2

T43

1

T51

1

clear_none

auto[1]

auto[1]

auto[1]

17

1

T80

1

T242

1

T377

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1311	1			T1	6		T2	2		T3	2
clear_all	auto[1]	63	1			T117	2		T160	1		T269	2
clear_one[1]	auto[0]	681	1			T1	4		T11	1		T13	1
clear_one[1]	auto[1]	42	1			T11	2		T253	2		T144	1
clear_one[2]	auto[0]	643	1			T1	6		T2	1		T11	1
clear_one[2]	auto[1]	32	1			T253	1		T135	1		T145	7
clear_one[3]	auto[0]	636	1			T1	1		T11	1		T12	1
clear_one[3]	auto[1]	33	1			T11	1		T145	1		T296	7
clear_none	auto[0]	1747	1			T1	11		T2	1		T3	1
clear_none	auto[1]	68	1			T117	5		T79	2		T253	1