Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11381

1

T1

88

T2

10

T3

11

auto[Attestation]

7753

1

T1

54

T2

5

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2869	1			T1	26		T2	3		T3	4
auto[Aes]	3434	1			T1	24		T2	1		T3	2
auto[Kmac]	3459	1			T1	15		T2	3		T3	4
auto[Otbn]	3344	1			T1	24		T2	2		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7668	1			T1	59		T2	2		T3	4
auto[OpGenId]	6028	1			T1	53		T2	6		T3	4
auto[OpGenSwOut]	6075	1			T1	54		T2	7		T3	5
auto[OpGenHwOut]	7031	1			T1	35		T2	2		T3	8
auto[OpDisable]	132	1			T1	1		T46	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10689

1

T1

70

T2

6

T3

14

auto[OpDoneFail]

16245

1

T1

132

T2

11

T3

7

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6534	1			T1	59		T2	9		T3	6
auto[StInit]	3805	1			T1	21		T2	4		T3	3
auto[StCreatorRootKey]	3315	1			T1	22		T2	4		T3	3
auto[StOwnerIntKey]	2718	1			T1	18		T3	2		T11	1
auto[StOwnerKey]	2501	1			T1	14		T3	7		T11	3
auto[StDisabled]	8061	1			T1	68		T11	8		T13	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	365	1			T1	5		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T39	1		T51	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T1	1		T43	1		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T1	1		T87	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	73	1			T17	1		T54	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T1	1		T84	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T1	2		T11	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T1	1		T84	1		T206	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T11	1		T117	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	60	1			T17	1		T43	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T1	1		T24	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	237	1			T1	2		T11	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	338	1			T1	3		T2	2		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	84	1			T1	1		T34	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T1	1		T113	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T1	1		T24	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T3	1		T204	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	235	1			T84	1		T111	1		T43	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	320	1			T1	5		T14	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T1	2		T2	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T1	2		T35	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T117	1		T51	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T87	1		T44	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	199	1			T1	2		T84	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	78	1			T1	1		T51	3		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T34	1		T39	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	95	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T87	1		T43	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T43	1		T44	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	226	1			T1	3		T84	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	84	1			T1	1		T51	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T1	3		T33	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T24	1		T58	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	73	1			T17	1		T24	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	239	1			T1	2		T84	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	83	1			T51	2		T44	3		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	103	1			T17	1		T23	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T1	1		T24	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T84	1		T24	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T117	1		T53	2		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	209	1			T1	3		T24	2		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T1	2		T58	1		T209	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	91	1			T43	1		T51	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T1	1		T51	1		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T43	2		T21	1		T53	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	60	1			T1	1		T3	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T1	2		T84	2		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	295	1			T1	4		T3	1		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T1	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T209	1		T211	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T17	1		T21	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T79	2		T6	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	201	1			T1	2		T23	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	455	1			T3	1		T14	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	123	1			T15	1		T35	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	114	1			T11	1		T15	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T1	1		T111	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	291	1			T1	4		T23	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	492	1			T2	1		T13	3		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T1	1		T17	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T13	1		T87	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T13	1		T110	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	105	1			T3	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	288	1			T1	1		T13	1		T85	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	450	1			T1	3		T3	1		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T1	1		T16	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T1	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T16	1		T132	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T23	1		T86	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	272	1			T1	1		T16	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	53	1			T1	1		T51	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T11	1		T24	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T39	1		T129	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T44	1		T65	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T51	1		T53	2		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	192	1			T1	4		T23	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T1	1		T43	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	114	1			T33	1		T87	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T15	2		T33	1		T112	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T1	1		T17	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T112	1		T51	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	292	1			T1	3		T23	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	40	1			T1	2		T209	1		T140	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	140	1			T13	1		T17	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T85	1		T110	1		T206	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T84	1		T85	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	99	1			T3	2		T13	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	269	1			T1	1		T11	1		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	44	1			T51	1		T209	2		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	101	1			T2	1		T23	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	127	1			T1	1		T86	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T86	1		T24	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T3	1		T16	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	277	1			T11	1		T16	2		T23	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T1	2		T17	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	693	1			T1	6		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	197	1			T1	1		T11	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	687	1			T1	5		T11	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T1	2		T3	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	680	1			T1	4		T2	2		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	217	1			T1	2		T87	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	644	1			T1	9		T2	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	211	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	432	1			T1	4		T34	1		T84	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	431	1			T1	6		T33	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	212	1			T1	1		T84	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	415	1			T1	3		T17	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T1	2		T3	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	416	1			T1	4		T84	2		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	178	1			T17	1		T21	1		T79	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	637	1			T1	7		T3	1		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	279	1			T1	2		T3	1		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	878	1			T1	4		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T3	1		T13	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	920	1			T1	2		T2	1		T13	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T1	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	877	1			T1	5		T3	1		T11	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	163	1			T39	1		T51	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	348	1			T1	5		T11	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T1	1		T15	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	484	1			T1	4		T33	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T3	2		T13	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	468	1			T1	3		T11	1		T13	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T1	1		T3	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	449	1			T2	1		T11	1		T16	2