Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32948

1

T1

233

T2

19

T3

23

auto[1]

242

1

T11

8

T117

10

T79

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32956	1			T1	233		T2	19		T3	23
auto[134217728:268435455]	6	1			T79	1		T402	1		T314	1
auto[268435456:402653183]	8	1			T11	1		T117	1		T147	1
auto[402653184:536870911]	4	1			T150	1		T390	1		T323	1
auto[536870912:671088639]	8	1			T144	1		T242	1		T145	1
auto[671088640:805306367]	7	1			T160	1		T253	1		T150	1
auto[805306368:939524095]	10	1			T11	1		T117	1		T147	1
auto[939524096:1073741823]	3	1			T391	1		T403	1		T404	1
auto[1073741824:1207959551]	1	1			T146	1		-	-		-	-
auto[1207959552:1342177279]	5	1			T11	1		T117	1		T390	1
auto[1342177280:1476395007]	6	1			T135	1		T269	1		T150	1
auto[1476395008:1610612735]	13	1			T11	2		T160	1		T269	2
auto[1610612736:1744830463]	13	1			T296	2		T150	1		T151	1
auto[1744830464:1879048191]	9	1			T11	1		T253	3		T145	1
auto[1879048192:2013265919]	5	1			T276	1		T239	1		T405	1
auto[2013265920:2147483647]	6	1			T144	1		T239	1		T241	1
auto[2147483648:2281701375]	13	1			T11	1		T253	2		T242	1
auto[2281701376:2415919103]	10	1			T117	1		T253	1		T145	1
auto[2415919104:2550136831]	6	1			T117	1		T151	1		T283	1
auto[2550136832:2684354559]	7	1			T390	2		T314	1		T406	1
auto[2684354560:2818572287]	10	1			T117	1		T79	1		T407	1
auto[2818572288:2952790015]	7	1			T117	1		T296	1		T146	1
auto[2952790016:3087007743]	10	1			T11	1		T150	1		T390	2
auto[3087007744:3221225471]	10	1			T117	1		T269	1		T145	2
auto[3221225472:3355443199]	7	1			T253	1		T145	1		T239	1
auto[3355443200:3489660927]	6	1			T146	1		T276	1		T150	1
auto[3489660928:3623878655]	8	1			T253	1		T135	1		T145	1
auto[3623878656:3758096383]	10	1			T145	1		T150	1		T151	1
auto[3758096384:3892314111]	6	1			T150	1		T283	1		T391	1
auto[3892314112:4026531839]	9	1			T117	2		T269	1		T150	1
auto[4026531840:4160749567]	5	1			T390	1		T307	1		T283	1
auto[4160749568:4294967295]	6	1			T269	1		T144	1		T146	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32948	1			T1	233		T2	19		T3	23
auto[0:134217727]	auto[1]	8	1			T253	1		T269	1		T296	1
auto[134217728:268435455]	auto[1]	6	1			T79	1		T402	1		T314	1
auto[268435456:402653183]	auto[1]	8	1			T11	1		T117	1		T147	1
auto[402653184:536870911]	auto[1]	4	1			T150	1		T390	1		T323	1
auto[536870912:671088639]	auto[1]	8	1			T144	1		T242	1		T145	1
auto[671088640:805306367]	auto[1]	7	1			T160	1		T253	1		T150	1
auto[805306368:939524095]	auto[1]	10	1			T11	1		T117	1		T147	1
auto[939524096:1073741823]	auto[1]	3	1			T391	1		T403	1		T404	1
auto[1073741824:1207959551]	auto[1]	1	1			T146	1		-	-		-	-
auto[1207959552:1342177279]	auto[1]	5	1			T11	1		T117	1		T390	1
auto[1342177280:1476395007]	auto[1]	6	1			T135	1		T269	1		T150	1
auto[1476395008:1610612735]	auto[1]	13	1			T11	2		T160	1		T269	2
auto[1610612736:1744830463]	auto[1]	13	1			T296	2		T150	1		T151	1
auto[1744830464:1879048191]	auto[1]	9	1			T11	1		T253	3		T145	1
auto[1879048192:2013265919]	auto[1]	5	1			T276	1		T239	1		T405	1
auto[2013265920:2147483647]	auto[1]	6	1			T144	1		T239	1		T241	1
auto[2147483648:2281701375]	auto[1]	13	1			T11	1		T253	2		T242	1
auto[2281701376:2415919103]	auto[1]	10	1			T117	1		T253	1		T145	1
auto[2415919104:2550136831]	auto[1]	6	1			T117	1		T151	1		T283	1
auto[2550136832:2684354559]	auto[1]	7	1			T390	2		T314	1		T406	1
auto[2684354560:2818572287]	auto[1]	10	1			T117	1		T79	1		T407	1
auto[2818572288:2952790015]	auto[1]	7	1			T117	1		T296	1		T146	1
auto[2952790016:3087007743]	auto[1]	10	1			T11	1		T150	1		T390	2
auto[3087007744:3221225471]	auto[1]	10	1			T117	1		T269	1		T145	2
auto[3221225472:3355443199]	auto[1]	7	1			T253	1		T145	1		T239	1
auto[3355443200:3489660927]	auto[1]	6	1			T146	1		T276	1		T150	1
auto[3489660928:3623878655]	auto[1]	8	1			T253	1		T135	1		T145	1
auto[3623878656:3758096383]	auto[1]	10	1			T145	1		T150	1		T151	1
auto[3758096384:3892314111]	auto[1]	6	1			T150	1		T283	1		T391	1
auto[3892314112:4026531839]	auto[1]	9	1			T117	2		T269	1		T150	1
auto[4026531840:4160749567]	auto[1]	5	1			T390	1		T307	1		T283	1
auto[4160749568:4294967295]	auto[1]	6	1			T269	1		T144	1		T146	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1567

1

T1

16

T2

6

T11

4

auto[1]

1784

1

T1

8

T2

2

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T1	1		T113	1		T37	1
auto[134217728:268435455]	95	1			T2	1		T24	1		T113	2
auto[268435456:402653183]	92	1			T2	1		T33	1		T43	1
auto[402653184:536870911]	100	1			T1	1		T12	1		T24	1
auto[536870912:671088639]	106	1			T1	1		T11	1		T113	1
auto[671088640:805306367]	106	1			T23	1		T84	1		T204	1
auto[805306368:939524095]	115	1			T1	2		T3	1		T11	1
auto[939524096:1073741823]	110	1			T17	1		T87	1		T51	1
auto[1073741824:1207959551]	108	1			T3	1		T24	1		T37	1
auto[1207959552:1342177279]	98	1			T1	3		T11	1		T14	1
auto[1342177280:1476395007]	94	1			T2	1		T36	1		T47	1
auto[1476395008:1610612735]	106	1			T1	1		T38	1		T117	1
auto[1610612736:1744830463]	97	1			T1	1		T43	1		T203	1
auto[1744830464:1879048191]	105	1			T1	2		T17	1		T204	1
auto[1879048192:2013265919]	111	1			T84	1		T53	1		T54	1
auto[2013265920:2147483647]	103	1			T1	2		T2	1		T84	1
auto[2147483648:2281701375]	114	1			T1	1		T2	1		T113	1
auto[2281701376:2415919103]	113	1			T33	1		T46	1		T38	1
auto[2415919104:2550136831]	99	1			T1	1		T14	1		T15	1
auto[2550136832:2684354559]	93	1			T21	1		T44	1		T4	1
auto[2684354560:2818572287]	99	1			T1	3		T12	1		T14	1
auto[2818572288:2952790015]	125	1			T2	1		T43	1		T51	1
auto[2952790016:3087007743]	108	1			T1	1		T12	1		T36	1
auto[3087007744:3221225471]	116	1			T1	2		T47	1		T43	1
auto[3221225472:3355443199]	101	1			T15	1		T24	1		T53	2
auto[3355443200:3489660927]	113	1			T2	1		T3	1		T206	1
auto[3489660928:3623878655]	108	1			T11	2		T87	1		T26	1
auto[3623878656:3758096383]	114	1			T1	1		T33	1		T84	2
auto[3758096384:3892314111]	97	1			T2	1		T33	1		T46	1
auto[3892314112:4026531839]	93	1			T43	1		T50	2		T53	1
auto[4026531840:4160749567]	113	1			T12	1		T204	1		T43	2
auto[4160749568:4294967295]	101	1			T1	1		T11	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T37	1		T160	1		T377	1
auto[0:134217727]	auto[1]	51	1			T1	1		T113	1		T51	1
auto[134217728:268435455]	auto[0]	46	1			T47	1		T25	1		T43	1
auto[134217728:268435455]	auto[1]	49	1			T2	1		T24	1		T113	2
auto[268435456:402653183]	auto[0]	40	1			T2	1		T33	1		T43	1
auto[268435456:402653183]	auto[1]	52	1			T51	1		T79	1		T160	1
auto[402653184:536870911]	auto[0]	52	1			T1	1		T12	1		T203	1
auto[402653184:536870911]	auto[1]	48	1			T24	1		T58	1		T209	1
auto[536870912:671088639]	auto[0]	53	1			T1	1		T11	1		T113	1
auto[536870912:671088639]	auto[1]	53	1			T39	1		T43	1		T44	1
auto[671088640:805306367]	auto[0]	40	1			T23	1		T84	1		T27	1
auto[671088640:805306367]	auto[1]	66	1			T204	1		T209	1		T5	1
auto[805306368:939524095]	auto[0]	60	1			T1	2		T11	1		T43	1
auto[805306368:939524095]	auto[1]	55	1			T3	1		T117	2		T53	1
auto[939524096:1073741823]	auto[0]	56	1			T17	1		T87	1		T51	1
auto[939524096:1073741823]	auto[1]	54	1			T20	1		T53	2		T65	1
auto[1073741824:1207959551]	auto[0]	51	1			T37	1		T43	1		T203	1
auto[1073741824:1207959551]	auto[1]	57	1			T3	1		T24	1		T117	1
auto[1207959552:1342177279]	auto[0]	45	1			T1	1		T11	1		T14	1
auto[1207959552:1342177279]	auto[1]	53	1			T1	2		T15	1		T24	1
auto[1342177280:1476395007]	auto[0]	44	1			T2	1		T44	1		T211	1
auto[1342177280:1476395007]	auto[1]	50	1			T36	1		T47	1		T51	1
auto[1476395008:1610612735]	auto[0]	44	1			T1	1		T43	2		T203	1
auto[1476395008:1610612735]	auto[1]	62	1			T38	1		T117	1		T43	1
auto[1610612736:1744830463]	auto[0]	44	1			T58	1		T65	1		T90	1
auto[1610612736:1744830463]	auto[1]	53	1			T1	1		T43	1		T203	1
auto[1744830464:1879048191]	auto[0]	45	1			T1	1		T204	1		T53	1
auto[1744830464:1879048191]	auto[1]	60	1			T1	1		T17	1		T25	1
auto[1879048192:2013265919]	auto[0]	45	1			T395	1		T211	1		T63	2
auto[1879048192:2013265919]	auto[1]	66	1			T84	1		T53	1		T54	1
auto[2013265920:2147483647]	auto[0]	56	1			T1	1		T2	1		T84	1
auto[2013265920:2147483647]	auto[1]	47	1			T1	1		T36	1		T113	1
auto[2147483648:2281701375]	auto[0]	63	1			T1	1		T2	1		T37	1
auto[2147483648:2281701375]	auto[1]	51	1			T113	1		T43	1		T203	2
auto[2281701376:2415919103]	auto[0]	47	1			T33	1		T38	1		T44	1
auto[2281701376:2415919103]	auto[1]	66	1			T46	1		T43	1		T54	2
auto[2415919104:2550136831]	auto[0]	56	1			T1	1		T14	1		T15	1
auto[2415919104:2550136831]	auto[1]	43	1			T25	1		T53	1		T209	1
auto[2550136832:2684354559]	auto[0]	40	1			T21	1		T4	1		T58	1
auto[2550136832:2684354559]	auto[1]	53	1			T44	1		T356	1		T58	1
auto[2684354560:2818572287]	auto[0]	47	1			T1	2		T12	1		T14	1
auto[2684354560:2818572287]	auto[1]	52	1			T1	1		T17	1		T43	1
auto[2818572288:2952790015]	auto[0]	65	1			T51	1		T20	1		T27	1
auto[2818572288:2952790015]	auto[1]	60	1			T2	1		T43	1		T53	2
auto[2952790016:3087007743]	auto[0]	48	1			T1	1		T12	1		T36	1
auto[2952790016:3087007743]	auto[1]	60	1			T204	1		T43	2		T51	1
auto[3087007744:3221225471]	auto[0]	55	1			T1	1		T43	1		T51	1
auto[3087007744:3221225471]	auto[1]	61	1			T1	1		T47	1		T53	1
auto[3221225472:3355443199]	auto[0]	42	1			T15	1		T24	1		T53	1
auto[3221225472:3355443199]	auto[1]	59	1			T53	1		T44	1		T22	1
auto[3355443200:3489660927]	auto[0]	47	1			T2	1		T206	1		T43	1
auto[3355443200:3489660927]	auto[1]	66	1			T3	1		T26	1		T117	1
auto[3489660928:3623878655]	auto[0]	50	1			T11	1		T47	1		T21	1
auto[3489660928:3623878655]	auto[1]	58	1			T11	1		T87	1		T26	1
auto[3623878656:3758096383]	auto[0]	55	1			T1	1		T33	1		T84	1
auto[3623878656:3758096383]	auto[1]	59	1			T84	1		T204	1		T53	1
auto[3758096384:3892314111]	auto[0]	41	1			T2	1		T33	1		T46	1
auto[3758096384:3892314111]	auto[1]	56	1			T113	1		T117	1		T51	1
auto[3892314112:4026531839]	auto[0]	44	1			T50	1		T44	1		T395	1
auto[3892314112:4026531839]	auto[1]	49	1			T43	1		T50	1		T53	1
auto[4026531840:4160749567]	auto[0]	57	1			T12	1		T43	1		T21	1
auto[4026531840:4160749567]	auto[1]	56	1			T204	1		T43	1		T44	1
auto[4160749568:4294967295]	auto[0]	42	1			T1	1		T26	1		T79	1
auto[4160749568:4294967295]	auto[1]	59	1			T11	1		T39	1		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1562

1

T1

18

T2

5

T11

4

auto[1]

1790

1

T1

6

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T1	3		T3	1		T87	1
auto[134217728:268435455]	104	1			T43	1		T51	1		T4	1
auto[268435456:402653183]	101	1			T84	1		T36	1		T117	2
auto[402653184:536870911]	108	1			T1	2		T2	1		T15	1
auto[536870912:671088639]	104	1			T2	1		T11	1		T113	1
auto[671088640:805306367]	106	1			T1	1		T33	1		T36	1
auto[805306368:939524095]	105	1			T2	2		T11	1		T47	1
auto[939524096:1073741823]	99	1			T1	1		T84	1		T26	1
auto[1073741824:1207959551]	99	1			T1	1		T12	1		T33	1
auto[1207959552:1342177279]	85	1			T1	2		T113	1		T26	1
auto[1342177280:1476395007]	113	1			T1	1		T23	1		T36	1
auto[1476395008:1610612735]	113	1			T17	1		T23	1		T87	1
auto[1610612736:1744830463]	109	1			T1	1		T11	1		T84	1
auto[1744830464:1879048191]	110	1			T1	1		T11	1		T14	1
auto[1879048192:2013265919]	102	1			T1	3		T17	1		T24	1
auto[2013265920:2147483647]	96	1			T50	1		T80	1		T89	1
auto[2147483648:2281701375]	119	1			T1	1		T3	1		T43	1
auto[2281701376:2415919103]	94	1			T15	1		T113	1		T37	1
auto[2415919104:2550136831]	105	1			T1	1		T204	2		T43	2
auto[2550136832:2684354559]	113	1			T3	1		T24	1		T39	1
auto[2684354560:2818572287]	104	1			T1	2		T11	1		T46	1
auto[2818572288:2952790015]	105	1			T2	1		T43	2		T20	1
auto[2952790016:3087007743]	92	1			T1	2		T2	1		T43	1
auto[3087007744:3221225471]	105	1			T113	1		T21	2		T27	1
auto[3221225472:3355443199]	115	1			T14	2		T17	1		T37	1
auto[3355443200:3489660927]	116	1			T84	1		T87	1		T113	1
auto[3489660928:3623878655]	100	1			T33	2		T43	1		T51	1
auto[3623878656:3758096383]	101	1			T46	1		T38	1		T43	2
auto[3758096384:3892314111]	111	1			T1	1		T87	1		T47	1
auto[3892314112:4026531839]	97	1			T12	1		T37	1		T206	1
auto[4026531840:4160749567]	103	1			T2	1		T12	2		T15	1
auto[4160749568:4294967295]	103	1			T1	1		T2	1		T11	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T1	3		T47	1		T51	1
auto[0:134217727]	auto[1]	66	1			T3	1		T87	1		T203	1
auto[134217728:268435455]	auto[0]	46	1			T51	1		T4	1		T58	1
auto[134217728:268435455]	auto[1]	58	1			T43	1		T210	1		T134	1
auto[268435456:402653183]	auto[0]	32	1			T58	1		T212	1		T140	3
auto[268435456:402653183]	auto[1]	69	1			T84	1		T36	1		T117	2
auto[402653184:536870911]	auto[0]	53	1			T1	1		T2	1		T15	1
auto[402653184:536870911]	auto[1]	55	1			T1	1		T84	1		T113	1
auto[536870912:671088639]	auto[0]	53	1			T113	1		T43	1		T203	1
auto[536870912:671088639]	auto[1]	51	1			T2	1		T11	1		T204	1
auto[671088640:805306367]	auto[0]	53	1			T1	1		T33	1		T36	1
auto[671088640:805306367]	auto[1]	53	1			T43	1		T53	1		T89	1
auto[805306368:939524095]	auto[0]	52	1			T2	2		T11	1		T47	1
auto[805306368:939524095]	auto[1]	53	1			T43	1		T54	1		T256	1
auto[939524096:1073741823]	auto[0]	51	1			T1	1		T201	1		T62	1
auto[939524096:1073741823]	auto[1]	48	1			T84	1		T26	1		T51	1
auto[1073741824:1207959551]	auto[0]	54	1			T1	1		T12	1		T33	1
auto[1073741824:1207959551]	auto[1]	45	1			T211	1		T140	1		T269	1
auto[1207959552:1342177279]	auto[0]	43	1			T1	2		T25	1		T43	1
auto[1207959552:1342177279]	auto[1]	42	1			T113	1		T26	1		T117	1
auto[1342177280:1476395007]	auto[0]	48	1			T1	1		T23	1		T38	1
auto[1342177280:1476395007]	auto[1]	65	1			T36	1		T24	1		T47	1
auto[1476395008:1610612735]	auto[0]	50	1			T23	1		T203	1		T55	1
auto[1476395008:1610612735]	auto[1]	63	1			T17	1		T87	1		T24	2
auto[1610612736:1744830463]	auto[0]	60	1			T84	1		T53	1		T44	1
auto[1610612736:1744830463]	auto[1]	49	1			T1	1		T11	1		T113	1
auto[1744830464:1879048191]	auto[0]	54	1			T1	1		T11	1		T14	1
auto[1744830464:1879048191]	auto[1]	56	1			T204	1		T43	2		T51	1
auto[1879048192:2013265919]	auto[0]	37	1			T1	2		T37	1		T203	1
auto[1879048192:2013265919]	auto[1]	65	1			T1	1		T17	1		T24	1
auto[2013265920:2147483647]	auto[0]	42	1			T50	1		T58	1		T63	2
auto[2013265920:2147483647]	auto[1]	54	1			T80	1		T89	1		T216	1
auto[2147483648:2281701375]	auto[0]	59	1			T43	1		T20	2		T44	1
auto[2147483648:2281701375]	auto[1]	60	1			T1	1		T3	1		T20	1
auto[2281701376:2415919103]	auto[0]	40	1			T37	1		T27	1		T89	1
auto[2281701376:2415919103]	auto[1]	54	1			T15	1		T113	1		T51	2
auto[2415919104:2550136831]	auto[0]	40	1			T1	1		T204	1		T43	1
auto[2415919104:2550136831]	auto[1]	65	1			T204	1		T43	1		T44	2
auto[2550136832:2684354559]	auto[0]	57	1			T39	1		T203	1		T51	1
auto[2550136832:2684354559]	auto[1]	56	1			T3	1		T24	1		T50	1
auto[2684354560:2818572287]	auto[0]	53	1			T1	2		T11	1		T43	1
auto[2684354560:2818572287]	auto[1]	51	1			T46	1		T79	1		T58	1
auto[2818572288:2952790015]	auto[0]	50	1			T2	1		T43	1		T20	1
auto[2818572288:2952790015]	auto[1]	55	1			T43	1		T22	1		T58	1
auto[2952790016:3087007743]	auto[0]	52	1			T1	1		T43	1		T5	1
auto[2952790016:3087007743]	auto[1]	40	1			T1	1		T2	1		T253	1
auto[3087007744:3221225471]	auto[0]	51	1			T21	2		T27	1		T44	1
auto[3087007744:3221225471]	auto[1]	54	1			T113	1		T53	2		T44	1
auto[3221225472:3355443199]	auto[0]	44	1			T14	2		T17	1		T37	1
auto[3221225472:3355443199]	auto[1]	71	1			T44	2		T356	1		T251	2
auto[3355443200:3489660927]	auto[0]	60	1			T84	1		T37	1		T43	1
auto[3355443200:3489660927]	auto[1]	56	1			T87	1		T113	1		T25	1
auto[3489660928:3623878655]	auto[0]	48	1			T33	2		T51	1		T209	1
auto[3489660928:3623878655]	auto[1]	52	1			T43	1		T53	1		T65	1
auto[3623878656:3758096383]	auto[0]	47	1			T46	1		T43	1		T160	1
auto[3623878656:3758096383]	auto[1]	54	1			T38	1		T43	1		T160	1
auto[3758096384:3892314111]	auto[0]	42	1			T1	1		T87	1		T43	2
auto[3758096384:3892314111]	auto[1]	69	1			T47	1		T117	1		T39	1
auto[3892314112:4026531839]	auto[0]	44	1			T12	1		T43	1		T51	1
auto[3892314112:4026531839]	auto[1]	53	1			T37	1		T206	1		T51	2
auto[4026531840:4160749567]	auto[0]	47	1			T2	1		T12	2		T15	1
auto[4026531840:4160749567]	auto[1]	56	1			T43	1		T53	1		T80	2
auto[4160749568:4294967295]	auto[0]	51	1			T11	1		T51	1		T53	1
auto[4160749568:4294967295]	auto[1]	52	1			T1	1		T2	1		T117	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1544

1

T1

18

T2

6

T11

3

auto[1]

1807

1

T1

6

T2

2

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	1		T43	1		T203	1
auto[134217728:268435455]	118	1			T12	1		T36	1		T203	1
auto[268435456:402653183]	82	1			T3	1		T84	1		T43	1
auto[402653184:536870911]	95	1			T1	1		T11	1		T24	2
auto[536870912:671088639]	105	1			T1	3		T113	2		T204	3
auto[671088640:805306367]	108	1			T1	2		T15	1		T36	1
auto[805306368:939524095]	110	1			T46	1		T37	1		T117	1
auto[939524096:1073741823]	131	1			T47	1		T39	1		T43	3
auto[1073741824:1207959551]	92	1			T1	2		T12	1		T24	1
auto[1207959552:1342177279]	104	1			T12	1		T87	1		T43	1
auto[1342177280:1476395007]	95	1			T1	1		T2	1		T15	1
auto[1476395008:1610612735]	82	1			T11	1		T15	1		T33	1
auto[1610612736:1744830463]	116	1			T1	1		T43	2		T51	1
auto[1744830464:1879048191]	112	1			T1	1		T23	1		T47	1
auto[1879048192:2013265919]	97	1			T11	1		T14	1		T84	1
auto[2013265920:2147483647]	108	1			T2	1		T33	1		T84	1
auto[2147483648:2281701375]	123	1			T87	1		T113	1		T38	1
auto[2281701376:2415919103]	105	1			T2	1		T11	1		T38	1
auto[2415919104:2550136831]	107	1			T1	3		T2	1		T17	1
auto[2550136832:2684354559]	102	1			T1	1		T17	1		T84	1
auto[2684354560:2818572287]	108	1			T1	1		T117	1		T203	2
auto[2818572288:2952790015]	110	1			T2	1		T14	1		T17	1
auto[2952790016:3087007743]	114	1			T1	1		T46	1		T203	2
auto[3087007744:3221225471]	117	1			T1	1		T14	1		T87	1
auto[3221225472:3355443199]	95	1			T1	1		T84	1		T21	1
auto[3355443200:3489660927]	120	1			T33	1		T36	1		T24	1
auto[3489660928:3623878655]	101	1			T1	1		T11	1		T23	1
auto[3623878656:3758096383]	87	1			T1	2		T2	1		T11	1
auto[3758096384:3892314111]	89	1			T37	1		T117	1		T25	1
auto[3892314112:4026531839]	94	1			T1	2		T12	1		T37	1
auto[4026531840:4160749567]	107	1			T3	1		T206	1		T204	1
auto[4160749568:4294967295]	108	1			T2	1		T3	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T2	1		T43	1		T203	1
auto[0:134217727]	auto[1]	53	1			T80	1		T58	1		T213	1
auto[134217728:268435455]	auto[0]	55	1			T12	1		T36	1		T203	1
auto[134217728:268435455]	auto[1]	63	1			T209	1		T63	1		T140	2
auto[268435456:402653183]	auto[0]	41	1			T84	1		T44	1		T58	1
auto[268435456:402653183]	auto[1]	41	1			T3	1		T43	1		T51	1
auto[402653184:536870911]	auto[0]	39	1			T24	1		T37	1		T43	1
auto[402653184:536870911]	auto[1]	56	1			T1	1		T11	1		T24	1
auto[536870912:671088639]	auto[0]	51	1			T1	2		T204	1		T53	1
auto[536870912:671088639]	auto[1]	54	1			T1	1		T113	2		T204	2
auto[671088640:805306367]	auto[0]	44	1			T1	2		T395	1		T90	1
auto[671088640:805306367]	auto[1]	64	1			T15	1		T36	1		T51	3
auto[805306368:939524095]	auto[0]	53	1			T46	1		T43	1		T44	2
auto[805306368:939524095]	auto[1]	57	1			T37	1		T117	1		T25	1
auto[939524096:1073741823]	auto[0]	71	1			T47	1		T43	1		T203	1
auto[939524096:1073741823]	auto[1]	60	1			T39	1		T43	2		T51	1
auto[1073741824:1207959551]	auto[0]	39	1			T1	2		T12	1		T53	1
auto[1073741824:1207959551]	auto[1]	53	1			T24	1		T113	1		T43	1
auto[1207959552:1342177279]	auto[0]	57	1			T12	1		T87	1		T43	1
auto[1207959552:1342177279]	auto[1]	47	1			T209	1		T285	1		T101	1
auto[1342177280:1476395007]	auto[0]	51	1			T1	1		T2	1		T15	1
auto[1342177280:1476395007]	auto[1]	44	1			T58	1		T210	1		T67	1
auto[1476395008:1610612735]	auto[0]	43	1			T11	1		T15	1		T33	1
auto[1476395008:1610612735]	auto[1]	39	1			T53	1		T58	1		T123	1
auto[1610612736:1744830463]	auto[0]	50	1			T1	1		T43	1		T21	1
auto[1610612736:1744830463]	auto[1]	66	1			T43	1		T51	1		T53	2
auto[1744830464:1879048191]	auto[0]	61	1			T1	1		T23	1		T39	1
auto[1744830464:1879048191]	auto[1]	51	1			T47	1		T25	1		T53	1
auto[1879048192:2013265919]	auto[0]	49	1			T14	1		T84	1		T51	1
auto[1879048192:2013265919]	auto[1]	48	1			T11	1		T51	1		T58	1
auto[2013265920:2147483647]	auto[0]	47	1			T2	1		T33	1		T84	1
auto[2013265920:2147483647]	auto[1]	61	1			T24	1		T26	1		T117	1
auto[2147483648:2281701375]	auto[0]	53	1			T43	1		T395	1		T58	1
auto[2147483648:2281701375]	auto[1]	70	1			T87	1		T113	1		T38	1
auto[2281701376:2415919103]	auto[0]	42	1			T2	1		T38	1		T51	1
auto[2281701376:2415919103]	auto[1]	63	1			T11	1		T43	1		T44	1
auto[2415919104:2550136831]	auto[0]	46	1			T1	3		T2	1		T203	1
auto[2415919104:2550136831]	auto[1]	61	1			T17	1		T113	1		T53	1
auto[2550136832:2684354559]	auto[0]	48	1			T39	1		T27	1		T79	1
auto[2550136832:2684354559]	auto[1]	54	1			T1	1		T17	1		T84	1
auto[2684354560:2818572287]	auto[0]	49	1			T1	1		T53	1		T160	1
auto[2684354560:2818572287]	auto[1]	59	1			T117	1		T203	2		T89	1
auto[2818572288:2952790015]	auto[0]	53	1			T2	1		T14	1		T33	1
auto[2818572288:2952790015]	auto[1]	57	1			T17	1		T113	1		T90	1
auto[2952790016:3087007743]	auto[0]	47	1			T203	2		T53	1		T54	1
auto[2952790016:3087007743]	auto[1]	67	1			T1	1		T46	1		T356	1
auto[3087007744:3221225471]	auto[0]	46	1			T1	1		T14	1		T37	1
auto[3087007744:3221225471]	auto[1]	71	1			T87	1		T117	1		T356	1
auto[3221225472:3355443199]	auto[0]	43	1			T1	1		T21	1		T22	1
auto[3221225472:3355443199]	auto[1]	52	1			T84	1		T80	1		T160	1
auto[3355443200:3489660927]	auto[0]	50	1			T33	1		T36	1		T27	1
auto[3355443200:3489660927]	auto[1]	70	1			T24	1		T45	1		T67	1
auto[3489660928:3623878655]	auto[0]	41	1			T1	1		T11	1		T21	1
auto[3489660928:3623878655]	auto[1]	60	1			T23	1		T53	1		T80	1
auto[3623878656:3758096383]	auto[0]	44	1			T1	2		T11	1		T204	1
auto[3623878656:3758096383]	auto[1]	43	1			T2	1		T113	1		T160	1
auto[3758096384:3892314111]	auto[0]	40	1			T37	1		T117	1		T91	1
auto[3758096384:3892314111]	auto[1]	49	1			T25	1		T43	2		T201	1
auto[3892314112:4026531839]	auto[0]	42	1			T12	1		T37	1		T43	1
auto[3892314112:4026531839]	auto[1]	52	1			T1	2		T53	3		T216	1
auto[4026531840:4160749567]	auto[0]	50	1			T206	1		T204	1		T50	1
auto[4026531840:4160749567]	auto[1]	57	1			T3	1		T44	1		T80	1
auto[4160749568:4294967295]	auto[0]	43	1			T43	1		T203	1		T51	1
auto[4160749568:4294967295]	auto[1]	65	1			T2	1		T3	1		T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T1

16

T2

6

T11

3

auto[1]

1816

1

T1

8

T2

2

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T11	1		T46	2		T39	1
auto[134217728:268435455]	134	1			T1	2		T11	1		T14	1
auto[268435456:402653183]	109	1			T23	1		T37	1		T43	1
auto[402653184:536870911]	106	1			T14	1		T15	1		T43	1
auto[536870912:671088639]	107	1			T1	1		T3	1		T33	1
auto[671088640:805306367]	106	1			T33	1		T47	2		T43	1
auto[805306368:939524095]	127	1			T11	1		T14	1		T206	1
auto[939524096:1073741823]	106	1			T2	1		T87	1		T204	1
auto[1073741824:1207959551]	119	1			T2	1		T84	1		T43	1
auto[1207959552:1342177279]	93	1			T1	1		T25	1		T43	1
auto[1342177280:1476395007]	93	1			T15	1		T17	1		T26	1
auto[1476395008:1610612735]	108	1			T33	1		T39	1		T43	1
auto[1610612736:1744830463]	99	1			T1	1		T87	1		T113	1
auto[1744830464:1879048191]	109	1			T1	2		T3	1		T11	1
auto[1879048192:2013265919]	93	1			T33	1		T24	1		T26	1
auto[2013265920:2147483647]	89	1			T1	1		T117	1		T203	2
auto[2147483648:2281701375]	92	1			T1	1		T37	1		T47	1
auto[2281701376:2415919103]	116	1			T1	2		T113	1		T43	2
auto[2415919104:2550136831]	96	1			T2	1		T23	1		T87	1
auto[2550136832:2684354559]	103	1			T1	1		T11	1		T24	2
auto[2684354560:2818572287]	96	1			T1	2		T79	1		T80	2
auto[2818572288:2952790015]	106	1			T1	1		T11	1		T38	1
auto[2952790016:3087007743]	82	1			T1	1		T36	1		T113	1
auto[3087007744:3221225471]	117	1			T1	3		T12	1		T84	1
auto[3221225472:3355443199]	120	1			T1	4		T12	1		T20	1
auto[3355443200:3489660927]	115	1			T12	1		T17	1		T84	1
auto[3489660928:3623878655]	85	1			T204	1		T44	2		T89	1
auto[3623878656:3758096383]	99	1			T2	1		T113	1		T51	2
auto[3758096384:3892314111]	101	1			T1	1		T2	1		T12	1
auto[3892314112:4026531839]	106	1			T2	1		T117	2		T204	1
auto[4026531840:4160749567]	95	1			T2	1		T84	1		T87	1
auto[4160749568:4294967295]	112	1			T2	1		T3	1		T15	1