Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2966

1

T1

24

T2

4

T3

3

auto[1]

246

1

T11

5

T117

12

T79

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T11	2		T12	1		T84	1
auto[134217728:268435455]	100	1			T33	1		T113	1		T117	2
auto[268435456:402653183]	101	1			T2	1		T11	1		T17	1
auto[402653184:536870911]	105	1			T1	1		T11	1		T24	1
auto[536870912:671088639]	95	1			T1	1		T36	1		T25	1
auto[671088640:805306367]	89	1			T204	1		T43	1		T395	1
auto[805306368:939524095]	88	1			T1	1		T14	1		T117	1
auto[939524096:1073741823]	100	1			T1	1		T113	1		T117	1
auto[1073741824:1207959551]	116	1			T11	1		T36	1		T26	1
auto[1207959552:1342177279]	104	1			T1	1		T84	1		T113	1
auto[1342177280:1476395007]	102	1			T17	1		T113	1		T37	1
auto[1476395008:1610612735]	84	1			T1	2		T23	1		T24	1
auto[1610612736:1744830463]	104	1			T1	1		T17	1		T84	1
auto[1744830464:1879048191]	105	1			T1	1		T11	1		T46	1
auto[1879048192:2013265919]	108	1			T2	1		T33	1		T113	1
auto[2013265920:2147483647]	108	1			T1	1		T11	1		T87	1
auto[2147483648:2281701375]	112	1			T1	2		T11	1		T117	2
auto[2281701376:2415919103]	99	1			T1	2		T84	1		T24	1
auto[2415919104:2550136831]	87	1			T12	1		T47	1		T43	1
auto[2550136832:2684354559]	93	1			T1	1		T54	1		T58	2
auto[2684354560:2818572287]	97	1			T1	1		T2	1		T11	1
auto[2818572288:2952790015]	106	1			T11	1		T87	1		T24	1
auto[2952790016:3087007743]	86	1			T3	1		T15	1		T38	1
auto[3087007744:3221225471]	96	1			T1	1		T3	1		T117	1
auto[3221225472:3355443199]	109	1			T15	1		T26	1		T51	1
auto[3355443200:3489660927]	103	1			T1	1		T2	1		T15	1
auto[3489660928:3623878655]	102	1			T1	1		T206	1		T117	2
auto[3623878656:3758096383]	110	1			T1	2		T23	1		T36	1
auto[3758096384:3892314111]	96	1			T14	1		T87	1		T26	1
auto[3892314112:4026531839]	116	1			T1	2		T33	2		T24	1
auto[4026531840:4160749567]	103	1			T1	1		T11	1		T12	1
auto[4160749568:4294967295]	92	1			T3	1		T12	1		T46	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	86	1			T11	1		T12	1		T84	1
auto[0:134217727]	auto[1]	10	1			T11	1		T135	1		T145	2
auto[134217728:268435455]	auto[0]	88	1			T33	1		T113	1		T51	1
auto[134217728:268435455]	auto[1]	12	1			T117	2		T135	2		T146	1
auto[268435456:402653183]	auto[0]	94	1			T2	1		T17	1		T37	1
auto[268435456:402653183]	auto[1]	7	1			T11	1		T254	1		T417	1
auto[402653184:536870911]	auto[0]	98	1			T1	1		T11	1		T24	1
auto[402653184:536870911]	auto[1]	7	1			T135	2		T146	1		T151	1
auto[536870912:671088639]	auto[0]	91	1			T1	1		T36	1		T25	1
auto[536870912:671088639]	auto[1]	4	1			T253	1		T269	1		T283	1
auto[671088640:805306367]	auto[0]	85	1			T204	1		T43	1		T395	1
auto[671088640:805306367]	auto[1]	4	1			T390	1		T239	1		T418	1
auto[805306368:939524095]	auto[0]	82	1			T1	1		T14	1		T204	1
auto[805306368:939524095]	auto[1]	6	1			T117	1		T150	1		T151	1
auto[939524096:1073741823]	auto[0]	97	1			T1	1		T113	1		T117	1
auto[939524096:1073741823]	auto[1]	3	1			T240	1		T402	1		T419	1
auto[1073741824:1207959551]	auto[0]	105	1			T11	1		T36	1		T26	1
auto[1073741824:1207959551]	auto[1]	11	1			T117	1		T253	1		T135	1
auto[1207959552:1342177279]	auto[0]	93	1			T1	1		T84	1		T113	1
auto[1207959552:1342177279]	auto[1]	11	1			T79	1		T160	1		T145	2
auto[1342177280:1476395007]	auto[0]	95	1			T17	1		T113	1		T37	1
auto[1342177280:1476395007]	auto[1]	7	1			T296	1		T252	1		T283	1
auto[1476395008:1610612735]	auto[0]	77	1			T1	2		T23	1		T24	1
auto[1476395008:1610612735]	auto[1]	7	1			T147	1		T150	1		T402	1
auto[1610612736:1744830463]	auto[0]	93	1			T1	1		T17	1		T84	1
auto[1610612736:1744830463]	auto[1]	11	1			T160	1		T144	1		T296	1
auto[1744830464:1879048191]	auto[0]	99	1			T1	1		T46	1		T113	1
auto[1744830464:1879048191]	auto[1]	6	1			T11	1		T117	1		T79	1
auto[1879048192:2013265919]	auto[0]	103	1			T2	1		T33	1		T113	1
auto[1879048192:2013265919]	auto[1]	5	1			T269	1		T150	1		T283	1
auto[2013265920:2147483647]	auto[0]	98	1			T1	1		T87	1		T51	1
auto[2013265920:2147483647]	auto[1]	10	1			T11	1		T117	1		T296	1
auto[2147483648:2281701375]	auto[0]	100	1			T1	2		T39	1		T53	1
auto[2147483648:2281701375]	auto[1]	12	1			T11	1		T117	2		T135	1
auto[2281701376:2415919103]	auto[0]	95	1			T1	2		T84	1		T24	1
auto[2281701376:2415919103]	auto[1]	4	1			T144	1		T390	1		T391	1
auto[2415919104:2550136831]	auto[0]	80	1			T12	1		T47	1		T43	1
auto[2415919104:2550136831]	auto[1]	7	1			T135	1		T269	1		T296	1
auto[2550136832:2684354559]	auto[0]	79	1			T1	1		T54	1		T58	2
auto[2550136832:2684354559]	auto[1]	14	1			T145	1		T296	1		T146	1
auto[2684354560:2818572287]	auto[0]	91	1			T1	1		T2	1		T11	1
auto[2684354560:2818572287]	auto[1]	6	1			T242	1		T390	2		T415	1
auto[2818572288:2952790015]	auto[0]	100	1			T11	1		T87	1		T24	1
auto[2818572288:2952790015]	auto[1]	6	1			T145	2		T307	1		T240	1
auto[2952790016:3087007743]	auto[0]	78	1			T3	1		T15	1		T38	1
auto[2952790016:3087007743]	auto[1]	8	1			T117	1		T242	1		T296	1
auto[3087007744:3221225471]	auto[0]	94	1			T1	1		T3	1		T117	1
auto[3087007744:3221225471]	auto[1]	2	1			T404	1		T412	1		-	-
auto[3221225472:3355443199]	auto[0]	99	1			T15	1		T26	1		T51	1
auto[3221225472:3355443199]	auto[1]	10	1			T253	1		T146	3		T147	2
auto[3355443200:3489660927]	auto[0]	94	1			T1	1		T2	1		T15	1
auto[3355443200:3489660927]	auto[1]	9	1			T144	1		T296	2		T150	1
auto[3489660928:3623878655]	auto[0]	96	1			T1	1		T206	1		T25	1
auto[3489660928:3623878655]	auto[1]	6	1			T117	2		T252	1		T390	1
auto[3623878656:3758096383]	auto[0]	99	1			T1	2		T23	1		T36	1
auto[3623878656:3758096383]	auto[1]	11	1			T253	1		T145	1		T296	1
auto[3758096384:3892314111]	auto[0]	89	1			T14	1		T87	1		T26	1
auto[3758096384:3892314111]	auto[1]	7	1			T117	1		T135	1		T147	1
auto[3892314112:4026531839]	auto[0]	107	1			T1	2		T33	2		T24	1
auto[3892314112:4026531839]	auto[1]	9	1			T296	2		T390	1		T283	1
auto[4026531840:4160749567]	auto[0]	97	1			T1	1		T11	1		T12	1
auto[4026531840:4160749567]	auto[1]	6	1			T323	1		T407	1		T406	1
auto[4160749568:4294967295]	auto[0]	84	1			T3	1		T12	1		T46	1
auto[4160749568:4294967295]	auto[1]	8	1			T144	1		T296	1		T150	2