Unified Coverage Report :: Group Instance : sealing_sw_binding_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1566

1

T1

19

T2

7

T11

3

auto[1]

1784

1

T1

5

T2

1

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T1	1		T2	1		T11	1
auto[134217728:268435455]	102	1			T1	1		T11	1		T117	1
auto[268435456:402653183]	96	1			T1	1		T11	1		T12	1
auto[402653184:536870911]	123	1			T1	3		T12	1		T15	1
auto[536870912:671088639]	95	1			T1	2		T33	1		T26	1
auto[671088640:805306367]	101	1			T24	1		T206	1		T117	1
auto[805306368:939524095]	92	1			T1	1		T11	1		T17	2
auto[939524096:1073741823]	107	1			T1	1		T113	1		T204	1
auto[1073741824:1207959551]	103	1			T1	1		T2	1		T3	1
auto[1207959552:1342177279]	109	1			T1	1		T11	1		T43	2
auto[1342177280:1476395007]	99	1			T113	1		T26	1		T53	1
auto[1476395008:1610612735]	107	1			T1	1		T2	1		T113	1
auto[1610612736:1744830463]	115	1			T23	1		T47	1		T117	1
auto[1744830464:1879048191]	102	1			T3	1		T33	1		T203	1
auto[1879048192:2013265919]	115	1			T2	1		T37	1		T26	1
auto[2013265920:2147483647]	89	1			T12	1		T14	1		T87	1
auto[2147483648:2281701375]	105	1			T84	1		T24	1		T39	1
auto[2281701376:2415919103]	112	1			T24	2		T43	1		T20	1
auto[2415919104:2550136831]	116	1			T1	1		T2	2		T113	1
auto[2550136832:2684354559]	121	1			T3	1		T113	1		T38	1
auto[2684354560:2818572287]	86	1			T1	1		T117	1		T43	1
auto[2818572288:2952790015]	94	1			T1	2		T2	1		T84	1
auto[2952790016:3087007743]	111	1			T1	1		T2	1		T36	1
auto[3087007744:3221225471]	97	1			T1	1		T37	1		T43	1
auto[3221225472:3355443199]	92	1			T37	1		T53	1		T54	1
auto[3355443200:3489660927]	99	1			T1	1		T14	1		T36	1
auto[3489660928:3623878655]	110	1			T1	1		T15	1		T17	1
auto[3623878656:3758096383]	108	1			T1	1		T15	1		T25	1
auto[3758096384:3892314111]	89	1			T1	1		T23	1		T47	1
auto[3892314112:4026531839]	116	1			T1	1		T11	1		T12	1
auto[4026531840:4160749567]	116	1			T43	1		T51	2		T50	1
auto[4160749568:4294967295]	103	1			T14	1		T84	1		T87	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T1	1		T11	1		T33	2
auto[0:134217727]	auto[1]	65	1			T2	1		T51	1		T50	1
auto[134217728:268435455]	auto[0]	50	1			T1	1		T43	1		T53	1
auto[134217728:268435455]	auto[1]	52	1			T11	1		T117	1		T43	2
auto[268435456:402653183]	auto[0]	44	1			T1	1		T12	1		T46	1
auto[268435456:402653183]	auto[1]	52	1			T11	1		T87	2		T43	1
auto[402653184:536870911]	auto[0]	58	1			T1	2		T12	1		T15	1
auto[402653184:536870911]	auto[1]	65	1			T1	1		T84	1		T43	1
auto[536870912:671088639]	auto[0]	42	1			T1	2		T33	1		T43	1
auto[536870912:671088639]	auto[1]	53	1			T26	1		T89	1		T58	1
auto[671088640:805306367]	auto[0]	54	1			T206	1		T44	2		T4	1
auto[671088640:805306367]	auto[1]	47	1			T24	1		T117	1		T58	1
auto[805306368:939524095]	auto[0]	53	1			T1	1		T11	1		T17	1
auto[805306368:939524095]	auto[1]	39	1			T17	1		T53	1		T40	1
auto[939524096:1073741823]	auto[0]	55	1			T1	1		T43	3		T203	1
auto[939524096:1073741823]	auto[1]	52	1			T113	1		T204	1		T58	3
auto[1073741824:1207959551]	auto[0]	44	1			T2	1		T37	1		T204	1
auto[1073741824:1207959551]	auto[1]	59	1			T1	1		T3	1		T356	1
auto[1207959552:1342177279]	auto[0]	57	1			T1	1		T11	1		T53	2
auto[1207959552:1342177279]	auto[1]	52	1			T43	2		T356	1		T210	1
auto[1342177280:1476395007]	auto[0]	45	1			T44	1		T65	1		T18	1
auto[1342177280:1476395007]	auto[1]	54	1			T113	1		T26	1		T53	1
auto[1476395008:1610612735]	auto[0]	45	1			T2	1		T44	1		T54	1
auto[1476395008:1610612735]	auto[1]	62	1			T1	1		T113	1		T43	1
auto[1610612736:1744830463]	auto[0]	50	1			T23	1		T47	1		T203	1
auto[1610612736:1744830463]	auto[1]	65	1			T117	1		T51	1		T53	1
auto[1744830464:1879048191]	auto[0]	50	1			T33	1		T203	1		T53	1
auto[1744830464:1879048191]	auto[1]	52	1			T3	1		T58	1		T209	1
auto[1879048192:2013265919]	auto[0]	70	1			T2	1		T37	1		T26	1
auto[1879048192:2013265919]	auto[1]	45	1			T44	1		T89	1		T55	1
auto[2013265920:2147483647]	auto[0]	42	1			T87	1		T53	1		T44	2
auto[2013265920:2147483647]	auto[1]	47	1			T12	1		T14	1		T46	1
auto[2147483648:2281701375]	auto[0]	53	1			T84	1		T39	1		T53	1
auto[2147483648:2281701375]	auto[1]	52	1			T24	1		T51	2		T4	1
auto[2281701376:2415919103]	auto[0]	58	1			T24	1		T21	2		T27	1
auto[2281701376:2415919103]	auto[1]	54	1			T24	1		T43	1		T20	1
auto[2415919104:2550136831]	auto[0]	51	1			T1	1		T2	2		T43	1
auto[2415919104:2550136831]	auto[1]	65	1			T113	1		T204	1		T25	1
auto[2550136832:2684354559]	auto[0]	54	1			T113	1		T38	1		T43	1
auto[2550136832:2684354559]	auto[1]	67	1			T3	1		T51	1		T80	1
auto[2684354560:2818572287]	auto[0]	34	1			T117	1		T21	1		T63	1
auto[2684354560:2818572287]	auto[1]	52	1			T1	1		T43	1		T65	1
auto[2818572288:2952790015]	auto[0]	44	1			T1	2		T2	1		T84	1
auto[2818572288:2952790015]	auto[1]	50	1			T43	1		T44	1		T80	1
auto[2952790016:3087007743]	auto[0]	52	1			T1	1		T2	1		T37	1
auto[2952790016:3087007743]	auto[1]	59	1			T36	1		T43	1		T53	1
auto[3087007744:3221225471]	auto[0]	32	1			T37	1		T90	1		T6	1
auto[3087007744:3221225471]	auto[1]	65	1			T1	1		T43	1		T51	1
auto[3221225472:3355443199]	auto[0]	39	1			T37	1		T54	1		T45	1
auto[3221225472:3355443199]	auto[1]	53	1			T53	1		T216	1		T6	1
auto[3355443200:3489660927]	auto[0]	39	1			T1	1		T14	1		T53	1
auto[3355443200:3489660927]	auto[1]	60	1			T36	1		T24	1		T113	1
auto[3489660928:3623878655]	auto[0]	47	1			T1	1		T15	1		T47	1
auto[3489660928:3623878655]	auto[1]	63	1			T17	1		T38	1		T53	1
auto[3623878656:3758096383]	auto[0]	45	1			T1	1		T25	1		T21	1
auto[3623878656:3758096383]	auto[1]	63	1			T15	1		T203	1		T51	1
auto[3758096384:3892314111]	auto[0]	47	1			T1	1		T23	1		T51	1
auto[3758096384:3892314111]	auto[1]	42	1			T47	1		T53	1		T65	1
auto[3892314112:4026531839]	auto[0]	51	1			T1	1		T12	1		T36	1
auto[3892314112:4026531839]	auto[1]	65	1			T11	1		T113	1		T43	1
auto[4026531840:4160749567]	auto[0]	62	1			T43	1		T50	1		T55	1
auto[4026531840:4160749567]	auto[1]	54	1			T51	2		T44	1		T54	1
auto[4160749568:4294967295]	auto[0]	44	1			T14	1		T51	1		T44	1
auto[4160749568:4294967295]	auto[1]	59	1			T84	1		T87	1		T47	1