Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4642

1

T1

32

T2

16

T3

2

auto[1]

2058

1

T1

16

T3

4

T12

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	188	1			T1	2		T204	2		T43	2
auto[134217728:268435455]	202	1			T2	2		T33	2		T117	4
auto[268435456:402653183]	220	1			T1	2		T3	2		T84	2
auto[402653184:536870911]	206	1			T1	2		T11	2		T15	2
auto[536870912:671088639]	246	1			T2	2		T11	4		T15	2
auto[671088640:805306367]	236	1			T1	4		T37	2		T51	2
auto[805306368:939524095]	208	1			T14	2		T43	2		T51	4
auto[939524096:1073741823]	212	1			T1	2		T24	2		T113	2
auto[1073741824:1207959551]	202	1			T1	2		T14	2		T17	2
auto[1207959552:1342177279]	246	1			T1	4		T3	2		T113	2
auto[1342177280:1476395007]	226	1			T2	2		T17	2		T24	2
auto[1476395008:1610612735]	216	1			T1	4		T3	2		T33	2
auto[1610612736:1744830463]	180	1			T2	2		T25	2		T43	2
auto[1744830464:1879048191]	164	1			T50	2		T20	2		T53	4
auto[1879048192:2013265919]	190	1			T2	4		T25	2		T44	2
auto[2013265920:2147483647]	210	1			T1	2		T33	2		T87	2
auto[2147483648:2281701375]	160	1			T2	2		T12	2		T87	2
auto[2281701376:2415919103]	210	1			T36	2		T47	2		T204	2
auto[2415919104:2550136831]	216	1			T1	2		T84	4		T87	2
auto[2550136832:2684354559]	196	1			T11	2		T14	2		T23	2
auto[2684354560:2818572287]	200	1			T117	2		T43	2		T51	2
auto[2818572288:2952790015]	224	1			T1	4		T113	2		T37	2
auto[2952790016:3087007743]	214	1			T84	2		T53	6		T44	2
auto[3087007744:3221225471]	176	1			T1	2		T33	2		T36	2
auto[3221225472:3355443199]	212	1			T1	2		T113	2		T37	2
auto[3355443200:3489660927]	198	1			T1	2		T12	4		T17	2
auto[3489660928:3623878655]	246	1			T1	4		T2	2		T87	2
auto[3623878656:3758096383]	222	1			T1	2		T12	2		T23	2
auto[3758096384:3892314111]	244	1			T36	2		T113	2		T26	2
auto[3892314112:4026531839]	188	1			T1	2		T26	2		T43	2
auto[4026531840:4160749567]	234	1			T15	2		T26	2		T203	2
auto[4160749568:4294967295]	208	1			T1	4		T11	4		T37	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	124	1			T51	2		T53	2		T209	2
auto[0:134217727]	auto[1]	64	1			T1	2		T204	2		T43	2
auto[134217728:268435455]	auto[0]	128	1			T2	2		T117	4		T43	2
auto[134217728:268435455]	auto[1]	74	1			T33	2		T45	2		T91	2
auto[268435456:402653183]	auto[0]	164	1			T1	2		T84	2		T39	2
auto[268435456:402653183]	auto[1]	56	1			T3	2		T43	2		T20	2
auto[402653184:536870911]	auto[0]	140	1			T11	2		T15	2		T51	2
auto[402653184:536870911]	auto[1]	66	1			T1	2		T51	2		T58	2
auto[536870912:671088639]	auto[0]	194	1			T2	2		T11	4		T15	2
auto[536870912:671088639]	auto[1]	52	1			T91	2		T209	2		T247	2
auto[671088640:805306367]	auto[0]	162	1			T1	2		T44	4		T4	2
auto[671088640:805306367]	auto[1]	74	1			T1	2		T37	2		T51	2
auto[805306368:939524095]	auto[0]	134	1			T14	2		T51	4		T21	2
auto[805306368:939524095]	auto[1]	74	1			T43	2		T22	2		T216	2
auto[939524096:1073741823]	auto[0]	138	1			T1	2		T24	2		T113	2
auto[939524096:1073741823]	auto[1]	74	1			T296	2		T294	2		T377	2
auto[1073741824:1207959551]	auto[0]	148	1			T1	2		T17	2		T47	2
auto[1073741824:1207959551]	auto[1]	54	1			T14	2		T25	2		T43	2
auto[1207959552:1342177279]	auto[0]	178	1			T1	2		T3	2		T117	2
auto[1207959552:1342177279]	auto[1]	68	1			T1	2		T113	2		T39	2
auto[1342177280:1476395007]	auto[0]	154	1			T2	2		T24	2		T46	2
auto[1342177280:1476395007]	auto[1]	72	1			T17	2		T43	2		T58	2
auto[1476395008:1610612735]	auto[0]	132	1			T1	4		T113	2		T117	2
auto[1476395008:1610612735]	auto[1]	84	1			T3	2		T33	2		T43	2
auto[1610612736:1744830463]	auto[0]	114	1			T2	2		T43	2		T203	2
auto[1610612736:1744830463]	auto[1]	66	1			T25	2		T44	2		T356	2
auto[1744830464:1879048191]	auto[0]	112	1			T50	2		T20	2		T216	2
auto[1744830464:1879048191]	auto[1]	52	1			T53	4		T58	2		T253	2
auto[1879048192:2013265919]	auto[0]	142	1			T2	4		T44	2		T80	2
auto[1879048192:2013265919]	auto[1]	48	1			T25	2		T209	2		T134	2
auto[2013265920:2147483647]	auto[0]	142	1			T87	2		T113	2		T117	2
auto[2013265920:2147483647]	auto[1]	68	1			T1	2		T33	2		T356	2
auto[2147483648:2281701375]	auto[0]	88	1			T2	2		T12	2		T87	2
auto[2147483648:2281701375]	auto[1]	72	1			T37	2		T51	2		T209	2
auto[2281701376:2415919103]	auto[0]	154	1			T36	2		T44	8		T160	2
auto[2281701376:2415919103]	auto[1]	56	1			T47	2		T204	2		T43	2
auto[2415919104:2550136831]	auto[0]	136	1			T84	4		T53	2		T44	2
auto[2415919104:2550136831]	auto[1]	80	1			T1	2		T87	2		T43	2
auto[2550136832:2684354559]	auto[0]	140	1			T11	2		T14	2		T43	2
auto[2550136832:2684354559]	auto[1]	56	1			T23	2		T24	2		T4	2
auto[2684354560:2818572287]	auto[0]	148	1			T117	2		T43	2		T51	2
auto[2684354560:2818572287]	auto[1]	52	1			T5	2		T135	2		T306	2
auto[2818572288:2952790015]	auto[0]	146	1			T1	4		T37	2		T47	2
auto[2818572288:2952790015]	auto[1]	78	1			T113	2		T38	2		T203	2
auto[2952790016:3087007743]	auto[0]	158	1			T53	4		T44	2		T89	2
auto[2952790016:3087007743]	auto[1]	56	1			T84	2		T53	2		T256	2
auto[3087007744:3221225471]	auto[0]	120	1			T36	2		T204	2		T53	2
auto[3087007744:3221225471]	auto[1]	56	1			T1	2		T33	2		T196	2
auto[3221225472:3355443199]	auto[0]	136	1			T1	2		T113	2		T47	2
auto[3221225472:3355443199]	auto[1]	76	1			T37	2		T206	2		T51	2
auto[3355443200:3489660927]	auto[0]	130	1			T1	2		T17	2		T38	2
auto[3355443200:3489660927]	auto[1]	68	1			T12	4		T43	2		T45	2
auto[3489660928:3623878655]	auto[0]	186	1			T1	2		T2	2		T43	2
auto[3489660928:3623878655]	auto[1]	60	1			T1	2		T87	2		T51	2
auto[3623878656:3758096383]	auto[0]	156	1			T1	2		T84	2		T46	2
auto[3623878656:3758096383]	auto[1]	66	1			T12	2		T23	2		T6	2
auto[3758096384:3892314111]	auto[0]	182	1			T36	2		T113	2		T26	2
auto[3758096384:3892314111]	auto[1]	62	1			T54	2		T45	2		T58	2
auto[3892314112:4026531839]	auto[0]	140	1			T1	2		T26	2		T43	2
auto[3892314112:4026531839]	auto[1]	48	1			T305	2		T210	2		T140	2
auto[4026531840:4160749567]	auto[0]	156	1			T203	2		T53	2		T54	2
auto[4026531840:4160749567]	auto[1]	78	1			T15	2		T26	2		T53	2
auto[4160749568:4294967295]	auto[0]	160	1			T1	4		T11	4		T43	4
auto[4160749568:4294967295]	auto[1]	48	1			T37	2		T53	2		T58	2