Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.07 98.52 100.00 99.02 98.41 91.09


Total test records in report: 1081
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T1008 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1585034594 Jul 26 07:09:05 PM PDT 24 Jul 26 07:09:07 PM PDT 24 67427221 ps
T1009 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2414898235 Jul 26 07:09:45 PM PDT 24 Jul 26 07:09:46 PM PDT 24 44127576 ps
T1010 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2889284495 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:17 PM PDT 24 20154764 ps
T1011 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1152689430 Jul 26 07:09:28 PM PDT 24 Jul 26 07:09:30 PM PDT 24 52432178 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1194305493 Jul 26 07:08:19 PM PDT 24 Jul 26 07:08:22 PM PDT 24 101366698 ps
T1013 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.840219945 Jul 26 07:08:53 PM PDT 24 Jul 26 07:08:54 PM PDT 24 30471536 ps
T1014 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3737312228 Jul 26 07:09:28 PM PDT 24 Jul 26 07:09:33 PM PDT 24 313541783 ps
T181 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3381600844 Jul 26 07:09:14 PM PDT 24 Jul 26 07:09:18 PM PDT 24 147981111 ps
T1015 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2620303961 Jul 26 07:09:14 PM PDT 24 Jul 26 07:09:16 PM PDT 24 31525241 ps
T1016 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.93292503 Jul 26 07:09:47 PM PDT 24 Jul 26 07:09:48 PM PDT 24 95347517 ps
T179 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3841698886 Jul 26 07:08:21 PM PDT 24 Jul 26 07:08:26 PM PDT 24 374725933 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3840948678 Jul 26 07:09:07 PM PDT 24 Jul 26 07:09:08 PM PDT 24 64917756 ps
T1018 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1233517250 Jul 26 07:09:38 PM PDT 24 Jul 26 07:09:42 PM PDT 24 3045513037 ps
T1019 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2147455753 Jul 26 07:09:28 PM PDT 24 Jul 26 07:09:30 PM PDT 24 35039045 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1807680463 Jul 26 07:09:03 PM PDT 24 Jul 26 07:09:04 PM PDT 24 62645492 ps
T188 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1855637142 Jul 26 07:08:55 PM PDT 24 Jul 26 07:09:00 PM PDT 24 95853181 ps
T185 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.583942451 Jul 26 07:09:28 PM PDT 24 Jul 26 07:09:34 PM PDT 24 358138390 ps
T1021 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1345128048 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:18 PM PDT 24 375401140 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.49002817 Jul 26 07:08:25 PM PDT 24 Jul 26 07:08:26 PM PDT 24 14863760 ps
T1023 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.48773869 Jul 26 07:08:53 PM PDT 24 Jul 26 07:08:55 PM PDT 24 406343184 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1739593822 Jul 26 07:09:28 PM PDT 24 Jul 26 07:09:29 PM PDT 24 33733596 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1294097387 Jul 26 07:09:17 PM PDT 24 Jul 26 07:09:21 PM PDT 24 56558041 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.254026332 Jul 26 07:09:38 PM PDT 24 Jul 26 07:09:46 PM PDT 24 386369042 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2139255334 Jul 26 07:08:18 PM PDT 24 Jul 26 07:08:27 PM PDT 24 510879758 ps
T1028 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1078376218 Jul 26 07:09:42 PM PDT 24 Jul 26 07:09:48 PM PDT 24 206781256 ps
T1029 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2232350010 Jul 26 07:09:13 PM PDT 24 Jul 26 07:09:17 PM PDT 24 319817147 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.64314279 Jul 26 07:09:37 PM PDT 24 Jul 26 07:09:40 PM PDT 24 242080507 ps
T1031 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1136776268 Jul 26 07:09:05 PM PDT 24 Jul 26 07:09:06 PM PDT 24 91669732 ps
T1032 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2441380113 Jul 26 07:08:52 PM PDT 24 Jul 26 07:08:54 PM PDT 24 101235043 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1029105781 Jul 26 07:09:17 PM PDT 24 Jul 26 07:09:19 PM PDT 24 37666211 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1277269748 Jul 26 07:08:39 PM PDT 24 Jul 26 07:08:40 PM PDT 24 40684468 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1347688666 Jul 26 07:08:21 PM PDT 24 Jul 26 07:08:25 PM PDT 24 77735234 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2840016095 Jul 26 07:08:28 PM PDT 24 Jul 26 07:08:29 PM PDT 24 145203423 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.463500559 Jul 26 07:08:22 PM PDT 24 Jul 26 07:08:36 PM PDT 24 1089258879 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4047145731 Jul 26 07:09:20 PM PDT 24 Jul 26 07:09:21 PM PDT 24 140339799 ps
T1039 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3141346464 Jul 26 07:08:40 PM PDT 24 Jul 26 07:08:42 PM PDT 24 43165455 ps
T182 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2669975701 Jul 26 07:09:15 PM PDT 24 Jul 26 07:09:19 PM PDT 24 568735308 ps
T1040 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2373048887 Jul 26 07:09:47 PM PDT 24 Jul 26 07:09:48 PM PDT 24 6747268 ps
T1041 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2729500780 Jul 26 07:08:53 PM PDT 24 Jul 26 07:08:55 PM PDT 24 52692716 ps
T1042 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3485187164 Jul 26 07:09:40 PM PDT 24 Jul 26 07:09:40 PM PDT 24 35737773 ps
T384 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4202234904 Jul 26 07:09:03 PM PDT 24 Jul 26 07:09:07 PM PDT 24 438910152 ps
T1043 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3647922528 Jul 26 07:09:07 PM PDT 24 Jul 26 07:09:09 PM PDT 24 213526203 ps
T1044 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4158527325 Jul 26 07:09:46 PM PDT 24 Jul 26 07:09:46 PM PDT 24 63559026 ps
T1045 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1208252967 Jul 26 07:09:39 PM PDT 24 Jul 26 07:09:41 PM PDT 24 184884774 ps
T1046 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2984542293 Jul 26 07:09:47 PM PDT 24 Jul 26 07:09:48 PM PDT 24 11485333 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3360048785 Jul 26 07:08:40 PM PDT 24 Jul 26 07:08:45 PM PDT 24 293192367 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1667258927 Jul 26 07:08:39 PM PDT 24 Jul 26 07:08:42 PM PDT 24 140612487 ps
T1049 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.670779663 Jul 26 07:09:39 PM PDT 24 Jul 26 07:09:40 PM PDT 24 13070924 ps
T1050 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2867895487 Jul 26 07:09:47 PM PDT 24 Jul 26 07:09:48 PM PDT 24 14154193 ps
T1051 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3244662868 Jul 26 07:09:38 PM PDT 24 Jul 26 07:09:39 PM PDT 24 35334024 ps
T186 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3594373057 Jul 26 07:08:53 PM PDT 24 Jul 26 07:08:56 PM PDT 24 51603703 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2117194825 Jul 26 07:09:27 PM PDT 24 Jul 26 07:09:30 PM PDT 24 567511168 ps
T1053 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2026792067 Jul 26 07:08:50 PM PDT 24 Jul 26 07:08:52 PM PDT 24 47045931 ps
T1054 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2979226740 Jul 26 07:09:50 PM PDT 24 Jul 26 07:09:51 PM PDT 24 9501537 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4076289309 Jul 26 07:09:05 PM PDT 24 Jul 26 07:09:12 PM PDT 24 279170064 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1878476210 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:18 PM PDT 24 97091529 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1494562645 Jul 26 07:09:17 PM PDT 24 Jul 26 07:09:20 PM PDT 24 36456743 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1944871806 Jul 26 07:08:39 PM PDT 24 Jul 26 07:08:41 PM PDT 24 94783927 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2219363491 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:17 PM PDT 24 17048544 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3779435362 Jul 26 07:08:19 PM PDT 24 Jul 26 07:08:21 PM PDT 24 59788329 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2833872683 Jul 26 07:08:26 PM PDT 24 Jul 26 07:08:27 PM PDT 24 15780942 ps
T1062 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.903834914 Jul 26 07:09:03 PM PDT 24 Jul 26 07:09:04 PM PDT 24 86401057 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.145299296 Jul 26 07:09:13 PM PDT 24 Jul 26 07:09:20 PM PDT 24 279987486 ps
T1064 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1942139431 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:19 PM PDT 24 94897479 ps
T1065 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1790748958 Jul 26 07:09:20 PM PDT 24 Jul 26 07:09:26 PM PDT 24 317068889 ps
T1066 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1329695609 Jul 26 07:09:03 PM PDT 24 Jul 26 07:09:04 PM PDT 24 28841838 ps
T1067 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.646921707 Jul 26 07:09:02 PM PDT 24 Jul 26 07:09:13 PM PDT 24 2393490071 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2260257107 Jul 26 07:08:19 PM PDT 24 Jul 26 07:08:22 PM PDT 24 68997421 ps
T1069 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1488817041 Jul 26 07:08:30 PM PDT 24 Jul 26 07:08:37 PM PDT 24 252628057 ps
T1070 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.774525755 Jul 26 07:09:38 PM PDT 24 Jul 26 07:09:39 PM PDT 24 191728638 ps
T1071 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3119708288 Jul 26 07:09:42 PM PDT 24 Jul 26 07:09:43 PM PDT 24 31252813 ps
T1072 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3791062114 Jul 26 07:08:55 PM PDT 24 Jul 26 07:08:56 PM PDT 24 85226655 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1203409284 Jul 26 07:09:04 PM PDT 24 Jul 26 07:09:06 PM PDT 24 147337961 ps
T1074 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2657560545 Jul 26 07:08:06 PM PDT 24 Jul 26 07:08:08 PM PDT 24 152010616 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.842591388 Jul 26 07:08:22 PM PDT 24 Jul 26 07:08:39 PM PDT 24 2901917506 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1278048642 Jul 26 07:08:27 PM PDT 24 Jul 26 07:08:28 PM PDT 24 31383673 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3749142098 Jul 26 07:08:28 PM PDT 24 Jul 26 07:08:33 PM PDT 24 69480192 ps
T1078 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.504836276 Jul 26 07:08:18 PM PDT 24 Jul 26 07:08:19 PM PDT 24 21263520 ps
T1079 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3198197711 Jul 26 07:09:16 PM PDT 24 Jul 26 07:09:19 PM PDT 24 495046723 ps
T1080 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3602105200 Jul 26 07:08:52 PM PDT 24 Jul 26 07:08:53 PM PDT 24 26308697 ps
T1081 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2715217564 Jul 26 07:08:52 PM PDT 24 Jul 26 07:08:53 PM PDT 24 45756501 ps

Test location /workspace/coverage/default/16.keymgr_stress_all.635905301
Short name T1
Test name
Test status
Simulation time 527229313 ps
CPU time 19.95 seconds
Started Jul 26 07:22:41 PM PDT 24
Finished Jul 26 07:23:01 PM PDT 24
Peak memory 222308 kb
Host smart-935fcc5a-0a28-441f-9b01-09374144f870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635905301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.635905301
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1416877477
Short name T51
Test name
Test status
Simulation time 1089775680 ps
CPU time 17.76 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 220988 kb
Host smart-030f9461-9949-4087-8118-45aac92c062a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416877477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1416877477
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4259580171
Short name T43
Test name
Test status
Simulation time 4491411567 ps
CPU time 57.16 seconds
Started Jul 26 07:21:23 PM PDT 24
Finished Jul 26 07:22:20 PM PDT 24
Peak memory 216376 kb
Host smart-01a910ec-9441-49c4-bc6e-ad4fbd6ee888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259580171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4259580171
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1806133927
Short name T8
Test name
Test status
Simulation time 815856254 ps
CPU time 10.59 seconds
Started Jul 26 07:21:28 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 230788 kb
Host smart-627febac-cbf1-4bd6-8a6b-b9a260ccc882
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806133927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1806133927
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.405462095
Short name T58
Test name
Test status
Simulation time 4410770360 ps
CPU time 47.39 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 222324 kb
Host smart-7c8851ed-69cf-4017-9e14-f3f6f32acbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405462095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.405462095
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3605994352
Short name T119
Test name
Test status
Simulation time 214418826 ps
CPU time 7.82 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:25 PM PDT 24
Peak memory 214076 kb
Host smart-fd7a6e13-0ddc-4686-8230-580d2a5534df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605994352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3605994352
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1915346649
Short name T217
Test name
Test status
Simulation time 3673329171 ps
CPU time 68.43 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:26:13 PM PDT 24
Peak memory 222452 kb
Host smart-202c5ee6-3f7c-4860-bad2-cdc21427f7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915346649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1915346649
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2816059948
Short name T117
Test name
Test status
Simulation time 20357510714 ps
CPU time 111.96 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:26:27 PM PDT 24
Peak memory 222332 kb
Host smart-86b621a7-d0b3-4d83-9f38-8b39bb4ddc81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816059948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2816059948
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.465060692
Short name T203
Test name
Test status
Simulation time 108947743 ps
CPU time 5.2 seconds
Started Jul 26 07:24:05 PM PDT 24
Finished Jul 26 07:24:11 PM PDT 24
Peak memory 207020 kb
Host smart-843284d8-93a4-4104-b124-e2438a343329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465060692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.465060692
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1899255671
Short name T7
Test name
Test status
Simulation time 142500660 ps
CPU time 4.86 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 209440 kb
Host smart-56545544-4bfc-4989-ab8e-62ae00860dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899255671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1899255671
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1992182190
Short name T140
Test name
Test status
Simulation time 29499849358 ps
CPU time 175.87 seconds
Started Jul 26 07:22:11 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 222108 kb
Host smart-559a45c0-1b0b-4270-adf1-7df5a4de8a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992182190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1992182190
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1792542591
Short name T150
Test name
Test status
Simulation time 300202927 ps
CPU time 12.01 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:12 PM PDT 24
Peak memory 214916 kb
Host smart-e3a5bc0c-4d03-47fa-a593-c19eae528ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792542591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1792542591
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4127935540
Short name T11
Test name
Test status
Simulation time 382297060 ps
CPU time 10.64 seconds
Started Jul 26 07:22:31 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 215128 kb
Host smart-23be9c71-b175-4640-8b06-8293d151ce83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127935540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4127935540
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.720718367
Short name T20
Test name
Test status
Simulation time 84292400 ps
CPU time 4.14 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 220868 kb
Host smart-2dc9e4f3-d946-4cdb-99b2-af57e8acd485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720718367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.720718367
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3843504984
Short name T409
Test name
Test status
Simulation time 352545128 ps
CPU time 9.04 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:54 PM PDT 24
Peak memory 214168 kb
Host smart-33e4a326-d139-49b5-8297-ce3cbfa0d4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843504984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3843504984
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3642947796
Short name T209
Test name
Test status
Simulation time 1236572618 ps
CPU time 30.35 seconds
Started Jul 26 07:25:19 PM PDT 24
Finished Jul 26 07:25:50 PM PDT 24
Peak memory 222068 kb
Host smart-df5b9cc9-d8e4-4c67-b710-3c8bc2133941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642947796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3642947796
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3645594632
Short name T53
Test name
Test status
Simulation time 2980596899 ps
CPU time 19.93 seconds
Started Jul 26 07:25:09 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 222416 kb
Host smart-ab16d992-e3d0-4eb8-98b8-5d21302dd7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645594632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3645594632
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1681598501
Short name T239
Test name
Test status
Simulation time 394586890 ps
CPU time 10.58 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 214228 kb
Host smart-8564bc77-a92a-4540-a48a-c5818d339814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681598501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1681598501
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2994981245
Short name T115
Test name
Test status
Simulation time 323322770 ps
CPU time 2.5 seconds
Started Jul 26 07:09:32 PM PDT 24
Finished Jul 26 07:09:35 PM PDT 24
Peak memory 214068 kb
Host smart-cde857b1-d0e4-4ff3-a1f2-0e84c38eaec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994981245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2994981245
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.806003711
Short name T35
Test name
Test status
Simulation time 5591300619 ps
CPU time 40.42 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:22:31 PM PDT 24
Peak memory 211764 kb
Host smart-c39c4900-4339-4ba4-bd82-93ea3e476818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806003711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.806003711
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2596914638
Short name T19
Test name
Test status
Simulation time 85347786 ps
CPU time 3.62 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 216080 kb
Host smart-10cd9743-ada6-4b42-914a-ef40d0e4abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596914638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2596914638
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3128680056
Short name T390
Test name
Test status
Simulation time 3270122023 ps
CPU time 91.32 seconds
Started Jul 26 07:25:14 PM PDT 24
Finished Jul 26 07:26:45 PM PDT 24
Peak memory 214416 kb
Host smart-f322cf93-8a06-4436-bbd0-bfceb695cebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128680056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3128680056
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.690772522
Short name T55
Test name
Test status
Simulation time 127687425 ps
CPU time 4.19 seconds
Started Jul 26 07:25:15 PM PDT 24
Finished Jul 26 07:25:19 PM PDT 24
Peak memory 218456 kb
Host smart-fdcad7cf-08ad-42a1-863c-c1cddb1d46ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690772522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.690772522
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1350432666
Short name T228
Test name
Test status
Simulation time 2251534705 ps
CPU time 35.63 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:55 PM PDT 24
Peak memory 222372 kb
Host smart-1e73e135-2596-4c57-986e-7263ad92cfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350432666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1350432666
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.965681993
Short name T214
Test name
Test status
Simulation time 106363429 ps
CPU time 2.59 seconds
Started Jul 26 07:23:03 PM PDT 24
Finished Jul 26 07:23:05 PM PDT 24
Peak memory 209148 kb
Host smart-5e85a004-b3b4-4df4-9080-0a0dbfd885d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965681993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.965681993
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1752779336
Short name T21
Test name
Test status
Simulation time 707627889 ps
CPU time 7.31 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:23 PM PDT 24
Peak memory 211240 kb
Host smart-901e832e-518c-4b05-ad8f-048e5c8e965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752779336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1752779336
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1588349409
Short name T198
Test name
Test status
Simulation time 1116345917 ps
CPU time 41.81 seconds
Started Jul 26 07:21:03 PM PDT 24
Finished Jul 26 07:21:45 PM PDT 24
Peak memory 222276 kb
Host smart-cee44baa-ec16-4e52-8bc3-7c9f0f441c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588349409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1588349409
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3901668811
Short name T404
Test name
Test status
Simulation time 2444817006 ps
CPU time 30.6 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:23:11 PM PDT 24
Peak memory 215524 kb
Host smart-0ddda073-4388-436a-8032-6f688ae0034e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901668811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3901668811
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3524754710
Short name T613
Test name
Test status
Simulation time 82609981 ps
CPU time 3.06 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 210200 kb
Host smart-9bad8ed2-ee99-4505-a6b4-400eb39ae61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524754710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3524754710
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2987330907
Short name T63
Test name
Test status
Simulation time 1451717698 ps
CPU time 19.78 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 222452 kb
Host smart-5b951533-c607-498a-b1ec-6e313b909ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987330907 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2987330907
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2456228506
Short name T253
Test name
Test status
Simulation time 472438076 ps
CPU time 5.96 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:22 PM PDT 24
Peak memory 214116 kb
Host smart-02a83074-26c5-446e-89b8-2db3fcf97f53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456228506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2456228506
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2517941530
Short name T232
Test name
Test status
Simulation time 5801934406 ps
CPU time 54.99 seconds
Started Jul 26 07:21:36 PM PDT 24
Finished Jul 26 07:22:31 PM PDT 24
Peak memory 215552 kb
Host smart-68ab1567-ddd1-461a-a82f-35262151a388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517941530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2517941530
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4000336500
Short name T170
Test name
Test status
Simulation time 784894219 ps
CPU time 6.34 seconds
Started Jul 26 07:09:20 PM PDT 24
Finished Jul 26 07:09:27 PM PDT 24
Peak memory 213876 kb
Host smart-d0f8ebb0-6824-4e01-acf7-1d2afc2e3915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000336500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4000336500
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.276098634
Short name T422
Test name
Test status
Simulation time 28889997 ps
CPU time 0.79 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:02 PM PDT 24
Peak memory 205852 kb
Host smart-d8143dc2-262f-452b-b201-9ce38a00c726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276098634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.276098634
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3823016861
Short name T144
Test name
Test status
Simulation time 179499375 ps
CPU time 3.6 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 214156 kb
Host smart-9f75eb14-994c-4875-a72b-d1ff26a2e6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823016861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3823016861
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2115771950
Short name T234
Test name
Test status
Simulation time 6712582821 ps
CPU time 62.33 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 216048 kb
Host smart-66ada543-f04d-4890-b932-300d2bc0273d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115771950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2115771950
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2965128055
Short name T146
Test name
Test status
Simulation time 538058285 ps
CPU time 14.53 seconds
Started Jul 26 07:21:24 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 215380 kb
Host smart-3d9e9b91-46eb-49e0-a7df-0e4f9ca1c064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965128055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2965128055
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.436819982
Short name T12
Test name
Test status
Simulation time 46618173 ps
CPU time 1.72 seconds
Started Jul 26 07:21:34 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 214156 kb
Host smart-fec8c38e-ee86-4405-940d-7c9cf698a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436819982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.436819982
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.561279076
Short name T93
Test name
Test status
Simulation time 13761812083 ps
CPU time 68.38 seconds
Started Jul 26 07:25:21 PM PDT 24
Finished Jul 26 07:26:30 PM PDT 24
Peak memory 222252 kb
Host smart-32602fc1-edbe-4448-a2a5-0e0759cf1453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561279076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.561279076
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3246605225
Short name T245
Test name
Test status
Simulation time 52028105 ps
CPU time 2.95 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 214072 kb
Host smart-a22ef5c6-97ea-4c20-99e9-14375dfc54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246605225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3246605225
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.190021005
Short name T227
Test name
Test status
Simulation time 48320586125 ps
CPU time 592.2 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:33:24 PM PDT 24
Peak memory 230612 kb
Host smart-b7837b29-e448-4da8-b811-f9917b177a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190021005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.190021005
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2640261671
Short name T264
Test name
Test status
Simulation time 54971802 ps
CPU time 2.35 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 214104 kb
Host smart-a2f1eef5-6de6-42ef-99d9-9dcddb721857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640261671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2640261671
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2455166021
Short name T26
Test name
Test status
Simulation time 3421132769 ps
CPU time 58.02 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 222628 kb
Host smart-290bfad1-0852-4f80-8a8c-b58c868a12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455166021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2455166021
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2863207689
Short name T68
Test name
Test status
Simulation time 79897635 ps
CPU time 2.99 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 217080 kb
Host smart-d2b954c2-4854-4a29-acaa-d89568b89714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863207689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2863207689
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1249321502
Short name T160
Test name
Test status
Simulation time 48266218 ps
CPU time 2.86 seconds
Started Jul 26 07:22:30 PM PDT 24
Finished Jul 26 07:22:33 PM PDT 24
Peak memory 215296 kb
Host smart-98ec75af-2ced-4858-bb63-46e120351a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249321502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1249321502
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4233748517
Short name T172
Test name
Test status
Simulation time 433408120 ps
CPU time 3.34 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 213916 kb
Host smart-d2ca830a-d29e-4c05-b82b-3d182e834430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233748517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4233748517
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2774508381
Short name T116
Test name
Test status
Simulation time 402130491 ps
CPU time 6.32 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:59 PM PDT 24
Peak memory 214184 kb
Host smart-97f96505-e219-44e0-8eac-44c085af1f41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774508381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2774508381
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2339221049
Short name T48
Test name
Test status
Simulation time 1291238704 ps
CPU time 28.39 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:28 PM PDT 24
Peak memory 216472 kb
Host smart-236a80e5-6b62-478f-9cbd-4e133a4e3485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339221049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2339221049
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1172184623
Short name T162
Test name
Test status
Simulation time 43199292 ps
CPU time 3.51 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:43 PM PDT 24
Peak memory 217132 kb
Host smart-ca149005-f604-4239-9f22-b9660d75ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172184623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1172184623
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1730706208
Short name T196
Test name
Test status
Simulation time 2893038387 ps
CPU time 19.65 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:22:59 PM PDT 24
Peak memory 215760 kb
Host smart-b641a0b7-b3f3-4770-a44c-b45f8711440e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730706208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1730706208
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3581689666
Short name T381
Test name
Test status
Simulation time 106898555 ps
CPU time 2 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 214156 kb
Host smart-01a16d0d-a24e-480f-b9bc-5c76459388a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581689666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3581689666
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2280061711
Short name T24
Test name
Test status
Simulation time 42347423 ps
CPU time 3.17 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 209248 kb
Host smart-d3d10559-6c76-4006-b877-463e43aa0d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280061711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2280061711
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4061553129
Short name T308
Test name
Test status
Simulation time 52970645 ps
CPU time 3.49 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 214868 kb
Host smart-79bde09b-ec3d-43f7-9ede-2eff1c255687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061553129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4061553129
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.575487817
Short name T71
Test name
Test status
Simulation time 1149648508 ps
CPU time 40.53 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 217428 kb
Host smart-6da37097-673d-4f71-a101-fb34c7cf42c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575487817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.575487817
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2669975701
Short name T182
Test name
Test status
Simulation time 568735308 ps
CPU time 4.16 seconds
Started Jul 26 07:09:15 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 214944 kb
Host smart-8c83ed29-09b1-4e00-810d-1c5c75cc5a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669975701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2669975701
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.583942451
Short name T185
Test name
Test status
Simulation time 358138390 ps
CPU time 6.45 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:34 PM PDT 24
Peak memory 213848 kb
Host smart-cdf141e4-d6f0-40f7-ae37-3700f779ac5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583942451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.583942451
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3943319297
Short name T175
Test name
Test status
Simulation time 216625392 ps
CPU time 8.47 seconds
Started Jul 26 07:09:30 PM PDT 24
Finished Jul 26 07:09:39 PM PDT 24
Peak memory 213880 kb
Host smart-bb47a9e1-e3bf-40da-a55a-ac224a2d9620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943319297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3943319297
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1031140657
Short name T171
Test name
Test status
Simulation time 319659650 ps
CPU time 5.31 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:08 PM PDT 24
Peak memory 213888 kb
Host smart-39634239-9190-418a-8352-addf0fd4bff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031140657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1031140657
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3587114495
Short name T9
Test name
Test status
Simulation time 639548810 ps
CPU time 21.2 seconds
Started Jul 26 07:21:01 PM PDT 24
Finished Jul 26 07:21:22 PM PDT 24
Peak memory 239700 kb
Host smart-a5f1eb06-1f17-4671-b660-8add205684d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587114495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3587114495
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.414829736
Short name T166
Test name
Test status
Simulation time 47105723 ps
CPU time 2.82 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 216896 kb
Host smart-efa0498a-0606-4a2c-984d-4ab50f690b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414829736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.414829736
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.561531153
Short name T345
Test name
Test status
Simulation time 788120517 ps
CPU time 22.54 seconds
Started Jul 26 07:20:58 PM PDT 24
Finished Jul 26 07:21:21 PM PDT 24
Peak memory 217844 kb
Host smart-ee50ca0c-67a8-4e79-bfaa-d731ea5014a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561531153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.561531153
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2416203970
Short name T57
Test name
Test status
Simulation time 86038038 ps
CPU time 2.12 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:01 PM PDT 24
Peak memory 209592 kb
Host smart-6664313c-98d3-488c-8562-48737ee7d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416203970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2416203970
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1983078125
Short name T374
Test name
Test status
Simulation time 1979278352 ps
CPU time 27.23 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:31 PM PDT 24
Peak memory 222180 kb
Host smart-1c5d957f-e750-44f9-80c2-d714be8a5d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983078125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1983078125
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1928869051
Short name T402
Test name
Test status
Simulation time 63072909 ps
CPU time 4.24 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:44 PM PDT 24
Peak memory 214164 kb
Host smart-43428b2e-f0de-4e2d-81c3-7478c1d43107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928869051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1928869051
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.11171856
Short name T112
Test name
Test status
Simulation time 223260100 ps
CPU time 3.05 seconds
Started Jul 26 07:21:36 PM PDT 24
Finished Jul 26 07:21:40 PM PDT 24
Peak memory 208496 kb
Host smart-a4aa327b-5d53-4a7d-9f92-1f05980e5d53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.11171856
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1098041846
Short name T904
Test name
Test status
Simulation time 1705479534 ps
CPU time 61.31 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:22:37 PM PDT 24
Peak memory 222276 kb
Host smart-dd38b594-9e03-4397-a1c8-5e7cb2e5d8ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098041846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1098041846
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1308732601
Short name T414
Test name
Test status
Simulation time 180777134 ps
CPU time 3.76 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:51 PM PDT 24
Peak memory 214116 kb
Host smart-6fa40992-3c56-49fc-93eb-182b97b759f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308732601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1308732601
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.712870639
Short name T183
Test name
Test status
Simulation time 97877176 ps
CPU time 2.92 seconds
Started Jul 26 07:08:07 PM PDT 24
Finished Jul 26 07:08:10 PM PDT 24
Peak memory 213820 kb
Host smart-3a92de73-549e-4b13-8f11-4f70d7dbcff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712870639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
712870639
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1345832218
Short name T161
Test name
Test status
Simulation time 123648131 ps
CPU time 4.29 seconds
Started Jul 26 07:23:02 PM PDT 24
Finished Jul 26 07:23:06 PM PDT 24
Peak memory 222408 kb
Host smart-d6116d93-7ac1-41cc-a91d-2d18f4397bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345832218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1345832218
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1358144755
Short name T164
Test name
Test status
Simulation time 118903330 ps
CPU time 4.53 seconds
Started Jul 26 07:25:18 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 222476 kb
Host smart-2241f50a-8abd-4ddb-a11b-98463d0e75d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358144755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1358144755
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1754543317
Short name T163
Test name
Test status
Simulation time 212920038 ps
CPU time 3.96 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 217868 kb
Host smart-37adb18d-bc9e-4355-8fd9-2e40300f073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754543317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1754543317
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1004781799
Short name T167
Test name
Test status
Simulation time 258749088 ps
CPU time 4.38 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 222440 kb
Host smart-31e92a7e-7b6c-493d-aade-68304b64527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004781799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1004781799
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2072617996
Short name T289
Test name
Test status
Simulation time 396802859 ps
CPU time 5.01 seconds
Started Jul 26 07:22:18 PM PDT 24
Finished Jul 26 07:22:23 PM PDT 24
Peak memory 222216 kb
Host smart-daa2c357-f3a9-4b22-93a0-548962532807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072617996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2072617996
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.718128740
Short name T149
Test name
Test status
Simulation time 4644048879 ps
CPU time 28.6 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:57 PM PDT 24
Peak memory 216508 kb
Host smart-fad00d4b-39df-4280-bb6b-c27411a02778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718128740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.718128740
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.412831024
Short name T312
Test name
Test status
Simulation time 690167627 ps
CPU time 8.28 seconds
Started Jul 26 07:22:31 PM PDT 24
Finished Jul 26 07:22:39 PM PDT 24
Peak memory 208772 kb
Host smart-276fd35d-5aff-4bf0-94d6-4be8aac60672
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412831024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.412831024
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3727104172
Short name T320
Test name
Test status
Simulation time 92187708 ps
CPU time 4.34 seconds
Started Jul 26 07:22:56 PM PDT 24
Finished Jul 26 07:23:00 PM PDT 24
Peak memory 215152 kb
Host smart-c2fe28c5-6472-4cae-9db1-303f443c8d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727104172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3727104172
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.668234461
Short name T291
Test name
Test status
Simulation time 31732504 ps
CPU time 2.07 seconds
Started Jul 26 07:22:48 PM PDT 24
Finished Jul 26 07:22:50 PM PDT 24
Peak memory 214116 kb
Host smart-ee9dd50b-5484-4f8c-be78-937618658f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668234461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.668234461
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1776376908
Short name T127
Test name
Test status
Simulation time 9126150455 ps
CPU time 21.81 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:22 PM PDT 24
Peak memory 223916 kb
Host smart-36bd5e7a-158d-4aac-8493-be09f5b8c006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776376908 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1776376908
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2063870912
Short name T885
Test name
Test status
Simulation time 106870790 ps
CPU time 3.79 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 222240 kb
Host smart-069698b6-f859-459e-997e-69196ed961e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063870912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2063870912
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1729559745
Short name T342
Test name
Test status
Simulation time 72137175 ps
CPU time 4.43 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:20 PM PDT 24
Peak memory 215152 kb
Host smart-738cf4fa-132d-45d9-b645-b2e94a3a16ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729559745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1729559745
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2389467021
Short name T349
Test name
Test status
Simulation time 20711448359 ps
CPU time 51.67 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 222336 kb
Host smart-e3ad5307-dd6d-4ef2-9853-8bef4bc856e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389467021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2389467021
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1378654915
Short name T189
Test name
Test status
Simulation time 418546643 ps
CPU time 3.28 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:20 PM PDT 24
Peak memory 213884 kb
Host smart-066d564e-22a4-4d93-ae77-fc55b3e90e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378654915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1378654915
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3841698886
Short name T179
Test name
Test status
Simulation time 374725933 ps
CPU time 5.21 seconds
Started Jul 26 07:08:21 PM PDT 24
Finished Jul 26 07:08:26 PM PDT 24
Peak memory 213948 kb
Host smart-b9ace3e1-b26f-484b-8bf8-57a7f8cdab89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841698886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3841698886
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.862635437
Short name T184
Test name
Test status
Simulation time 215981232 ps
CPU time 5.25 seconds
Started Jul 26 07:09:02 PM PDT 24
Finished Jul 26 07:09:07 PM PDT 24
Peak memory 215356 kb
Host smart-85829e88-169e-4ac9-a32e-e5b98585bb09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862635437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
862635437
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.716117879
Short name T165
Test name
Test status
Simulation time 736930659 ps
CPU time 3.29 seconds
Started Jul 26 07:22:11 PM PDT 24
Finished Jul 26 07:22:15 PM PDT 24
Peak memory 217348 kb
Host smart-b99ca386-c058-4ae2-a809-4a981a54b512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716117879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.716117879
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2344296432
Short name T22
Test name
Test status
Simulation time 652649909 ps
CPU time 5.18 seconds
Started Jul 26 07:20:46 PM PDT 24
Finished Jul 26 07:20:52 PM PDT 24
Peak memory 214204 kb
Host smart-f02dae21-f5b5-4205-b171-7776050458aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344296432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2344296432
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.473582
Short name T142
Test name
Test status
Simulation time 964047892 ps
CPU time 6.87 seconds
Started Jul 26 07:20:50 PM PDT 24
Finished Jul 26 07:20:57 PM PDT 24
Peak memory 208580 kb
Host smart-f873e7cd-f427-481f-9556-7430d39bd154
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.473582
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.55581587
Short name T343
Test name
Test status
Simulation time 256055123 ps
CPU time 2.91 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:02 PM PDT 24
Peak memory 215096 kb
Host smart-7b9902b6-bd97-41e5-94cf-d553963a1b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55581587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.55581587
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2210362349
Short name T124
Test name
Test status
Simulation time 2172718178 ps
CPU time 21.96 seconds
Started Jul 26 07:21:00 PM PDT 24
Finished Jul 26 07:21:22 PM PDT 24
Peak memory 222424 kb
Host smart-63d3d561-d5bc-46f3-8d1f-d3d18be0f324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210362349 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2210362349
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1975412206
Short name T663
Test name
Test status
Simulation time 331554109 ps
CPU time 12.88 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:25 PM PDT 24
Peak memory 222364 kb
Host smart-afacebad-89d7-46f9-a164-989a05c05222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975412206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1975412206
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2686291683
Short name T70
Test name
Test status
Simulation time 214570569 ps
CPU time 2.85 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 207936 kb
Host smart-bc1586e5-520b-496a-9c11-a8bf29f6f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686291683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2686291683
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3683474100
Short name T358
Test name
Test status
Simulation time 69485695 ps
CPU time 3.12 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 214080 kb
Host smart-3df2a26e-76f4-4e01-892d-ce2791a20e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683474100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3683474100
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1147939797
Short name T5
Test name
Test status
Simulation time 95931667 ps
CPU time 2.82 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 219712 kb
Host smart-34dba089-85a9-4e5c-8dec-def19d0bc400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147939797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1147939797
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.456389566
Short name T350
Test name
Test status
Simulation time 2682073974 ps
CPU time 9.93 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:39 PM PDT 24
Peak memory 214900 kb
Host smart-8dbe4c60-abc1-4de1-aad7-1e017a76ebe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456389566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.456389566
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3674238244
Short name T237
Test name
Test status
Simulation time 180165077 ps
CPU time 4.91 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:22:47 PM PDT 24
Peak memory 208520 kb
Host smart-6f810ea1-39fb-443a-984f-665dda6815dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674238244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3674238244
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1263696602
Short name T563
Test name
Test status
Simulation time 69261920 ps
CPU time 2.49 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 210328 kb
Host smart-a0e54a4f-c22c-4f5a-b7e6-6a52b6993517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263696602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1263696602
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1968109846
Short name T406
Test name
Test status
Simulation time 142297635 ps
CPU time 8.48 seconds
Started Jul 26 07:22:43 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 222272 kb
Host smart-418bbb7e-0ea8-46c5-b9c5-ee3fb271d646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968109846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1968109846
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1565046554
Short name T333
Test name
Test status
Simulation time 120526491 ps
CPU time 2.16 seconds
Started Jul 26 07:22:47 PM PDT 24
Finished Jul 26 07:22:49 PM PDT 24
Peak memory 220268 kb
Host smart-29be4e4d-f6ff-49fd-b9a6-099f1d00f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565046554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1565046554
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3511328119
Short name T14
Test name
Test status
Simulation time 1119385842 ps
CPU time 3.95 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:16 PM PDT 24
Peak memory 221592 kb
Host smart-bcb5aaeb-da68-48e1-8476-f0a4afe22335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511328119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3511328119
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2501574130
Short name T362
Test name
Test status
Simulation time 127886675 ps
CPU time 5.42 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 214040 kb
Host smart-44b656e7-237b-4f05-8bbb-25dfa5d67ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501574130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2501574130
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.232983559
Short name T287
Test name
Test status
Simulation time 380541772 ps
CPU time 2.06 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 214220 kb
Host smart-c090c884-ddce-481a-8246-61d39cda3132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232983559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.232983559
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3099698194
Short name T73
Test name
Test status
Simulation time 140836425 ps
CPU time 1.88 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:32 PM PDT 24
Peak memory 208412 kb
Host smart-46ba2967-fb35-484a-b6ad-0790095d7cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099698194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3099698194
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.562037149
Short name T259
Test name
Test status
Simulation time 35272816 ps
CPU time 1.84 seconds
Started Jul 26 07:24:04 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 214060 kb
Host smart-82352af8-2723-40d2-88fc-d462aef3390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562037149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.562037149
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1009865981
Short name T299
Test name
Test status
Simulation time 750202860 ps
CPU time 15.6 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:50 PM PDT 24
Peak memory 219988 kb
Host smart-b7f9e822-dc81-44a9-815a-cdd86603e3d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009865981 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1009865981
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3886913834
Short name T314
Test name
Test status
Simulation time 245185480 ps
CPU time 12.26 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:16 PM PDT 24
Peak memory 215028 kb
Host smart-e7f0d696-6248-4915-8634-67296963b5c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886913834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3886913834
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3846902681
Short name T133
Test name
Test status
Simulation time 401749399 ps
CPU time 13.92 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:36 PM PDT 24
Peak memory 220088 kb
Host smart-0b8b494e-53e9-4668-8774-ee8b9beab064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846902681 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3846902681
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1111548455
Short name T90
Test name
Test status
Simulation time 282993043 ps
CPU time 2.96 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 214128 kb
Host smart-57b0da42-82d9-4335-9d55-d47234bc6818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111548455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1111548455
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2139255334
Short name T1027
Test name
Test status
Simulation time 510879758 ps
CPU time 8.65 seconds
Started Jul 26 07:08:18 PM PDT 24
Finished Jul 26 07:08:27 PM PDT 24
Peak memory 205748 kb
Host smart-a0fc8346-5f6d-459b-97cb-6665734428ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139255334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
139255334
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.463500559
Short name T1037
Test name
Test status
Simulation time 1089258879 ps
CPU time 14.72 seconds
Started Jul 26 07:08:22 PM PDT 24
Finished Jul 26 07:08:36 PM PDT 24
Peak memory 205712 kb
Host smart-1350324e-f748-41d8-a4c2-e23a25b2b765
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463500559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.463500559
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2833872683
Short name T1061
Test name
Test status
Simulation time 15780942 ps
CPU time 1.09 seconds
Started Jul 26 07:08:26 PM PDT 24
Finished Jul 26 07:08:27 PM PDT 24
Peak memory 205704 kb
Host smart-4fa35051-52a9-4f3b-96e8-383d346b6b65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833872683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
833872683
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.107375383
Short name T939
Test name
Test status
Simulation time 194101396 ps
CPU time 2.37 seconds
Started Jul 26 07:08:20 PM PDT 24
Finished Jul 26 07:08:22 PM PDT 24
Peak memory 213880 kb
Host smart-70d6326a-fbac-4873-8a0a-811149b852b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107375383 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.107375383
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.504836276
Short name T1078
Test name
Test status
Simulation time 21263520 ps
CPU time 1.01 seconds
Started Jul 26 07:08:18 PM PDT 24
Finished Jul 26 07:08:19 PM PDT 24
Peak memory 205488 kb
Host smart-3cfafa9a-d3ac-49d2-8933-60e091386cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504836276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.504836276
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2593636530
Short name T956
Test name
Test status
Simulation time 36991842 ps
CPU time 0.69 seconds
Started Jul 26 07:08:06 PM PDT 24
Finished Jul 26 07:08:07 PM PDT 24
Peak memory 205480 kb
Host smart-1e9bbad4-e26a-46c6-9492-5086b0a5f1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593636530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2593636530
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1050688545
Short name T953
Test name
Test status
Simulation time 412802843 ps
CPU time 3.94 seconds
Started Jul 26 07:08:26 PM PDT 24
Finished Jul 26 07:08:30 PM PDT 24
Peak memory 205680 kb
Host smart-0b1836a4-9370-44e7-84b5-f84acc95aace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050688545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1050688545
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1216409398
Short name T936
Test name
Test status
Simulation time 71326086 ps
CPU time 2.55 seconds
Started Jul 26 07:08:07 PM PDT 24
Finished Jul 26 07:08:10 PM PDT 24
Peak memory 214192 kb
Host smart-7c22a3b3-6484-4052-9440-7fb3276f8f89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216409398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1216409398
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.183022506
Short name T981
Test name
Test status
Simulation time 134512469 ps
CPU time 6.02 seconds
Started Jul 26 07:08:07 PM PDT 24
Finished Jul 26 07:08:14 PM PDT 24
Peak memory 214236 kb
Host smart-1fce350b-4b7d-4b01-a6fe-94192ac55e04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183022506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.183022506
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2657560545
Short name T1074
Test name
Test status
Simulation time 152010616 ps
CPU time 1.29 seconds
Started Jul 26 07:08:06 PM PDT 24
Finished Jul 26 07:08:08 PM PDT 24
Peak memory 214072 kb
Host smart-97cf4a8c-f30c-4840-ad27-aaa42a174823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657560545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2657560545
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.232036531
Short name T152
Test name
Test status
Simulation time 67144088 ps
CPU time 4.79 seconds
Started Jul 26 07:08:25 PM PDT 24
Finished Jul 26 07:08:30 PM PDT 24
Peak memory 205724 kb
Host smart-6e8a63c6-5db8-4c64-95ee-1790d669bef0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232036531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.232036531
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.842591388
Short name T1075
Test name
Test status
Simulation time 2901917506 ps
CPU time 17.32 seconds
Started Jul 26 07:08:22 PM PDT 24
Finished Jul 26 07:08:39 PM PDT 24
Peak memory 205676 kb
Host smart-fb725be7-374d-4920-bd23-14d714542ac0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842591388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.842591388
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3779435362
Short name T1060
Test name
Test status
Simulation time 59788329 ps
CPU time 1.16 seconds
Started Jul 26 07:08:19 PM PDT 24
Finished Jul 26 07:08:21 PM PDT 24
Peak memory 205640 kb
Host smart-106b7c41-cc7a-470c-8a87-79da58ab14bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779435362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
779435362
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2260257107
Short name T1068
Test name
Test status
Simulation time 68997421 ps
CPU time 2.25 seconds
Started Jul 26 07:08:19 PM PDT 24
Finished Jul 26 07:08:22 PM PDT 24
Peak memory 219932 kb
Host smart-a6c0b1e5-ae97-4818-be86-84f5f5a6b3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260257107 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2260257107
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3857307810
Short name T156
Test name
Test status
Simulation time 22466425 ps
CPU time 1.02 seconds
Started Jul 26 07:08:21 PM PDT 24
Finished Jul 26 07:08:22 PM PDT 24
Peak memory 205536 kb
Host smart-39322f75-c0fb-4c4a-9bb7-a9b72d48ab3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857307810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3857307810
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.49002817
Short name T1022
Test name
Test status
Simulation time 14863760 ps
CPU time 0.73 seconds
Started Jul 26 07:08:25 PM PDT 24
Finished Jul 26 07:08:26 PM PDT 24
Peak memory 205416 kb
Host smart-c66f0152-b95d-4c47-afdc-b8ed906b2361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49002817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.49002817
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1885713340
Short name T995
Test name
Test status
Simulation time 68686071 ps
CPU time 2.53 seconds
Started Jul 26 07:08:23 PM PDT 24
Finished Jul 26 07:08:26 PM PDT 24
Peak memory 205760 kb
Host smart-5d9312db-c1b0-4c63-91a7-cc9a53326be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885713340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1885713340
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3513293131
Short name T1001
Test name
Test status
Simulation time 173453671 ps
CPU time 1.61 seconds
Started Jul 26 07:08:20 PM PDT 24
Finished Jul 26 07:08:22 PM PDT 24
Peak memory 214216 kb
Host smart-dc13a7a6-9a62-4c8f-88d1-839473e6b922
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513293131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3513293131
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1347688666
Short name T1035
Test name
Test status
Simulation time 77735234 ps
CPU time 3.63 seconds
Started Jul 26 07:08:21 PM PDT 24
Finished Jul 26 07:08:25 PM PDT 24
Peak memory 214124 kb
Host smart-25953ebb-7010-40de-893e-9da02c835202
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347688666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1347688666
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2415723525
Short name T191
Test name
Test status
Simulation time 136091062 ps
CPU time 4.68 seconds
Started Jul 26 07:08:19 PM PDT 24
Finished Jul 26 07:08:24 PM PDT 24
Peak memory 213952 kb
Host smart-b4daf105-7fdd-4e10-ab12-10259a834b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415723525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2415723525
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1194305493
Short name T1012
Test name
Test status
Simulation time 101366698 ps
CPU time 2.82 seconds
Started Jul 26 07:08:19 PM PDT 24
Finished Jul 26 07:08:22 PM PDT 24
Peak memory 205752 kb
Host smart-96037608-5a97-4e3b-89a4-b521fdbc00ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194305493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1194305493
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1878476210
Short name T1056
Test name
Test status
Simulation time 97091529 ps
CPU time 1.42 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:18 PM PDT 24
Peak memory 205764 kb
Host smart-c4cc1c2e-cfb3-4e46-b784-607ae64d75b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878476210 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1878476210
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1345128048
Short name T1021
Test name
Test status
Simulation time 375401140 ps
CPU time 1.12 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:18 PM PDT 24
Peak memory 205740 kb
Host smart-3aa1f4f6-573d-4711-b741-64a3f08d9e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345128048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1345128048
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.831976971
Short name T955
Test name
Test status
Simulation time 21263692 ps
CPU time 0.88 seconds
Started Jul 26 07:09:18 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 205396 kb
Host smart-543daec6-ebf3-4571-9a21-942cdc69a63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831976971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.831976971
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1494562645
Short name T1057
Test name
Test status
Simulation time 36456743 ps
CPU time 2.49 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:20 PM PDT 24
Peak memory 205764 kb
Host smart-93b3f621-75ce-441a-afd0-28ad1cad174b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494562645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1494562645
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2466450970
Short name T952
Test name
Test status
Simulation time 263666633 ps
CPU time 2.86 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:06 PM PDT 24
Peak memory 214192 kb
Host smart-9b632707-5c32-40a9-b5d4-50da81a3b4e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466450970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2466450970
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2134607062
Short name T976
Test name
Test status
Simulation time 70034899 ps
CPU time 3.46 seconds
Started Jul 26 07:09:05 PM PDT 24
Finished Jul 26 07:09:09 PM PDT 24
Peak memory 214156 kb
Host smart-dfa9ec74-b1c0-4162-80f7-90d4e0f9b4a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134607062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2134607062
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1203409284
Short name T1073
Test name
Test status
Simulation time 147337961 ps
CPU time 2.08 seconds
Started Jul 26 07:09:04 PM PDT 24
Finished Jul 26 07:09:06 PM PDT 24
Peak memory 213964 kb
Host smart-fc1d419e-0c2d-430f-9b3f-73d7dce925eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203409284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1203409284
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.145299296
Short name T1063
Test name
Test status
Simulation time 279987486 ps
CPU time 6.9 seconds
Started Jul 26 07:09:13 PM PDT 24
Finished Jul 26 07:09:20 PM PDT 24
Peak memory 213864 kb
Host smart-bf6dee91-3922-4b98-8d12-51224cbfeeb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145299296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.145299296
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3311974073
Short name T929
Test name
Test status
Simulation time 230594360 ps
CPU time 1.53 seconds
Started Jul 26 07:09:20 PM PDT 24
Finished Jul 26 07:09:22 PM PDT 24
Peak memory 213884 kb
Host smart-00d6adaf-c35e-4ef6-a5fd-7277210f2e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311974073 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3311974073
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4047145731
Short name T1038
Test name
Test status
Simulation time 140339799 ps
CPU time 1.54 seconds
Started Jul 26 07:09:20 PM PDT 24
Finished Jul 26 07:09:21 PM PDT 24
Peak memory 205532 kb
Host smart-a25f97f6-1c9f-4017-b58b-39818456e433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047145731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4047145731
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1189544949
Short name T924
Test name
Test status
Simulation time 17638068 ps
CPU time 0.78 seconds
Started Jul 26 07:09:15 PM PDT 24
Finished Jul 26 07:09:16 PM PDT 24
Peak memory 205444 kb
Host smart-edea1260-89d3-4187-ac11-57ac60d35604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189544949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1189544949
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3454285503
Short name T155
Test name
Test status
Simulation time 215832401 ps
CPU time 4.03 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:21 PM PDT 24
Peak memory 205716 kb
Host smart-93220d4d-6645-4945-9c1f-b23b01049d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454285503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3454285503
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4232249907
Short name T192
Test name
Test status
Simulation time 453892721 ps
CPU time 2.23 seconds
Started Jul 26 07:09:14 PM PDT 24
Finished Jul 26 07:09:16 PM PDT 24
Peak memory 214080 kb
Host smart-53c1b09f-05a9-47c0-a1ff-c8686e8abf81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232249907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4232249907
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2961896354
Short name T967
Test name
Test status
Simulation time 806046999 ps
CPU time 14.85 seconds
Started Jul 26 07:09:14 PM PDT 24
Finished Jul 26 07:09:29 PM PDT 24
Peak memory 214156 kb
Host smart-1e9040ce-38d6-49a7-ad91-5b6a5876d104
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961896354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2961896354
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2475109117
Short name T927
Test name
Test status
Simulation time 107135601 ps
CPU time 4.3 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:21 PM PDT 24
Peak memory 216968 kb
Host smart-61a445bb-ccff-4566-b5a8-0682564370b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475109117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2475109117
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3381600844
Short name T181
Test name
Test status
Simulation time 147981111 ps
CPU time 3.76 seconds
Started Jul 26 07:09:14 PM PDT 24
Finished Jul 26 07:09:18 PM PDT 24
Peak memory 213900 kb
Host smart-29ed7692-a53e-4dfd-ab3c-24896b44e970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381600844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3381600844
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1029105781
Short name T1033
Test name
Test status
Simulation time 37666211 ps
CPU time 1.73 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 213964 kb
Host smart-684f44db-d046-4632-aea8-6b1c95ae1f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029105781 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1029105781
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2620303961
Short name T1015
Test name
Test status
Simulation time 31525241 ps
CPU time 1.66 seconds
Started Jul 26 07:09:14 PM PDT 24
Finished Jul 26 07:09:16 PM PDT 24
Peak memory 205608 kb
Host smart-eb6ac7bb-c90c-4fbf-8257-0f49676d2668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620303961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2620303961
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2219363491
Short name T1059
Test name
Test status
Simulation time 17048544 ps
CPU time 0.78 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:17 PM PDT 24
Peak memory 205476 kb
Host smart-0c1d3db1-749e-4293-a1f1-87e06b83f11a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219363491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2219363491
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2232350010
Short name T1029
Test name
Test status
Simulation time 319817147 ps
CPU time 3.22 seconds
Started Jul 26 07:09:13 PM PDT 24
Finished Jul 26 07:09:17 PM PDT 24
Peak memory 205708 kb
Host smart-b5c275b8-839a-45c8-91e2-15299bc195dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232350010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2232350010
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3198197711
Short name T1079
Test name
Test status
Simulation time 495046723 ps
CPU time 2.02 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 214152 kb
Host smart-df733497-2036-44bf-a4ea-5f8e1e37da68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198197711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3198197711
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.920152852
Short name T938
Test name
Test status
Simulation time 525896290 ps
CPU time 6.48 seconds
Started Jul 26 07:09:13 PM PDT 24
Finished Jul 26 07:09:20 PM PDT 24
Peak memory 214160 kb
Host smart-147db086-d569-455c-8c08-dd606e86b8bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920152852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.920152852
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1790748958
Short name T1065
Test name
Test status
Simulation time 317068889 ps
CPU time 5.63 seconds
Started Jul 26 07:09:20 PM PDT 24
Finished Jul 26 07:09:26 PM PDT 24
Peak memory 222052 kb
Host smart-c88b98d7-6123-4287-b639-495babe3a285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790748958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1790748958
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.819997044
Short name T950
Test name
Test status
Simulation time 32957378 ps
CPU time 1.2 seconds
Started Jul 26 07:09:18 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 205648 kb
Host smart-8cf68748-13a6-4507-90c0-135f07cc72ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819997044 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.819997044
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1998021917
Short name T154
Test name
Test status
Simulation time 20445228 ps
CPU time 1 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:18 PM PDT 24
Peak memory 205504 kb
Host smart-56d468b7-93f8-4954-9c54-19248af8a4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998021917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1998021917
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4191148671
Short name T977
Test name
Test status
Simulation time 41220020 ps
CPU time 0.73 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:17 PM PDT 24
Peak memory 205488 kb
Host smart-5aabdb33-7c76-4224-9fbb-e45f84826851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191148671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4191148671
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2561989135
Short name T158
Test name
Test status
Simulation time 316912697 ps
CPU time 2.45 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:20 PM PDT 24
Peak memory 205720 kb
Host smart-4ab21329-8983-4342-91be-736e8e2ba903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561989135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2561989135
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2635073303
Short name T121
Test name
Test status
Simulation time 221551520 ps
CPU time 3.19 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 214080 kb
Host smart-69758b70-2d4a-4413-b17b-59b0c14f31c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635073303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2635073303
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.48087477
Short name T972
Test name
Test status
Simulation time 318804798 ps
CPU time 4.48 seconds
Started Jul 26 07:09:20 PM PDT 24
Finished Jul 26 07:09:24 PM PDT 24
Peak memory 214084 kb
Host smart-76a500b3-9662-48a6-bd1b-f77d884fad76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48087477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_shadow_reg_errors_with_csr_rw.48087477
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1294097387
Short name T1025
Test name
Test status
Simulation time 56558041 ps
CPU time 3.61 seconds
Started Jul 26 07:09:17 PM PDT 24
Finished Jul 26 07:09:21 PM PDT 24
Peak memory 213888 kb
Host smart-628579a6-897c-43f0-99bb-6bb91dbfcd9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294097387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1294097387
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4292506321
Short name T968
Test name
Test status
Simulation time 114742716 ps
CPU time 1.58 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 213988 kb
Host smart-cc5728fc-394a-4276-8c00-1a0a36ce333f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292506321 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4292506321
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2685932964
Short name T1004
Test name
Test status
Simulation time 14946077 ps
CPU time 1.29 seconds
Started Jul 26 07:09:31 PM PDT 24
Finished Jul 26 07:09:33 PM PDT 24
Peak memory 213920 kb
Host smart-5c98862e-0936-4061-82d2-4baf29fe73a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685932964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2685932964
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2889284495
Short name T1010
Test name
Test status
Simulation time 20154764 ps
CPU time 0.84 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:17 PM PDT 24
Peak memory 205376 kb
Host smart-58f64799-30ea-4656-a3b7-531e3531d3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889284495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2889284495
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2475025478
Short name T157
Test name
Test status
Simulation time 63490331 ps
CPU time 2.01 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:31 PM PDT 24
Peak memory 205684 kb
Host smart-62daf076-f383-446a-801f-ffe14f1c1e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475025478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2475025478
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.891144096
Short name T966
Test name
Test status
Simulation time 2639459779 ps
CPU time 3.03 seconds
Started Jul 26 07:09:14 PM PDT 24
Finished Jul 26 07:09:17 PM PDT 24
Peak memory 214088 kb
Host smart-9da80456-c360-4140-8955-28c0ae23bfcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891144096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.891144096
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1942139431
Short name T1064
Test name
Test status
Simulation time 94897479 ps
CPU time 2.42 seconds
Started Jul 26 07:09:16 PM PDT 24
Finished Jul 26 07:09:19 PM PDT 24
Peak memory 213932 kb
Host smart-49074947-7ebd-4267-b2c8-90a315dda34b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942139431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1942139431
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2147455753
Short name T1019
Test name
Test status
Simulation time 35039045 ps
CPU time 1.36 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 213972 kb
Host smart-04725a4f-9c47-4fd6-b60d-e205a636f535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147455753 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2147455753
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1784082866
Short name T947
Test name
Test status
Simulation time 110240821 ps
CPU time 1.07 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 205564 kb
Host smart-77eb6f76-d1df-4bb5-93f7-1fd68f39089f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784082866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1784082866
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.386794743
Short name T934
Test name
Test status
Simulation time 13340103 ps
CPU time 0.71 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 205460 kb
Host smart-ff33c40a-f431-4987-bc3b-a0103b940ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386794743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.386794743
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2237958795
Short name T961
Test name
Test status
Simulation time 82558319 ps
CPU time 2.45 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:31 PM PDT 24
Peak memory 213860 kb
Host smart-636b1371-ad4c-43d6-aaa7-7f98f0f79f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237958795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2237958795
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3278117575
Short name T940
Test name
Test status
Simulation time 180103821 ps
CPU time 2.72 seconds
Started Jul 26 07:09:30 PM PDT 24
Finished Jul 26 07:09:32 PM PDT 24
Peak memory 214196 kb
Host smart-444f2263-1813-41cf-b6e0-d6266252921a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278117575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3278117575
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4031192735
Short name T951
Test name
Test status
Simulation time 467974788 ps
CPU time 4.74 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:34 PM PDT 24
Peak memory 213932 kb
Host smart-a9134594-1e13-49e7-961c-f5407e59de73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031192735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4031192735
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2117194825
Short name T1052
Test name
Test status
Simulation time 567511168 ps
CPU time 3.4 seconds
Started Jul 26 07:09:27 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 213916 kb
Host smart-4a416b5c-8d6c-49e9-86f0-1ecc8d269fab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117194825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2117194825
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2353953481
Short name T964
Test name
Test status
Simulation time 174699039 ps
CPU time 1.52 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 213972 kb
Host smart-8d92dcc5-0873-4cd5-b189-4b1f7070e523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353953481 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2353953481
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4118923412
Short name T954
Test name
Test status
Simulation time 51593093 ps
CPU time 1.16 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 205632 kb
Host smart-f545dc3d-42e4-4689-a86d-bb98b28eef52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118923412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4118923412
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1739593822
Short name T1024
Test name
Test status
Simulation time 33733596 ps
CPU time 0.7 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:29 PM PDT 24
Peak memory 205488 kb
Host smart-6abe7fe9-8c24-4066-bd7a-6f797bea32aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739593822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1739593822
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1152689430
Short name T1011
Test name
Test status
Simulation time 52432178 ps
CPU time 2.03 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 205768 kb
Host smart-b2d0eecd-1b61-42ee-9a59-d83dbb002309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152689430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1152689430
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3377404918
Short name T996
Test name
Test status
Simulation time 285264567 ps
CPU time 6.64 seconds
Started Jul 26 07:09:33 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 214124 kb
Host smart-fcaf6d0e-8b49-4291-9074-780b5bb7a99a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377404918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3377404918
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.880719969
Short name T1003
Test name
Test status
Simulation time 303834046 ps
CPU time 2 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:30 PM PDT 24
Peak memory 213888 kb
Host smart-bcd69199-e71d-41ba-8471-9631892f5073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880719969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.880719969
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1208252967
Short name T1045
Test name
Test status
Simulation time 184884774 ps
CPU time 1.68 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:41 PM PDT 24
Peak memory 213860 kb
Host smart-6e15a6de-4745-4015-bf46-6883c1ee278d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208252967 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1208252967
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.286495547
Short name T932
Test name
Test status
Simulation time 72026466 ps
CPU time 1.11 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205696 kb
Host smart-718f5371-5363-476d-af44-e4330c98722c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286495547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.286495547
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1869647794
Short name T982
Test name
Test status
Simulation time 10962531 ps
CPU time 0.83 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:39 PM PDT 24
Peak memory 205484 kb
Host smart-e2b11dac-beba-44fa-b42e-65e1b2a67083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869647794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1869647794
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.64314279
Short name T1030
Test name
Test status
Simulation time 242080507 ps
CPU time 2.94 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205660 kb
Host smart-f4ef25af-3b8d-4ff2-adc4-78011ed441b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64314279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sam
e_csr_outstanding.64314279
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4241103811
Short name T120
Test name
Test status
Simulation time 1827759796 ps
CPU time 4.08 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:33 PM PDT 24
Peak memory 214100 kb
Host smart-a8ecdf97-ce03-4dff-ba67-79bca107421b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241103811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4241103811
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3069129227
Short name T1005
Test name
Test status
Simulation time 902881360 ps
CPU time 5.92 seconds
Started Jul 26 07:09:29 PM PDT 24
Finished Jul 26 07:09:35 PM PDT 24
Peak memory 220224 kb
Host smart-523cb295-f05a-4c21-b7bf-bc12a2eab293
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069129227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3069129227
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3737312228
Short name T1014
Test name
Test status
Simulation time 313541783 ps
CPU time 5.52 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:33 PM PDT 24
Peak memory 217052 kb
Host smart-3302a911-c761-4c2f-8c7e-9951f78cddc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737312228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3737312228
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3954426020
Short name T387
Test name
Test status
Simulation time 2165195933 ps
CPU time 4.15 seconds
Started Jul 26 07:09:28 PM PDT 24
Finished Jul 26 07:09:32 PM PDT 24
Peak memory 214036 kb
Host smart-620d6c59-35c2-4a50-a3be-8de066cf9c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954426020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3954426020
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.927152026
Short name T943
Test name
Test status
Simulation time 123262910 ps
CPU time 1.07 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:41 PM PDT 24
Peak memory 205696 kb
Host smart-106beca5-1f41-4c3f-be4f-641a02be8f28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927152026 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.927152026
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3572111498
Short name T153
Test name
Test status
Simulation time 89230582 ps
CPU time 1.44 seconds
Started Jul 26 07:09:42 PM PDT 24
Finished Jul 26 07:09:44 PM PDT 24
Peak memory 205716 kb
Host smart-0383aaa5-871d-4cb5-8bcc-102c15074d04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572111498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3572111498
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3883118551
Short name T998
Test name
Test status
Simulation time 20765003 ps
CPU time 0.72 seconds
Started Jul 26 07:09:41 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 205412 kb
Host smart-92570da0-433e-4966-b930-904fcba83fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883118551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3883118551
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2900833517
Short name T965
Test name
Test status
Simulation time 81977713 ps
CPU time 1.68 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:38 PM PDT 24
Peak memory 205628 kb
Host smart-f5e0e6c7-a5ad-48d3-94e6-4fd9ec2d7ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900833517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2900833517
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1078376218
Short name T1028
Test name
Test status
Simulation time 206781256 ps
CPU time 5.63 seconds
Started Jul 26 07:09:42 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 214188 kb
Host smart-9b936ad0-7d83-4c1e-9914-3e7d96569117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078376218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1078376218
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1098234129
Short name T930
Test name
Test status
Simulation time 691274504 ps
CPU time 7.16 seconds
Started Jul 26 07:09:36 PM PDT 24
Finished Jul 26 07:09:43 PM PDT 24
Peak memory 214180 kb
Host smart-90f8bb0f-2189-4fbf-aac4-fa1709479f10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098234129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1098234129
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1233517250
Short name T1018
Test name
Test status
Simulation time 3045513037 ps
CPU time 3.53 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 213948 kb
Host smart-c455140b-e487-47de-b7f6-51883b03cbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233517250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1233517250
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.291237177
Short name T176
Test name
Test status
Simulation time 451330109 ps
CPU time 6.28 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:43 PM PDT 24
Peak memory 213960 kb
Host smart-218b4f0e-3647-4620-b4b6-b4085ed4797a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291237177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.291237177
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.774525755
Short name T1070
Test name
Test status
Simulation time 191728638 ps
CPU time 1.2 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:39 PM PDT 24
Peak memory 205688 kb
Host smart-6156ed7c-96c9-4754-a23b-3b85d1a6b3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774525755 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.774525755
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2414898235
Short name T1009
Test name
Test status
Simulation time 44127576 ps
CPU time 1.14 seconds
Started Jul 26 07:09:45 PM PDT 24
Finished Jul 26 07:09:46 PM PDT 24
Peak memory 205684 kb
Host smart-25e7ac9e-2257-49f6-84f6-f162a6d8c4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414898235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2414898235
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.670779663
Short name T1049
Test name
Test status
Simulation time 13070924 ps
CPU time 0.67 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205452 kb
Host smart-e1eb13c4-ece0-425e-b209-81132cc9ce4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670779663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.670779663
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2336845253
Short name T1007
Test name
Test status
Simulation time 50346240 ps
CPU time 1.66 seconds
Started Jul 26 07:09:40 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 205688 kb
Host smart-f2ad1855-cc54-45a7-819a-3403645f544c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336845253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2336845253
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4195508938
Short name T999
Test name
Test status
Simulation time 196596020 ps
CPU time 2.46 seconds
Started Jul 26 07:09:44 PM PDT 24
Finished Jul 26 07:09:46 PM PDT 24
Peak memory 214056 kb
Host smart-2e9121ff-1c32-46f3-9bf4-7051500f1476
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195508938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4195508938
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.254026332
Short name T1026
Test name
Test status
Simulation time 386369042 ps
CPU time 8.15 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:46 PM PDT 24
Peak memory 214128 kb
Host smart-c1ba3bd7-73d8-4be6-b062-0692e7146828
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254026332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.254026332
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.109295743
Short name T979
Test name
Test status
Simulation time 123259555 ps
CPU time 2.16 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 213976 kb
Host smart-93ce3d34-f51b-4c51-8c0e-bb11770b931a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109295743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.109295743
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3749142098
Short name T1077
Test name
Test status
Simulation time 69480192 ps
CPU time 4.22 seconds
Started Jul 26 07:08:28 PM PDT 24
Finished Jul 26 07:08:33 PM PDT 24
Peak memory 205796 kb
Host smart-d73cf824-6cb9-4928-ae9e-aa12a66cefbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749142098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
749142098
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3702141029
Short name T962
Test name
Test status
Simulation time 859879819 ps
CPU time 11.61 seconds
Started Jul 26 07:08:29 PM PDT 24
Finished Jul 26 07:08:41 PM PDT 24
Peak memory 205720 kb
Host smart-65b1abe0-8b57-4999-b712-2b48f080fc98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702141029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
702141029
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1491480281
Short name T987
Test name
Test status
Simulation time 23432836 ps
CPU time 1.17 seconds
Started Jul 26 07:08:27 PM PDT 24
Finished Jul 26 07:08:29 PM PDT 24
Peak memory 205592 kb
Host smart-6265b41f-8ebe-4e7f-8089-44b66dffea65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491480281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
491480281
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.674496714
Short name T986
Test name
Test status
Simulation time 102103196 ps
CPU time 1.08 seconds
Started Jul 26 07:08:28 PM PDT 24
Finished Jul 26 07:08:30 PM PDT 24
Peak memory 205792 kb
Host smart-567eab11-6668-4dfd-b180-6ea01d0d6354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674496714 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.674496714
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2151308864
Short name T948
Test name
Test status
Simulation time 13409766 ps
CPU time 1.05 seconds
Started Jul 26 07:08:29 PM PDT 24
Finished Jul 26 07:08:30 PM PDT 24
Peak memory 205712 kb
Host smart-9996e7c9-5d8f-4761-a23b-d513442fbfc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151308864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2151308864
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3451484701
Short name T958
Test name
Test status
Simulation time 13029065 ps
CPU time 0.71 seconds
Started Jul 26 07:08:18 PM PDT 24
Finished Jul 26 07:08:19 PM PDT 24
Peak memory 205448 kb
Host smart-8004d6be-4258-450b-ad94-7694421abb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451484701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3451484701
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3501925121
Short name T974
Test name
Test status
Simulation time 100116991 ps
CPU time 1.53 seconds
Started Jul 26 07:08:29 PM PDT 24
Finished Jul 26 07:08:31 PM PDT 24
Peak memory 205620 kb
Host smart-95286b3f-6c0b-4551-8f11-84f97ca9e4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501925121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3501925121
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2253425094
Short name T997
Test name
Test status
Simulation time 168257702 ps
CPU time 4.86 seconds
Started Jul 26 07:08:26 PM PDT 24
Finished Jul 26 07:08:31 PM PDT 24
Peak memory 214120 kb
Host smart-3cdb7f3d-faa6-4241-9306-f3a65179fa58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253425094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2253425094
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2602000298
Short name T992
Test name
Test status
Simulation time 331441569 ps
CPU time 4.78 seconds
Started Jul 26 07:08:21 PM PDT 24
Finished Jul 26 07:08:26 PM PDT 24
Peak memory 214152 kb
Host smart-2c58df4c-8c6c-4021-b144-d18bea25ff4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602000298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2602000298
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1762791126
Short name T920
Test name
Test status
Simulation time 300732064 ps
CPU time 2.33 seconds
Started Jul 26 07:08:26 PM PDT 24
Finished Jul 26 07:08:29 PM PDT 24
Peak memory 215052 kb
Host smart-82852d49-a22c-4a9c-8402-7b05106a9338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762791126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1762791126
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2490754035
Short name T926
Test name
Test status
Simulation time 20054426 ps
CPU time 0.82 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205404 kb
Host smart-5b09b628-383e-4042-b7a6-6edcb7158942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490754035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2490754035
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.587728262
Short name T914
Test name
Test status
Simulation time 10947466 ps
CPU time 0.74 seconds
Started Jul 26 07:09:42 PM PDT 24
Finished Jul 26 07:09:43 PM PDT 24
Peak memory 205556 kb
Host smart-67771a9d-e4b4-47ff-9731-f17f6891d869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587728262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.587728262
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2947231729
Short name T989
Test name
Test status
Simulation time 54381137 ps
CPU time 0.78 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205484 kb
Host smart-01f1e956-e5d2-4385-913d-180da8866a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947231729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2947231729
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3477470196
Short name T963
Test name
Test status
Simulation time 9184939 ps
CPU time 0.87 seconds
Started Jul 26 07:09:42 PM PDT 24
Finished Jul 26 07:09:43 PM PDT 24
Peak memory 205476 kb
Host smart-d4e6a16a-2d62-4792-a421-f33dc74c7799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477470196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3477470196
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.338808244
Short name T931
Test name
Test status
Simulation time 8546488 ps
CPU time 0.82 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205328 kb
Host smart-3cb223ba-cc00-486f-afea-cc91aec95e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338808244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.338808244
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4071577121
Short name T1002
Test name
Test status
Simulation time 39784403 ps
CPU time 0.81 seconds
Started Jul 26 07:09:39 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205488 kb
Host smart-14d411d2-1474-4d7c-a189-139eeb99a7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071577121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4071577121
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3485187164
Short name T1042
Test name
Test status
Simulation time 35737773 ps
CPU time 0.73 seconds
Started Jul 26 07:09:40 PM PDT 24
Finished Jul 26 07:09:40 PM PDT 24
Peak memory 205420 kb
Host smart-ee4b12a1-c82a-4ead-855c-a1ed90187d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485187164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3485187164
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.912908423
Short name T922
Test name
Test status
Simulation time 8355808 ps
CPU time 0.7 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:38 PM PDT 24
Peak memory 205492 kb
Host smart-1edddb28-0e11-444b-ab22-4d6967969601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912908423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.912908423
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2668958935
Short name T983
Test name
Test status
Simulation time 41539064 ps
CPU time 0.73 seconds
Started Jul 26 07:09:41 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 205468 kb
Host smart-ef8bc841-b4f6-4c61-aa10-3b1bbd141b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668958935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2668958935
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.147947070
Short name T1000
Test name
Test status
Simulation time 8497458 ps
CPU time 0.82 seconds
Started Jul 26 07:09:41 PM PDT 24
Finished Jul 26 07:09:42 PM PDT 24
Peak memory 205420 kb
Host smart-cb9de1bb-c55c-4547-b144-0cac759993f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147947070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.147947070
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1488817041
Short name T1069
Test name
Test status
Simulation time 252628057 ps
CPU time 7.01 seconds
Started Jul 26 07:08:30 PM PDT 24
Finished Jul 26 07:08:37 PM PDT 24
Peak memory 205768 kb
Host smart-1cf511b4-e907-4109-a501-a1728e8f19e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488817041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
488817041
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2799155140
Short name T928
Test name
Test status
Simulation time 3539896406 ps
CPU time 17.78 seconds
Started Jul 26 07:08:32 PM PDT 24
Finished Jul 26 07:08:50 PM PDT 24
Peak memory 205848 kb
Host smart-83f639d6-1cbd-4d7a-9b17-ec6de0f03b2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799155140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
799155140
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1278048642
Short name T1076
Test name
Test status
Simulation time 31383673 ps
CPU time 1.1 seconds
Started Jul 26 07:08:27 PM PDT 24
Finished Jul 26 07:08:28 PM PDT 24
Peak memory 205748 kb
Host smart-39b43c2f-b310-41b7-8a5a-8707eb4215b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278048642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
278048642
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3141346464
Short name T1039
Test name
Test status
Simulation time 43165455 ps
CPU time 1.57 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:42 PM PDT 24
Peak memory 213996 kb
Host smart-b5fb6604-1aed-46cf-8c2f-fd01da82c37b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141346464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3141346464
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2840016095
Short name T1036
Test name
Test status
Simulation time 145203423 ps
CPU time 0.98 seconds
Started Jul 26 07:08:28 PM PDT 24
Finished Jul 26 07:08:29 PM PDT 24
Peak memory 205780 kb
Host smart-17713bd0-c410-4ea0-b81a-67befb9e56bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840016095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2840016095
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4033375875
Short name T971
Test name
Test status
Simulation time 9543757 ps
CPU time 0.7 seconds
Started Jul 26 07:08:28 PM PDT 24
Finished Jul 26 07:08:29 PM PDT 24
Peak memory 205484 kb
Host smart-e0f57c42-fa77-466e-8cd3-7dbe948e31ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033375875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4033375875
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2314334364
Short name T935
Test name
Test status
Simulation time 36576150 ps
CPU time 2.23 seconds
Started Jul 26 07:08:39 PM PDT 24
Finished Jul 26 07:08:42 PM PDT 24
Peak memory 205660 kb
Host smart-9d9dcfa8-712f-40fd-b5a7-e9b93c559f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314334364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2314334364
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1600720886
Short name T921
Test name
Test status
Simulation time 161495049 ps
CPU time 2.41 seconds
Started Jul 26 07:08:28 PM PDT 24
Finished Jul 26 07:08:31 PM PDT 24
Peak memory 214096 kb
Host smart-aef85cab-24b8-4e3c-bc3d-062a353b7fd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600720886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1600720886
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1861184671
Short name T1006
Test name
Test status
Simulation time 397005857 ps
CPU time 4.85 seconds
Started Jul 26 07:08:29 PM PDT 24
Finished Jul 26 07:08:34 PM PDT 24
Peak memory 220448 kb
Host smart-8c4b2440-7c4e-4fe1-92a1-3d56599147aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861184671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1861184671
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3654499108
Short name T200
Test name
Test status
Simulation time 259095159 ps
CPU time 2.88 seconds
Started Jul 26 07:08:30 PM PDT 24
Finished Jul 26 07:08:33 PM PDT 24
Peak memory 213856 kb
Host smart-67424273-0124-4ad9-94c7-3324091cc8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654499108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3654499108
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.403227766
Short name T173
Test name
Test status
Simulation time 248564579 ps
CPU time 5.24 seconds
Started Jul 26 07:08:29 PM PDT 24
Finished Jul 26 07:08:34 PM PDT 24
Peak memory 213860 kb
Host smart-954cd94b-fc0a-48ca-bed7-cb5deb54b243
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403227766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
403227766
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3244662868
Short name T1051
Test name
Test status
Simulation time 35334024 ps
CPU time 0.72 seconds
Started Jul 26 07:09:38 PM PDT 24
Finished Jul 26 07:09:39 PM PDT 24
Peak memory 205496 kb
Host smart-1b4f8ab6-efd9-41e4-ae13-d98ddd66edde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244662868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3244662868
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1447532893
Short name T923
Test name
Test status
Simulation time 123339293 ps
CPU time 0.72 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:38 PM PDT 24
Peak memory 205488 kb
Host smart-2ca669fb-819c-4e3d-956f-672327acaf21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447532893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1447532893
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3119708288
Short name T1071
Test name
Test status
Simulation time 31252813 ps
CPU time 0.72 seconds
Started Jul 26 07:09:42 PM PDT 24
Finished Jul 26 07:09:43 PM PDT 24
Peak memory 205468 kb
Host smart-b7b70a78-d09d-4a81-b644-7f91497d5fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119708288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3119708288
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3296127884
Short name T941
Test name
Test status
Simulation time 18791973 ps
CPU time 0.8 seconds
Started Jul 26 07:09:37 PM PDT 24
Finished Jul 26 07:09:38 PM PDT 24
Peak memory 205612 kb
Host smart-435e3b1d-7e61-4852-9346-9c78349de24c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296127884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3296127884
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2276826976
Short name T946
Test name
Test status
Simulation time 74584545 ps
CPU time 0.76 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205488 kb
Host smart-6814e71f-601a-4635-ab72-ced8b1e9b309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276826976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2276826976
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3432438650
Short name T988
Test name
Test status
Simulation time 10785210 ps
CPU time 0.71 seconds
Started Jul 26 07:09:48 PM PDT 24
Finished Jul 26 07:09:49 PM PDT 24
Peak memory 205416 kb
Host smart-ae937e8e-1f6f-44ff-8c5e-30065f4b4904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432438650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3432438650
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1352267587
Short name T978
Test name
Test status
Simulation time 59334343 ps
CPU time 0.84 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205464 kb
Host smart-34c43c4c-e1c2-435a-989b-8e9e3fa7c63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352267587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1352267587
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.621991174
Short name T942
Test name
Test status
Simulation time 16372701 ps
CPU time 0.69 seconds
Started Jul 26 07:09:46 PM PDT 24
Finished Jul 26 07:09:47 PM PDT 24
Peak memory 205492 kb
Host smart-32208829-dc26-4cad-957e-75c221e1206f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621991174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.621991174
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2867997539
Short name T917
Test name
Test status
Simulation time 68661915 ps
CPU time 0.83 seconds
Started Jul 26 07:09:49 PM PDT 24
Finished Jul 26 07:09:50 PM PDT 24
Peak memory 205408 kb
Host smart-386afb17-e4d8-40f4-85e4-f157147e4e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867997539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2867997539
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2979226740
Short name T1054
Test name
Test status
Simulation time 9501537 ps
CPU time 0.8 seconds
Started Jul 26 07:09:50 PM PDT 24
Finished Jul 26 07:09:51 PM PDT 24
Peak memory 205408 kb
Host smart-f2b2ed45-a0c7-48d4-ba36-30fcaedaf4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979226740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2979226740
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3017909994
Short name T973
Test name
Test status
Simulation time 200185462 ps
CPU time 7.24 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:47 PM PDT 24
Peak memory 205600 kb
Host smart-bfc7fb79-31f1-4127-a5f7-e5e8ed99b91e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017909994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
017909994
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1645296627
Short name T168
Test name
Test status
Simulation time 1529200412 ps
CPU time 32.01 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:09:12 PM PDT 24
Peak memory 205760 kb
Host smart-d240eadd-801b-4fe9-8d6e-f9d6cab9fdf5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645296627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
645296627
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1277269748
Short name T1034
Test name
Test status
Simulation time 40684468 ps
CPU time 0.97 seconds
Started Jul 26 07:08:39 PM PDT 24
Finished Jul 26 07:08:40 PM PDT 24
Peak memory 205708 kb
Host smart-ba5c5661-9d98-4de0-873e-989944391331
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277269748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
277269748
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3277267723
Short name T174
Test name
Test status
Simulation time 45232527 ps
CPU time 1.4 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:42 PM PDT 24
Peak memory 213900 kb
Host smart-0cdbf0ec-2ba4-4618-85f0-aa78e76771b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277267723 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3277267723
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1002248672
Short name T925
Test name
Test status
Simulation time 56296010 ps
CPU time 0.86 seconds
Started Jul 26 07:08:43 PM PDT 24
Finished Jul 26 07:08:44 PM PDT 24
Peak memory 205452 kb
Host smart-4a1051a9-10ec-408f-b968-6b1beb61f9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002248672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1002248672
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3520668552
Short name T945
Test name
Test status
Simulation time 11247323 ps
CPU time 0.71 seconds
Started Jul 26 07:08:39 PM PDT 24
Finished Jul 26 07:08:40 PM PDT 24
Peak memory 205420 kb
Host smart-720e8e45-f5b1-48fd-915b-0ace1b5ad4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520668552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3520668552
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1667258927
Short name T1048
Test name
Test status
Simulation time 140612487 ps
CPU time 2.03 seconds
Started Jul 26 07:08:39 PM PDT 24
Finished Jul 26 07:08:42 PM PDT 24
Peak memory 205616 kb
Host smart-82406360-0e91-4313-8f9a-8c3976164edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667258927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1667258927
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3360048785
Short name T1047
Test name
Test status
Simulation time 293192367 ps
CPU time 4.95 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:45 PM PDT 24
Peak memory 214184 kb
Host smart-85628fb7-7613-4591-b536-eb09368fb75f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360048785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3360048785
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3918026723
Short name T994
Test name
Test status
Simulation time 374888031 ps
CPU time 9.04 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:49 PM PDT 24
Peak memory 214240 kb
Host smart-5b9343ab-85d7-48cd-90c9-af8388b8b819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918026723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3918026723
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1944871806
Short name T1058
Test name
Test status
Simulation time 94783927 ps
CPU time 2.47 seconds
Started Jul 26 07:08:39 PM PDT 24
Finished Jul 26 07:08:41 PM PDT 24
Peak memory 213932 kb
Host smart-30cb3b12-5ca8-4042-9444-4fa8f583a578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944871806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1944871806
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3263454760
Short name T933
Test name
Test status
Simulation time 118204129 ps
CPU time 4.72 seconds
Started Jul 26 07:08:40 PM PDT 24
Finished Jul 26 07:08:45 PM PDT 24
Peak memory 213820 kb
Host smart-f486892e-26c3-4c80-ba4e-b881775df33e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263454760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3263454760
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4158527325
Short name T1044
Test name
Test status
Simulation time 63559026 ps
CPU time 0.69 seconds
Started Jul 26 07:09:46 PM PDT 24
Finished Jul 26 07:09:46 PM PDT 24
Peak memory 205376 kb
Host smart-c7866836-61e5-481b-b5f8-7ba21a2ef625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158527325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4158527325
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2984542293
Short name T1046
Test name
Test status
Simulation time 11485333 ps
CPU time 0.74 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205468 kb
Host smart-6bb6ef53-80fc-4970-a725-6ced7cb64e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984542293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2984542293
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1079933766
Short name T916
Test name
Test status
Simulation time 92685372 ps
CPU time 0.82 seconds
Started Jul 26 07:09:48 PM PDT 24
Finished Jul 26 07:09:49 PM PDT 24
Peak memory 205472 kb
Host smart-8087a244-84c6-4a6f-bd39-3c587f527878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079933766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1079933766
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1522025509
Short name T993
Test name
Test status
Simulation time 10941047 ps
CPU time 0.74 seconds
Started Jul 26 07:09:48 PM PDT 24
Finished Jul 26 07:09:49 PM PDT 24
Peak memory 205408 kb
Host smart-36bd54a4-f7d4-47a4-9988-11eeefc5d5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522025509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1522025509
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.758305233
Short name T937
Test name
Test status
Simulation time 33975923 ps
CPU time 0.73 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205460 kb
Host smart-5ab28db2-a0e0-493a-b920-5606a98dca06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758305233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.758305233
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.903230366
Short name T919
Test name
Test status
Simulation time 32418867 ps
CPU time 0.71 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205492 kb
Host smart-fe9fea94-c2aa-456c-b1f9-01bab987e511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903230366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.903230366
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2663213723
Short name T915
Test name
Test status
Simulation time 26002033 ps
CPU time 0.73 seconds
Started Jul 26 07:09:50 PM PDT 24
Finished Jul 26 07:09:50 PM PDT 24
Peak memory 205496 kb
Host smart-eb65cce4-dc36-43a3-b5df-8a654072b7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663213723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2663213723
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2373048887
Short name T1040
Test name
Test status
Simulation time 6747268 ps
CPU time 0.75 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205524 kb
Host smart-dd709637-8743-44b8-9fdd-83a10e062ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373048887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2373048887
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.93292503
Short name T1016
Test name
Test status
Simulation time 95347517 ps
CPU time 0.69 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205472 kb
Host smart-d34e609e-389e-46f7-a38a-2fa4217b002a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93292503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.93292503
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2867895487
Short name T1050
Test name
Test status
Simulation time 14154193 ps
CPU time 0.73 seconds
Started Jul 26 07:09:47 PM PDT 24
Finished Jul 26 07:09:48 PM PDT 24
Peak memory 205444 kb
Host smart-19242d62-10d8-4819-a6e1-89846fc6d0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867895487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2867895487
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2026792067
Short name T1053
Test name
Test status
Simulation time 47045931 ps
CPU time 1.98 seconds
Started Jul 26 07:08:50 PM PDT 24
Finished Jul 26 07:08:52 PM PDT 24
Peak memory 213996 kb
Host smart-73567bde-65f5-4fee-883d-daacbf202bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026792067 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2026792067
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2715217564
Short name T1081
Test name
Test status
Simulation time 45756501 ps
CPU time 1.31 seconds
Started Jul 26 07:08:52 PM PDT 24
Finished Jul 26 07:08:53 PM PDT 24
Peak memory 205644 kb
Host smart-f71130ed-ad30-4b54-a36f-cc2c1e2f73a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715217564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2715217564
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3602105200
Short name T1080
Test name
Test status
Simulation time 26308697 ps
CPU time 0.75 seconds
Started Jul 26 07:08:52 PM PDT 24
Finished Jul 26 07:08:53 PM PDT 24
Peak memory 205488 kb
Host smart-9a3e11bf-b2ee-4435-80fe-1defca55ab7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602105200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3602105200
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3911086008
Short name T159
Test name
Test status
Simulation time 1442026314 ps
CPU time 4.16 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:57 PM PDT 24
Peak memory 205664 kb
Host smart-53fd3c9a-9624-401c-a242-c509bd78bec3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911086008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3911086008
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.48773869
Short name T1023
Test name
Test status
Simulation time 406343184 ps
CPU time 2.02 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:55 PM PDT 24
Peak memory 214196 kb
Host smart-b318d548-b79a-4012-9e08-68fc47abdcde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48773869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.48773869
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1231767052
Short name T991
Test name
Test status
Simulation time 437526793 ps
CPU time 4.43 seconds
Started Jul 26 07:08:54 PM PDT 24
Finished Jul 26 07:08:59 PM PDT 24
Peak memory 214224 kb
Host smart-ead5b092-41d0-4683-aa35-ea62507d6c82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231767052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1231767052
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.836397275
Short name T969
Test name
Test status
Simulation time 50255967 ps
CPU time 2.95 seconds
Started Jul 26 07:08:50 PM PDT 24
Finished Jul 26 07:08:53 PM PDT 24
Peak memory 216340 kb
Host smart-9301d177-2a75-4690-8d15-3eaed048884f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836397275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.836397275
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3594373057
Short name T186
Test name
Test status
Simulation time 51603703 ps
CPU time 3.01 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:56 PM PDT 24
Peak memory 205984 kb
Host smart-ad9d3bae-632a-4598-b7bf-b0d107358928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594373057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3594373057
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2441380113
Short name T1032
Test name
Test status
Simulation time 101235043 ps
CPU time 1.93 seconds
Started Jul 26 07:08:52 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 214176 kb
Host smart-e3431dc9-d0cf-4524-b9ba-4a10cc825c58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441380113 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2441380113
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2571644243
Short name T957
Test name
Test status
Simulation time 11070047 ps
CPU time 0.94 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 205548 kb
Host smart-93ca6268-e9aa-479e-ac36-204bb8bd19d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571644243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2571644243
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.840219945
Short name T1013
Test name
Test status
Simulation time 30471536 ps
CPU time 0.88 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 205496 kb
Host smart-b6a57642-eef3-4dda-91c3-ac4b3ab12dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840219945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.840219945
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2729500780
Short name T1041
Test name
Test status
Simulation time 52692716 ps
CPU time 1.39 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:55 PM PDT 24
Peak memory 205684 kb
Host smart-85f2d6bf-09d5-4e10-9579-2899b52f1bed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729500780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2729500780
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3637242769
Short name T980
Test name
Test status
Simulation time 231793643 ps
CPU time 1.7 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 214224 kb
Host smart-752d368f-6fa9-4459-a8ab-bfa3ff4f8992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637242769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3637242769
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3110094844
Short name T985
Test name
Test status
Simulation time 115662484 ps
CPU time 4.33 seconds
Started Jul 26 07:08:53 PM PDT 24
Finished Jul 26 07:08:57 PM PDT 24
Peak memory 213832 kb
Host smart-a1161067-bcb4-4930-a80f-0114ad3ae9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110094844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3110094844
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1855637142
Short name T188
Test name
Test status
Simulation time 95853181 ps
CPU time 4.44 seconds
Started Jul 26 07:08:55 PM PDT 24
Finished Jul 26 07:09:00 PM PDT 24
Peak memory 213860 kb
Host smart-624c459e-724e-4bf5-af73-488d92ce516c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855637142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1855637142
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2369280702
Short name T944
Test name
Test status
Simulation time 23921234 ps
CPU time 1.14 seconds
Started Jul 26 07:09:02 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205764 kb
Host smart-682644d6-bdb5-40b7-a8bc-fbb05bebeacf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369280702 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2369280702
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1329695609
Short name T1066
Test name
Test status
Simulation time 28841838 ps
CPU time 1.6 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205748 kb
Host smart-9c37cb06-874c-4776-ac57-a5e67246c250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329695609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1329695609
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.312301719
Short name T990
Test name
Test status
Simulation time 48306633 ps
CPU time 0.81 seconds
Started Jul 26 07:09:04 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205484 kb
Host smart-8dbc92f5-f4de-4d25-a7b7-cd5991db05e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312301719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.312301719
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3142596307
Short name T984
Test name
Test status
Simulation time 159759925 ps
CPU time 2.51 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:06 PM PDT 24
Peak memory 205708 kb
Host smart-ed087c05-c762-49c8-8381-30b35212810f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142596307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3142596307
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3791062114
Short name T1072
Test name
Test status
Simulation time 85226655 ps
CPU time 1.48 seconds
Started Jul 26 07:08:55 PM PDT 24
Finished Jul 26 07:08:56 PM PDT 24
Peak memory 214204 kb
Host smart-b62bf189-ceff-4c4a-8017-57f0cf4be0cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791062114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3791062114
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4092575093
Short name T960
Test name
Test status
Simulation time 184327122 ps
CPU time 6.71 seconds
Started Jul 26 07:08:51 PM PDT 24
Finished Jul 26 07:08:57 PM PDT 24
Peak memory 220280 kb
Host smart-a809991c-ccdd-4727-82e7-401e4eabe819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092575093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.4092575093
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.64035350
Short name T975
Test name
Test status
Simulation time 97402576 ps
CPU time 1.74 seconds
Started Jul 26 07:08:52 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 213916 kb
Host smart-8f69d405-269f-40ab-89ae-7d2322644887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64035350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.64035350
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4227992459
Short name T970
Test name
Test status
Simulation time 71971238 ps
CPU time 1.56 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:05 PM PDT 24
Peak memory 214040 kb
Host smart-2cdc6068-ba2d-4420-a3c8-a241d4a75913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227992459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4227992459
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3658795437
Short name T959
Test name
Test status
Simulation time 16788374 ps
CPU time 0.97 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205540 kb
Host smart-d283da09-8f1c-416e-952a-ba5a228d162c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658795437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3658795437
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1807680463
Short name T1020
Test name
Test status
Simulation time 62645492 ps
CPU time 0.79 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205484 kb
Host smart-fa2c5a17-ad47-4cc3-ad42-dd4bac00872c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807680463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1807680463
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1585034594
Short name T1008
Test name
Test status
Simulation time 67427221 ps
CPU time 2.71 seconds
Started Jul 26 07:09:05 PM PDT 24
Finished Jul 26 07:09:07 PM PDT 24
Peak memory 205772 kb
Host smart-0a3a3304-2172-4698-8ce5-7b09f7d39ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585034594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1585034594
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1869761950
Short name T118
Test name
Test status
Simulation time 219610085 ps
CPU time 3.56 seconds
Started Jul 26 07:09:04 PM PDT 24
Finished Jul 26 07:09:07 PM PDT 24
Peak memory 214152 kb
Host smart-9005c338-7f9f-44bb-a9e4-cfa91a2d4ad5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869761950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1869761950
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.646921707
Short name T1067
Test name
Test status
Simulation time 2393490071 ps
CPU time 10.68 seconds
Started Jul 26 07:09:02 PM PDT 24
Finished Jul 26 07:09:13 PM PDT 24
Peak memory 221392 kb
Host smart-da8bc9a7-9e8e-4243-9cb6-51d611f6521b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646921707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.646921707
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1331700992
Short name T949
Test name
Test status
Simulation time 634028880 ps
CPU time 5.25 seconds
Started Jul 26 07:09:07 PM PDT 24
Finished Jul 26 07:09:12 PM PDT 24
Peak memory 213908 kb
Host smart-e5273fa5-d422-4d34-8895-671c73dbeefb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331700992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1331700992
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4202234904
Short name T384
Test name
Test status
Simulation time 438910152 ps
CPU time 4.14 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:07 PM PDT 24
Peak memory 214828 kb
Host smart-5ef078fa-8b8d-4e41-b55b-f3fd0bf04a72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202234904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4202234904
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2833413257
Short name T918
Test name
Test status
Simulation time 46028849 ps
CPU time 1.62 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 213996 kb
Host smart-d0455bc3-2fde-4c40-b355-b1d595003a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833413257 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2833413257
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1136776268
Short name T1031
Test name
Test status
Simulation time 91669732 ps
CPU time 1.08 seconds
Started Jul 26 07:09:05 PM PDT 24
Finished Jul 26 07:09:06 PM PDT 24
Peak memory 205696 kb
Host smart-770cc397-ff7d-42a5-9139-f888a43de9a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136776268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1136776268
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.903834914
Short name T1062
Test name
Test status
Simulation time 86401057 ps
CPU time 0.84 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 205496 kb
Host smart-1937d7f0-28eb-49f8-bac8-ed5a89b09e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903834914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.903834914
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3647922528
Short name T1043
Test name
Test status
Simulation time 213526203 ps
CPU time 2.55 seconds
Started Jul 26 07:09:07 PM PDT 24
Finished Jul 26 07:09:09 PM PDT 24
Peak memory 205796 kb
Host smart-983044de-a551-416c-8977-663e1f9a7fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647922528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3647922528
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1372372658
Short name T114
Test name
Test status
Simulation time 176482475 ps
CPU time 3.33 seconds
Started Jul 26 07:09:03 PM PDT 24
Finished Jul 26 07:09:06 PM PDT 24
Peak memory 214136 kb
Host smart-77f72c26-bc6f-4e00-b156-2d8411e1d58b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372372658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1372372658
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4076289309
Short name T1055
Test name
Test status
Simulation time 279170064 ps
CPU time 7.13 seconds
Started Jul 26 07:09:05 PM PDT 24
Finished Jul 26 07:09:12 PM PDT 24
Peak memory 214164 kb
Host smart-996c7969-c852-4e6d-a840-ded273b011ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076289309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4076289309
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3840948678
Short name T1017
Test name
Test status
Simulation time 64917756 ps
CPU time 1.6 seconds
Started Jul 26 07:09:07 PM PDT 24
Finished Jul 26 07:09:08 PM PDT 24
Peak memory 205752 kb
Host smart-af5d81ab-482b-496c-9c52-bb109a748f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840948678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3840948678
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1869685587
Short name T705
Test name
Test status
Simulation time 71602614 ps
CPU time 0.84 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:00 PM PDT 24
Peak memory 205876 kb
Host smart-51856dfe-d0c4-40a5-9f7b-3eed4e128ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869685587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1869685587
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3061259284
Short name T391
Test name
Test status
Simulation time 196307159 ps
CPU time 2.66 seconds
Started Jul 26 07:20:48 PM PDT 24
Finished Jul 26 07:20:50 PM PDT 24
Peak memory 214200 kb
Host smart-f14be929-69c9-465a-b6ca-dac16eb0c5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061259284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3061259284
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2904863034
Short name T634
Test name
Test status
Simulation time 113048493 ps
CPU time 3.74 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 222528 kb
Host smart-022236a4-11ef-408a-812a-71314469cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904863034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2904863034
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.321588270
Short name T199
Test name
Test status
Simulation time 237034786 ps
CPU time 5.58 seconds
Started Jul 26 07:20:48 PM PDT 24
Finished Jul 26 07:20:53 PM PDT 24
Peak memory 207892 kb
Host smart-f30e7eed-0ed4-4a30-bcdc-f891ee1457d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321588270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.321588270
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1064781193
Short name T262
Test name
Test status
Simulation time 156110992 ps
CPU time 4.34 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:04 PM PDT 24
Peak memory 214168 kb
Host smart-7a688a9f-f232-45e4-87e5-a9f6d9a5d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064781193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1064781193
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.255138189
Short name T134
Test name
Test status
Simulation time 1208732147 ps
CPU time 16.33 seconds
Started Jul 26 07:20:48 PM PDT 24
Finished Jul 26 07:21:05 PM PDT 24
Peak memory 222368 kb
Host smart-046ab031-30fe-4cd2-b305-c33886742c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255138189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.255138189
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.549837093
Short name T898
Test name
Test status
Simulation time 179381879 ps
CPU time 3.08 seconds
Started Jul 26 07:20:49 PM PDT 24
Finished Jul 26 07:20:53 PM PDT 24
Peak memory 222288 kb
Host smart-d9f0ac84-660a-4dc0-a699-11c6d4881e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549837093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.549837093
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3083981807
Short name T738
Test name
Test status
Simulation time 293136598 ps
CPU time 5.86 seconds
Started Jul 26 07:20:49 PM PDT 24
Finished Jul 26 07:20:55 PM PDT 24
Peak memory 207860 kb
Host smart-1366e7af-c4a0-4c1a-8d62-52f5e30d34b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083981807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3083981807
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3488790855
Short name T348
Test name
Test status
Simulation time 84096297 ps
CPU time 3.88 seconds
Started Jul 26 07:20:47 PM PDT 24
Finished Jul 26 07:20:51 PM PDT 24
Peak memory 208552 kb
Host smart-f13dfd3f-faee-477c-a1fe-55648c15e2e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488790855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3488790855
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1937902291
Short name T280
Test name
Test status
Simulation time 1142776123 ps
CPU time 32.28 seconds
Started Jul 26 07:20:50 PM PDT 24
Finished Jul 26 07:21:22 PM PDT 24
Peak memory 207768 kb
Host smart-38761c70-f376-4c11-a881-aab2b5880ea4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937902291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1937902291
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2246735464
Short name T715
Test name
Test status
Simulation time 90602963 ps
CPU time 2.8 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:02 PM PDT 24
Peak memory 214184 kb
Host smart-e4db990d-588e-46b8-9b62-885b8f6321ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246735464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2246735464
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3382738033
Short name T562
Test name
Test status
Simulation time 134611317 ps
CPU time 2.64 seconds
Started Jul 26 07:20:48 PM PDT 24
Finished Jul 26 07:20:50 PM PDT 24
Peak memory 206692 kb
Host smart-82e0be88-25d1-4198-a340-48cf05ef39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382738033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3382738033
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.768374671
Short name T863
Test name
Test status
Simulation time 10683233520 ps
CPU time 33.77 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:33 PM PDT 24
Peak memory 218484 kb
Host smart-10388852-97ec-4bcb-baa5-e2cec894d58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768374671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.768374671
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.790174488
Short name T570
Test name
Test status
Simulation time 395897696 ps
CPU time 10.99 seconds
Started Jul 26 07:21:01 PM PDT 24
Finished Jul 26 07:21:12 PM PDT 24
Peak memory 220168 kb
Host smart-9a791783-2d71-4c35-9e78-377657efe726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790174488 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.790174488
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2682895380
Short name T549
Test name
Test status
Simulation time 1267924894 ps
CPU time 4.55 seconds
Started Jul 26 07:20:47 PM PDT 24
Finished Jul 26 07:20:52 PM PDT 24
Peak memory 207492 kb
Host smart-cedcdc7c-3b37-4108-a76f-f077f6271c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682895380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2682895380
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3960442245
Short name T677
Test name
Test status
Simulation time 87725018 ps
CPU time 3.76 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 210112 kb
Host smart-a8aea7da-bb14-4c13-8164-16f99ad5a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960442245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3960442245
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.859302051
Short name T853
Test name
Test status
Simulation time 11787935 ps
CPU time 0.73 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:13 PM PDT 24
Peak memory 205936 kb
Host smart-0d03b47c-89c2-4b75-8f77-ee07a16f7309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859302051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.859302051
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.395433267
Short name T601
Test name
Test status
Simulation time 493887442 ps
CPU time 5.68 seconds
Started Jul 26 07:21:01 PM PDT 24
Finished Jul 26 07:21:07 PM PDT 24
Peak memory 214024 kb
Host smart-7700a5bc-a948-4dd2-9fd8-b2db01a89e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395433267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.395433267
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3704281567
Short name T59
Test name
Test status
Simulation time 31125666 ps
CPU time 2.4 seconds
Started Jul 26 07:21:01 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 207180 kb
Host smart-38ee65af-fd86-4771-aa11-5a501f0715ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704281567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3704281567
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1135539488
Short name T92
Test name
Test status
Simulation time 597711107 ps
CPU time 10.36 seconds
Started Jul 26 07:20:58 PM PDT 24
Finished Jul 26 07:21:08 PM PDT 24
Peak memory 222276 kb
Host smart-61588608-ce0b-4353-a730-76f874ba84af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135539488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1135539488
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1160552296
Short name T902
Test name
Test status
Simulation time 30264897 ps
CPU time 2.36 seconds
Started Jul 26 07:20:58 PM PDT 24
Finished Jul 26 07:21:00 PM PDT 24
Peak memory 209372 kb
Host smart-389cc7fc-a8c1-4ca0-8660-906ebd2e19f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160552296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1160552296
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3400451091
Short name T659
Test name
Test status
Simulation time 231963441 ps
CPU time 4.85 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:04 PM PDT 24
Peak memory 207336 kb
Host smart-f3c60e13-52a7-4157-8ef8-a998819e7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400451091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3400451091
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2048177370
Short name T42
Test name
Test status
Simulation time 1482972928 ps
CPU time 9.65 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:22 PM PDT 24
Peak memory 237992 kb
Host smart-53f62055-080a-4d65-8bd4-b750aee2c695
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048177370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2048177370
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4102891482
Short name T780
Test name
Test status
Simulation time 787465978 ps
CPU time 4.28 seconds
Started Jul 26 07:21:00 PM PDT 24
Finished Jul 26 07:21:04 PM PDT 24
Peak memory 208240 kb
Host smart-2acf746f-392f-4bd8-aeba-4e6cd04a5de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102891482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4102891482
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2827863651
Short name T667
Test name
Test status
Simulation time 220912961 ps
CPU time 2.67 seconds
Started Jul 26 07:21:01 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 206652 kb
Host smart-7caf359f-8835-462a-b640-9c99f0b94c87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827863651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2827863651
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1758452160
Short name T589
Test name
Test status
Simulation time 215903366 ps
CPU time 5.39 seconds
Started Jul 26 07:20:58 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 208264 kb
Host smart-e71990b2-a809-4a5c-9430-88521d139cbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758452160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1758452160
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1226949620
Short name T870
Test name
Test status
Simulation time 113357816 ps
CPU time 4.39 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 207864 kb
Host smart-2d9ab8c1-8be7-40b0-b00f-55d26bff0bf9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226949620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1226949620
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4270989514
Short name T411
Test name
Test status
Simulation time 51402499 ps
CPU time 2.91 seconds
Started Jul 26 07:21:00 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 209124 kb
Host smart-43368764-49ad-4243-bf60-e55930eed246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270989514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4270989514
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3054157861
Short name T660
Test name
Test status
Simulation time 33788321 ps
CPU time 2.17 seconds
Started Jul 26 07:20:59 PM PDT 24
Finished Jul 26 07:21:01 PM PDT 24
Peak memory 207044 kb
Host smart-1919b7dc-b19d-467d-bbd9-df7b7024aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054157861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3054157861
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3455050021
Short name T522
Test name
Test status
Simulation time 204421040 ps
CPU time 0.79 seconds
Started Jul 26 07:22:16 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 205812 kb
Host smart-7e2184d2-9e64-4937-8bc3-b57676b88f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455050021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3455050021
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4257891256
Short name T418
Test name
Test status
Simulation time 36261190 ps
CPU time 2.99 seconds
Started Jul 26 07:21:59 PM PDT 24
Finished Jul 26 07:22:03 PM PDT 24
Peak memory 215468 kb
Host smart-f238c4bb-632f-48b9-a90e-eac3167cdeaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257891256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4257891256
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2453479753
Short name T27
Test name
Test status
Simulation time 367021566 ps
CPU time 4.47 seconds
Started Jul 26 07:22:11 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 214460 kb
Host smart-b7678863-30f4-41d5-a923-9177f20a4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453479753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2453479753
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4205457730
Short name T737
Test name
Test status
Simulation time 923888073 ps
CPU time 8.3 seconds
Started Jul 26 07:22:00 PM PDT 24
Finished Jul 26 07:22:08 PM PDT 24
Peak memory 208044 kb
Host smart-5ec0ec30-06b4-443f-8efc-96001a37e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205457730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4205457730
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1552648627
Short name T103
Test name
Test status
Simulation time 193222181 ps
CPU time 4.75 seconds
Started Jul 26 07:22:11 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 214112 kb
Host smart-b16d5a32-b737-47ab-9929-d87ff3bfdfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552648627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1552648627
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.869537265
Short name T766
Test name
Test status
Simulation time 591924843 ps
CPU time 4.4 seconds
Started Jul 26 07:22:10 PM PDT 24
Finished Jul 26 07:22:15 PM PDT 24
Peak memory 207176 kb
Host smart-00a45f1e-8818-4825-b9ab-477eba1341bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869537265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.869537265
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1801517185
Short name T331
Test name
Test status
Simulation time 108989054 ps
CPU time 4.67 seconds
Started Jul 26 07:22:02 PM PDT 24
Finished Jul 26 07:22:07 PM PDT 24
Peak memory 209424 kb
Host smart-5d03bec9-c21e-43e9-99c4-959d921de8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801517185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1801517185
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.595823023
Short name T719
Test name
Test status
Simulation time 125754331 ps
CPU time 3 seconds
Started Jul 26 07:21:59 PM PDT 24
Finished Jul 26 07:22:02 PM PDT 24
Peak memory 206712 kb
Host smart-2fe08b77-134e-4ebb-bb6b-ee4717256a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595823023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.595823023
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4139408006
Short name T466
Test name
Test status
Simulation time 29870380 ps
CPU time 2.25 seconds
Started Jul 26 07:22:00 PM PDT 24
Finished Jul 26 07:22:02 PM PDT 24
Peak memory 206856 kb
Host smart-ab13e67c-7429-4950-a45f-011d332b04b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139408006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4139408006
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3771323919
Short name T909
Test name
Test status
Simulation time 807192641 ps
CPU time 5.15 seconds
Started Jul 26 07:22:00 PM PDT 24
Finished Jul 26 07:22:05 PM PDT 24
Peak memory 208140 kb
Host smart-f7a03107-dac0-4aca-8360-6667c5b624b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771323919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3771323919
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.711816526
Short name T826
Test name
Test status
Simulation time 87425445 ps
CPU time 1.87 seconds
Started Jul 26 07:21:57 PM PDT 24
Finished Jul 26 07:21:59 PM PDT 24
Peak memory 206816 kb
Host smart-de6d797a-595a-4457-869b-53b4ee43c8c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711816526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.711816526
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.715500084
Short name T560
Test name
Test status
Simulation time 142037460 ps
CPU time 2.17 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:14 PM PDT 24
Peak memory 218084 kb
Host smart-6365842c-6c98-4c39-894b-bf299603ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715500084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.715500084
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1930965406
Short name T648
Test name
Test status
Simulation time 341858104 ps
CPU time 2.92 seconds
Started Jul 26 07:22:00 PM PDT 24
Finished Jul 26 07:22:03 PM PDT 24
Peak memory 206700 kb
Host smart-9233b3c5-e611-4770-8f06-475a06fcf421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930965406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1930965406
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1065964497
Short name T244
Test name
Test status
Simulation time 318404460 ps
CPU time 3.62 seconds
Started Jul 26 07:22:13 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 214100 kb
Host smart-09ff3307-7947-4d67-bbfa-3d230411aa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065964497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1065964497
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3177834671
Short name T485
Test name
Test status
Simulation time 114301427 ps
CPU time 2.45 seconds
Started Jul 26 07:22:10 PM PDT 24
Finished Jul 26 07:22:12 PM PDT 24
Peak memory 210084 kb
Host smart-fa8aeaa6-faa7-408b-9a7c-045016e09c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177834671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3177834671
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.133646452
Short name T797
Test name
Test status
Simulation time 11238140 ps
CPU time 0.7 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:26 PM PDT 24
Peak memory 205916 kb
Host smart-f46662f1-e47f-49e0-abc9-728d67d49209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133646452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.133646452
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.744135495
Short name T415
Test name
Test status
Simulation time 131989118 ps
CPU time 2.75 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:15 PM PDT 24
Peak memory 214140 kb
Host smart-99545acf-5259-4d48-801e-34f96e261745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744135495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.744135495
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3835602658
Short name T730
Test name
Test status
Simulation time 33252220 ps
CPU time 2.25 seconds
Started Jul 26 07:22:13 PM PDT 24
Finished Jul 26 07:22:15 PM PDT 24
Peak memory 207580 kb
Host smart-754e7686-a581-4c78-ab63-93d6b9178265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835602658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3835602658
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2192539976
Short name T292
Test name
Test status
Simulation time 129833938 ps
CPU time 2.86 seconds
Started Jul 26 07:22:14 PM PDT 24
Finished Jul 26 07:22:17 PM PDT 24
Peak memory 214140 kb
Host smart-bff3f14f-0a15-4156-9fb7-00885b1a49ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192539976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2192539976
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3879824016
Short name T581
Test name
Test status
Simulation time 128986983 ps
CPU time 2.6 seconds
Started Jul 26 07:22:11 PM PDT 24
Finished Jul 26 07:22:14 PM PDT 24
Peak memory 215428 kb
Host smart-47990870-c3a9-48d4-8ce5-53cb59adabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879824016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3879824016
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2784924418
Short name T507
Test name
Test status
Simulation time 101816364 ps
CPU time 1.53 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:14 PM PDT 24
Peak memory 205944 kb
Host smart-cbb63841-d960-4547-952e-bd27f451071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784924418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2784924418
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3235462471
Short name T714
Test name
Test status
Simulation time 128824483 ps
CPU time 5.98 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:18 PM PDT 24
Peak memory 209860 kb
Host smart-859f976c-8eb2-4003-9368-1aaf9db0087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235462471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3235462471
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.275704631
Short name T508
Test name
Test status
Simulation time 480634767 ps
CPU time 2.92 seconds
Started Jul 26 07:22:13 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 208524 kb
Host smart-9fc8cd56-ff87-453c-8034-9ef0bc72aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275704631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.275704631
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1984319597
Short name T464
Test name
Test status
Simulation time 189322702 ps
CPU time 3.4 seconds
Started Jul 26 07:22:21 PM PDT 24
Finished Jul 26 07:22:25 PM PDT 24
Peak memory 206804 kb
Host smart-5ec59edf-4e6f-43ed-9a3f-b3227ecb61b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984319597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1984319597
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3782776325
Short name T873
Test name
Test status
Simulation time 145604343 ps
CPU time 4.1 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 207928 kb
Host smart-8ed93183-1ea8-482a-933f-308fb4e3cf9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782776325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3782776325
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2139755546
Short name T795
Test name
Test status
Simulation time 148076751 ps
CPU time 3.63 seconds
Started Jul 26 07:22:13 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 208820 kb
Host smart-31336169-6d2c-415c-996d-87c44433467c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139755546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2139755546
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2589643756
Short name T500
Test name
Test status
Simulation time 242035111 ps
CPU time 4.02 seconds
Started Jul 26 07:22:12 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 215948 kb
Host smart-88499a8b-cdac-4abd-a699-a938018c7e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589643756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2589643756
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.389740103
Short name T646
Test name
Test status
Simulation time 3074628621 ps
CPU time 6.56 seconds
Started Jul 26 07:22:10 PM PDT 24
Finished Jul 26 07:22:17 PM PDT 24
Peak memory 206752 kb
Host smart-b5baf555-2e5e-47f1-af04-762024fb8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389740103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.389740103
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3311088657
Short name T128
Test name
Test status
Simulation time 106225638 ps
CPU time 6.51 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 219228 kb
Host smart-89023ad3-e42b-4fa4-9d16-448baea87b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311088657 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3311088657
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1714694043
Short name T543
Test name
Test status
Simulation time 539184132 ps
CPU time 16.95 seconds
Started Jul 26 07:22:21 PM PDT 24
Finished Jul 26 07:22:38 PM PDT 24
Peak memory 218200 kb
Host smart-f3ae506d-cd78-42ee-9eca-550860823422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714694043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1714694043
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.73088665
Short name T683
Test name
Test status
Simulation time 532225835 ps
CPU time 2.68 seconds
Started Jul 26 07:22:13 PM PDT 24
Finished Jul 26 07:22:16 PM PDT 24
Peak memory 209936 kb
Host smart-a80e5d0d-e597-4dab-a884-eb602df129fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73088665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.73088665
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3978457657
Short name T141
Test name
Test status
Simulation time 12129049 ps
CPU time 0.83 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 205816 kb
Host smart-417738c4-c3e7-4c6d-ac2a-6c4b67ab59c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978457657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3978457657
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1367315248
Short name T420
Test name
Test status
Simulation time 170715259 ps
CPU time 2.41 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 214136 kb
Host smart-d5c5efb8-394b-4313-a520-ff53ea283533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367315248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1367315248
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3840671437
Short name T807
Test name
Test status
Simulation time 382214425 ps
CPU time 4.22 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 214164 kb
Host smart-71facb4b-0446-4eca-a8ed-e9d30174f88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840671437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3840671437
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_random.2189190555
Short name T844
Test name
Test status
Simulation time 1102553497 ps
CPU time 10.87 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:37 PM PDT 24
Peak memory 207908 kb
Host smart-132c7ed4-11c6-439c-aa7e-844ff05f4c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189190555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2189190555
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.104289443
Short name T894
Test name
Test status
Simulation time 1090976643 ps
CPU time 37 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 208192 kb
Host smart-ab1df2c5-c900-4a92-975f-480eebc6a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104289443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.104289443
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2002166170
Short name T354
Test name
Test status
Simulation time 175828259 ps
CPU time 4.86 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 208684 kb
Host smart-0d6c194e-7766-4165-b569-82b88864b67d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002166170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2002166170
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3224439033
Short name T138
Test name
Test status
Simulation time 935443990 ps
CPU time 2.85 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 206644 kb
Host smart-921c3525-f08a-4af7-a046-2daf5c9603ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224439033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3224439033
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1184463140
Short name T528
Test name
Test status
Simulation time 380475497 ps
CPU time 2.85 seconds
Started Jul 26 07:22:27 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 206844 kb
Host smart-b16206dc-33cb-4bcb-bbb7-acf6328990bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184463140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1184463140
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.779856947
Short name T3
Test name
Test status
Simulation time 4080964749 ps
CPU time 16.33 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 209116 kb
Host smart-91b3ab9f-1df9-43b6-96c2-7fcdd1330d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779856947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.779856947
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2100858942
Short name T399
Test name
Test status
Simulation time 564646454 ps
CPU time 4.12 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:31 PM PDT 24
Peak memory 208324 kb
Host smart-27c3eb58-5718-43ae-8868-d4457d6b55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100858942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2100858942
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3183848755
Short name T761
Test name
Test status
Simulation time 526605469 ps
CPU time 19.64 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:44 PM PDT 24
Peak memory 222320 kb
Host smart-e20fa3e6-0664-4257-b99f-be7105a85552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183848755 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3183848755
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3684363513
Short name T582
Test name
Test status
Simulation time 875499390 ps
CPU time 7.93 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 207836 kb
Host smart-43ba2f16-a0da-4347-8ebf-2a3d014f34c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684363513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3684363513
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1482988818
Short name T41
Test name
Test status
Simulation time 208592661 ps
CPU time 2.5 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 209920 kb
Host smart-3bb9c1e6-f7a5-449a-966e-9688a9d702ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482988818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1482988818
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.916819779
Short name T556
Test name
Test status
Simulation time 20449944 ps
CPU time 0.71 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:26 PM PDT 24
Peak memory 205884 kb
Host smart-86621a10-6449-4e69-a49f-619a35eb47ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916819779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.916819779
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4285413622
Short name T416
Test name
Test status
Simulation time 281023166 ps
CPU time 2.64 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 214132 kb
Host smart-e45a563c-03e8-4f5f-9818-66d15473930b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285413622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4285413622
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3862581223
Short name T32
Test name
Test status
Simulation time 50058747 ps
CPU time 2.6 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 222548 kb
Host smart-cd0a1bef-e0d7-477d-b668-4a528f5a5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862581223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3862581223
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1782345918
Short name T519
Test name
Test status
Simulation time 119237467 ps
CPU time 2.84 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 208824 kb
Host smart-577ad5b9-cd28-4d2b-97b9-bf951d2ba7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782345918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1782345918
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3337062036
Short name T101
Test name
Test status
Simulation time 306601185 ps
CPU time 5.48 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:31 PM PDT 24
Peak memory 214156 kb
Host smart-292faa25-1653-407a-850e-4a46d9d6038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337062036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3337062036
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3375262636
Short name T364
Test name
Test status
Simulation time 114424667 ps
CPU time 2.32 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 215188 kb
Host smart-1f162c17-cf34-4cee-b627-cecba6deddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375262636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3375262636
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3047179368
Short name T325
Test name
Test status
Simulation time 42828938 ps
CPU time 2.99 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 219976 kb
Host smart-1894aae3-b712-4a06-b42d-bd5fe5afffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047179368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3047179368
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2185813410
Short name T84
Test name
Test status
Simulation time 137927784 ps
CPU time 5.79 seconds
Started Jul 26 07:22:23 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 207928 kb
Host smart-bd35a98a-f31b-4ef1-b2ce-6b1b5f9a9df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185813410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2185813410
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.725223035
Short name T812
Test name
Test status
Simulation time 333901249 ps
CPU time 6.35 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 208356 kb
Host smart-f179573d-bc53-4bbc-8587-f1b14ecae9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725223035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.725223035
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3738953663
Short name T590
Test name
Test status
Simulation time 69922165 ps
CPU time 3.13 seconds
Started Jul 26 07:22:24 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 207120 kb
Host smart-8cafe8ad-7788-4965-b42c-7897eb80b22f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738953663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3738953663
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3972254869
Short name T13
Test name
Test status
Simulation time 22757107 ps
CPU time 1.83 seconds
Started Jul 26 07:22:27 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 207272 kb
Host smart-d14658b1-ca87-4eb7-8575-02d5718c1971
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972254869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3972254869
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2850028155
Short name T703
Test name
Test status
Simulation time 45620543 ps
CPU time 2.33 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 206476 kb
Host smart-dbb695d1-7557-405e-9998-b75ed91457b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850028155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2850028155
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3748527707
Short name T243
Test name
Test status
Simulation time 52670266 ps
CPU time 2.06 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 207580 kb
Host smart-599481f8-f79f-4443-a539-0ad96025852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748527707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3748527707
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.276304420
Short name T629
Test name
Test status
Simulation time 85255687 ps
CPU time 2.63 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 206648 kb
Host smart-d288d960-a5db-441c-a886-2aa948e3433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276304420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.276304420
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1906140968
Short name T122
Test name
Test status
Simulation time 595162118 ps
CPU time 19.49 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:45 PM PDT 24
Peak memory 222412 kb
Host smart-5298ebd3-b7c2-43f4-b3ad-a170c8616ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906140968 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1906140968
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.560097639
Short name T593
Test name
Test status
Simulation time 31633920 ps
CPU time 2.25 seconds
Started Jul 26 07:22:27 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 207340 kb
Host smart-e04a0e28-ad89-4670-ab5b-73ea09d5c658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560097639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.560097639
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4150568607
Short name T588
Test name
Test status
Simulation time 364438079 ps
CPU time 2.71 seconds
Started Jul 26 07:22:25 PM PDT 24
Finished Jul 26 07:22:28 PM PDT 24
Peak memory 209704 kb
Host smart-21123d13-ef3d-40d4-ab3e-fddfae4fdada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150568607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4150568607
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2068747497
Short name T584
Test name
Test status
Simulation time 24529252 ps
CPU time 0.78 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:27 PM PDT 24
Peak memory 205840 kb
Host smart-3de1186b-5c8c-4138-b8c5-1b810ddbd91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068747497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2068747497
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4046572692
Short name T610
Test name
Test status
Simulation time 190399527 ps
CPU time 2.82 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 207584 kb
Host smart-613e58ac-d761-4adb-b661-4635df3bbb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046572692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4046572692
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1054397836
Short name T272
Test name
Test status
Simulation time 785245609 ps
CPU time 5.35 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:34 PM PDT 24
Peak memory 213936 kb
Host smart-13d08986-1cca-4d32-9cd1-d620cc0886cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054397836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1054397836
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1792578984
Short name T235
Test name
Test status
Simulation time 358708834 ps
CPU time 4.66 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:33 PM PDT 24
Peak memory 209572 kb
Host smart-d2da8dc0-154b-4b96-930b-b489c9e0adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792578984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1792578984
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2675751364
Short name T568
Test name
Test status
Simulation time 266358793 ps
CPU time 2.45 seconds
Started Jul 26 07:22:27 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 219920 kb
Host smart-37e989db-1230-4088-8c92-27220e7571e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675751364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2675751364
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1504770134
Short name T266
Test name
Test status
Simulation time 933890642 ps
CPU time 24.95 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 218356 kb
Host smart-1c8e4611-58ef-43a1-8869-bb71f1efcd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504770134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1504770134
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1191682018
Short name T326
Test name
Test status
Simulation time 434821084 ps
CPU time 2.6 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 206680 kb
Host smart-47da188d-4de3-471d-b5a1-8e7efddb47bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191682018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1191682018
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.346892797
Short name T550
Test name
Test status
Simulation time 154472704 ps
CPU time 5.98 seconds
Started Jul 26 07:22:30 PM PDT 24
Finished Jul 26 07:22:36 PM PDT 24
Peak memory 207876 kb
Host smart-72681145-346c-41cc-b7a4-12bd78a3d3ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346892797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.346892797
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2102781095
Short name T375
Test name
Test status
Simulation time 52177229 ps
CPU time 2.75 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 206720 kb
Host smart-f6a2206a-7ee9-4ad1-b2da-907d52cfe50b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102781095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2102781095
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2432240884
Short name T913
Test name
Test status
Simulation time 252645046 ps
CPU time 5.81 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:34 PM PDT 24
Peak memory 207816 kb
Host smart-ec276170-4521-4d36-be36-3ef304d07940
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432240884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2432240884
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2758844972
Short name T347
Test name
Test status
Simulation time 102596682 ps
CPU time 2.29 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:31 PM PDT 24
Peak memory 207876 kb
Host smart-8718b021-21b7-487c-925c-03dff64306cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758844972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2758844972
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1428098690
Short name T855
Test name
Test status
Simulation time 191061852 ps
CPU time 4 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:33 PM PDT 24
Peak memory 208452 kb
Host smart-e4260d41-f15d-42d1-bb5d-dfd649f09859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428098690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1428098690
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.404788408
Short name T215
Test name
Test status
Simulation time 1601868284 ps
CPU time 36.51 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:23:06 PM PDT 24
Peak memory 216608 kb
Host smart-be41d79c-2942-400e-a69d-53e3ded541ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404788408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.404788408
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.793732132
Short name T910
Test name
Test status
Simulation time 238212822 ps
CPU time 5.38 seconds
Started Jul 26 07:22:28 PM PDT 24
Finished Jul 26 07:22:34 PM PDT 24
Peak memory 207884 kb
Host smart-56c25a37-d499-4173-9724-7a9cf2f3de55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793732132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.793732132
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1152391371
Short name T865
Test name
Test status
Simulation time 272295692 ps
CPU time 3.01 seconds
Started Jul 26 07:22:31 PM PDT 24
Finished Jul 26 07:22:34 PM PDT 24
Peak memory 210336 kb
Host smart-7055325a-87e3-4d0e-a36d-868490d0301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152391371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1152391371
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3460415130
Short name T437
Test name
Test status
Simulation time 89920175 ps
CPU time 0.78 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 205872 kb
Host smart-b32f5418-ddef-463d-bbd1-0b411d081c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460415130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3460415130
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2305786623
Short name T64
Test name
Test status
Simulation time 285153409 ps
CPU time 2.75 seconds
Started Jul 26 07:22:27 PM PDT 24
Finished Jul 26 07:22:30 PM PDT 24
Peak memory 206864 kb
Host smart-93e40da1-009a-4f4d-81b5-80512076e5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305786623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2305786623
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.327322407
Short name T89
Test name
Test status
Simulation time 182041130 ps
CPU time 3.3 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 214208 kb
Host smart-b3f7fc41-38e5-4be2-b7bc-bd9c60c3900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327322407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.327322407
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3973810509
Short name T571
Test name
Test status
Simulation time 148449467 ps
CPU time 1.9 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 214108 kb
Host smart-1e7d0293-7a73-45f3-a172-29fe9f89f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973810509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3973810509
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3390551782
Short name T212
Test name
Test status
Simulation time 63698135 ps
CPU time 3.07 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 214128 kb
Host smart-a1278d30-8c41-4f4c-82b2-ffab8663da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390551782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3390551782
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.502336702
Short name T600
Test name
Test status
Simulation time 145336104 ps
CPU time 4.95 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:34 PM PDT 24
Peak memory 207400 kb
Host smart-82120769-3195-453e-9270-d3eccaf4576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502336702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.502336702
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1544489782
Short name T540
Test name
Test status
Simulation time 295759903 ps
CPU time 2.46 seconds
Started Jul 26 07:22:26 PM PDT 24
Finished Jul 26 07:22:29 PM PDT 24
Peak memory 206680 kb
Host smart-a86c2eaf-e049-4379-898a-2a78673ab5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544489782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1544489782
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4121527618
Short name T798
Test name
Test status
Simulation time 134310552 ps
CPU time 3.09 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 206564 kb
Host smart-a5e9cb71-3dc9-4317-a5ba-39ba75dc5795
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121527618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4121527618
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.496387874
Short name T16
Test name
Test status
Simulation time 74016488 ps
CPU time 3.69 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:33 PM PDT 24
Peak memory 208544 kb
Host smart-6c646216-6272-405a-b1a4-b9d960a3205f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496387874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.496387874
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1402416207
Short name T129
Test name
Test status
Simulation time 1059822552 ps
CPU time 17.63 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:23:00 PM PDT 24
Peak memory 209252 kb
Host smart-04b8e252-3cbd-42ac-8c85-e4de1edf17ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402416207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1402416207
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2948196865
Short name T661
Test name
Test status
Simulation time 173418851 ps
CPU time 2.3 seconds
Started Jul 26 07:22:29 PM PDT 24
Finished Jul 26 07:22:32 PM PDT 24
Peak memory 207776 kb
Host smart-dc0c9673-6e59-4ba2-b5b7-92d764614234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948196865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2948196865
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3172671244
Short name T44
Test name
Test status
Simulation time 15790783149 ps
CPU time 154.91 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 215104 kb
Host smart-509bc69b-a0fa-41ee-9b6f-2e1cb210749d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172671244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3172671244
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.173337780
Short name T69
Test name
Test status
Simulation time 1704229364 ps
CPU time 23.8 seconds
Started Jul 26 07:22:37 PM PDT 24
Finished Jul 26 07:23:01 PM PDT 24
Peak memory 221220 kb
Host smart-0536a461-45ab-4370-8260-6fd592134418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173337780 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.173337780
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3162985907
Short name T718
Test name
Test status
Simulation time 144754548 ps
CPU time 6.51 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:46 PM PDT 24
Peak memory 214148 kb
Host smart-7124f28e-4af9-4ad7-96ca-fc67eccadfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162985907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3162985907
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3962844801
Short name T187
Test name
Test status
Simulation time 256989644 ps
CPU time 2.43 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 209928 kb
Host smart-c88ee2d2-bbbe-44e7-a336-2580ba6ab4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962844801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3962844801
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.817069565
Short name T645
Test name
Test status
Simulation time 22619168 ps
CPU time 0.89 seconds
Started Jul 26 07:22:37 PM PDT 24
Finished Jul 26 07:22:38 PM PDT 24
Peak memory 205864 kb
Host smart-1a2f9af5-7475-4c76-85a0-eaa2db1e41d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817069565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.817069565
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.470185239
Short name T306
Test name
Test status
Simulation time 108523428 ps
CPU time 4.71 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:22:47 PM PDT 24
Peak memory 210552 kb
Host smart-b387b4a7-41e6-4985-84d8-b3b16473455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470185239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.470185239
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1902000797
Short name T341
Test name
Test status
Simulation time 114212012 ps
CPU time 4.97 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:44 PM PDT 24
Peak memory 209292 kb
Host smart-f6464a55-bc86-468d-8ced-dfa26efe24ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902000797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1902000797
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1721471519
Short name T265
Test name
Test status
Simulation time 98504129 ps
CPU time 3.17 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 214096 kb
Host smart-5cb3522e-6c03-468a-99c9-64175f61fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721471519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1721471519
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2222017568
Short name T65
Test name
Test status
Simulation time 55182782 ps
CPU time 3.58 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 208788 kb
Host smart-9e28a3d4-9fa5-4d2a-85e8-c08543d17d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222017568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2222017568
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3996904292
Short name T594
Test name
Test status
Simulation time 660785996 ps
CPU time 7.8 seconds
Started Jul 26 07:22:41 PM PDT 24
Finished Jul 26 07:22:49 PM PDT 24
Peak memory 217996 kb
Host smart-1c6b3dfc-9f80-4ce1-8f6e-ab6ba8a67f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996904292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3996904292
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2198116499
Short name T793
Test name
Test status
Simulation time 357277944 ps
CPU time 4.54 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 207752 kb
Host smart-4d22df97-3856-4219-b5a7-2bdedbebb459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198116499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2198116499
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.859156693
Short name T545
Test name
Test status
Simulation time 833324514 ps
CPU time 7.98 seconds
Started Jul 26 07:22:43 PM PDT 24
Finished Jul 26 07:22:51 PM PDT 24
Peak memory 208516 kb
Host smart-f9eb0827-4997-4c49-b5db-35609a267dc5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859156693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.859156693
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1176371508
Short name T746
Test name
Test status
Simulation time 385567357 ps
CPU time 2.75 seconds
Started Jul 26 07:22:41 PM PDT 24
Finished Jul 26 07:22:44 PM PDT 24
Peak memory 206700 kb
Host smart-83c9edb1-660d-40ec-8e3b-2c7637ca7dc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176371508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1176371508
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1932234669
Short name T521
Test name
Test status
Simulation time 627104441 ps
CPU time 6.84 seconds
Started Jul 26 07:22:37 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 208512 kb
Host smart-de7fce3b-3dfd-4602-be80-92626163d93f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932234669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1932234669
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1832132474
Short name T213
Test name
Test status
Simulation time 66816234 ps
CPU time 2.97 seconds
Started Jul 26 07:22:41 PM PDT 24
Finished Jul 26 07:22:45 PM PDT 24
Peak memory 208696 kb
Host smart-1e8bc9e1-27da-40c9-bf02-6fb843528cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832132474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1832132474
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2221907334
Short name T427
Test name
Test status
Simulation time 78095267 ps
CPU time 3.12 seconds
Started Jul 26 07:22:37 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 208304 kb
Host smart-4c5d47b4-4a64-4a56-aa45-5e53fc7c86b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221907334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2221907334
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1513630001
Short name T665
Test name
Test status
Simulation time 266548461 ps
CPU time 11 seconds
Started Jul 26 07:22:43 PM PDT 24
Finished Jul 26 07:22:54 PM PDT 24
Peak memory 222416 kb
Host smart-c6d0f643-6ef4-4d97-a6cb-d7d3d0bc1bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513630001 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1513630001
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2885514827
Short name T799
Test name
Test status
Simulation time 78422880 ps
CPU time 2.91 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 214116 kb
Host smart-525e7ad5-b60e-4050-a972-17241adf831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885514827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2885514827
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.71165539
Short name T509
Test name
Test status
Simulation time 63091983 ps
CPU time 2.32 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 209688 kb
Host smart-f937d63f-f0f4-439f-9e09-c0e74719ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71165539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.71165539
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2743193402
Short name T864
Test name
Test status
Simulation time 10600984 ps
CPU time 0.73 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:40 PM PDT 24
Peak memory 205856 kb
Host smart-0001d772-a46f-4859-8008-749727f254d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743193402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2743193402
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.596815221
Short name T412
Test name
Test status
Simulation time 205677255 ps
CPU time 4.09 seconds
Started Jul 26 07:22:41 PM PDT 24
Finished Jul 26 07:22:45 PM PDT 24
Peak memory 214116 kb
Host smart-0c59d437-f0c2-4750-bb3d-b54b4976abb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596815221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.596815221
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4254822642
Short name T40
Test name
Test status
Simulation time 105330946 ps
CPU time 4.31 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 214096 kb
Host smart-b0aa397b-44e9-4375-9077-0da3af70e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254822642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4254822642
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1720865151
Short name T309
Test name
Test status
Simulation time 28768873 ps
CPU time 2.03 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:22:45 PM PDT 24
Peak memory 209848 kb
Host smart-739e49f3-8b0c-47d2-8aa2-3637960cd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720865151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1720865151
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1262044235
Short name T304
Test name
Test status
Simulation time 88894531 ps
CPU time 3.36 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 222244 kb
Host smart-24be4775-5e5e-46db-b68f-0bf256b4a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262044235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1262044235
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.1252073633
Short name T255
Test name
Test status
Simulation time 1528312065 ps
CPU time 39.69 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:23:20 PM PDT 24
Peak memory 219612 kb
Host smart-6fad9fe2-e5b6-4452-be50-6402cf96477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252073633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1252073633
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1868594568
Short name T693
Test name
Test status
Simulation time 25696174 ps
CPU time 1.83 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 206664 kb
Host smart-a8fe6c49-8daf-4d19-a9f9-b78dde1492d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868594568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1868594568
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1088179631
Short name T684
Test name
Test status
Simulation time 631079078 ps
CPU time 4.44 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 207832 kb
Host smart-8eb4767f-bbf8-4705-9726-26d3617bda7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088179631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1088179631
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.54580117
Short name T552
Test name
Test status
Simulation time 155073806 ps
CPU time 3.06 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 206680 kb
Host smart-e76e9ef3-49af-4789-ae47-1fc00ded3ace
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54580117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.54580117
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.202446123
Short name T755
Test name
Test status
Simulation time 203829142 ps
CPU time 5.22 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:43 PM PDT 24
Peak memory 207908 kb
Host smart-c449b2da-1dcb-406b-987c-9e294b492776
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202446123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.202446123
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2535890138
Short name T860
Test name
Test status
Simulation time 81685092 ps
CPU time 2.19 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 207740 kb
Host smart-252f5063-2bfb-4263-8806-6fa18c7ea482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535890138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2535890138
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2217309808
Short name T664
Test name
Test status
Simulation time 127181091 ps
CPU time 4.22 seconds
Started Jul 26 07:22:37 PM PDT 24
Finished Jul 26 07:22:41 PM PDT 24
Peak memory 208404 kb
Host smart-d481ba52-d66b-4cb8-9ca0-2b699d69ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217309808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2217309808
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3721318321
Short name T886
Test name
Test status
Simulation time 4957371008 ps
CPU time 9.47 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 219972 kb
Host smart-298eeb62-377f-474e-b830-5bff9fd6316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721318321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3721318321
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2694635816
Short name T657
Test name
Test status
Simulation time 38276485 ps
CPU time 0.81 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:50 PM PDT 24
Peak memory 205912 kb
Host smart-8ddb1fbc-fd98-4b84-b059-36b37192ee42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694635816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2694635816
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1335068529
Short name T467
Test name
Test status
Simulation time 158936216 ps
CPU time 5.55 seconds
Started Jul 26 07:22:51 PM PDT 24
Finished Jul 26 07:22:57 PM PDT 24
Peak memory 210492 kb
Host smart-c18083df-9113-43b6-9425-7a18433c8e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335068529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1335068529
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1094359375
Short name T882
Test name
Test status
Simulation time 67765721 ps
CPU time 2.84 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 210088 kb
Host smart-1c253385-2a7f-450a-b4de-d0258ba796bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094359375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1094359375
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.280727293
Short name T216
Test name
Test status
Simulation time 319464898 ps
CPU time 3.8 seconds
Started Jul 26 07:22:50 PM PDT 24
Finished Jul 26 07:22:53 PM PDT 24
Peak memory 214164 kb
Host smart-6224a48b-e9e2-442a-98a6-f929c156deee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280727293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.280727293
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1157725626
Short name T876
Test name
Test status
Simulation time 195555895 ps
CPU time 7.54 seconds
Started Jul 26 07:22:39 PM PDT 24
Finished Jul 26 07:22:47 PM PDT 24
Peak memory 209964 kb
Host smart-faad0b6d-490b-4ffa-a3c1-5bd415b8c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157725626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1157725626
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2169246785
Short name T819
Test name
Test status
Simulation time 108782041 ps
CPU time 3.53 seconds
Started Jul 26 07:22:43 PM PDT 24
Finished Jul 26 07:22:46 PM PDT 24
Peak memory 208368 kb
Host smart-c087a591-3edf-4815-8d09-910d9e8e418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169246785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2169246785
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.210615936
Short name T431
Test name
Test status
Simulation time 125466685 ps
CPU time 3.81 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:22:44 PM PDT 24
Peak memory 208460 kb
Host smart-c28454a0-63ac-4647-b29a-21931ac7a358
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210615936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.210615936
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3189031901
Short name T587
Test name
Test status
Simulation time 137465011 ps
CPU time 2.65 seconds
Started Jul 26 07:22:42 PM PDT 24
Finished Jul 26 07:22:45 PM PDT 24
Peak memory 208768 kb
Host smart-2e1cb864-5550-43a4-8822-c4dc34819538
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189031901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3189031901
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2463423642
Short name T825
Test name
Test status
Simulation time 281730672 ps
CPU time 3.93 seconds
Started Jul 26 07:22:38 PM PDT 24
Finished Jul 26 07:22:42 PM PDT 24
Peak memory 208652 kb
Host smart-9f267793-76ac-4b77-9cf3-28d925b32e99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463423642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2463423642
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2057605059
Short name T529
Test name
Test status
Simulation time 104190369 ps
CPU time 2.61 seconds
Started Jul 26 07:22:50 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 209116 kb
Host smart-6a471359-7db3-4e48-8246-4d65634d5af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057605059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2057605059
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1123414206
Short name T640
Test name
Test status
Simulation time 181914585 ps
CPU time 4.57 seconds
Started Jul 26 07:22:40 PM PDT 24
Finished Jul 26 07:22:44 PM PDT 24
Peak memory 207200 kb
Host smart-c1481943-a7b8-44c5-8e3f-45155a843061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123414206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1123414206
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.892734909
Short name T668
Test name
Test status
Simulation time 2164790414 ps
CPU time 64.78 seconds
Started Jul 26 07:22:50 PM PDT 24
Finished Jul 26 07:23:55 PM PDT 24
Peak memory 214228 kb
Host smart-470c67ca-4c7b-4154-88b9-48c6ed1be3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892734909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.892734909
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.906601014
Short name T329
Test name
Test status
Simulation time 544328121 ps
CPU time 2.38 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 207584 kb
Host smart-36e4a594-944a-4c67-972b-401aa5c02278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906601014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.906601014
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2353802351
Short name T495
Test name
Test status
Simulation time 176507724 ps
CPU time 2.31 seconds
Started Jul 26 07:22:48 PM PDT 24
Finished Jul 26 07:22:51 PM PDT 24
Peak memory 210252 kb
Host smart-6e569051-3b1b-474c-9d15-aaa202ea3452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353802351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2353802351
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1806774220
Short name T240
Test name
Test status
Simulation time 62216889 ps
CPU time 2.93 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 214212 kb
Host smart-42508048-e4ef-4b26-847f-b570e4db5326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806774220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1806774220
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2197452611
Short name T656
Test name
Test status
Simulation time 51921133 ps
CPU time 2.53 seconds
Started Jul 26 07:22:53 PM PDT 24
Finished Jul 26 07:22:56 PM PDT 24
Peak memory 218048 kb
Host smart-1df851ba-5d16-400f-bf85-99076f647ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197452611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2197452611
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2321754277
Short name T752
Test name
Test status
Simulation time 109772045 ps
CPU time 4.57 seconds
Started Jul 26 07:22:54 PM PDT 24
Finished Jul 26 07:22:59 PM PDT 24
Peak memory 222320 kb
Host smart-c5c3fb65-4647-4535-951a-f8124c9a5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321754277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2321754277
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3883611243
Short name T606
Test name
Test status
Simulation time 58817893 ps
CPU time 3.27 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:53 PM PDT 24
Peak memory 209148 kb
Host smart-8a8aad0c-37b3-4239-a32c-9c0ce08e4182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883611243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3883611243
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2321381146
Short name T536
Test name
Test status
Simulation time 1575849843 ps
CPU time 27.07 seconds
Started Jul 26 07:22:50 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 208668 kb
Host smart-64eba850-e395-41c6-8133-252929d564ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321381146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2321381146
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2040198778
Short name T789
Test name
Test status
Simulation time 32055025 ps
CPU time 2.32 seconds
Started Jul 26 07:22:48 PM PDT 24
Finished Jul 26 07:22:50 PM PDT 24
Peak memory 206860 kb
Host smart-9cc503cf-5518-4926-8582-5f29b692c7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040198778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2040198778
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4215888593
Short name T572
Test name
Test status
Simulation time 88076429 ps
CPU time 3.9 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:53 PM PDT 24
Peak memory 206788 kb
Host smart-e0ac2030-73cf-425f-a08b-7bda499e1821
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215888593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4215888593
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1703423080
Short name T136
Test name
Test status
Simulation time 522684033 ps
CPU time 13.33 seconds
Started Jul 26 07:22:55 PM PDT 24
Finished Jul 26 07:23:08 PM PDT 24
Peak memory 208832 kb
Host smart-f4e45215-0cfc-427f-aa38-89433418a659
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703423080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1703423080
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1127975805
Short name T820
Test name
Test status
Simulation time 49698267 ps
CPU time 2.29 seconds
Started Jul 26 07:22:49 PM PDT 24
Finished Jul 26 07:22:52 PM PDT 24
Peak memory 206752 kb
Host smart-6ff66b3f-7650-4840-99ee-e6554eb8b268
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127975805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1127975805
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.861667089
Short name T206
Test name
Test status
Simulation time 40985807 ps
CPU time 1.7 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 207712 kb
Host smart-bfbec283-3c86-48e3-93b2-b6cc7f60bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861667089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.861667089
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1438022857
Short name T423
Test name
Test status
Simulation time 146314561 ps
CPU time 2.83 seconds
Started Jul 26 07:22:51 PM PDT 24
Finished Jul 26 07:22:54 PM PDT 24
Peak memory 208440 kb
Host smart-3374bcf8-5bc8-4098-93f4-2397230998a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438022857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1438022857
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1617598840
Short name T54
Test name
Test status
Simulation time 777462131 ps
CPU time 8.33 seconds
Started Jul 26 07:22:58 PM PDT 24
Finished Jul 26 07:23:06 PM PDT 24
Peak memory 216844 kb
Host smart-6a901a6c-8a4e-4e02-b973-8a4334fc72a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617598840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1617598840
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2340679911
Short name T857
Test name
Test status
Simulation time 1508091342 ps
CPU time 11.39 seconds
Started Jul 26 07:22:59 PM PDT 24
Finished Jul 26 07:23:11 PM PDT 24
Peak memory 222340 kb
Host smart-5c1dd8c5-3633-44fd-b540-87954c0165c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340679911 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2340679911
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3573833824
Short name T23
Test name
Test status
Simulation time 741079470 ps
CPU time 3.85 seconds
Started Jul 26 07:22:54 PM PDT 24
Finished Jul 26 07:22:58 PM PDT 24
Peak memory 207828 kb
Host smart-45e08b8b-8ac8-4299-b404-58e6456e66cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573833824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3573833824
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3045816161
Short name T169
Test name
Test status
Simulation time 103557144 ps
CPU time 4.26 seconds
Started Jul 26 07:23:03 PM PDT 24
Finished Jul 26 07:23:07 PM PDT 24
Peak memory 209804 kb
Host smart-3765e25b-840f-4089-849b-18780b8e5187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045816161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3045816161
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4242526205
Short name T131
Test name
Test status
Simulation time 30922362 ps
CPU time 0.78 seconds
Started Jul 26 07:21:29 PM PDT 24
Finished Jul 26 07:21:30 PM PDT 24
Peak memory 205844 kb
Host smart-93e73f49-5855-4865-b5d7-e3e48247365f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242526205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4242526205
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1084049526
Short name T145
Test name
Test status
Simulation time 4228211788 ps
CPU time 116.85 seconds
Started Jul 26 07:21:13 PM PDT 24
Finished Jul 26 07:23:10 PM PDT 24
Peak memory 215036 kb
Host smart-c4f9fee7-0149-47dc-912c-a5e8500828da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084049526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1084049526
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1279296558
Short name T633
Test name
Test status
Simulation time 473627125 ps
CPU time 4 seconds
Started Jul 26 07:21:16 PM PDT 24
Finished Jul 26 07:21:21 PM PDT 24
Peak memory 214040 kb
Host smart-c748f9f1-c535-45fd-9998-c505d9927dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279296558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1279296558
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.31849937
Short name T583
Test name
Test status
Simulation time 104274765 ps
CPU time 4.94 seconds
Started Jul 26 07:21:11 PM PDT 24
Finished Jul 26 07:21:16 PM PDT 24
Peak memory 208936 kb
Host smart-2ec06102-3baa-479b-802c-bb5b3d8429c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31849937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.31849937
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4121268784
Short name T555
Test name
Test status
Simulation time 245326915 ps
CPU time 5.54 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:17 PM PDT 24
Peak memory 222280 kb
Host smart-2c4ae818-67c2-4ffe-968a-e25d82890442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121268784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4121268784
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2362049264
Short name T837
Test name
Test status
Simulation time 37045259 ps
CPU time 2.71 seconds
Started Jul 26 07:21:13 PM PDT 24
Finished Jul 26 07:21:15 PM PDT 24
Peak memory 208464 kb
Host smart-8a58af6f-f460-49d3-8996-abef86e6e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362049264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2362049264
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3803202256
Short name T514
Test name
Test status
Simulation time 238036862 ps
CPU time 6.11 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:18 PM PDT 24
Peak memory 218264 kb
Host smart-c4b6bd6d-d09b-4ceb-86ca-054fab5c9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803202256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3803202256
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.300593849
Short name T109
Test name
Test status
Simulation time 512393855 ps
CPU time 8.06 seconds
Started Jul 26 07:21:23 PM PDT 24
Finished Jul 26 07:21:31 PM PDT 24
Peak memory 229052 kb
Host smart-d031442c-f53e-46b0-ace8-4856f9efb972
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300593849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.300593849
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3707395962
Short name T708
Test name
Test status
Simulation time 824505923 ps
CPU time 28.86 seconds
Started Jul 26 07:21:10 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 208328 kb
Host smart-1c9db84b-a1dd-42e6-8223-2e17749e4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707395962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3707395962
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.409888870
Short name T769
Test name
Test status
Simulation time 76656735 ps
CPU time 2.3 seconds
Started Jul 26 07:21:13 PM PDT 24
Finished Jul 26 07:21:15 PM PDT 24
Peak memory 206876 kb
Host smart-f611ddf1-4ced-43fb-af9e-7ced7afeb508
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409888870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.409888870
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.213351213
Short name T376
Test name
Test status
Simulation time 116858852 ps
CPU time 4.01 seconds
Started Jul 26 07:21:13 PM PDT 24
Finished Jul 26 07:21:17 PM PDT 24
Peak memory 208892 kb
Host smart-d34ce919-cd57-410d-acab-ce8dcd637842
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213351213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.213351213
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2945985469
Short name T747
Test name
Test status
Simulation time 254328489 ps
CPU time 3.86 seconds
Started Jul 26 07:21:17 PM PDT 24
Finished Jul 26 07:21:20 PM PDT 24
Peak memory 208580 kb
Host smart-cae8aefa-e13c-42e4-a800-f76a0282b425
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945985469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2945985469
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1860015975
Short name T639
Test name
Test status
Simulation time 109360193 ps
CPU time 2.5 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:14 PM PDT 24
Peak memory 208228 kb
Host smart-46b089d3-0c11-4097-a91a-c96867a2a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860015975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1860015975
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2229976886
Short name T771
Test name
Test status
Simulation time 188471259 ps
CPU time 3.28 seconds
Started Jul 26 07:21:12 PM PDT 24
Finished Jul 26 07:21:15 PM PDT 24
Peak memory 208208 kb
Host smart-1dc2f094-d80f-46f5-afcd-a337a0dbe87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229976886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2229976886
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1358161624
Short name T897
Test name
Test status
Simulation time 679490433 ps
CPU time 17.85 seconds
Started Jul 26 07:21:14 PM PDT 24
Finished Jul 26 07:21:32 PM PDT 24
Peak memory 214684 kb
Host smart-6921d673-1c90-4569-afe0-2acd0b9094e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358161624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1358161624
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3783757011
Short name T373
Test name
Test status
Simulation time 443750927 ps
CPU time 5.37 seconds
Started Jul 26 07:21:10 PM PDT 24
Finished Jul 26 07:21:16 PM PDT 24
Peak memory 207220 kb
Host smart-88dd14c2-4006-46b3-8027-ba01d368cddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783757011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3783757011
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2340358704
Short name T441
Test name
Test status
Simulation time 44006418 ps
CPU time 2.09 seconds
Started Jul 26 07:21:15 PM PDT 24
Finished Jul 26 07:21:17 PM PDT 24
Peak memory 209912 kb
Host smart-3bcb4702-774c-4bb9-872c-c879296a77a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340358704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2340358704
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3617529975
Short name T856
Test name
Test status
Simulation time 12485834 ps
CPU time 0.72 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:02 PM PDT 24
Peak memory 205852 kb
Host smart-06dc5e9c-2dcf-46c4-9968-12cab8557282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617529975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3617529975
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3526486214
Short name T636
Test name
Test status
Simulation time 244689951 ps
CPU time 2.16 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 214108 kb
Host smart-a90e523a-7164-4cba-95e7-885e674f9523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526486214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3526486214
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2727282253
Short name T95
Test name
Test status
Simulation time 146459338 ps
CPU time 4.17 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:05 PM PDT 24
Peak memory 209540 kb
Host smart-9c785f8b-3da3-4397-8c7e-b2a699cdaece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727282253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2727282253
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2615409866
Short name T263
Test name
Test status
Simulation time 405267162 ps
CPU time 4.88 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:06 PM PDT 24
Peak memory 214080 kb
Host smart-9f336424-9071-4a1d-aecb-58dba1edaaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615409866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2615409866
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1503919698
Short name T470
Test name
Test status
Simulation time 302494122 ps
CPU time 4.03 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:04 PM PDT 24
Peak memory 209632 kb
Host smart-3a4dc73f-a0c3-42ca-9041-c8eafd1d7a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503919698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1503919698
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1060150084
Short name T669
Test name
Test status
Simulation time 293666411 ps
CPU time 4.15 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:04 PM PDT 24
Peak memory 208140 kb
Host smart-63e85534-d477-4f89-b94f-e3d932d94111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060150084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1060150084
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2486022462
Short name T394
Test name
Test status
Simulation time 239835579 ps
CPU time 3.36 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:04 PM PDT 24
Peak memory 206752 kb
Host smart-ef6c4fb0-7937-429e-b44d-1909892b1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486022462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2486022462
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1687976232
Short name T195
Test name
Test status
Simulation time 202238246 ps
CPU time 2.99 seconds
Started Jul 26 07:23:02 PM PDT 24
Finished Jul 26 07:23:05 PM PDT 24
Peak memory 206872 kb
Host smart-a273876f-2186-473b-9cdb-e823eef1d6d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687976232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1687976232
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.51250651
Short name T510
Test name
Test status
Simulation time 50413032 ps
CPU time 2.91 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 208584 kb
Host smart-367bc019-14a0-45a4-ac2e-904743a006f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51250651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.51250651
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.464481940
Short name T564
Test name
Test status
Simulation time 1404998222 ps
CPU time 34.31 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 207836 kb
Host smart-32d312a9-010f-45fa-ac3c-cb97dbf71d09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464481940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.464481940
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.18194725
Short name T565
Test name
Test status
Simulation time 263962352 ps
CPU time 2.99 seconds
Started Jul 26 07:22:59 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 209824 kb
Host smart-d5ce7c74-e139-4f0b-86cb-e3477e01f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18194725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.18194725
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1665105806
Short name T574
Test name
Test status
Simulation time 233490663 ps
CPU time 2.99 seconds
Started Jul 26 07:22:59 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 206524 kb
Host smart-243f2d0b-1c77-416e-87c3-d06b87726e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665105806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1665105806
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3559882085
Short name T887
Test name
Test status
Simulation time 102495537 ps
CPU time 4.27 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:05 PM PDT 24
Peak memory 208484 kb
Host smart-86483a07-b41b-48ab-8ef3-bbb734e52db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559882085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3559882085
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.786962605
Short name T731
Test name
Test status
Simulation time 363294679 ps
CPU time 2.11 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:02 PM PDT 24
Peak memory 209732 kb
Host smart-5e83baa1-d780-4b91-abeb-85cde0adab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786962605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.786962605
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1252869283
Short name T682
Test name
Test status
Simulation time 16845860 ps
CPU time 0.78 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:17 PM PDT 24
Peak memory 205844 kb
Host smart-50158ec2-d235-4849-b34c-1a73011692c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252869283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1252869283
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4084660287
Short name T323
Test name
Test status
Simulation time 148491354 ps
CPU time 7.87 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 214264 kb
Host smart-ed04bdf4-04c0-44f8-9630-5ee30794ff46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084660287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4084660287
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2215952963
Short name T697
Test name
Test status
Simulation time 311925809 ps
CPU time 5.92 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 216644 kb
Host smart-2f324b44-fc7e-473b-a5d1-1eba32c03e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215952963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2215952963
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1391645547
Short name T475
Test name
Test status
Simulation time 254048112 ps
CPU time 3.54 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:20 PM PDT 24
Peak memory 206796 kb
Host smart-b98c90c8-4286-4fd1-b0b4-f29fbf3761c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391645547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1391645547
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.813639944
Short name T843
Test name
Test status
Simulation time 580618069 ps
CPU time 4.81 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 214816 kb
Host smart-2ef82fc2-61a2-4077-a62b-ef47d66d299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813639944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.813639944
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.243231948
Short name T679
Test name
Test status
Simulation time 719583790 ps
CPU time 5.03 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 218336 kb
Host smart-e6715ee2-0d91-4285-9b46-756141eb9a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243231948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.243231948
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2757673866
Short name T726
Test name
Test status
Simulation time 43413467 ps
CPU time 2.78 seconds
Started Jul 26 07:23:00 PM PDT 24
Finished Jul 26 07:23:03 PM PDT 24
Peak memory 208548 kb
Host smart-cd983685-d030-4041-979b-8616e47c2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757673866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2757673866
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.874833834
Short name T554
Test name
Test status
Simulation time 2368749786 ps
CPU time 25.31 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:27 PM PDT 24
Peak memory 208984 kb
Host smart-bbffcaa7-cb4c-406f-a907-6c7be3a84d2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874833834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.874833834
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2866510192
Short name T704
Test name
Test status
Simulation time 489374389 ps
CPU time 7.52 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:09 PM PDT 24
Peak memory 208384 kb
Host smart-29d724fd-dea4-4df7-9db7-674163b2c2dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866510192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2866510192
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3003565
Short name T197
Test name
Test status
Simulation time 187780961 ps
CPU time 2.59 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:04 PM PDT 24
Peak memory 206816 kb
Host smart-3bcbcda8-7a2d-46a3-8483-5539d0ad4129
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3003565
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3066701727
Short name T294
Test name
Test status
Simulation time 77214588 ps
CPU time 3.03 seconds
Started Jul 26 07:23:17 PM PDT 24
Finished Jul 26 07:23:20 PM PDT 24
Peak memory 218484 kb
Host smart-24f075ba-e54e-4e41-bdb7-445897d69111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066701727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3066701727
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3580287141
Short name T602
Test name
Test status
Simulation time 65292464 ps
CPU time 3.01 seconds
Started Jul 26 07:23:01 PM PDT 24
Finished Jul 26 07:23:04 PM PDT 24
Peak memory 208200 kb
Host smart-94423fbd-e6fc-43e0-83b0-8913ce2dbf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580287141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3580287141
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2784428100
Short name T607
Test name
Test status
Simulation time 455150816 ps
CPU time 12.08 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:25 PM PDT 24
Peak memory 215204 kb
Host smart-66dd76c1-d741-4e58-b554-4802a20d2df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784428100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2784428100
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1192949636
Short name T123
Test name
Test status
Simulation time 406987949 ps
CPU time 16.19 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 222344 kb
Host smart-59751504-968a-4d95-9727-d3630d39f227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192949636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1192949636
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.236352700
Short name T695
Test name
Test status
Simulation time 133766710 ps
CPU time 4.85 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 214236 kb
Host smart-f969392e-8512-4294-b73b-bbbcf1d75c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236352700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.236352700
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1065495441
Short name T60
Test name
Test status
Simulation time 2181738782 ps
CPU time 10.21 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:25 PM PDT 24
Peak memory 209816 kb
Host smart-7f52a5a7-055f-4217-aea8-469a926ab865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065495441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1065495441
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1236025165
Short name T832
Test name
Test status
Simulation time 12112627 ps
CPU time 0.88 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:14 PM PDT 24
Peak memory 205884 kb
Host smart-4e7d518b-b77c-4195-bfa9-bbf8312e23dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236025165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1236025165
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4083876567
Short name T75
Test name
Test status
Simulation time 59456362 ps
CPU time 2.42 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 208480 kb
Host smart-82425640-0aba-40f7-baf8-2f62f8aedf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083876567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4083876567
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2912669970
Short name T442
Test name
Test status
Simulation time 249452967 ps
CPU time 2.05 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:17 PM PDT 24
Peak memory 214188 kb
Host smart-b2a85a46-d3bd-4c90-94ad-a82cdb8fcc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912669970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2912669970
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3062534131
Short name T741
Test name
Test status
Simulation time 91050380 ps
CPU time 3.04 seconds
Started Jul 26 07:23:18 PM PDT 24
Finished Jul 26 07:23:21 PM PDT 24
Peak memory 214432 kb
Host smart-db3e48f5-7c3d-42b4-9af7-7eafeedb3000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062534131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3062534131
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3281895416
Short name T230
Test name
Test status
Simulation time 64315221 ps
CPU time 3.91 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 210036 kb
Host smart-1a78504c-d392-42d9-950e-8b969333126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281895416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3281895416
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3285279907
Short name T275
Test name
Test status
Simulation time 175637204 ps
CPU time 7.21 seconds
Started Jul 26 07:23:18 PM PDT 24
Finished Jul 26 07:23:25 PM PDT 24
Peak memory 209988 kb
Host smart-5c53400d-0618-4889-8de2-5ceb86a3cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285279907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3285279907
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4002858995
Short name T673
Test name
Test status
Simulation time 213411134 ps
CPU time 4.41 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 206736 kb
Host smart-87aeca06-41d7-4f50-b3ed-9b8a816bc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002858995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4002858995
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2423525970
Short name T762
Test name
Test status
Simulation time 366368640 ps
CPU time 3.36 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 208332 kb
Host smart-54c74cd1-f834-4094-8e2c-b37501b34714
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423525970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2423525970
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3426434959
Short name T85
Test name
Test status
Simulation time 847792234 ps
CPU time 21.59 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:37 PM PDT 24
Peak memory 207968 kb
Host smart-caa4cecf-7dcf-4fa6-92aa-4e28d98de306
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426434959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3426434959
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1668531833
Short name T892
Test name
Test status
Simulation time 110466988 ps
CPU time 2.8 seconds
Started Jul 26 07:23:17 PM PDT 24
Finished Jul 26 07:23:20 PM PDT 24
Peak memory 206896 kb
Host smart-2bdb09ec-1624-4be1-a8c5-2c4d27d68e9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668531833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1668531833
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.281538084
Short name T824
Test name
Test status
Simulation time 63150686 ps
CPU time 2.3 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 209544 kb
Host smart-4d47c4ce-a8cc-4750-982b-6de028d7f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281538084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.281538084
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.342704184
Short name T456
Test name
Test status
Simulation time 63133452 ps
CPU time 2.7 seconds
Started Jul 26 07:23:17 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 208272 kb
Host smart-5f0b83ab-f289-4872-a60a-048add62f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342704184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.342704184
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1682642833
Short name T270
Test name
Test status
Simulation time 1213926859 ps
CPU time 15.64 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:30 PM PDT 24
Peak memory 214204 kb
Host smart-5a97cbb2-6953-473a-86f7-6303264edce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682642833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1682642833
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3054628254
Short name T499
Test name
Test status
Simulation time 412444537 ps
CPU time 5.18 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 207432 kb
Host smart-84a59983-25d0-44f6-8971-bfdc8ef28094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054628254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3054628254
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.709606374
Short name T388
Test name
Test status
Simulation time 100671052 ps
CPU time 1.43 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:16 PM PDT 24
Peak memory 209652 kb
Host smart-3a7f30d7-124d-4733-b3e4-da6315eb6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709606374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.709606374
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4116978672
Short name T425
Test name
Test status
Simulation time 24869504 ps
CPU time 1.06 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 205912 kb
Host smart-56da86c1-9c4b-43c0-92b5-e2115169c050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116978672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4116978672
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1349163688
Short name T725
Test name
Test status
Simulation time 225515245 ps
CPU time 3.25 seconds
Started Jul 26 07:23:30 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 222552 kb
Host smart-759ba497-f139-4aa8-887e-46dcf423a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349163688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1349163688
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2070317288
Short name T621
Test name
Test status
Simulation time 104965200 ps
CPU time 1.97 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:17 PM PDT 24
Peak memory 208916 kb
Host smart-721fe804-a046-4065-86c4-7ae3a5a428ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070317288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2070317288
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4249469092
Short name T709
Test name
Test status
Simulation time 37583422 ps
CPU time 1.98 seconds
Started Jul 26 07:23:17 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 214228 kb
Host smart-5280eee2-7e0c-4a8e-8b09-aec40cff5867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249469092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4249469092
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4055174562
Short name T787
Test name
Test status
Simulation time 161912009 ps
CPU time 4.6 seconds
Started Jul 26 07:23:15 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 214768 kb
Host smart-223f3371-cd24-4d74-8131-d619bb178d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055174562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4055174562
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.144531594
Short name T670
Test name
Test status
Simulation time 3057895549 ps
CPU time 42.4 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:58 PM PDT 24
Peak memory 218180 kb
Host smart-5f2f0c27-a5ee-490b-984d-8ab4562e600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144531594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.144531594
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1437898846
Short name T688
Test name
Test status
Simulation time 510174289 ps
CPU time 12.28 seconds
Started Jul 26 07:23:12 PM PDT 24
Finished Jul 26 07:23:25 PM PDT 24
Peak memory 208152 kb
Host smart-2a9953dd-c712-4af4-a34d-d3cde502a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437898846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1437898846
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.674379797
Short name T692
Test name
Test status
Simulation time 49255896 ps
CPU time 2.58 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:18 PM PDT 24
Peak memory 207212 kb
Host smart-6e7130ae-24b3-4b79-be20-598a332f41ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674379797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.674379797
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3281422046
Short name T547
Test name
Test status
Simulation time 428675575 ps
CPU time 6.46 seconds
Started Jul 26 07:23:16 PM PDT 24
Finished Jul 26 07:23:23 PM PDT 24
Peak memory 207808 kb
Host smart-776fb776-bcac-4aef-a7c3-0c25ed302fab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281422046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3281422046
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2878593871
Short name T458
Test name
Test status
Simulation time 498842935 ps
CPU time 4.72 seconds
Started Jul 26 07:23:14 PM PDT 24
Finished Jul 26 07:23:19 PM PDT 24
Peak memory 207844 kb
Host smart-c7ba9b6f-957e-49e4-ba97-190be14bb580
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878593871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2878593871
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1651553479
Short name T866
Test name
Test status
Simulation time 143282920 ps
CPU time 3.11 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 222240 kb
Host smart-a5adfb01-4962-4299-957d-727df064e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651553479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1651553479
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4042864071
Short name T426
Test name
Test status
Simulation time 114004122 ps
CPU time 3.6 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:17 PM PDT 24
Peak memory 206620 kb
Host smart-77d1184d-1ee0-46e3-ad9d-25323874df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042864071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4042864071
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1537060910
Short name T330
Test name
Test status
Simulation time 49894940366 ps
CPU time 193.55 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:26:42 PM PDT 24
Peak memory 222336 kb
Host smart-ead208bb-3f3a-45a9-9d72-fd034eb85e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537060910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1537060910
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1043322632
Short name T828
Test name
Test status
Simulation time 88265489 ps
CPU time 3.15 seconds
Started Jul 26 07:23:13 PM PDT 24
Finished Jul 26 07:23:16 PM PDT 24
Peak memory 208288 kb
Host smart-6802f40c-c1e1-42be-aaa6-80effc7c0e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043322632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1043322632
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3295155435
Short name T177
Test name
Test status
Simulation time 358898017 ps
CPU time 2.56 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 214096 kb
Host smart-24ed000c-946d-423d-b9b4-f3c59b745bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295155435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3295155435
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3582357440
Short name T108
Test name
Test status
Simulation time 18394901 ps
CPU time 0.71 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 205848 kb
Host smart-1730bc98-d68c-49aa-8c0a-10bd1328cf08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582357440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3582357440
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2895810160
Short name T135
Test name
Test status
Simulation time 531922491 ps
CPU time 7.7 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 214100 kb
Host smart-a7b48237-5ad4-49d2-bbb1-787d041c373a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895810160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2895810160
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1454751113
Short name T222
Test name
Test status
Simulation time 103633179 ps
CPU time 3.88 seconds
Started Jul 26 07:23:30 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 221640 kb
Host smart-ac534c34-1f80-479e-9721-03953d0d7e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454751113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1454751113
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3373932037
Short name T286
Test name
Test status
Simulation time 207241899 ps
CPU time 3.18 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 207256 kb
Host smart-ec3886cf-a73a-40b4-82e2-fc8c73b393bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373932037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3373932037
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4280785238
Short name T899
Test name
Test status
Simulation time 53503625 ps
CPU time 1.84 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 206308 kb
Host smart-ab944441-3b91-4916-9b55-48f2c32d01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280785238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4280785238
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1918845147
Short name T805
Test name
Test status
Simulation time 27905930 ps
CPU time 1.69 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 214052 kb
Host smart-82ed8e2c-2b88-45df-987f-5aa10f2aa902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918845147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1918845147
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2762489820
Short name T256
Test name
Test status
Simulation time 42244937 ps
CPU time 3.08 seconds
Started Jul 26 07:23:27 PM PDT 24
Finished Jul 26 07:23:30 PM PDT 24
Peak memory 220148 kb
Host smart-f767bc98-9f40-44aa-bf16-5a52e68cf26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762489820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2762489820
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3666515906
Short name T729
Test name
Test status
Simulation time 159986908 ps
CPU time 6.88 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 218184 kb
Host smart-fc692504-9a50-4b37-8b4e-5a9395b9aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666515906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3666515906
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3464519796
Short name T765
Test name
Test status
Simulation time 186671891 ps
CPU time 5.56 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 208780 kb
Host smart-d8713c34-4a4d-413d-b564-021a8921d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464519796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3464519796
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.132865720
Short name T461
Test name
Test status
Simulation time 265268214 ps
CPU time 5.1 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 208516 kb
Host smart-2e632836-1b85-42b3-a559-ddedb5d1da43
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132865720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.132865720
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4263566725
Short name T845
Test name
Test status
Simulation time 145565909 ps
CPU time 2.17 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 206748 kb
Host smart-94c65696-c979-4600-ad4e-118d59eeed63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263566725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4263566725
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3789777635
Short name T473
Test name
Test status
Simulation time 1261238490 ps
CPU time 2.82 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 206696 kb
Host smart-d3aa9990-1072-4b44-b50f-6dbd6cded103
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789777635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3789777635
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3978787552
Short name T472
Test name
Test status
Simulation time 337817687 ps
CPU time 3.77 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 218060 kb
Host smart-4a161de9-0d63-4c12-9520-251263efb0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978787552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3978787552
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2692067153
Short name T815
Test name
Test status
Simulation time 42428181 ps
CPU time 2.05 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:31 PM PDT 24
Peak memory 208112 kb
Host smart-702131a7-9697-4c47-be7a-0b0cf2c14fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692067153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2692067153
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.327067347
Short name T609
Test name
Test status
Simulation time 57928650 ps
CPU time 0.74 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 205860 kb
Host smart-801d45db-2108-4b68-8456-ac1b79a8bac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327067347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.327067347
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.292816068
Short name T542
Test name
Test status
Simulation time 284666254 ps
CPU time 3.8 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 209116 kb
Host smart-8951e42c-ab0e-404c-a716-62a0542f3bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292816068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.292816068
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2379688621
Short name T52
Test name
Test status
Simulation time 215142907 ps
CPU time 2.23 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:31 PM PDT 24
Peak memory 209832 kb
Host smart-f337afc7-1922-407e-86e1-dd09a0caddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379688621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2379688621
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1557146431
Short name T598
Test name
Test status
Simulation time 17976219 ps
CPU time 1.04 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 205976 kb
Host smart-cec54ef2-4d27-42e4-b5e9-adbdc03d181a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557146431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1557146431
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1840740857
Short name T413
Test name
Test status
Simulation time 55407368 ps
CPU time 2.4 seconds
Started Jul 26 07:23:30 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 214160 kb
Host smart-2e79af32-9c37-4a24-b240-1e7d927a0d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840740857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1840740857
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1421583330
Short name T655
Test name
Test status
Simulation time 711778014 ps
CPU time 20.67 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:52 PM PDT 24
Peak memory 214144 kb
Host smart-5bece517-5d52-4f54-b02c-2b17609e99e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421583330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1421583330
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3915754182
Short name T888
Test name
Test status
Simulation time 136041942 ps
CPU time 2.18 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:31 PM PDT 24
Peak memory 214216 kb
Host smart-69739ad0-2785-4e82-9f5d-8f9343ee5a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915754182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3915754182
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1221562963
Short name T699
Test name
Test status
Simulation time 9671235310 ps
CPU time 60.03 seconds
Started Jul 26 07:23:35 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 221264 kb
Host smart-116c0bf7-8505-4dff-9adc-0919c7ebd516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221562963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1221562963
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1173987016
Short name T318
Test name
Test status
Simulation time 111724183 ps
CPU time 4.19 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 214056 kb
Host smart-41f83bf7-69fd-4419-8a05-448f5ce3b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173987016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1173987016
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3700716467
Short name T469
Test name
Test status
Simulation time 181357480 ps
CPU time 4.84 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 209216 kb
Host smart-100b75c7-b9d0-462a-a57f-f92ea0d5ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700716467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3700716467
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.738362605
Short name T430
Test name
Test status
Simulation time 104602250 ps
CPU time 4.87 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 208320 kb
Host smart-f3be4b3b-8ba7-4255-9478-ded76f9ae37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738362605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.738362605
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1661495916
Short name T781
Test name
Test status
Simulation time 178935390 ps
CPU time 6.75 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:37 PM PDT 24
Peak memory 206884 kb
Host smart-d9ee1bd9-026e-4a2d-8fa2-2ad974ec3c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661495916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1661495916
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1032787312
Short name T775
Test name
Test status
Simulation time 126238297 ps
CPU time 3.25 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 208784 kb
Host smart-5c5cbd05-a350-4ad3-aa2b-e0a9e77dc899
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032787312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1032787312
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.562573253
Short name T462
Test name
Test status
Simulation time 101029485 ps
CPU time 1.72 seconds
Started Jul 26 07:23:34 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 206736 kb
Host smart-f3a72127-47ba-4d54-b511-1b0504e581ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562573253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.562573253
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.240485082
Short name T712
Test name
Test status
Simulation time 606856262 ps
CPU time 4.55 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 206848 kb
Host smart-8a525a6e-f484-44b6-9c6a-cb37ac6360af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240485082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.240485082
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.906516440
Short name T498
Test name
Test status
Simulation time 118502303 ps
CPU time 2.38 seconds
Started Jul 26 07:23:30 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 208908 kb
Host smart-1913f14b-aea1-4400-a838-4cf79ead4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906516440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.906516440
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1489266698
Short name T753
Test name
Test status
Simulation time 172740454 ps
CPU time 4.95 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:23:37 PM PDT 24
Peak memory 207036 kb
Host smart-c27e27d5-4268-4d11-b6fe-e012ab461916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489266698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1489266698
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1387727241
Short name T457
Test name
Test status
Simulation time 3976152346 ps
CPU time 25.97 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:55 PM PDT 24
Peak memory 208612 kb
Host smart-1bc65045-5ef5-43ff-94ec-6b6f79e65339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387727241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1387727241
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.957740985
Short name T862
Test name
Test status
Simulation time 42310208 ps
CPU time 2.34 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 209616 kb
Host smart-6083448f-a290-473f-923a-9b07846fce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957740985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.957740985
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4168964503
Short name T575
Test name
Test status
Simulation time 19462969 ps
CPU time 0.81 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 205812 kb
Host smart-7dfef439-15c8-45ce-b7a5-fd1c0f524f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168964503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4168964503
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4145568685
Short name T252
Test name
Test status
Simulation time 293271077 ps
CPU time 3.56 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:34 PM PDT 24
Peak memory 215364 kb
Host smart-3efa8b58-71d3-4b52-955d-f3307b2af9f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145568685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4145568685
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1306765548
Short name T74
Test name
Test status
Simulation time 88913406 ps
CPU time 4.04 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 209928 kb
Host smart-4e313dac-6dc2-499f-8116-c59359628cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306765548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1306765548
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1741988884
Short name T676
Test name
Test status
Simulation time 125674722 ps
CPU time 4.23 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:37 PM PDT 24
Peak memory 222152 kb
Host smart-9959bf36-9766-4112-b628-97b09f9f8572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741988884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1741988884
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3709804786
Short name T517
Test name
Test status
Simulation time 84129829 ps
CPU time 2.47 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:31 PM PDT 24
Peak memory 222312 kb
Host smart-b1c60a94-4e94-423a-ae5b-54d8f27b86fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709804786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3709804786
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1300397547
Short name T372
Test name
Test status
Simulation time 1285796039 ps
CPU time 4.09 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 206692 kb
Host smart-bb45473a-7fca-43f4-8dfd-e381c137b04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300397547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1300397547
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2196600198
Short name T625
Test name
Test status
Simulation time 359456079 ps
CPU time 3.96 seconds
Started Jul 26 07:23:29 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 208392 kb
Host smart-a75d0f6a-951f-43ab-ba0a-cc5154e4cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196600198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2196600198
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2957942260
Short name T365
Test name
Test status
Simulation time 209210674 ps
CPU time 7.5 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:41 PM PDT 24
Peak memory 208868 kb
Host smart-32c4d5e8-4812-456f-aa95-09254a13dd9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957942260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2957942260
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4026902866
Short name T525
Test name
Test status
Simulation time 88179453 ps
CPU time 1.89 seconds
Started Jul 26 07:23:34 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 207400 kb
Host smart-5461d2fa-3a1b-4084-a804-0fc24bdb8179
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026902866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4026902866
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3133603007
Short name T249
Test name
Test status
Simulation time 133392629 ps
CPU time 2.58 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:36 PM PDT 24
Peak memory 208400 kb
Host smart-1a5552e7-8e21-46fe-a85b-d3149fcff67f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133603007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3133603007
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2514897749
Short name T208
Test name
Test status
Simulation time 158195429 ps
CPU time 3.04 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 208448 kb
Host smart-7a23f696-984b-4652-a77c-5c10759ed3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514897749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2514897749
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3169742105
Short name T652
Test name
Test status
Simulation time 138976397 ps
CPU time 2.31 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:31 PM PDT 24
Peak memory 206712 kb
Host smart-d4848c1f-28ec-45d1-9539-7dbdfb68ddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169742105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3169742105
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.619775700
Short name T357
Test name
Test status
Simulation time 375383615 ps
CPU time 14 seconds
Started Jul 26 07:23:33 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 214904 kb
Host smart-ac9981c8-4879-4701-a99c-0440cd0b7a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619775700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.619775700
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.175790163
Short name T624
Test name
Test status
Simulation time 150071611 ps
CPU time 3.66 seconds
Started Jul 26 07:23:28 PM PDT 24
Finished Jul 26 07:23:32 PM PDT 24
Peak memory 208840 kb
Host smart-9616d295-ac00-4802-93d0-59c260ebb408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175790163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.175790163
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2665432350
Short name T524
Test name
Test status
Simulation time 192124956 ps
CPU time 1.54 seconds
Started Jul 26 07:23:31 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 209656 kb
Host smart-e0a1ef5e-9d7a-4134-8d0d-9ed722c97d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665432350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2665432350
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2590332520
Short name T429
Test name
Test status
Simulation time 35221660 ps
CPU time 0.83 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:45 PM PDT 24
Peak memory 205876 kb
Host smart-f034d59d-3be5-41c3-879b-43e3413a164b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590332520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2590332520
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2453330085
Short name T479
Test name
Test status
Simulation time 18833742 ps
CPU time 1.48 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:44 PM PDT 24
Peak memory 214280 kb
Host smart-00fe8491-bbf5-4e34-b5e7-78257028e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453330085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2453330085
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2368147392
Short name T236
Test name
Test status
Simulation time 236559342 ps
CPU time 4.03 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 220168 kb
Host smart-1607f810-c60c-46ff-bc9b-0bacf252ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368147392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2368147392
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.958056928
Short name T378
Test name
Test status
Simulation time 62956813 ps
CPU time 2.19 seconds
Started Jul 26 07:23:48 PM PDT 24
Finished Jul 26 07:23:51 PM PDT 24
Peak memory 215312 kb
Host smart-6f1e8c62-e6ca-444d-b11d-18ce5e9e10df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958056928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.958056928
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1669644252
Short name T231
Test name
Test status
Simulation time 746771897 ps
CPU time 4.28 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 220064 kb
Host smart-6752da86-d71f-441e-b6fd-3afb30746028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669644252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1669644252
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.511714594
Short name T355
Test name
Test status
Simulation time 98262013 ps
CPU time 5.05 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 214160 kb
Host smart-942d860c-81c7-4a94-800a-948b6c31d76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511714594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.511714594
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2956537967
Short name T680
Test name
Test status
Simulation time 112863402 ps
CPU time 2.59 seconds
Started Jul 26 07:23:32 PM PDT 24
Finished Jul 26 07:23:35 PM PDT 24
Peak memory 206780 kb
Host smart-42a4fa15-8c41-4676-a630-67afd5470d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956537967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2956537967
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2773590692
Short name T497
Test name
Test status
Simulation time 31161683 ps
CPU time 2.22 seconds
Started Jul 26 07:23:49 PM PDT 24
Finished Jul 26 07:23:51 PM PDT 24
Peak memory 206804 kb
Host smart-0373bf4c-4929-48ad-8a54-e88bde86a9e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773590692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2773590692
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.797247794
Short name T526
Test name
Test status
Simulation time 51962733 ps
CPU time 2.98 seconds
Started Jul 26 07:23:30 PM PDT 24
Finished Jul 26 07:23:33 PM PDT 24
Peak memory 208160 kb
Host smart-a0cebd63-095a-41c3-b087-f07161fa8e04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797247794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.797247794
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2515050302
Short name T701
Test name
Test status
Simulation time 273561782 ps
CPU time 5.77 seconds
Started Jul 26 07:23:40 PM PDT 24
Finished Jul 26 07:23:46 PM PDT 24
Peak memory 208012 kb
Host smart-ce9b0888-d4db-49e4-9a70-0cb33883a880
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515050302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2515050302
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2250207195
Short name T338
Test name
Test status
Simulation time 2566338173 ps
CPU time 8.58 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:53 PM PDT 24
Peak memory 214216 kb
Host smart-92b58c5b-8c62-4aed-ae6c-d0744e1af607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250207195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2250207195
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.842960689
Short name T503
Test name
Test status
Simulation time 155283872 ps
CPU time 1.91 seconds
Started Jul 26 07:23:35 PM PDT 24
Finished Jul 26 07:23:37 PM PDT 24
Peak memory 208480 kb
Host smart-af13991f-73d7-4e06-a720-aea874294c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842960689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.842960689
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3867902586
Short name T271
Test name
Test status
Simulation time 12415163567 ps
CPU time 51.73 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 216176 kb
Host smart-bf241214-bb6e-4a9b-a6d1-e4037f328d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867902586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3867902586
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1015448428
Short name T371
Test name
Test status
Simulation time 1238986997 ps
CPU time 4.16 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:49 PM PDT 24
Peak memory 209944 kb
Host smart-34f9b5d2-c02e-4474-ab80-799413444790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015448428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1015448428
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3002656522
Short name T852
Test name
Test status
Simulation time 35555134 ps
CPU time 1.45 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:44 PM PDT 24
Peak memory 210244 kb
Host smart-a2a0e9e2-92f1-481e-a521-46e198e6aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002656522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3002656522
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.164042302
Short name T446
Test name
Test status
Simulation time 24443689 ps
CPU time 0.75 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:45 PM PDT 24
Peak memory 205876 kb
Host smart-732f5023-8b95-4ac7-baeb-46a8a5df2762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164042302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.164042302
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2247201195
Short name T242
Test name
Test status
Simulation time 549018402 ps
CPU time 4 seconds
Started Jul 26 07:23:49 PM PDT 24
Finished Jul 26 07:23:53 PM PDT 24
Peak memory 215356 kb
Host smart-65282ba8-dcc3-4ffb-8e97-aa5b6a16bfb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247201195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2247201195
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2613057219
Short name T617
Test name
Test status
Simulation time 1817513386 ps
CPU time 4.72 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:50 PM PDT 24
Peak memory 209616 kb
Host smart-0676f3a1-f981-452e-9557-67e110e459f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613057219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2613057219
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3870340310
Short name T67
Test name
Test status
Simulation time 93466218 ps
CPU time 2.62 seconds
Started Jul 26 07:23:41 PM PDT 24
Finished Jul 26 07:23:44 PM PDT 24
Peak memory 222276 kb
Host smart-e735f5e2-8575-4acf-8705-55ba54a75610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870340310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3870340310
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2267563768
Short name T651
Test name
Test status
Simulation time 136219894 ps
CPU time 4.25 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 214120 kb
Host smart-52afd233-d726-4073-80db-9bc383ca04fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267563768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2267563768
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3342495765
Short name T336
Test name
Test status
Simulation time 379216089 ps
CPU time 4.39 seconds
Started Jul 26 07:23:48 PM PDT 24
Finished Jul 26 07:23:52 PM PDT 24
Peak memory 214908 kb
Host smart-4e27cfae-a4cb-4e54-842d-5bff382fd5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342495765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3342495765
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.615075984
Short name T482
Test name
Test status
Simulation time 56450868 ps
CPU time 3.08 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:46 PM PDT 24
Peak memory 209400 kb
Host smart-0084048f-7040-4a6c-b60b-76b18e619a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615075984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.615075984
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.5791793
Short name T748
Test name
Test status
Simulation time 243385775 ps
CPU time 4.83 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 208424 kb
Host smart-8767e840-0b46-423a-b43d-7b1f0c14b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5791793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.5791793
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1095532656
Short name T248
Test name
Test status
Simulation time 135039759 ps
CPU time 4.35 seconds
Started Jul 26 07:23:47 PM PDT 24
Finished Jul 26 07:23:51 PM PDT 24
Peak memory 208424 kb
Host smart-68d79894-3e86-4e09-aa59-ec5fc30095f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095532656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1095532656
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1932563615
Short name T642
Test name
Test status
Simulation time 67519058 ps
CPU time 2.34 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:44 PM PDT 24
Peak memory 207192 kb
Host smart-c1e80cab-09f9-41a2-af51-104c829f3b5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932563615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1932563615
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.346575645
Short name T671
Test name
Test status
Simulation time 336581267 ps
CPU time 8.91 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:51 PM PDT 24
Peak memory 207908 kb
Host smart-187e07b8-1aa5-48a8-8d51-ebb669b1431a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346575645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.346575645
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3162607585
Short name T313
Test name
Test status
Simulation time 764992491 ps
CPU time 5.01 seconds
Started Jul 26 07:23:42 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 208500 kb
Host smart-c9be2c40-cfe2-46d4-9f9e-dd75f92055df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162607585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3162607585
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3698679447
Short name T210
Test name
Test status
Simulation time 238325854 ps
CPU time 5.02 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 214128 kb
Host smart-1a998e5a-1a4f-4e4e-9a03-b2d4aa0103aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698679447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3698679447
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1451889831
Short name T513
Test name
Test status
Simulation time 339354480 ps
CPU time 2.99 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 206724 kb
Host smart-65f50d07-8b7a-4d70-978e-883c26bcff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451889831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1451889831
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3176481925
Short name T211
Test name
Test status
Simulation time 52238435 ps
CPU time 3.04 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 207844 kb
Host smart-cd9a1584-ff86-4c30-9198-f78e167637c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176481925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3176481925
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2788723243
Short name T877
Test name
Test status
Simulation time 159216264 ps
CPU time 2.25 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 209696 kb
Host smart-4af2fa7e-0269-483a-9fe1-c48d227038fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788723243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2788723243
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1316984156
Short name T818
Test name
Test status
Simulation time 15571180 ps
CPU time 0.91 seconds
Started Jul 26 07:24:00 PM PDT 24
Finished Jul 26 07:24:01 PM PDT 24
Peak memory 205740 kb
Host smart-69308e0c-0da7-4231-a873-ffcffefd070d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316984156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1316984156
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.468450408
Short name T410
Test name
Test status
Simulation time 51161086 ps
CPU time 3.71 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 214128 kb
Host smart-601c76cf-6f1d-41cd-8c28-0e01f042757d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468450408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.468450408
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3776414641
Short name T400
Test name
Test status
Simulation time 240891683 ps
CPU time 3.59 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:05 PM PDT 24
Peak memory 218464 kb
Host smart-e67a706e-0778-4021-94fd-090e7757f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776414641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3776414641
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2231825991
Short name T878
Test name
Test status
Simulation time 1211966823 ps
CPU time 10.53 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:55 PM PDT 24
Peak memory 208496 kb
Host smart-4a3b0733-811d-4bec-a0d1-4499a1864274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231825991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2231825991
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3618867965
Short name T696
Test name
Test status
Simulation time 766220301 ps
CPU time 4.38 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:05 PM PDT 24
Peak memory 214044 kb
Host smart-e784e3bd-d857-4667-9fc3-c06560f75d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618867965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3618867965
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.98926675
Short name T764
Test name
Test status
Simulation time 210394052 ps
CPU time 3.78 seconds
Started Jul 26 07:23:43 PM PDT 24
Finished Jul 26 07:23:47 PM PDT 24
Peak memory 209596 kb
Host smart-27018255-a78a-42e3-8d2a-d8b7e4f080f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98926675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.98926675
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2116753003
Short name T597
Test name
Test status
Simulation time 605350626 ps
CPU time 7.21 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:52 PM PDT 24
Peak memory 208724 kb
Host smart-cae1bc59-5946-4631-9c98-a9c57ceffcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116753003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2116753003
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1129792644
Short name T784
Test name
Test status
Simulation time 145471942 ps
CPU time 2.35 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 206624 kb
Host smart-1eedeb7f-98fc-4612-a9e4-fb19d61fff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129792644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1129792644
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3552101823
Short name T585
Test name
Test status
Simulation time 74147694 ps
CPU time 2.37 seconds
Started Jul 26 07:23:41 PM PDT 24
Finished Jul 26 07:23:43 PM PDT 24
Peak memory 206816 kb
Host smart-d60cff6e-d982-49a5-912e-f05937ecd78d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552101823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3552101823
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3213932006
Short name T901
Test name
Test status
Simulation time 63185857 ps
CPU time 3.15 seconds
Started Jul 26 07:23:44 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 208596 kb
Host smart-ac249d81-11a9-4a8e-adc2-387f3b36c660
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213932006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3213932006
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.605407324
Short name T687
Test name
Test status
Simulation time 56424709 ps
CPU time 3.03 seconds
Started Jul 26 07:23:45 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 208384 kb
Host smart-33eb1a64-d523-4729-948e-821818c00d53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605407324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.605407324
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2472745574
Short name T455
Test name
Test status
Simulation time 44603637 ps
CPU time 1.8 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:03 PM PDT 24
Peak memory 207828 kb
Host smart-7a9e5e5f-732f-49e2-a295-4eeeb8822022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472745574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2472745574
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2890842509
Short name T707
Test name
Test status
Simulation time 114114786 ps
CPU time 2.09 seconds
Started Jul 26 07:23:46 PM PDT 24
Finished Jul 26 07:23:48 PM PDT 24
Peak memory 206000 kb
Host smart-4890fb9d-cb5d-47cf-92db-57b64d61b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890842509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2890842509
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1475624807
Short name T202
Test name
Test status
Simulation time 61548822397 ps
CPU time 349.83 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:29:51 PM PDT 24
Peak memory 222388 kb
Host smart-7abfa9bb-8953-4fab-833d-b0c64a2f896a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475624807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1475624807
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.776952385
Short name T139
Test name
Test status
Simulation time 83684520 ps
CPU time 3.87 seconds
Started Jul 26 07:24:04 PM PDT 24
Finished Jul 26 07:24:07 PM PDT 24
Peak memory 209236 kb
Host smart-f46f754b-d28a-490f-aa5f-0fe4d3b0dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776952385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.776952385
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2469398668
Short name T732
Test name
Test status
Simulation time 289893662 ps
CPU time 3.77 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 210660 kb
Host smart-e77ce9d4-ee4c-4020-a92f-77cff959e271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469398668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2469398668
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.911258252
Short name T579
Test name
Test status
Simulation time 58175273 ps
CPU time 0.78 seconds
Started Jul 26 07:21:31 PM PDT 24
Finished Jul 26 07:21:32 PM PDT 24
Peak memory 205844 kb
Host smart-d97db33f-72e5-4699-9173-4d6500b6fc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911258252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.911258252
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1983842987
Short name T283
Test name
Test status
Simulation time 1883517787 ps
CPU time 26.88 seconds
Started Jul 26 07:21:25 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 215064 kb
Host smart-53806e88-8ba8-4f29-93e9-7c32b332a05e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983842987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1983842987
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2339854242
Short name T721
Test name
Test status
Simulation time 744535388 ps
CPU time 5.56 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:36 PM PDT 24
Peak memory 208940 kb
Host smart-a789f695-80c3-464b-b480-fd9f0c6fa3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339854242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2339854242
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.514390421
Short name T612
Test name
Test status
Simulation time 33449170 ps
CPU time 2.5 seconds
Started Jul 26 07:21:26 PM PDT 24
Finished Jul 26 07:21:28 PM PDT 24
Peak memory 214240 kb
Host smart-8f92181a-f764-49cd-a8fd-f336b50edee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514390421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.514390421
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.951347930
Short name T694
Test name
Test status
Simulation time 43161397 ps
CPU time 1.7 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:32 PM PDT 24
Peak memory 214072 kb
Host smart-9ea363c5-60e2-40b0-a436-54aeec46506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951347930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.951347930
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1659776711
Short name T871
Test name
Test status
Simulation time 90512252 ps
CPU time 3.23 seconds
Started Jul 26 07:21:31 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 217852 kb
Host smart-cfd40e37-94a0-4e53-ab1e-a7ae3e70436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659776711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1659776711
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3932530331
Short name T906
Test name
Test status
Simulation time 1104694599 ps
CPU time 12.72 seconds
Started Jul 26 07:21:28 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 208984 kb
Host smart-3b3737ee-ae03-44ca-b5fb-0268d62dad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932530331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3932530331
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3675876737
Short name T785
Test name
Test status
Simulation time 590867908 ps
CPU time 7 seconds
Started Jul 26 07:21:32 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 208300 kb
Host smart-6ef9cd87-6ed5-44f8-a2f7-124eb58e746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675876737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3675876737
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.654598021
Short name T637
Test name
Test status
Simulation time 52032909 ps
CPU time 2.77 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:33 PM PDT 24
Peak memory 206852 kb
Host smart-e098c8c1-086a-4def-9e5d-39a567c9a059
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654598021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.654598021
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2711862201
Short name T841
Test name
Test status
Simulation time 1324306767 ps
CPU time 6.54 seconds
Started Jul 26 07:21:29 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 207884 kb
Host smart-548759e0-7fa0-451b-a2b8-aabfabddf662
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711862201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2711862201
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.184000925
Short name T86
Test name
Test status
Simulation time 23037644 ps
CPU time 1.89 seconds
Started Jul 26 07:21:31 PM PDT 24
Finished Jul 26 07:21:33 PM PDT 24
Peak memory 206696 kb
Host smart-72d4eb12-513b-4d84-9ce5-42a3351be784
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184000925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.184000925
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3004839233
Short name T278
Test name
Test status
Simulation time 1169062006 ps
CPU time 15.96 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:46 PM PDT 24
Peak memory 218344 kb
Host smart-ec4a55c9-847f-4385-8272-54e8624dcb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004839233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3004839233
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.201632373
Short name T530
Test name
Test status
Simulation time 405661283 ps
CPU time 2.6 seconds
Started Jul 26 07:21:33 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 208384 kb
Host smart-3c3cc3e9-dcef-4aa4-b3b7-7df29bed5aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201632373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.201632373
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2824030400
Short name T611
Test name
Test status
Simulation time 1840612051 ps
CPU time 14.32 seconds
Started Jul 26 07:21:24 PM PDT 24
Finished Jul 26 07:21:38 PM PDT 24
Peak memory 207876 kb
Host smart-2834f334-9f45-4d7e-b1cb-8f1f3d9e3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824030400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2824030400
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1043694699
Short name T61
Test name
Test status
Simulation time 67587660 ps
CPU time 2.76 seconds
Started Jul 26 07:21:33 PM PDT 24
Finished Jul 26 07:21:37 PM PDT 24
Peak memory 209732 kb
Host smart-4b1c871b-0b4b-40ef-80f8-def0bfc11d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043694699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1043694699
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3358372270
Short name T106
Test name
Test status
Simulation time 15595973 ps
CPU time 0.77 seconds
Started Jul 26 07:24:03 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 205852 kb
Host smart-cef469fe-555e-4272-aaeb-73376a0ce223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358372270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3358372270
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3831949971
Short name T389
Test name
Test status
Simulation time 32613793 ps
CPU time 2.53 seconds
Started Jul 26 07:23:59 PM PDT 24
Finished Jul 26 07:24:02 PM PDT 24
Peak memory 214856 kb
Host smart-ad9b8406-f5f3-431a-91e0-c55061d46f32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831949971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3831949971
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.113165391
Short name T46
Test name
Test status
Simulation time 25436331 ps
CPU time 2.02 seconds
Started Jul 26 07:23:59 PM PDT 24
Finished Jul 26 07:24:01 PM PDT 24
Peak memory 209860 kb
Host smart-7562764d-8804-4353-adb5-f0f2f6014dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113165391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.113165391
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.94533460
Short name T782
Test name
Test status
Simulation time 510080488 ps
CPU time 9.86 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:12 PM PDT 24
Peak memory 214080 kb
Host smart-5da004de-2aa6-4067-a50e-96607c80fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94533460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.94533460
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2977351466
Short name T4
Test name
Test status
Simulation time 72769823 ps
CPU time 2.65 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 222312 kb
Host smart-c52772db-9072-47d8-a950-8de5cb4a2525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977351466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2977351466
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1492662048
Short name T720
Test name
Test status
Simulation time 99021802 ps
CPU time 4.74 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:07 PM PDT 24
Peak memory 208452 kb
Host smart-57859a56-28af-4f59-9eb8-8765ea288c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492662048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1492662048
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1264225088
Short name T603
Test name
Test status
Simulation time 169902952 ps
CPU time 2.67 seconds
Started Jul 26 07:24:05 PM PDT 24
Finished Jul 26 07:24:08 PM PDT 24
Peak memory 206700 kb
Host smart-aa4b9db1-d5b5-4ed9-ab0f-5da137071d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264225088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1264225088
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2123871319
Short name T284
Test name
Test status
Simulation time 419780239 ps
CPU time 5.02 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 206976 kb
Host smart-902e4850-c27f-4690-b16a-dcdc2899cb6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123871319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2123871319
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3157032870
Short name T527
Test name
Test status
Simulation time 282232009 ps
CPU time 4.33 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:05 PM PDT 24
Peak memory 208516 kb
Host smart-e558ecde-6305-40d4-af8b-356721c4e1e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157032870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3157032870
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1362644728
Short name T397
Test name
Test status
Simulation time 1467843574 ps
CPU time 6.2 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:09 PM PDT 24
Peak memory 207804 kb
Host smart-2d3e05d4-74b5-4d5e-aef2-40bac4cbd1ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362644728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1362644728
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2405979528
Short name T488
Test name
Test status
Simulation time 126892172 ps
CPU time 3.59 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:05 PM PDT 24
Peak memory 214152 kb
Host smart-3e39f8e0-51a2-413b-bfaa-0be4961a7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405979528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2405979528
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2737681216
Short name T450
Test name
Test status
Simulation time 151890630 ps
CPU time 3.49 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 206708 kb
Host smart-990267b7-5023-451b-97cb-63b982db2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737681216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2737681216
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3381784252
Short name T267
Test name
Test status
Simulation time 105975044 ps
CPU time 4.2 seconds
Started Jul 26 07:23:59 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 209952 kb
Host smart-cbe66bfc-4500-41ac-ab3a-638a8d9a2b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381784252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3381784252
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1758885535
Short name T872
Test name
Test status
Simulation time 375662494 ps
CPU time 7.75 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:09 PM PDT 24
Peak memory 209008 kb
Host smart-e40a9324-1883-45f1-9d50-e7f00c8014fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758885535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1758885535
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2219691244
Short name T777
Test name
Test status
Simulation time 810169910 ps
CPU time 18.35 seconds
Started Jul 26 07:23:59 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 210844 kb
Host smart-6f23b4b0-b9d8-4d28-b3ac-7ef680d2ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219691244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2219691244
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3403977793
Short name T443
Test name
Test status
Simulation time 49833439 ps
CPU time 0.75 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 205872 kb
Host smart-a5ee5b3d-1acc-4739-a79e-ef51ee874468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403977793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3403977793
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2777005262
Short name T421
Test name
Test status
Simulation time 77996542 ps
CPU time 3 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 214156 kb
Host smart-b1ced00f-d1c4-40c4-8451-f122b90dd357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777005262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2777005262
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3549450255
Short name T29
Test name
Test status
Simulation time 71012014 ps
CPU time 1.61 seconds
Started Jul 26 07:24:00 PM PDT 24
Finished Jul 26 07:24:02 PM PDT 24
Peak memory 222244 kb
Host smart-9688afa2-0091-4a49-8f0d-9567da74e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549450255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3549450255
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2825068689
Short name T903
Test name
Test status
Simulation time 58952536 ps
CPU time 2.27 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 207372 kb
Host smart-28b4eea5-6336-4a5d-adbf-34ad45736728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825068689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2825068689
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.431400758
Short name T99
Test name
Test status
Simulation time 512480704 ps
CPU time 8.94 seconds
Started Jul 26 07:24:03 PM PDT 24
Finished Jul 26 07:24:12 PM PDT 24
Peak memory 209416 kb
Host smart-952695fd-6085-4b15-875b-48663421c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431400758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.431400758
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.682996218
Short name T218
Test name
Test status
Simulation time 159157113 ps
CPU time 2.14 seconds
Started Jul 26 07:24:04 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 219048 kb
Host smart-c68b45c6-60f5-428e-b5c3-dbd5332737f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682996218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.682996218
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2935900837
Short name T649
Test name
Test status
Simulation time 4192656881 ps
CPU time 25.31 seconds
Started Jul 26 07:24:03 PM PDT 24
Finished Jul 26 07:24:28 PM PDT 24
Peak memory 210300 kb
Host smart-89e79f7e-6048-4612-8d72-c80fa032209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935900837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2935900837
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.987499235
Short name T895
Test name
Test status
Simulation time 564242038 ps
CPU time 4.67 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:06 PM PDT 24
Peak memory 207824 kb
Host smart-c11905dc-4a2b-4ea1-9b23-9156325f76c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987499235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.987499235
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1322793483
Short name T773
Test name
Test status
Simulation time 3777387007 ps
CPU time 40.85 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:43 PM PDT 24
Peak memory 208888 kb
Host smart-aec56ff9-7fb3-4b1a-b358-8ebd958fdf79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322793483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1322793483
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2557321067
Short name T834
Test name
Test status
Simulation time 519304383 ps
CPU time 5.73 seconds
Started Jul 26 07:24:01 PM PDT 24
Finished Jul 26 07:24:07 PM PDT 24
Peak memory 208432 kb
Host smart-add9b543-12da-41e8-9a73-36abe123355c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557321067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2557321067
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1858714061
Short name T491
Test name
Test status
Simulation time 196695029 ps
CPU time 5.96 seconds
Started Jul 26 07:24:04 PM PDT 24
Finished Jul 26 07:24:10 PM PDT 24
Peak memory 207648 kb
Host smart-20eda25d-3703-4e9a-9be1-4d50e12e6248
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858714061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1858714061
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.636537301
Short name T576
Test name
Test status
Simulation time 218548602 ps
CPU time 4.61 seconds
Started Jul 26 07:24:03 PM PDT 24
Finished Jul 26 07:24:08 PM PDT 24
Peak memory 210304 kb
Host smart-5e4da8b8-e066-42df-83e0-d74aa71054f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636537301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.636537301
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.330359053
Short name T790
Test name
Test status
Simulation time 78346406 ps
CPU time 2.53 seconds
Started Jul 26 07:24:02 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 208284 kb
Host smart-067e1d6b-f14d-4cec-9163-9ec8384a3658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330359053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.330359053
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2932052955
Short name T201
Test name
Test status
Simulation time 830325966 ps
CPU time 17.21 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 219844 kb
Host smart-9dae178c-3b89-4f90-9552-fe7e10827565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932052955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2932052955
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2113004572
Short name T830
Test name
Test status
Simulation time 278403915 ps
CPU time 3.76 seconds
Started Jul 26 07:24:00 PM PDT 24
Finished Jul 26 07:24:04 PM PDT 24
Peak memory 217960 kb
Host smart-3e01a95e-7a0f-4296-8f69-5caf3d7e2c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113004572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2113004572
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.141411307
Short name T180
Test name
Test status
Simulation time 87815685 ps
CPU time 1.59 seconds
Started Jul 26 07:24:14 PM PDT 24
Finished Jul 26 07:24:16 PM PDT 24
Peak memory 209716 kb
Host smart-14a151d7-9434-43ed-be32-1e3874d50d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141411307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.141411307
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3009813902
Short name T690
Test name
Test status
Simulation time 13301824 ps
CPU time 0.76 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:17 PM PDT 24
Peak memory 205852 kb
Host smart-0623076a-9cc3-4bc4-95fa-e1969703ad05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009813902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3009813902
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1924712712
Short name T650
Test name
Test status
Simulation time 229451643 ps
CPU time 2.69 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 210392 kb
Host smart-5507c352-0dc4-4207-956f-839b2e357acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924712712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1924712712
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3321288867
Short name T757
Test name
Test status
Simulation time 34492745 ps
CPU time 2.07 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 207812 kb
Host smart-17740447-8d52-4bf3-b4cc-8c7da8b9add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321288867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3321288867
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3870898117
Short name T102
Test name
Test status
Simulation time 339385903 ps
CPU time 3.49 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 214136 kb
Host smart-63bd24c0-a293-4377-ac69-efca2c842b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870898117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3870898117
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1528245293
Short name T288
Test name
Test status
Simulation time 354065214 ps
CPU time 4.59 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 222164 kb
Host smart-0c0c8724-f407-49da-8445-c4d46f30395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528245293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1528245293
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2540231035
Short name T700
Test name
Test status
Simulation time 825695642 ps
CPU time 4.85 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:23 PM PDT 24
Peak memory 222280 kb
Host smart-30a3a17c-c041-483d-83b9-1338c9921d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540231035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2540231035
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4253631258
Short name T744
Test name
Test status
Simulation time 143656975 ps
CPU time 4.18 seconds
Started Jul 26 07:24:14 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 208036 kb
Host smart-106c3339-2791-4c62-b09d-f69b6e262039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253631258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4253631258
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2938607256
Short name T207
Test name
Test status
Simulation time 548284827 ps
CPU time 14.33 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:30 PM PDT 24
Peak memory 207884 kb
Host smart-ccad1bbb-8c69-4923-8ce8-bc01fbaf7bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938607256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2938607256
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3611681402
Short name T250
Test name
Test status
Simulation time 125654113 ps
CPU time 2.83 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 208400 kb
Host smart-7d29b987-06b5-4019-a239-6b364f48c84c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611681402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3611681402
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2862559770
Short name T698
Test name
Test status
Simulation time 60974078 ps
CPU time 2.35 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 206736 kb
Host smart-d2ea72e0-de19-4896-97d0-48a02f4a86ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862559770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2862559770
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1114725679
Short name T541
Test name
Test status
Simulation time 7082600216 ps
CPU time 37.76 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:53 PM PDT 24
Peak memory 208928 kb
Host smart-395a2b25-6d45-4658-a831-21a28d260a13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114725679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1114725679
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1154661949
Short name T305
Test name
Test status
Simulation time 180008881 ps
CPU time 3.15 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 209744 kb
Host smart-c1e4c12a-f72f-4acd-b22c-140c5db5a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154661949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1154661949
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.567309788
Short name T686
Test name
Test status
Simulation time 652439295 ps
CPU time 4.29 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 207004 kb
Host smart-708522da-b84e-44fd-b5bd-bb2cf7c4662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567309788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.567309788
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3566049141
Short name T890
Test name
Test status
Simulation time 699798779 ps
CPU time 8.22 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:26 PM PDT 24
Peak memory 209028 kb
Host smart-ac087c72-6a43-48b7-be0a-265b3e2c38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566049141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3566049141
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4167565903
Short name T874
Test name
Test status
Simulation time 113406400 ps
CPU time 4.01 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 210744 kb
Host smart-954c7095-eaca-4e9b-9af9-ba0276c1d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167565903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4167565903
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4150386104
Short name T424
Test name
Test status
Simulation time 16080054 ps
CPU time 0.95 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 205948 kb
Host smart-be7c845b-f29e-42ba-9961-d89972872e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150386104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4150386104
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1046905633
Short name T147
Test name
Test status
Simulation time 245209846 ps
CPU time 4.69 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 215156 kb
Host smart-7ec79913-3f32-47ce-aa74-05d9d4eba7f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046905633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1046905633
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3898359687
Short name T219
Test name
Test status
Simulation time 351148993 ps
CPU time 2.82 seconds
Started Jul 26 07:24:14 PM PDT 24
Finished Jul 26 07:24:17 PM PDT 24
Peak memory 215764 kb
Host smart-b7c1f8e7-38e8-4a9f-aecb-acc260920f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898359687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3898359687
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.362659671
Short name T849
Test name
Test status
Simulation time 428047714 ps
CPU time 3.22 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 207468 kb
Host smart-84b778a8-0155-4a6e-bd13-30e4c1970fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362659671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.362659671
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.356333510
Short name T653
Test name
Test status
Simulation time 98364348 ps
CPU time 4.76 seconds
Started Jul 26 07:24:21 PM PDT 24
Finished Jul 26 07:24:26 PM PDT 24
Peak memory 222096 kb
Host smart-0c3e65de-277d-4341-ba2c-2a571cc801d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356333510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.356333510
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3910868853
Short name T486
Test name
Test status
Simulation time 162934164 ps
CPU time 4.7 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 209220 kb
Host smart-0d8ee208-5fc8-4afd-a1c6-9b8ba2418b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910868853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3910868853
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2872867991
Short name T297
Test name
Test status
Simulation time 1060123247 ps
CPU time 11.85 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:29 PM PDT 24
Peak memory 214192 kb
Host smart-a1adaf84-e5ba-45cc-ba88-951c965a6384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872867991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2872867991
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3686731075
Short name T811
Test name
Test status
Simulation time 128380538 ps
CPU time 3.95 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:23 PM PDT 24
Peak memory 206656 kb
Host smart-501eaa0b-e231-4a4a-91b7-52c21d1935c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686731075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3686731075
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4235176979
Short name T891
Test name
Test status
Simulation time 153026858 ps
CPU time 2.57 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:18 PM PDT 24
Peak memory 207424 kb
Host smart-333b3ad1-c0b7-4324-a03a-543015288a9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235176979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4235176979
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.667917582
Short name T445
Test name
Test status
Simulation time 36407526 ps
CPU time 1.67 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 206736 kb
Host smart-5603d737-dcf4-4338-b879-76a83f61b024
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667917582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.667917582
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.766232394
Short name T493
Test name
Test status
Simulation time 180780872 ps
CPU time 2.39 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:19 PM PDT 24
Peak memory 208744 kb
Host smart-2e61dc96-8f1f-4dba-98b3-09f9b98d489b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766232394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.766232394
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1855191929
Short name T487
Test name
Test status
Simulation time 236927060 ps
CPU time 5.22 seconds
Started Jul 26 07:24:15 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 207912 kb
Host smart-d4088c7a-2635-4fd5-95d2-8203344aaf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855191929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1855191929
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.144166554
Short name T778
Test name
Test status
Simulation time 304978771 ps
CPU time 2.79 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 208212 kb
Host smart-946178e8-2b69-496b-af71-c03f9dfcc73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144166554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.144166554
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1778892063
Short name T340
Test name
Test status
Simulation time 209498215 ps
CPU time 9.07 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:27 PM PDT 24
Peak memory 222404 kb
Host smart-44434bf0-51ff-4157-a457-3ddb0ec6da3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778892063 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1778892063
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2959813415
Short name T779
Test name
Test status
Simulation time 506886022 ps
CPU time 6.31 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:22 PM PDT 24
Peak memory 214004 kb
Host smart-ebb62fa3-90c8-4c79-af6a-2a376a023321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959813415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2959813415
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1020322708
Short name T531
Test name
Test status
Simulation time 182393311 ps
CPU time 1.85 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 209884 kb
Host smart-b065a99b-2400-4ebb-988e-bfa8c39a62ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020322708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1020322708
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.388351383
Short name T448
Test name
Test status
Simulation time 21668955 ps
CPU time 0.74 seconds
Started Jul 26 07:24:20 PM PDT 24
Finished Jul 26 07:24:21 PM PDT 24
Peak memory 205844 kb
Host smart-d1d749e2-f054-4f17-9710-8d4cc48b79ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388351383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.388351383
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2456229967
Short name T276
Test name
Test status
Simulation time 214915702 ps
CPU time 4.22 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:22 PM PDT 24
Peak memory 215420 kb
Host smart-083a96d6-c1b9-47bb-8b19-97da4c8945ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456229967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2456229967
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.359781192
Short name T66
Test name
Test status
Simulation time 1030124350 ps
CPU time 13.63 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:31 PM PDT 24
Peak memory 220584 kb
Host smart-3a82410c-006d-4043-9033-b3177f6d03e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359781192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.359781192
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3611890673
Short name T535
Test name
Test status
Simulation time 42942525 ps
CPU time 1.65 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 207220 kb
Host smart-3f8ca994-235a-4ad0-b3b2-dcf351b63c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611890673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3611890673
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3694195602
Short name T97
Test name
Test status
Simulation time 208971092 ps
CPU time 5.07 seconds
Started Jul 26 07:24:21 PM PDT 24
Finished Jul 26 07:24:26 PM PDT 24
Peak memory 209688 kb
Host smart-f3dfd28c-619f-407b-80de-34b409149782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694195602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3694195602
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1004579851
Short name T361
Test name
Test status
Simulation time 450281289 ps
CPU time 5.68 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:24 PM PDT 24
Peak memory 214172 kb
Host smart-f905eb86-d3ca-4cfa-97fc-555afe50b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004579851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1004579851
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2401531703
Short name T786
Test name
Test status
Simulation time 310574530 ps
CPU time 3.72 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 209028 kb
Host smart-0e7a3e48-f959-4501-8c35-8d8236c8db50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401531703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2401531703
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.389879792
Short name T702
Test name
Test status
Simulation time 187640205 ps
CPU time 6.45 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:25 PM PDT 24
Peak memory 218108 kb
Host smart-ba6cc250-8d35-4449-96ee-f41e88222037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389879792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.389879792
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2173445733
Short name T833
Test name
Test status
Simulation time 58382340 ps
CPU time 2.79 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 206716 kb
Host smart-87f27971-c26b-4c45-b010-c65a46aa0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173445733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2173445733
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1747603001
Short name T596
Test name
Test status
Simulation time 389115607 ps
CPU time 4.49 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:22 PM PDT 24
Peak memory 208672 kb
Host smart-5299508c-6030-4827-a897-97e04619eae8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747603001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1747603001
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2716652995
Short name T740
Test name
Test status
Simulation time 53378418 ps
CPU time 2.54 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:22 PM PDT 24
Peak memory 208668 kb
Host smart-f6513578-eefd-471a-bc27-b2c6ada060b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716652995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2716652995
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2441658752
Short name T257
Test name
Test status
Simulation time 275336871 ps
CPU time 3.64 seconds
Started Jul 26 07:24:16 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 206824 kb
Host smart-3d8b7b42-6ba5-4c93-872e-6e10bb32c14b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441658752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2441658752
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1725436589
Short name T15
Test name
Test status
Simulation time 66857621 ps
CPU time 2.75 seconds
Started Jul 26 07:24:17 PM PDT 24
Finished Jul 26 07:24:20 PM PDT 24
Peak memory 214116 kb
Host smart-689d8bb2-3c22-42b3-899b-8178a62a44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725436589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1725436589
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3273700791
Short name T813
Test name
Test status
Simulation time 197827569 ps
CPU time 4.86 seconds
Started Jul 26 07:24:18 PM PDT 24
Finished Jul 26 07:24:23 PM PDT 24
Peak memory 206648 kb
Host smart-3e9a40af-b101-4045-a6e2-1baa17b6d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273700791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3273700791
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2810454330
Short name T369
Test name
Test status
Simulation time 12701354313 ps
CPU time 112.81 seconds
Started Jul 26 07:24:21 PM PDT 24
Finished Jul 26 07:26:14 PM PDT 24
Peak memory 218536 kb
Host smart-75edacef-a05f-4bce-9341-571b837bd3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810454330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2810454330
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.944561590
Short name T867
Test name
Test status
Simulation time 3958512049 ps
CPU time 13.96 seconds
Started Jul 26 07:24:21 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 222384 kb
Host smart-b53c512f-985f-4b6f-bd56-de7fdbcc482c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944561590 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.944561590
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3486749141
Short name T481
Test name
Test status
Simulation time 463171232 ps
CPU time 9.14 seconds
Started Jul 26 07:24:19 PM PDT 24
Finished Jul 26 07:24:28 PM PDT 24
Peak memory 207484 kb
Host smart-7e5f7add-fa55-4267-afb5-80b5b5ecfb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486749141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3486749141
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2781959418
Short name T178
Test name
Test status
Simulation time 203612889 ps
CPU time 2.03 seconds
Started Jul 26 07:24:21 PM PDT 24
Finished Jul 26 07:24:23 PM PDT 24
Peak memory 209936 kb
Host smart-6a285d97-6137-47b3-bb03-7509dc7310d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781959418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2781959418
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1012431940
Short name T817
Test name
Test status
Simulation time 8014221 ps
CPU time 0.81 seconds
Started Jul 26 07:24:28 PM PDT 24
Finished Jul 26 07:24:29 PM PDT 24
Peak memory 205868 kb
Host smart-d8d22493-0021-496e-984a-cd5c10c65b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012431940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1012431940
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2923773186
Short name T403
Test name
Test status
Simulation time 38033983 ps
CPU time 2.76 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:32 PM PDT 24
Peak memory 214208 kb
Host smart-6e11b8dc-c6e9-4b74-a2db-f68ab06d1569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923773186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2923773186
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.870835853
Short name T31
Test name
Test status
Simulation time 117429981 ps
CPU time 2.68 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 214364 kb
Host smart-ee340b77-c666-4831-9717-fb7a2b3226e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870835853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.870835853
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1591750467
Short name T900
Test name
Test status
Simulation time 24632019 ps
CPU time 1.72 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 207724 kb
Host smart-e2e4f9c8-ff95-444c-a3c6-d5a311b79da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591750467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1591750467
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1843661214
Short name T100
Test name
Test status
Simulation time 89283976 ps
CPU time 4.22 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:38 PM PDT 24
Peak memory 214316 kb
Host smart-1313ca82-034a-44e4-a98c-c3f270803dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843661214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1843661214
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3831607976
Short name T322
Test name
Test status
Simulation time 414194959 ps
CPU time 3.97 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 206788 kb
Host smart-616f8163-0749-4786-86ce-b97bb3fd50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831607976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3831607976
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4001356153
Short name T50
Test name
Test status
Simulation time 99736795 ps
CPU time 1.8 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 222332 kb
Host smart-c44bf6d8-06e7-4591-a952-8c3ed8ea9341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001356153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4001356153
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2115768162
Short name T204
Test name
Test status
Simulation time 611944559 ps
CPU time 4.25 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 209068 kb
Host smart-2533da24-2c57-4069-a2ed-e02c3ca7f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115768162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2115768162
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2178132756
Short name T791
Test name
Test status
Simulation time 318005956 ps
CPU time 6.7 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 206888 kb
Host smart-19a78fa2-d15f-4a1f-bfb4-b6c71dcc1b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178132756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2178132756
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.407886910
Short name T722
Test name
Test status
Simulation time 447192202 ps
CPU time 2.9 seconds
Started Jul 26 07:24:29 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 206640 kb
Host smart-f01870f2-5516-4b69-87e8-df811dffb72e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407886910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.407886910
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3885369492
Short name T739
Test name
Test status
Simulation time 70491642 ps
CPU time 3.21 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 208428 kb
Host smart-abe1a2b2-e479-42a8-94e9-77fd656021f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885369492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3885369492
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4255486539
Short name T717
Test name
Test status
Simulation time 305417225 ps
CPU time 3.86 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 206884 kb
Host smart-58627404-9fc8-4255-a4f4-8a699401e8cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255486539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4255486539
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3777829574
Short name T879
Test name
Test status
Simulation time 145381505 ps
CPU time 2.39 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 208848 kb
Host smart-9a0b9b89-c2c1-4577-8408-dad5405bc8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777829574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3777829574
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3149867867
Short name T716
Test name
Test status
Simulation time 154430077 ps
CPU time 3.64 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 207828 kb
Host smart-8d23e14d-f9e9-49f0-8c10-e9a456e3aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149867867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3149867867
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.572089355
Short name T912
Test name
Test status
Simulation time 761430850 ps
CPU time 13.93 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 220600 kb
Host smart-1d237e19-b64f-487c-95d7-859557d5c720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572089355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.572089355
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2554697389
Short name T327
Test name
Test status
Simulation time 511342744 ps
CPU time 14.04 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:45 PM PDT 24
Peak memory 222428 kb
Host smart-f0b2df71-fba9-4585-afb3-1c4f7ee62e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554697389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2554697389
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2213110805
Short name T282
Test name
Test status
Simulation time 3902261390 ps
CPU time 52.43 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 208076 kb
Host smart-bba693e4-c81f-4433-846f-9fe3e4de8961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213110805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2213110805
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2510545411
Short name T453
Test name
Test status
Simulation time 70620509 ps
CPU time 2.86 seconds
Started Jul 26 07:24:29 PM PDT 24
Finished Jul 26 07:24:32 PM PDT 24
Peak memory 209900 kb
Host smart-37954980-2748-40ec-a1ca-fb1ebc9c68a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510545411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2510545411
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4294770342
Short name T107
Test name
Test status
Simulation time 20266580 ps
CPU time 0.72 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:30 PM PDT 24
Peak memory 205880 kb
Host smart-6257af7e-8f34-4f10-99a6-fa0df851af67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294770342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4294770342
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1330973707
Short name T79
Test name
Test status
Simulation time 204722869 ps
CPU time 2.97 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 214884 kb
Host smart-e041c628-80c1-4431-ad78-4ca455a7b618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330973707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1330973707
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1045949519
Short name T148
Test name
Test status
Simulation time 197594442 ps
CPU time 1.57 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:32 PM PDT 24
Peak memory 208544 kb
Host smart-2a0efedf-cb59-43b3-a387-b1fda068d1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045949519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1045949519
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3817351319
Short name T501
Test name
Test status
Simulation time 47628144 ps
CPU time 2.02 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 214208 kb
Host smart-8e547057-098f-4b20-bcac-59b43a9fcc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817351319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3817351319
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2320955511
Short name T104
Test name
Test status
Simulation time 677783265 ps
CPU time 5.28 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:40 PM PDT 24
Peak memory 214236 kb
Host smart-e3cfc01b-7d3b-427c-a8e6-57f5beb1561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320955511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2320955511
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3923954635
Short name T91
Test name
Test status
Simulation time 296408187 ps
CPU time 4.05 seconds
Started Jul 26 07:24:28 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 220612 kb
Host smart-81cb455e-9b7e-4876-98e8-c580898a7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923954635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3923954635
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_random.387470145
Short name T113
Test name
Test status
Simulation time 64284925 ps
CPU time 3.9 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 210316 kb
Host smart-e66f1eb8-6897-4615-b4dc-8b5cd09b47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387470145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.387470145
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3171630120
Short name T532
Test name
Test status
Simulation time 254833630 ps
CPU time 6.81 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 208076 kb
Host smart-abc4f18e-6040-4ee9-85ee-b4a360c03658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171630120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3171630120
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3271960101
Short name T586
Test name
Test status
Simulation time 230055643 ps
CPU time 2.4 seconds
Started Jul 26 07:24:29 PM PDT 24
Finished Jul 26 07:24:31 PM PDT 24
Peak memory 206764 kb
Host smart-24c4f0db-b355-4714-8598-f7cb8b084c8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271960101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3271960101
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2945303817
Short name T110
Test name
Test status
Simulation time 4169995742 ps
CPU time 12.1 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:24:43 PM PDT 24
Peak memory 208912 kb
Host smart-2c91535b-92be-49d7-84b2-832b2c3a2796
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945303817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2945303817
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2628594530
Short name T515
Test name
Test status
Simulation time 67504291 ps
CPU time 3.27 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:38 PM PDT 24
Peak memory 207744 kb
Host smart-fb798215-c22f-4ede-be80-415049e0d5e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628594530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2628594530
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4127395024
Short name T566
Test name
Test status
Simulation time 249101263 ps
CPU time 2.74 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 208696 kb
Host smart-2bdd7f50-5c5b-4527-bf1d-472f575c1cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127395024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4127395024
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.938160688
Short name T632
Test name
Test status
Simulation time 138050757 ps
CPU time 3.26 seconds
Started Jul 26 07:24:28 PM PDT 24
Finished Jul 26 07:24:31 PM PDT 24
Peak memory 206604 kb
Host smart-04d7e422-31e0-4f04-89c8-7032920cc562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938160688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.938160688
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1923386113
Short name T301
Test name
Test status
Simulation time 3896926119 ps
CPU time 37.69 seconds
Started Jul 26 07:24:31 PM PDT 24
Finished Jul 26 07:25:08 PM PDT 24
Peak memory 222380 kb
Host smart-2b70a05c-5f8f-4497-8945-240af8ade089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923386113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1923386113
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1672109359
Short name T367
Test name
Test status
Simulation time 338897066 ps
CPU time 13.43 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 222332 kb
Host smart-da207760-b16e-4801-b375-9a29ec1b186d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672109359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1672109359
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3939066682
Short name T34
Test name
Test status
Simulation time 309282853 ps
CPU time 2.44 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 210216 kb
Host smart-41ef1602-b24a-4701-809a-89bbf7fd35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939066682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3939066682
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3388087555
Short name T505
Test name
Test status
Simulation time 74159653 ps
CPU time 0.75 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:34 PM PDT 24
Peak memory 205940 kb
Host smart-e911cfa8-7638-46b5-b60f-0aa275791209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388087555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3388087555
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2591006850
Short name T38
Test name
Test status
Simulation time 119389998 ps
CPU time 2.94 seconds
Started Jul 26 07:24:36 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 220588 kb
Host smart-b146f140-0352-4b09-9365-c4407470e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591006850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2591006850
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2921096836
Short name T859
Test name
Test status
Simulation time 147125777 ps
CPU time 2.7 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 214136 kb
Host smart-c9bbf2f6-dcd3-4eb9-9544-fbf26ca8e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921096836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2921096836
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1710870356
Short name T751
Test name
Test status
Simulation time 355357787 ps
CPU time 2.91 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 214252 kb
Host smart-2459bfaa-ca7a-43af-8a06-d2f04e70fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710870356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1710870356
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2860751733
Short name T380
Test name
Test status
Simulation time 375274233 ps
CPU time 3.3 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 214156 kb
Host smart-67e04958-ff6f-4c13-a830-e8fa7b4d0856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860751733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2860751733
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2836660414
Short name T559
Test name
Test status
Simulation time 34633925 ps
CPU time 2.29 seconds
Started Jul 26 07:24:37 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 206708 kb
Host smart-6f26ef85-00e9-45ef-86c9-14058efea2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836660414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2836660414
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2352638733
Short name T736
Test name
Test status
Simulation time 301705463 ps
CPU time 4.06 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 209812 kb
Host smart-636bc415-6d96-4158-82e7-589a1ae92672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352638733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2352638733
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.740600374
Short name T608
Test name
Test status
Simulation time 365458463 ps
CPU time 5.9 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:38 PM PDT 24
Peak memory 206108 kb
Host smart-a1945a82-71e6-4a25-aad7-2855b69a30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740600374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.740600374
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1768164261
Short name T750
Test name
Test status
Simulation time 332673421 ps
CPU time 3.11 seconds
Started Jul 26 07:24:28 PM PDT 24
Finished Jul 26 07:24:31 PM PDT 24
Peak memory 206760 kb
Host smart-42aa2d6e-fd8f-4a20-8cbe-6f4d5cd5c2f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768164261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1768164261
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2060487108
Short name T310
Test name
Test status
Simulation time 96167333 ps
CPU time 3.01 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 208560 kb
Host smart-9ea22b40-0cf1-4860-8b59-a6d08d2e6f75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060487108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2060487108
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2219866933
Short name T868
Test name
Test status
Simulation time 645329651 ps
CPU time 5.92 seconds
Started Jul 26 07:24:29 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 207880 kb
Host smart-fe4c0fb7-7ecf-4f69-a9af-6efb2b7b5e49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219866933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2219866933
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2432851155
Short name T861
Test name
Test status
Simulation time 365991368 ps
CPU time 7.15 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:42 PM PDT 24
Peak memory 208920 kb
Host smart-664b816d-853e-4550-9cec-023e7416ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432851155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2432851155
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.268949991
Short name T674
Test name
Test status
Simulation time 633902373 ps
CPU time 3.65 seconds
Started Jul 26 07:24:32 PM PDT 24
Finished Jul 26 07:24:35 PM PDT 24
Peak memory 207296 kb
Host smart-182eb587-23da-4c18-ac7b-6e947042111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268949991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.268949991
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3069156315
Short name T377
Test name
Test status
Simulation time 307457069 ps
CPU time 12.08 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:47 PM PDT 24
Peak memory 216348 kb
Host smart-c0643ea3-6e5a-452f-9b6f-4a427c404647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069156315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3069156315
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.5161686
Short name T685
Test name
Test status
Simulation time 234211259 ps
CPU time 6.43 seconds
Started Jul 26 07:24:36 PM PDT 24
Finished Jul 26 07:24:43 PM PDT 24
Peak memory 208948 kb
Host smart-18d24a87-a48e-4ea3-9131-a2097c5ab613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5161686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.5161686
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1478558335
Short name T454
Test name
Test status
Simulation time 406958215 ps
CPU time 2.82 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:33 PM PDT 24
Peak memory 210336 kb
Host smart-41450997-d718-4ed9-98c2-7aa349473c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478558335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1478558335
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3299476014
Short name T538
Test name
Test status
Simulation time 20496055 ps
CPU time 0.81 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 205820 kb
Host smart-54d51dc3-e41f-4e2d-a896-48e9ea0568a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299476014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3299476014
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.353496133
Short name T405
Test name
Test status
Simulation time 493005280 ps
CPU time 4.28 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:38 PM PDT 24
Peak memory 214088 kb
Host smart-e4970b85-ed36-43f5-9ac6-f324086029f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353496133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.353496133
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3678457988
Short name T734
Test name
Test status
Simulation time 107828410 ps
CPU time 1.97 seconds
Started Jul 26 07:24:36 PM PDT 24
Finished Jul 26 07:24:38 PM PDT 24
Peak memory 215660 kb
Host smart-38bd286a-cb31-46e0-a583-6d612a31d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678457988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3678457988
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2175471736
Short name T678
Test name
Test status
Simulation time 54255736 ps
CPU time 2.31 seconds
Started Jul 26 07:24:38 PM PDT 24
Finished Jul 26 07:24:40 PM PDT 24
Peak memory 222304 kb
Host smart-002f7380-2170-45a1-9b66-93fef6cc2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175471736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2175471736
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1955450502
Short name T290
Test name
Test status
Simulation time 94167036 ps
CPU time 3 seconds
Started Jul 26 07:24:36 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 221124 kb
Host smart-8db170b8-509a-4eb0-904e-8f12c370bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955450502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1955450502
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1591815079
Short name T223
Test name
Test status
Simulation time 375697153 ps
CPU time 4.71 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:40 PM PDT 24
Peak memory 209964 kb
Host smart-0be4faca-e299-41bf-a521-394d1874f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591815079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1591815079
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1094486070
Short name T339
Test name
Test status
Simulation time 193590537 ps
CPU time 3.55 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 214180 kb
Host smart-dff0b0a2-6f0f-4f17-83c2-c90aac271fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094486070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1094486070
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2796181804
Short name T783
Test name
Test status
Simulation time 46399785 ps
CPU time 1.89 seconds
Started Jul 26 07:24:30 PM PDT 24
Finished Jul 26 07:24:32 PM PDT 24
Peak memory 208280 kb
Host smart-276c43e9-f064-42d8-a3eb-2f4c5ecd0fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796181804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2796181804
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2142993491
Short name T489
Test name
Test status
Simulation time 1943841640 ps
CPU time 24 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:58 PM PDT 24
Peak memory 207984 kb
Host smart-e634de09-f60c-43a3-bb5e-3c40ec6e7738
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142993491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2142993491
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2583542794
Short name T130
Test name
Test status
Simulation time 91014954 ps
CPU time 1.95 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 207244 kb
Host smart-45c282a3-6129-42b7-ba16-bd1c5b2e5943
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583542794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2583542794
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3339980842
Short name T328
Test name
Test status
Simulation time 243898651 ps
CPU time 3.05 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:36 PM PDT 24
Peak memory 208776 kb
Host smart-99cb758c-a710-4796-8256-4a5256369093
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339980842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3339980842
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3673368383
Short name T689
Test name
Test status
Simulation time 61230988 ps
CPU time 2.72 seconds
Started Jul 26 07:24:36 PM PDT 24
Finished Jul 26 07:24:39 PM PDT 24
Peak memory 215572 kb
Host smart-8b311d2f-f71b-40fd-8b36-42fc609d3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673368383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3673368383
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1749083012
Short name T814
Test name
Test status
Simulation time 92465502 ps
CPU time 3.04 seconds
Started Jul 26 07:24:33 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 206740 kb
Host smart-88a2a866-381d-4b29-b592-2a5838c344e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749083012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1749083012
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3206501723
Short name T298
Test name
Test status
Simulation time 1091304493 ps
CPU time 7.09 seconds
Started Jul 26 07:24:35 PM PDT 24
Finished Jul 26 07:24:42 PM PDT 24
Peak memory 218052 kb
Host smart-8ba26e6a-905b-4d34-8a66-567def41de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206501723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3206501723
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4198441437
Short name T125
Test name
Test status
Simulation time 141081690 ps
CPU time 1.94 seconds
Started Jul 26 07:24:34 PM PDT 24
Finished Jul 26 07:24:37 PM PDT 24
Peak memory 209896 kb
Host smart-9ea2373a-3dc8-491e-8796-0fdb38ce41f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198441437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4198441437
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1707397984
Short name T628
Test name
Test status
Simulation time 51379027 ps
CPU time 0.73 seconds
Started Jul 26 07:24:44 PM PDT 24
Finished Jul 26 07:24:45 PM PDT 24
Peak memory 205848 kb
Host smart-ebf51d10-e67e-41c1-9f8a-3d545c5d8e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707397984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1707397984
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.775972232
Short name T254
Test name
Test status
Simulation time 208282566 ps
CPU time 4.16 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:50 PM PDT 24
Peak memory 214908 kb
Host smart-2c790c17-9d98-4d76-8a17-2eb02b5217b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775972232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.775972232
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3909847250
Short name T691
Test name
Test status
Simulation time 77443771 ps
CPU time 2.34 seconds
Started Jul 26 07:24:43 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 214128 kb
Host smart-b93e8167-8db7-47e4-8852-ec66d35c8ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909847250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3909847250
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3240613883
Short name T72
Test name
Test status
Simulation time 304150988 ps
CPU time 2.35 seconds
Started Jul 26 07:24:43 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 207676 kb
Host smart-7d03b566-9991-4f28-ba2e-9381f5dbf414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240613883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3240613883
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1258897873
Short name T94
Test name
Test status
Simulation time 238859673 ps
CPU time 3.58 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 209000 kb
Host smart-ade422d8-f5c8-4523-8ffe-2511b866e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258897873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1258897873
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2199726643
Short name T47
Test name
Test status
Simulation time 34157882 ps
CPU time 2.08 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:47 PM PDT 24
Peak memory 214076 kb
Host smart-a8f2f6dc-43c9-4bd9-934e-c902c354833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199726643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2199726643
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2789911937
Short name T62
Test name
Test status
Simulation time 359101491 ps
CPU time 5.56 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:24:53 PM PDT 24
Peak memory 210384 kb
Host smart-fa0b7208-5409-4bfd-b715-d9fb9ac5a101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789911937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2789911937
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1555747635
Short name T315
Test name
Test status
Simulation time 447774219 ps
CPU time 5.98 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:24:53 PM PDT 24
Peak memory 214096 kb
Host smart-dbcb123c-d8ed-4967-804b-2ff6ec2af114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555747635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1555747635
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1169742322
Short name T474
Test name
Test status
Simulation time 160467537 ps
CPU time 2.8 seconds
Started Jul 26 07:24:49 PM PDT 24
Finished Jul 26 07:24:51 PM PDT 24
Peak memory 208484 kb
Host smart-3dae5405-0880-4a5c-89dc-81a14cfe0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169742322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1169742322
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2323364200
Short name T881
Test name
Test status
Simulation time 339864353 ps
CPU time 2.93 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:49 PM PDT 24
Peak memory 206736 kb
Host smart-0d2fbf4b-7be3-41f3-9b57-337b6ebaad49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323364200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2323364200
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.4210101693
Short name T143
Test name
Test status
Simulation time 611532349 ps
CPU time 7.54 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:54 PM PDT 24
Peak memory 207896 kb
Host smart-dc5c3d01-4707-4409-a5aa-aacacdbc7f2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210101693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.4210101693
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1269944060
Short name T829
Test name
Test status
Simulation time 22702962 ps
CPU time 1.88 seconds
Started Jul 26 07:24:44 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 206684 kb
Host smart-30f97f95-2ffd-4de3-9348-2768b7605bd3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269944060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1269944060
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1090740217
Short name T743
Test name
Test status
Simulation time 350821055 ps
CPU time 3.8 seconds
Started Jul 26 07:24:44 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 214112 kb
Host smart-13024cc8-bd1b-4fbc-a406-4ae4e43810ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090740217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1090740217
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1736401907
Short name T638
Test name
Test status
Simulation time 486464359 ps
CPU time 3.81 seconds
Started Jul 26 07:24:29 PM PDT 24
Finished Jul 26 07:24:32 PM PDT 24
Peak memory 207260 kb
Host smart-82c3c05a-b027-4117-a11e-24742fe3fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736401907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1736401907
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.434038315
Short name T226
Test name
Test status
Simulation time 728710106 ps
CPU time 23.29 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:25:09 PM PDT 24
Peak memory 215780 kb
Host smart-f979db7d-6e21-48bb-838c-6634ae3c32a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434038315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.434038315
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1402111620
Short name T268
Test name
Test status
Simulation time 2413487472 ps
CPU time 24.45 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:25:10 PM PDT 24
Peak memory 218512 kb
Host smart-77d40619-3baf-45ec-bf5a-90c1b973978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402111620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1402111620
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3306168637
Short name T383
Test name
Test status
Simulation time 76696867 ps
CPU time 1.88 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:24:49 PM PDT 24
Peak memory 209940 kb
Host smart-6dc5fbb1-86f9-4f07-ab4f-2254de93d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306168637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3306168637
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2169524047
Short name T463
Test name
Test status
Simulation time 8757533 ps
CPU time 0.82 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:21:36 PM PDT 24
Peak memory 205896 kb
Host smart-36ee9777-63aa-4a49-a0a1-17db0688a777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169524047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2169524047
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1458881830
Short name T18
Test name
Test status
Simulation time 143117563 ps
CPU time 1.31 seconds
Started Jul 26 07:21:22 PM PDT 24
Finished Jul 26 07:21:24 PM PDT 24
Peak memory 222548 kb
Host smart-51e4ae28-af7f-4f46-81b1-045be1cdb44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458881830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1458881830
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2953630728
Short name T821
Test name
Test status
Simulation time 19291049 ps
CPU time 1.32 seconds
Started Jul 26 07:21:26 PM PDT 24
Finished Jul 26 07:21:27 PM PDT 24
Peak memory 207460 kb
Host smart-c5850c1f-bf92-4327-8b3b-72a5b30a81c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953630728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2953630728
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3440625097
Short name T848
Test name
Test status
Simulation time 61621455 ps
CPU time 3.25 seconds
Started Jul 26 07:21:32 PM PDT 24
Finished Jul 26 07:21:36 PM PDT 24
Peak memory 208268 kb
Host smart-5ffbf037-6030-4eef-aa6f-a5a1a77a6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440625097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3440625097
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1200909538
Short name T302
Test name
Test status
Simulation time 592670130 ps
CPU time 4.46 seconds
Started Jul 26 07:21:28 PM PDT 24
Finished Jul 26 07:21:33 PM PDT 24
Peak memory 214056 kb
Host smart-9e3972f9-6710-4898-a251-01199c96e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200909538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1200909538
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1581330677
Short name T2
Test name
Test status
Simulation time 92379020 ps
CPU time 4.66 seconds
Started Jul 26 07:21:34 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 210068 kb
Host smart-4776c1da-2c53-4899-aa5b-8d878fc0fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581330677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1581330677
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2035681623
Short name T802
Test name
Test status
Simulation time 76948717 ps
CPU time 3.32 seconds
Started Jul 26 07:21:26 PM PDT 24
Finished Jul 26 07:21:29 PM PDT 24
Peak memory 207076 kb
Host smart-08920a37-5805-43e9-9108-b01857016413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035681623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2035681623
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1280205835
Short name T10
Test name
Test status
Simulation time 2148417551 ps
CPU time 18.74 seconds
Started Jul 26 07:21:38 PM PDT 24
Finished Jul 26 07:21:57 PM PDT 24
Peak memory 240164 kb
Host smart-2724a1a5-1fe3-4da0-84a7-9e4e5a969a27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280205835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1280205835
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.380450502
Short name T907
Test name
Test status
Simulation time 211997688 ps
CPU time 3.13 seconds
Started Jul 26 07:21:33 PM PDT 24
Finished Jul 26 07:21:36 PM PDT 24
Peak memory 206564 kb
Host smart-18eec14a-bab4-4b48-bd4d-5db7fb965122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380450502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.380450502
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2637947119
Short name T756
Test name
Test status
Simulation time 2448055736 ps
CPU time 16.61 seconds
Started Jul 26 07:21:28 PM PDT 24
Finished Jul 26 07:21:45 PM PDT 24
Peak memory 208108 kb
Host smart-25269864-1f26-4c3e-a56b-0fcb4afa537f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637947119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2637947119
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3016292086
Short name T735
Test name
Test status
Simulation time 81047750 ps
CPU time 3.67 seconds
Started Jul 26 07:21:31 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 208712 kb
Host smart-812ec5d5-fb9f-4819-94bf-dacc823a75e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016292086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3016292086
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.987082616
Short name T520
Test name
Test status
Simulation time 27917554 ps
CPU time 1.99 seconds
Started Jul 26 07:21:33 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 208344 kb
Host smart-5ba7ddf3-c19c-42b0-8a8b-b7282a3c6a56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987082616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.987082616
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2552534189
Short name T728
Test name
Test status
Simulation time 95692599 ps
CPU time 3.92 seconds
Started Jul 26 07:21:21 PM PDT 24
Finished Jul 26 07:21:25 PM PDT 24
Peak memory 218020 kb
Host smart-22d2bd80-c0b9-4f42-b938-8c71564cbb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552534189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2552534189
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3931337841
Short name T723
Test name
Test status
Simulation time 68214241 ps
CPU time 2.56 seconds
Started Jul 26 07:21:22 PM PDT 24
Finished Jul 26 07:21:25 PM PDT 24
Peak memory 208232 kb
Host smart-c7ac6607-cf2d-4023-ac23-b495b150106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931337841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3931337841
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2816815574
Short name T251
Test name
Test status
Simulation time 80750337 ps
CPU time 3.59 seconds
Started Jul 26 07:21:30 PM PDT 24
Finished Jul 26 07:21:34 PM PDT 24
Peak memory 218300 kb
Host smart-50471a62-00d8-489d-aa23-69e33f1abac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816815574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2816815574
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1256361950
Short name T644
Test name
Test status
Simulation time 50695408 ps
CPU time 2.08 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 209752 kb
Host smart-fbe5a2cb-c5de-43c3-bfd5-0a3d136a8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256361950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1256361950
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1826514747
Short name T494
Test name
Test status
Simulation time 92888561 ps
CPU time 0.77 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:46 PM PDT 24
Peak memory 205828 kb
Host smart-5ebf8589-b670-48e1-9231-2b2df8ac6f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826514747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1826514747
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2466439137
Short name T296
Test name
Test status
Simulation time 213319547 ps
CPU time 11.19 seconds
Started Jul 26 07:24:48 PM PDT 24
Finished Jul 26 07:24:59 PM PDT 24
Peak memory 214168 kb
Host smart-05bf8280-a534-4e9f-b4d8-4d94af04dd59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466439137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2466439137
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3998761106
Short name T39
Test name
Test status
Simulation time 128974396 ps
CPU time 5.63 seconds
Started Jul 26 07:24:49 PM PDT 24
Finished Jul 26 07:24:54 PM PDT 24
Peak memory 210244 kb
Host smart-9b260dce-452d-42be-ab9e-f0574126970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998761106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3998761106
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2918900793
Short name T471
Test name
Test status
Simulation time 22715097 ps
CPU time 1.59 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:24:49 PM PDT 24
Peak memory 208184 kb
Host smart-d7494bc3-0a6a-4016-90ba-af0f90a8d643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918900793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2918900793
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2200546478
Short name T36
Test name
Test status
Simulation time 54285354 ps
CPU time 3.02 seconds
Started Jul 26 07:24:49 PM PDT 24
Finished Jul 26 07:24:52 PM PDT 24
Peak memory 214124 kb
Host smart-698385cf-2b34-4404-80a8-de2fff786e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200546478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2200546478
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.683369877
Short name T569
Test name
Test status
Simulation time 398961623 ps
CPU time 3.44 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 214092 kb
Host smart-af891b3f-9a91-43fb-9d93-98161c858235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683369877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.683369877
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2050104192
Short name T293
Test name
Test status
Simulation time 82888171 ps
CPU time 5.02 seconds
Started Jul 26 07:24:43 PM PDT 24
Finished Jul 26 07:24:49 PM PDT 24
Peak memory 210708 kb
Host smart-fdf736b9-e83d-42d9-8942-2db3bf965059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050104192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2050104192
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2687245464
Short name T447
Test name
Test status
Simulation time 313248578 ps
CPU time 11.62 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:58 PM PDT 24
Peak memory 214108 kb
Host smart-f8ba8f3a-181d-4223-b391-879fd137c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687245464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2687245464
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.972763357
Short name T346
Test name
Test status
Simulation time 389543552 ps
CPU time 4.89 seconds
Started Jul 26 07:24:43 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 207896 kb
Host smart-cb2452dc-9cc9-45aa-814a-1a9bbd5d564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972763357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.972763357
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2383648386
Short name T516
Test name
Test status
Simulation time 73715566 ps
CPU time 2.33 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:47 PM PDT 24
Peak memory 206616 kb
Host smart-7f7a6bb1-653b-4000-a933-ecad747d4c74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383648386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2383648386
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3976964559
Short name T468
Test name
Test status
Simulation time 441502461 ps
CPU time 2.83 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:49 PM PDT 24
Peak memory 206796 kb
Host smart-6e4058fc-d99e-48a5-b322-042a411928d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976964559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3976964559
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2349283286
Short name T551
Test name
Test status
Simulation time 1707196503 ps
CPU time 54.43 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:25:41 PM PDT 24
Peak memory 208920 kb
Host smart-02b18b3c-3b94-4266-928a-73f72f534da6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349283286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2349283286
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.210545910
Short name T760
Test name
Test status
Simulation time 857353590 ps
CPU time 2.92 seconds
Started Jul 26 07:24:44 PM PDT 24
Finished Jul 26 07:24:47 PM PDT 24
Peak memory 208508 kb
Host smart-eb8c62af-9e64-4204-8ee7-0a6197848658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210545910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.210545910
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.629940887
Short name T78
Test name
Test status
Simulation time 141020133 ps
CPU time 2.4 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:24:50 PM PDT 24
Peak memory 207292 kb
Host smart-eef8955d-9477-4d71-84cc-947ef21ee10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629940887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.629940887
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.270023345
Short name T6
Test name
Test status
Simulation time 4099962863 ps
CPU time 26.66 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:25:11 PM PDT 24
Peak memory 216232 kb
Host smart-0fad504a-1659-42d1-834d-5fcb7288d66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270023345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.270023345
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1541920058
Short name T273
Test name
Test status
Simulation time 894647946 ps
CPU time 31.67 seconds
Started Jul 26 07:24:48 PM PDT 24
Finished Jul 26 07:25:20 PM PDT 24
Peak memory 222512 kb
Host smart-e1cfe788-f562-4446-a41a-4fc2d0dd246e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541920058 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1541920058
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1683602913
Short name T626
Test name
Test status
Simulation time 379115217 ps
CPU time 4.01 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:24:50 PM PDT 24
Peak memory 218088 kb
Host smart-95b917a6-5b2d-4650-a107-f709b2eb6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683602913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1683602913
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.829691474
Short name T758
Test name
Test status
Simulation time 39300289 ps
CPU time 2.18 seconds
Started Jul 26 07:24:45 PM PDT 24
Finished Jul 26 07:24:48 PM PDT 24
Peak memory 210000 kb
Host smart-f05cf2f5-3658-4fc1-9e1d-0a3baadf7cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829691474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.829691474
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2998091738
Short name T711
Test name
Test status
Simulation time 60670102 ps
CPU time 0.84 seconds
Started Jul 26 07:24:54 PM PDT 24
Finished Jul 26 07:24:55 PM PDT 24
Peak memory 206040 kb
Host smart-f13ed429-db98-4d67-9bb6-bf8d8f5d118b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998091738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2998091738
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3746468321
Short name T241
Test name
Test status
Simulation time 59095300 ps
CPU time 3.77 seconds
Started Jul 26 07:24:54 PM PDT 24
Finished Jul 26 07:24:57 PM PDT 24
Peak memory 214208 kb
Host smart-d091b46c-e1ee-48a2-b975-fbe2396ca8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746468321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3746468321
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3234560119
Short name T869
Test name
Test status
Simulation time 4304908803 ps
CPU time 14.63 seconds
Started Jul 26 07:24:57 PM PDT 24
Finished Jul 26 07:25:12 PM PDT 24
Peak memory 208320 kb
Host smart-c52af948-899f-48ee-91a4-11a6caaeba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234560119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3234560119
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1806062021
Short name T591
Test name
Test status
Simulation time 169528116 ps
CPU time 2.11 seconds
Started Jul 26 07:24:59 PM PDT 24
Finished Jul 26 07:25:01 PM PDT 24
Peak memory 214176 kb
Host smart-3bed2cb2-88ec-458c-b01d-f8443128d714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806062021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1806062021
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2544987019
Short name T261
Test name
Test status
Simulation time 129698467 ps
CPU time 2.96 seconds
Started Jul 26 07:24:57 PM PDT 24
Finished Jul 26 07:25:01 PM PDT 24
Peak memory 214092 kb
Host smart-a5188561-7958-492e-8836-149bbb427e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544987019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2544987019
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3517547083
Short name T662
Test name
Test status
Simulation time 213507673 ps
CPU time 3.12 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 222320 kb
Host smart-b6fbb85a-dd4c-4e65-aead-0404b96bc362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517547083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3517547083
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1092446320
Short name T836
Test name
Test status
Simulation time 88798044 ps
CPU time 3.89 seconds
Started Jul 26 07:24:59 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 208588 kb
Host smart-98962dcf-a814-47bf-a845-02ab43c48df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092446320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1092446320
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2821615272
Short name T759
Test name
Test status
Simulation time 1397729540 ps
CPU time 16.69 seconds
Started Jul 26 07:24:47 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 207952 kb
Host smart-7fbc8dc9-a46b-4082-a355-fe5a2d7b488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821615272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2821615272
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1729402254
Short name T880
Test name
Test status
Simulation time 744849286 ps
CPU time 3.42 seconds
Started Jul 26 07:24:54 PM PDT 24
Finished Jul 26 07:24:57 PM PDT 24
Peak memory 208524 kb
Host smart-24d5e49a-322e-4303-80c0-3c6d3b99ac7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729402254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1729402254
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1958200713
Short name T558
Test name
Test status
Simulation time 34986804 ps
CPU time 2.58 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 208624 kb
Host smart-a738c1ad-ea54-4ea8-bd63-4f6fef0be343
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958200713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1958200713
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.672999784
Short name T911
Test name
Test status
Simulation time 729813675 ps
CPU time 3.9 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:57 PM PDT 24
Peak memory 207924 kb
Host smart-b5e30d17-d39b-4d04-be3d-62f07d0bafa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672999784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.672999784
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.766624670
Short name T451
Test name
Test status
Simulation time 211033427 ps
CPU time 2.14 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 208024 kb
Host smart-26a1c06b-44a1-4217-bc19-8cb349c6193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766624670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.766624670
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4074549774
Short name T768
Test name
Test status
Simulation time 762805807 ps
CPU time 15.52 seconds
Started Jul 26 07:24:46 PM PDT 24
Finished Jul 26 07:25:01 PM PDT 24
Peak memory 208812 kb
Host smart-5f025c37-3dbd-44ee-97ab-c45a1522e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074549774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4074549774
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2036713558
Short name T193
Test name
Test status
Simulation time 592962520 ps
CPU time 6.78 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:25:00 PM PDT 24
Peak memory 208940 kb
Host smart-f27097e0-2519-4759-9c6d-412825fd5649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036713558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2036713558
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1469187300
Short name T382
Test name
Test status
Simulation time 85394784 ps
CPU time 2.22 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 209896 kb
Host smart-eddf7cfb-85ed-4063-b14e-ecb064b249cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469187300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1469187300
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3697747029
Short name T875
Test name
Test status
Simulation time 14873481 ps
CPU time 0.94 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 206088 kb
Host smart-c52aa967-a01c-469f-92f7-2c23e0c3af93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697747029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3697747029
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2323739000
Short name T269
Test name
Test status
Simulation time 56470220 ps
CPU time 4.18 seconds
Started Jul 26 07:24:59 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 215256 kb
Host smart-c21daed5-7e77-416e-9a4f-fbcf53c4515d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323739000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2323739000
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2419972238
Short name T908
Test name
Test status
Simulation time 121626776 ps
CPU time 3.19 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 214456 kb
Host smart-9dd25706-d102-4439-b7bc-ceabb3fc467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419972238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2419972238
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.674923039
Short name T351
Test name
Test status
Simulation time 194797924 ps
CPU time 3.41 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 208056 kb
Host smart-15772da6-a6ec-4373-8c0e-fe7b585550c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674923039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.674923039
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1367294913
Short name T335
Test name
Test status
Simulation time 62665262 ps
CPU time 2.64 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 214168 kb
Host smart-e545f2d7-bfdf-4eea-b846-157a72bda8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367294913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1367294913
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3882687284
Short name T379
Test name
Test status
Simulation time 5525062457 ps
CPU time 14.89 seconds
Started Jul 26 07:24:52 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 214408 kb
Host smart-d4cfd427-d0c3-4642-aa90-531e6d39a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882687284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3882687284
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4116680145
Short name T229
Test name
Test status
Simulation time 469719227 ps
CPU time 4.19 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 209428 kb
Host smart-afbf50b4-7e38-4b2b-964f-6a8e09d321f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116680145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4116680145
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4005013877
Short name T356
Test name
Test status
Simulation time 198991432 ps
CPU time 5.62 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 218212 kb
Host smart-a0a9c1ec-e1aa-42f0-b370-19561fabbbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005013877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4005013877
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1633086092
Short name T605
Test name
Test status
Simulation time 525158390 ps
CPU time 2.92 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 208560 kb
Host smart-576559bf-9863-4f89-a2b3-69e11206be8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633086092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1633086092
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1347531636
Short name T546
Test name
Test status
Simulation time 131846133 ps
CPU time 5.16 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:09 PM PDT 24
Peak memory 208512 kb
Host smart-73b7e85e-a2da-4201-bbae-e4743e571e96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347531636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1347531636
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3146223538
Short name T675
Test name
Test status
Simulation time 249766011 ps
CPU time 4.33 seconds
Started Jul 26 07:24:51 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 208916 kb
Host smart-a459545a-fe85-463d-bccb-d25261241109
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146223538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3146223538
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1536018578
Short name T806
Test name
Test status
Simulation time 154795795 ps
CPU time 2.45 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 206848 kb
Host smart-b3ec954f-86de-41e1-8869-2bf512348acf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536018578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1536018578
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1574753305
Short name T803
Test name
Test status
Simulation time 588489357 ps
CPU time 4.75 seconds
Started Jul 26 07:24:59 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 209816 kb
Host smart-198fa07c-d87b-464b-a6d7-bf90a54ff498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574753305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1574753305
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3010158420
Short name T523
Test name
Test status
Simulation time 50247773 ps
CPU time 2.45 seconds
Started Jul 26 07:24:51 PM PDT 24
Finished Jul 26 07:24:53 PM PDT 24
Peak memory 206716 kb
Host smart-769f5053-62b4-4f1c-9a9d-ccecc88423a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010158420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3010158420
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.333117062
Short name T332
Test name
Test status
Simulation time 507672162 ps
CPU time 20.17 seconds
Started Jul 26 07:24:59 PM PDT 24
Finished Jul 26 07:25:20 PM PDT 24
Peak memory 215156 kb
Host smart-f34f02f7-fe32-4a66-a6ec-f5ef73f3bcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333117062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.333117062
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3338643328
Short name T279
Test name
Test status
Simulation time 549223482 ps
CPU time 5.69 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 207436 kb
Host smart-345f8b9e-9e46-4102-9462-f11003abe050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338643328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3338643328
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.312640387
Short name T599
Test name
Test status
Simulation time 3206636471 ps
CPU time 28.72 seconds
Started Jul 26 07:24:54 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 211240 kb
Host smart-ed239bc5-8ebb-42ac-96f3-047ab33890fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312640387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.312640387
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3347640877
Short name T710
Test name
Test status
Simulation time 27864737 ps
CPU time 0.77 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:02 PM PDT 24
Peak memory 205712 kb
Host smart-773d257b-3354-4518-b133-fecfdf310638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347640877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3347640877
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1983816434
Short name T502
Test name
Test status
Simulation time 56394413 ps
CPU time 2.7 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 214384 kb
Host smart-857b968d-a13b-4b48-9181-0a078a66f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983816434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1983816434
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.271835999
Short name T444
Test name
Test status
Simulation time 135226757 ps
CPU time 3.59 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:08 PM PDT 24
Peak memory 208060 kb
Host smart-176cc61f-d2aa-4095-8441-f2a35c7dca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271835999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.271835999
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2596636533
Short name T557
Test name
Test status
Simulation time 75977969 ps
CPU time 3.27 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 214228 kb
Host smart-df74e900-4efd-46c7-82d1-ec4e5e6b57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596636533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2596636533
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3317326754
Short name T317
Test name
Test status
Simulation time 260001023 ps
CPU time 3.82 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 220296 kb
Host smart-d6e9b443-bb5a-469f-aa1e-7915f19acbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317326754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3317326754
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2087324094
Short name T484
Test name
Test status
Simulation time 140425370 ps
CPU time 4.49 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:09 PM PDT 24
Peak memory 219976 kb
Host smart-bd64dc1c-f829-4429-a2c6-441d14e2e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087324094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2087324094
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2085242705
Short name T353
Test name
Test status
Simulation time 184812374 ps
CPU time 3.66 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 208072 kb
Host smart-1ffaeaca-4257-410b-b8dc-5b7733486253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085242705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2085242705
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3905830742
Short name T311
Test name
Test status
Simulation time 441401567 ps
CPU time 4.16 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 208524 kb
Host smart-70b12f4e-aaca-405a-b6de-bd83b6541320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905830742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3905830742
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2632302451
Short name T767
Test name
Test status
Simulation time 491755449 ps
CPU time 4.39 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 206700 kb
Host smart-b1e3f6f1-c3f3-4f38-843a-964a126f693f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632302451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2632302451
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2666558749
Short name T839
Test name
Test status
Simulation time 87484345 ps
CPU time 2.53 seconds
Started Jul 26 07:24:57 PM PDT 24
Finished Jul 26 07:25:00 PM PDT 24
Peak memory 206792 kb
Host smart-ef4eafe8-8ca4-41a9-a126-ac02d15d0e9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666558749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2666558749
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1746194721
Short name T893
Test name
Test status
Simulation time 449225835 ps
CPU time 3.08 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 208680 kb
Host smart-05bc4372-d032-490a-9e79-7321ca80f1f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746194721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1746194721
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.90066739
Short name T366
Test name
Test status
Simulation time 36272683 ps
CPU time 1.9 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 217976 kb
Host smart-374cc6ed-0549-4d2e-b4bd-2bd9fbc36300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90066739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.90066739
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2662504083
Short name T800
Test name
Test status
Simulation time 260433726 ps
CPU time 2.83 seconds
Started Jul 26 07:24:53 PM PDT 24
Finished Jul 26 07:24:56 PM PDT 24
Peak memory 206996 kb
Host smart-25fd2377-75c4-4b78-af87-61fc0201d5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662504083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2662504083
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3241920832
Short name T126
Test name
Test status
Simulation time 4723594228 ps
CPU time 22.84 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 222380 kb
Host smart-6477ec2d-3d8e-4a03-a746-b0bb5296300b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241920832 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3241920832
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1533122051
Short name T622
Test name
Test status
Simulation time 501469807 ps
CPU time 4.8 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:09 PM PDT 24
Peak memory 207940 kb
Host smart-3bb8687c-7b45-4354-9e40-2da25af57d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533122051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1533122051
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3548781986
Short name T483
Test name
Test status
Simulation time 112302834 ps
CPU time 2.88 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 209980 kb
Host smart-7e46149d-87a7-43fb-a12a-9da291cf7daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548781986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3548781986
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3815054923
Short name T465
Test name
Test status
Simulation time 12806300 ps
CPU time 0.77 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 205892 kb
Host smart-6c9ba4ea-c449-4b78-a32c-bbc69b866d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815054923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3815054923
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2913450995
Short name T221
Test name
Test status
Simulation time 115172667 ps
CPU time 1.55 seconds
Started Jul 26 07:25:05 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 209600 kb
Host smart-629f6560-1fb0-485a-8536-20bbfc1645f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913450995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2913450995
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1839962063
Short name T76
Test name
Test status
Simulation time 117030149 ps
CPU time 2.63 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 208392 kb
Host smart-531721bc-ad31-4c13-b87d-8ad585a5a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839962063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1839962063
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1533695672
Short name T363
Test name
Test status
Simulation time 116263305 ps
CPU time 2.55 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 214100 kb
Host smart-dba1d608-c8cb-4842-8095-c8d30c02454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533695672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1533695672
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.23688480
Short name T303
Test name
Test status
Simulation time 43727414 ps
CPU time 2.5 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 214060 kb
Host smart-cb3f6dae-af94-4495-ad7e-623aa89cc43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23688480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.23688480
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1063221899
Short name T17
Test name
Test status
Simulation time 53292248 ps
CPU time 2.32 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 217996 kb
Host smart-ec1b65cd-4707-4f57-9461-92d6dec8ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063221899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1063221899
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3833069252
Short name T727
Test name
Test status
Simulation time 436899597 ps
CPU time 9.28 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:11 PM PDT 24
Peak memory 207728 kb
Host smart-5093db19-2761-43ef-bec1-d605902b9ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833069252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3833069252
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2468305128
Short name T300
Test name
Test status
Simulation time 78546058 ps
CPU time 2.53 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 207348 kb
Host smart-3e0acab2-e0d7-48cc-8a76-9bd39d043eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468305128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2468305128
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.139197488
Short name T281
Test name
Test status
Simulation time 3333507876 ps
CPU time 15.35 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:17 PM PDT 24
Peak memory 208780 kb
Host smart-fc9a931d-be21-4fae-bf96-a328c75b9bb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139197488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.139197488
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1770088032
Short name T478
Test name
Test status
Simulation time 67233863 ps
CPU time 3.41 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 206780 kb
Host smart-3c775bea-d01a-414c-aa1e-7dc3dff446b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770088032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1770088032
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4131284152
Short name T641
Test name
Test status
Simulation time 298286932 ps
CPU time 6.24 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:09 PM PDT 24
Peak memory 207804 kb
Host smart-f0c190f4-97fb-430a-8012-920064638ab1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131284152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4131284152
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.329672172
Short name T368
Test name
Test status
Simulation time 125071493 ps
CPU time 2.88 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 208276 kb
Host smart-3871b6b7-c02b-4edd-87fd-1c67b58ff254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329672172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.329672172
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3462389756
Short name T733
Test name
Test status
Simulation time 1574169976 ps
CPU time 47.07 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:25:52 PM PDT 24
Peak memory 208140 kb
Host smart-463499c2-3273-4b08-a5ab-a089b04af576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462389756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3462389756
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3521662998
Short name T512
Test name
Test status
Simulation time 1815668599 ps
CPU time 25.4 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 209208 kb
Host smart-d5d65528-a9cf-4be3-994c-801ce3103bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521662998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3521662998
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.762778217
Short name T434
Test name
Test status
Simulation time 238406515 ps
CPU time 2.91 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 209564 kb
Host smart-c2e520ff-bb33-4bb6-a582-14d45835f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762778217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.762778217
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1112002786
Short name T884
Test name
Test status
Simulation time 11614513 ps
CPU time 0.77 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:14 PM PDT 24
Peak memory 205848 kb
Host smart-518f4049-d574-445f-b92c-90b903fa2e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112002786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1112002786
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2080296653
Short name T808
Test name
Test status
Simulation time 66271725 ps
CPU time 3.27 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 208532 kb
Host smart-d03557a4-2b97-413c-af61-30d55c4592cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080296653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2080296653
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2289835013
Short name T105
Test name
Test status
Simulation time 67236488 ps
CPU time 2.24 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 208472 kb
Host smart-9c422a59-aa37-4efb-a40e-62adbe535cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289835013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2289835013
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1751721543
Short name T319
Test name
Test status
Simulation time 173305452 ps
CPU time 4.94 seconds
Started Jul 26 07:25:15 PM PDT 24
Finished Jul 26 07:25:20 PM PDT 24
Peak memory 222272 kb
Host smart-ddc94b15-228f-451c-a757-bc2e4220fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751721543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1751721543
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3686581914
Short name T45
Test name
Test status
Simulation time 548964315 ps
CPU time 3.95 seconds
Started Jul 26 07:25:00 PM PDT 24
Finished Jul 26 07:25:04 PM PDT 24
Peak memory 209656 kb
Host smart-6c909bc7-a9b7-41e6-a439-7ed5a233fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686581914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3686581914
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1297230240
Short name T87
Test name
Test status
Simulation time 8287875849 ps
CPU time 76.85 seconds
Started Jul 26 07:25:04 PM PDT 24
Finished Jul 26 07:26:21 PM PDT 24
Peak memory 209208 kb
Host smart-ff54702e-2e64-4291-b147-439b6ae5d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297230240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1297230240
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1772714260
Short name T433
Test name
Test status
Simulation time 263648920 ps
CPU time 2.39 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 206524 kb
Host smart-68dd9cf3-0c8c-42c8-bdc4-26af3804ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772714260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1772714260
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.466005525
Short name T630
Test name
Test status
Simulation time 103231421 ps
CPU time 3.54 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:07 PM PDT 24
Peak memory 206720 kb
Host smart-ac704eb6-cead-483d-bd3c-f85661d1033b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466005525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.466005525
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1621981810
Short name T604
Test name
Test status
Simulation time 120209136 ps
CPU time 2.37 seconds
Started Jul 26 07:25:01 PM PDT 24
Finished Jul 26 07:25:03 PM PDT 24
Peak memory 207136 kb
Host smart-81334b78-2585-401b-a1e0-beb244dfebbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621981810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1621981810
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2062555388
Short name T792
Test name
Test status
Simulation time 78615183 ps
CPU time 3.35 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:06 PM PDT 24
Peak memory 209060 kb
Host smart-01285290-c47d-4376-9362-80f1e3cab81f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062555388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2062555388
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1845595570
Short name T827
Test name
Test status
Simulation time 222023555 ps
CPU time 2.9 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 218124 kb
Host smart-00bbf1d3-0258-4a64-9b8f-14994838259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845595570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1845595570
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3008502127
Short name T194
Test name
Test status
Simulation time 146334305 ps
CPU time 2.41 seconds
Started Jul 26 07:25:02 PM PDT 24
Finished Jul 26 07:25:05 PM PDT 24
Peak memory 206668 kb
Host smart-55af02ed-aa6a-4cdd-b45e-480e8aa4fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008502127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3008502127
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1690563202
Short name T392
Test name
Test status
Simulation time 782010742 ps
CPU time 6.63 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:18 PM PDT 24
Peak memory 207492 kb
Host smart-5c247ac1-4f2c-492a-b058-56b9fc4efb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690563202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1690563202
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1182900103
Short name T190
Test name
Test status
Simulation time 473995555 ps
CPU time 16.38 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 222368 kb
Host smart-4d7bec24-e96c-45b2-b5c1-d2e53a0c2bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182900103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1182900103
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2887373752
Short name T847
Test name
Test status
Simulation time 83720164 ps
CPU time 4.36 seconds
Started Jul 26 07:25:03 PM PDT 24
Finished Jul 26 07:25:08 PM PDT 24
Peak memory 210032 kb
Host smart-f22a2504-30f2-4929-8aab-94719287f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887373752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2887373752
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1421150119
Short name T385
Test name
Test status
Simulation time 95208853 ps
CPU time 1.69 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:14 PM PDT 24
Peak memory 209768 kb
Host smart-d3f8c191-4d7c-4a62-9a15-ea6a641d2e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421150119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1421150119
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2809058984
Short name T77
Test name
Test status
Simulation time 66847485 ps
CPU time 0.77 seconds
Started Jul 26 07:25:14 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 205940 kb
Host smart-8763a994-cde6-4a2b-9367-cb4ce49faef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809058984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2809058984
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3453396874
Short name T28
Test name
Test status
Simulation time 5075668909 ps
CPU time 78.03 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:26:31 PM PDT 24
Peak memory 222300 kb
Host smart-9421eb46-7a82-4dac-8d85-2a2934100efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453396874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3453396874
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2306108126
Short name T658
Test name
Test status
Simulation time 50444129 ps
CPU time 2.51 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 208596 kb
Host smart-0ad1deb6-92e8-466d-bd2c-4ace2febfdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306108126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2306108126
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1266522405
Short name T96
Test name
Test status
Simulation time 256986479 ps
CPU time 3.83 seconds
Started Jul 26 07:25:15 PM PDT 24
Finished Jul 26 07:25:19 PM PDT 24
Peak memory 222320 kb
Host smart-b26913be-01b2-4afa-8f16-fda5de8eeccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266522405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1266522405
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3024867008
Short name T246
Test name
Test status
Simulation time 39758487 ps
CPU time 1.94 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 214124 kb
Host smart-15208ae3-be6b-4e41-9441-ce124e3c4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024867008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3024867008
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3488025110
Short name T896
Test name
Test status
Simulation time 805708805 ps
CPU time 5.53 seconds
Started Jul 26 07:25:16 PM PDT 24
Finished Jul 26 07:25:22 PM PDT 24
Peak memory 214308 kb
Host smart-7776c492-f308-4cb0-9e2a-dd279da7cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488025110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3488025110
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2241995178
Short name T435
Test name
Test status
Simulation time 307562125 ps
CPU time 4.14 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:16 PM PDT 24
Peak memory 207400 kb
Host smart-fecad4e3-8442-4766-95a8-607e36c2fe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241995178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2241995178
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.444661846
Short name T205
Test name
Test status
Simulation time 80217320 ps
CPU time 1.8 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 207000 kb
Host smart-6cb00c8d-30c6-49c9-8e64-af02383a7650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444661846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.444661846
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.366842689
Short name T539
Test name
Test status
Simulation time 215805078 ps
CPU time 3.45 seconds
Started Jul 26 07:25:10 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 206628 kb
Host smart-fbb5f777-e3a3-407c-8a0a-b324e2d26ad8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366842689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.366842689
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3031317618
Short name T742
Test name
Test status
Simulation time 34274377 ps
CPU time 2.42 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 208376 kb
Host smart-c51d8abe-a173-41e3-bbb3-5d007c697989
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031317618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3031317618
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2019954269
Short name T595
Test name
Test status
Simulation time 153273929 ps
CPU time 2.63 seconds
Started Jul 26 07:25:14 PM PDT 24
Finished Jul 26 07:25:17 PM PDT 24
Peak memory 206636 kb
Host smart-4c2efbbd-fcd4-4773-83af-1a86dd0e7193
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019954269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2019954269
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3907820794
Short name T396
Test name
Test status
Simulation time 255608791 ps
CPU time 3.13 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 218092 kb
Host smart-07d3202c-48cd-4089-82c8-56a02261924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907820794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3907820794
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.469455912
Short name T452
Test name
Test status
Simulation time 68158110 ps
CPU time 2.94 seconds
Started Jul 26 07:25:10 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 208448 kb
Host smart-41977106-0b1c-458f-aea0-7214e2877478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469455912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.469455912
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4179053422
Short name T220
Test name
Test status
Simulation time 2917434875 ps
CPU time 26.75 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:40 PM PDT 24
Peak memory 215476 kb
Host smart-20c14b64-2117-4813-b8d6-60a16a58ca1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179053422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4179053422
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.481900866
Short name T794
Test name
Test status
Simulation time 2450780416 ps
CPU time 23.43 seconds
Started Jul 26 07:25:10 PM PDT 24
Finished Jul 26 07:25:34 PM PDT 24
Peak memory 220960 kb
Host smart-a884318a-4fd1-4cf4-9c71-2a4d3315bea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481900866 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.481900866
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1438140110
Short name T344
Test name
Test status
Simulation time 472326391 ps
CPU time 5.92 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:17 PM PDT 24
Peak memory 214208 kb
Host smart-a582b1d4-2d79-4738-a5c6-a202bac30d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438140110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1438140110
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.874884764
Short name T518
Test name
Test status
Simulation time 139160521 ps
CPU time 2.04 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 209976 kb
Host smart-55fe9b81-1dd3-433f-9a47-5645e90f4383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874884764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.874884764
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1349131493
Short name T438
Test name
Test status
Simulation time 38159385 ps
CPU time 0.82 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:25 PM PDT 24
Peak memory 205820 kb
Host smart-2929071f-23fd-4bc3-8da8-7716c5deb172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349131493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1349131493
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1582125426
Short name T417
Test name
Test status
Simulation time 50795060 ps
CPU time 2.3 seconds
Started Jul 26 07:25:10 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 214112 kb
Host smart-86960f68-d9e1-4442-810b-41d44371d265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582125426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1582125426
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1879406599
Short name T804
Test name
Test status
Simulation time 226729427 ps
CPU time 2.51 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 219064 kb
Host smart-1318d828-abc1-472e-ab06-2265a6298747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879406599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1879406599
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.387071406
Short name T851
Test name
Test status
Simulation time 108801731 ps
CPU time 4.7 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 210040 kb
Host smart-8c02070a-297e-459d-a0af-809865c03cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387071406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.387071406
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2108475269
Short name T88
Test name
Test status
Simulation time 355801429 ps
CPU time 2.09 seconds
Started Jul 26 07:25:19 PM PDT 24
Finished Jul 26 07:25:21 PM PDT 24
Peak memory 209824 kb
Host smart-a368de47-8c96-4285-9fe0-e1cdb3cfd9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108475269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2108475269
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4189701352
Short name T619
Test name
Test status
Simulation time 204004740 ps
CPU time 3.62 seconds
Started Jul 26 07:25:21 PM PDT 24
Finished Jul 26 07:25:25 PM PDT 24
Peak memory 214244 kb
Host smart-50bc1084-b695-4e27-98ce-3edc48ec609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189701352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4189701352
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4193709948
Short name T840
Test name
Test status
Simulation time 1842983885 ps
CPU time 22.88 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:36 PM PDT 24
Peak memory 222272 kb
Host smart-6d37bfff-0206-4a1d-9456-0b461cb818d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193709948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4193709948
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3483905668
Short name T774
Test name
Test status
Simulation time 279138514 ps
CPU time 1.89 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:13 PM PDT 24
Peak memory 207144 kb
Host smart-6f68f224-5638-4480-bddc-78ddf2dddb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483905668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3483905668
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.237277996
Short name T614
Test name
Test status
Simulation time 817402901 ps
CPU time 5.24 seconds
Started Jul 26 07:25:11 PM PDT 24
Finished Jul 26 07:25:16 PM PDT 24
Peak memory 208240 kb
Host smart-8f4c34d0-d237-436f-96b1-8941e24b97e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237277996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.237277996
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1613069776
Short name T763
Test name
Test status
Simulation time 335450074 ps
CPU time 3.45 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 208508 kb
Host smart-d0c32d03-4830-4a24-97a4-b834589a36b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613069776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1613069776
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1588654436
Short name T537
Test name
Test status
Simulation time 369294780 ps
CPU time 2.88 seconds
Started Jul 26 07:25:13 PM PDT 24
Finished Jul 26 07:25:16 PM PDT 24
Peak memory 206872 kb
Host smart-a67ffcc1-59e4-425e-8bc7-f64e882a653e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588654436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1588654436
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.191224922
Short name T647
Test name
Test status
Simulation time 142092830 ps
CPU time 4.41 seconds
Started Jul 26 07:25:25 PM PDT 24
Finished Jul 26 07:25:30 PM PDT 24
Peak memory 218124 kb
Host smart-85c2ea6b-451d-480d-ba36-f2dda777f4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191224922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.191224922
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.604808174
Short name T754
Test name
Test status
Simulation time 130741538 ps
CPU time 3.09 seconds
Started Jul 26 07:25:12 PM PDT 24
Finished Jul 26 07:25:15 PM PDT 24
Peak memory 208588 kb
Host smart-3f7b5fd2-3a25-4489-bce5-675b2fb58b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604808174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.604808174
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3083823657
Short name T233
Test name
Test status
Simulation time 281867810 ps
CPU time 14.03 seconds
Started Jul 26 07:25:19 PM PDT 24
Finished Jul 26 07:25:33 PM PDT 24
Peak memory 222372 kb
Host smart-0f5df152-57c0-4c3d-8442-df5ab83f7933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083823657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3083823657
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3353576228
Short name T561
Test name
Test status
Simulation time 675447321 ps
CPU time 7.84 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:32 PM PDT 24
Peak memory 208416 kb
Host smart-7191f367-59ab-446c-b9de-b150ce87c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353576228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3353576228
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2510401433
Short name T618
Test name
Test status
Simulation time 69997220 ps
CPU time 1.96 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 209668 kb
Host smart-26f4431e-6e7a-489c-b034-ff6067090616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510401433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2510401433
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2609825780
Short name T477
Test name
Test status
Simulation time 121144449 ps
CPU time 0.76 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:21 PM PDT 24
Peak memory 205848 kb
Host smart-62af41c1-3a05-4c9f-a469-297f49d0d0ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609825780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2609825780
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2348530068
Short name T151
Test name
Test status
Simulation time 201109616 ps
CPU time 4.12 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:24 PM PDT 24
Peak memory 215560 kb
Host smart-2149f8c7-b9bc-4969-bfbc-0ff2090f601a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348530068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2348530068
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.863432057
Short name T285
Test name
Test status
Simulation time 84456139 ps
CPU time 3.9 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 214212 kb
Host smart-7393569f-6d7f-4676-8ece-57779214768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863432057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.863432057
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1124115031
Short name T681
Test name
Test status
Simulation time 64618510 ps
CPU time 3.74 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 214248 kb
Host smart-db4863f9-c2db-4722-9ddd-e0090946f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124115031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1124115031
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1065983237
Short name T544
Test name
Test status
Simulation time 86166674 ps
CPU time 3.78 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 222216 kb
Host smart-e8aedae9-fab8-43b6-8c94-716b6ccb2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065983237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1065983237
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2132374936
Short name T225
Test name
Test status
Simulation time 147379114 ps
CPU time 3.43 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 219644 kb
Host smart-f390aaa6-5865-4edc-9029-3a2f41f58cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132374936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2132374936
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3665267494
Short name T672
Test name
Test status
Simulation time 1099643142 ps
CPU time 9.52 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:33 PM PDT 24
Peak memory 214084 kb
Host smart-70d36d0b-62da-43fa-946a-a36a7fbb6def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665267494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3665267494
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.821873101
Short name T627
Test name
Test status
Simulation time 536131201 ps
CPU time 3.4 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:25 PM PDT 24
Peak memory 206904 kb
Host smart-03dde762-cc4f-4a53-be1d-d682b7f032e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821873101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.821873101
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1282394656
Short name T82
Test name
Test status
Simulation time 115434117 ps
CPU time 2.24 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:22 PM PDT 24
Peak memory 206744 kb
Host smart-6681db53-f0f6-49aa-b682-64897b23f8ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282394656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1282394656
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2381907613
Short name T496
Test name
Test status
Simulation time 713780287 ps
CPU time 4.86 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 208868 kb
Host smart-0c60d9a5-660b-4e11-8f5b-b3da7cb2ca2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381907613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2381907613
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.302578605
Short name T480
Test name
Test status
Simulation time 70037626 ps
CPU time 3.26 seconds
Started Jul 26 07:25:21 PM PDT 24
Finished Jul 26 07:25:25 PM PDT 24
Peak memory 207920 kb
Host smart-6f5d0646-8210-4a1b-9025-344abe075db0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302578605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.302578605
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.915930316
Short name T577
Test name
Test status
Simulation time 112507254 ps
CPU time 1.65 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:25 PM PDT 24
Peak memory 206660 kb
Host smart-594afa31-8ebe-444d-8889-4122703ebcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915930316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.915930316
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3541858047
Short name T796
Test name
Test status
Simulation time 65443230 ps
CPU time 2.58 seconds
Started Jul 26 07:25:18 PM PDT 24
Finished Jul 26 07:25:21 PM PDT 24
Peak memory 206756 kb
Host smart-2b168857-bef4-4298-8c7c-ed04785cc7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541858047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3541858047
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.575850306
Short name T393
Test name
Test status
Simulation time 1631634406 ps
CPU time 14.83 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:37 PM PDT 24
Peak memory 219020 kb
Host smart-7c47536f-747f-47ff-98af-29d3f850c45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575850306 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.575850306
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1714515714
Short name T476
Test name
Test status
Simulation time 74449123 ps
CPU time 3.66 seconds
Started Jul 26 07:25:26 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 207952 kb
Host smart-bf773b01-8418-4750-b7a1-57f106f4a488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714515714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1714515714
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1009944490
Short name T511
Test name
Test status
Simulation time 375568935 ps
CPU time 3.42 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:27 PM PDT 24
Peak memory 210076 kb
Host smart-c1659bd7-5936-4e4b-88fc-0001bb49ff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009944490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1009944490
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2450481580
Short name T592
Test name
Test status
Simulation time 33619948 ps
CPU time 0.84 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 205820 kb
Host smart-b8adb94f-f4d7-45bc-88b9-fe7f4c83d235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450481580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2450481580
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.662517293
Short name T408
Test name
Test status
Simulation time 57128750 ps
CPU time 2.38 seconds
Started Jul 26 07:25:26 PM PDT 24
Finished Jul 26 07:25:28 PM PDT 24
Peak memory 214216 kb
Host smart-aebe97a1-a6fd-431c-b212-2d52893ee780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662517293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.662517293
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.977959800
Short name T573
Test name
Test status
Simulation time 137350954 ps
CPU time 3.4 seconds
Started Jul 26 07:25:18 PM PDT 24
Finished Jul 26 07:25:22 PM PDT 24
Peak memory 220740 kb
Host smart-0e613050-4f70-4633-9052-0682492f1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977959800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.977959800
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4260477025
Short name T258
Test name
Test status
Simulation time 57137169 ps
CPU time 2.61 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 206688 kb
Host smart-5c957d35-957c-4949-9476-86e4152bd96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260477025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4260477025
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.325585329
Short name T98
Test name
Test status
Simulation time 2174867305 ps
CPU time 29.72 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:52 PM PDT 24
Peak memory 214272 kb
Host smart-beeadf3f-cc40-4b4c-bc93-5c369bcce6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325585329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.325585329
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1916515526
Short name T321
Test name
Test status
Simulation time 611634419 ps
CPU time 3.11 seconds
Started Jul 26 07:25:25 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 214156 kb
Host smart-7835a01f-8e9d-49c5-9639-7256fe126cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916515526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1916515526
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1081351970
Short name T224
Test name
Test status
Simulation time 123441319 ps
CPU time 4.75 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 209764 kb
Host smart-0f50ee74-9a89-48a1-ac59-0c9346c83ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081351970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1081351970
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3864456012
Short name T889
Test name
Test status
Simulation time 83608808 ps
CPU time 3.86 seconds
Started Jul 26 07:25:20 PM PDT 24
Finished Jul 26 07:25:24 PM PDT 24
Peak memory 207336 kb
Host smart-f9bc6111-9842-4422-be83-0613aa8b02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864456012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3864456012
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2630443708
Short name T111
Test name
Test status
Simulation time 699329591 ps
CPU time 6.35 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 208224 kb
Host smart-d5bd106c-a2cd-4805-ad24-4e47d1f64634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630443708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2630443708
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1685034305
Short name T274
Test name
Test status
Simulation time 2276431954 ps
CPU time 6.13 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:29 PM PDT 24
Peak memory 208520 kb
Host smart-54c5f3ce-e203-46ba-a973-a617dc422461
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685034305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1685034305
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.101074268
Short name T449
Test name
Test status
Simulation time 74854718 ps
CPU time 2 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:26 PM PDT 24
Peak memory 207112 kb
Host smart-31ba7272-7796-4013-b0c7-e6775914b4c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101074268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.101074268
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3987751
Short name T132
Test name
Test status
Simulation time 441299114 ps
CPU time 5.8 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:30 PM PDT 24
Peak memory 208692 kb
Host smart-0695455b-c657-416a-ade0-4c2cc79f2721
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3987751
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2469652582
Short name T440
Test name
Test status
Simulation time 68702509 ps
CPU time 1.27 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:23 PM PDT 24
Peak memory 214120 kb
Host smart-a0f23e3c-e2d7-41b3-921a-6b61441db039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469652582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2469652582
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3393323094
Short name T504
Test name
Test status
Simulation time 451760736 ps
CPU time 7.97 seconds
Started Jul 26 07:25:22 PM PDT 24
Finished Jul 26 07:25:30 PM PDT 24
Peak memory 208488 kb
Host smart-ea2a1532-f6d9-423f-b4b9-332c6275b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393323094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3393323094
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1332059179
Short name T770
Test name
Test status
Simulation time 1811415177 ps
CPU time 27.41 seconds
Started Jul 26 07:25:23 PM PDT 24
Finished Jul 26 07:25:51 PM PDT 24
Peak memory 222316 kb
Host smart-288aeb3e-2b18-43f6-8729-559bd042048f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332059179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1332059179
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1396982742
Short name T635
Test name
Test status
Simulation time 66033839 ps
CPU time 3.96 seconds
Started Jul 26 07:25:24 PM PDT 24
Finished Jul 26 07:25:28 PM PDT 24
Peak memory 214112 kb
Host smart-bf6442f3-8a66-47c2-a553-b10926f01979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396982742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1396982742
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1876120698
Short name T643
Test name
Test status
Simulation time 2516099590 ps
CPU time 12.43 seconds
Started Jul 26 07:25:26 PM PDT 24
Finished Jul 26 07:25:39 PM PDT 24
Peak memory 210680 kb
Host smart-b3f29a9d-0be6-4706-94f3-9a4c22a3db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876120698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1876120698
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3957174388
Short name T83
Test name
Test status
Simulation time 26239057 ps
CPU time 0.84 seconds
Started Jul 26 07:21:34 PM PDT 24
Finished Jul 26 07:21:35 PM PDT 24
Peak memory 205816 kb
Host smart-016c9536-d7ee-4d6d-b512-3ed8c8ddadd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957174388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3957174388
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3169857417
Short name T407
Test name
Test status
Simulation time 535189931 ps
CPU time 5.99 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:45 PM PDT 24
Peak memory 214220 kb
Host smart-7f541a74-0bce-43b0-887a-51ab83b58722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169857417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3169857417
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2498552149
Short name T749
Test name
Test status
Simulation time 163169508 ps
CPU time 2.46 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 208908 kb
Host smart-9ce3e069-b7dd-444f-ab51-5545da02c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498552149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2498552149
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2831241589
Short name T359
Test name
Test status
Simulation time 65756084 ps
CPU time 1.94 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:39 PM PDT 24
Peak memory 214164 kb
Host smart-06d058a8-7ecd-4286-9c30-aee0194e2c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831241589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2831241589
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3923603333
Short name T578
Test name
Test status
Simulation time 158242908 ps
CPU time 3.95 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 210064 kb
Host smart-0a0faf7e-3ed1-4104-80bc-5549a9709f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923603333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3923603333
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3110322342
Short name T277
Test name
Test status
Simulation time 121870163 ps
CPU time 3.16 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 214192 kb
Host smart-81489caa-6e7b-4ee6-b9d9-5e6c1a5b7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110322342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3110322342
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1696906689
Short name T580
Test name
Test status
Simulation time 201634267 ps
CPU time 3.83 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 208312 kb
Host smart-ffc627da-28e1-4082-87f3-28346a0dfcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696906689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1696906689
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3692190239
Short name T883
Test name
Test status
Simulation time 99296216 ps
CPU time 4.13 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:44 PM PDT 24
Peak memory 208436 kb
Host smart-d84861a9-6b9c-4406-b5da-8dec1bfacdaf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692190239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3692190239
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2348036311
Short name T850
Test name
Test status
Simulation time 43064626 ps
CPU time 1.68 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:21:37 PM PDT 24
Peak memory 206784 kb
Host smart-73757322-9d8f-43dd-a3b5-bc085590630c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348036311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2348036311
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3780379933
Short name T459
Test name
Test status
Simulation time 98927597 ps
CPU time 2.06 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 208740 kb
Host smart-80326498-feb0-40fd-9ca4-a71bdb0e6aee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780379933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3780379933
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1701338333
Short name T492
Test name
Test status
Simulation time 1033503956 ps
CPU time 2.56 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:21:38 PM PDT 24
Peak memory 208608 kb
Host smart-12d88071-839a-41a7-a2eb-2f5258ade6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701338333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1701338333
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1590548972
Short name T854
Test name
Test status
Simulation time 94952348 ps
CPU time 2.92 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 207872 kb
Host smart-9b8f3d48-0e73-498f-bee1-da57342b4a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590548972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1590548972
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3333678815
Short name T337
Test name
Test status
Simulation time 299938560 ps
CPU time 12.49 seconds
Started Jul 26 07:21:36 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 214976 kb
Host smart-deba3b6c-dadd-4ef8-aa5b-887b5d218238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333678815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3333678815
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1385225827
Short name T842
Test name
Test status
Simulation time 473376807 ps
CPU time 7.86 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:45 PM PDT 24
Peak memory 222340 kb
Host smart-9b6352e4-c31d-4f68-b386-6c8f89809de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385225827 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1385225827
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1869928554
Short name T776
Test name
Test status
Simulation time 120244990 ps
CPU time 4.81 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:44 PM PDT 24
Peak memory 208628 kb
Host smart-2de880bc-acc9-4bea-b06a-56916b1e8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869928554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1869928554
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2473632283
Short name T386
Test name
Test status
Simulation time 69035553 ps
CPU time 2.74 seconds
Started Jul 26 07:21:38 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 209888 kb
Host smart-f6eb8083-e9d8-4530-b280-f35696ad5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473632283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2473632283
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.663572574
Short name T137
Test name
Test status
Simulation time 10950735 ps
CPU time 0.72 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:38 PM PDT 24
Peak memory 205804 kb
Host smart-e15e9c7d-9a78-4f0a-a02d-87f34f164a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663572574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.663572574
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2620584540
Short name T788
Test name
Test status
Simulation time 151019348 ps
CPU time 2.1 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:21:37 PM PDT 24
Peak memory 209244 kb
Host smart-ab8512b9-6148-4a6b-8f4a-55e574221982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620584540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2620584540
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1900940849
Short name T772
Test name
Test status
Simulation time 89438029 ps
CPU time 3.23 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 208148 kb
Host smart-420a1fef-f6aa-4ec2-9a87-96d654d158ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900940849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1900940849
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2943377338
Short name T247
Test name
Test status
Simulation time 138602430 ps
CPU time 2.26 seconds
Started Jul 26 07:21:35 PM PDT 24
Finished Jul 26 07:21:37 PM PDT 24
Peak memory 214140 kb
Host smart-d8023d67-e6a7-4c33-a0e8-b81f580c5233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943377338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2943377338
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2827673898
Short name T816
Test name
Test status
Simulation time 38292979 ps
CPU time 2.17 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 208348 kb
Host smart-ae136b85-98b1-4359-b667-fb6b01cce964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827673898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2827673898
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3689302400
Short name T724
Test name
Test status
Simulation time 940055392 ps
CPU time 3.61 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 207716 kb
Host smart-1812999a-31fd-4e08-901c-0e0af9b5ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689302400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3689302400
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.380724047
Short name T432
Test name
Test status
Simulation time 36005340 ps
CPU time 2.21 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 208328 kb
Host smart-f9a45330-5707-4ebc-a4bc-a30d9ad15f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380724047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.380724047
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1719465399
Short name T623
Test name
Test status
Simulation time 273642506 ps
CPU time 3.4 seconds
Started Jul 26 07:21:38 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 206824 kb
Host smart-4c37fd8e-f615-4ba2-a857-3ae3da37ed3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719465399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1719465399
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1769577756
Short name T533
Test name
Test status
Simulation time 101756858 ps
CPU time 2.72 seconds
Started Jul 26 07:21:37 PM PDT 24
Finished Jul 26 07:21:40 PM PDT 24
Peak memory 208628 kb
Host smart-b32b7b93-1e64-4d3a-9d6b-95db5dbd7cda
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769577756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1769577756
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3418848027
Short name T33
Test name
Test status
Simulation time 103541455 ps
CPU time 2.46 seconds
Started Jul 26 07:21:36 PM PDT 24
Finished Jul 26 07:21:38 PM PDT 24
Peak memory 214104 kb
Host smart-1b303fee-4075-41c7-a338-5171820e8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418848027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3418848027
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.301267305
Short name T823
Test name
Test status
Simulation time 72533897 ps
CPU time 2.16 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 206752 kb
Host smart-ebc8b3ac-5d96-49fc-abae-f9661afc3b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301267305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.301267305
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2860580619
Short name T25
Test name
Test status
Simulation time 452553382 ps
CPU time 7.1 seconds
Started Jul 26 07:21:34 PM PDT 24
Finished Jul 26 07:21:41 PM PDT 24
Peak memory 209080 kb
Host smart-e8a5c727-05c4-429d-8ef6-4deceae040ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860580619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2860580619
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4042919583
Short name T401
Test name
Test status
Simulation time 593239968 ps
CPU time 3.9 seconds
Started Jul 26 07:21:34 PM PDT 24
Finished Jul 26 07:21:38 PM PDT 24
Peak memory 209948 kb
Host smart-c61e7a12-3b77-4b03-b2bf-ea989152ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042919583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4042919583
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1942234794
Short name T745
Test name
Test status
Simulation time 10951344 ps
CPU time 0.74 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:48 PM PDT 24
Peak memory 205824 kb
Host smart-05d77433-e534-440d-b200-96a7cb75a4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942234794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1942234794
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.510362997
Short name T307
Test name
Test status
Simulation time 376138182 ps
CPU time 3.22 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 214096 kb
Host smart-fa6edd5b-0f62-47d0-84fa-59ceb6ea9117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510362997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.510362997
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2287997904
Short name T858
Test name
Test status
Simulation time 227912471 ps
CPU time 2.87 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 209040 kb
Host smart-930d9ff6-841e-4cb3-b1b8-61da3f3dc8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287997904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2287997904
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.19103392
Short name T238
Test name
Test status
Simulation time 95020290 ps
CPU time 4.23 seconds
Started Jul 26 07:21:44 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 214124 kb
Host smart-7638dcdb-0ff2-464b-9929-d7d05d36c0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19103392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.19103392
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.860635058
Short name T37
Test name
Test status
Simulation time 94270038 ps
CPU time 3.36 seconds
Started Jul 26 07:21:48 PM PDT 24
Finished Jul 26 07:21:51 PM PDT 24
Peak memory 214096 kb
Host smart-94ee409a-62ad-46fb-9509-b5de1c4d6c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860635058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.860635058
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.307486546
Short name T615
Test name
Test status
Simulation time 40270312 ps
CPU time 1.97 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 208216 kb
Host smart-c5a129ba-bf31-4249-84e3-60d94f83ad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307486546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.307486546
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1112818840
Short name T553
Test name
Test status
Simulation time 116897936 ps
CPU time 5.32 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 206844 kb
Host smart-88fb924b-1b29-4cbe-9e0c-2517ace8a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112818840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1112818840
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1946031915
Short name T905
Test name
Test status
Simulation time 725401123 ps
CPU time 3.29 seconds
Started Jul 26 07:21:48 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 206688 kb
Host smart-951ac7bc-e344-4825-ba11-02219f926e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946031915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1946031915
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.757475076
Short name T439
Test name
Test status
Simulation time 61692503 ps
CPU time 2.86 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 206796 kb
Host smart-baf2d77b-792b-4944-8617-cc3f115f6565
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757475076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.757475076
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.265881163
Short name T654
Test name
Test status
Simulation time 65147036 ps
CPU time 2.45 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 208500 kb
Host smart-4c7587e5-defc-4d4e-a2ec-698c3849a00a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265881163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.265881163
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3919563638
Short name T631
Test name
Test status
Simulation time 27705649 ps
CPU time 2.17 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:21:53 PM PDT 24
Peak memory 208828 kb
Host smart-ac174fd5-8f33-4ed9-ae1d-df9ecbc6c97e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919563638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3919563638
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3846252347
Short name T506
Test name
Test status
Simulation time 148267628 ps
CPU time 2.16 seconds
Started Jul 26 07:21:49 PM PDT 24
Finished Jul 26 07:21:51 PM PDT 24
Peak memory 208644 kb
Host smart-f80338d2-f6e1-44ea-93c4-82491b5ef583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846252347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3846252347
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2064686219
Short name T398
Test name
Test status
Simulation time 429121832 ps
CPU time 3.19 seconds
Started Jul 26 07:21:39 PM PDT 24
Finished Jul 26 07:21:42 PM PDT 24
Peak memory 208296 kb
Host smart-90cc925a-ff39-45be-9527-97916d2aac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064686219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2064686219
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1329394679
Short name T295
Test name
Test status
Simulation time 2505205487 ps
CPU time 64.59 seconds
Started Jul 26 07:21:49 PM PDT 24
Finished Jul 26 07:22:54 PM PDT 24
Peak memory 222308 kb
Host smart-071ecba6-c1dc-49e4-9956-333aef1270e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329394679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1329394679
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1379152611
Short name T801
Test name
Test status
Simulation time 99472180 ps
CPU time 3.41 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:51 PM PDT 24
Peak memory 207928 kb
Host smart-ef41e6bd-d030-479a-bbcb-7ff8d78a1b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379152611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1379152611
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.577001917
Short name T56
Test name
Test status
Simulation time 221603838 ps
CPU time 2.22 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 209820 kb
Host smart-135d1aff-bd84-43b5-a7e9-39aa35db7509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577001917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.577001917
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1522092359
Short name T490
Test name
Test status
Simulation time 59923988 ps
CPU time 0.79 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:21:51 PM PDT 24
Peak memory 205796 kb
Host smart-e7496a77-ece4-419a-a7a2-eaa91508bf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522092359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1522092359
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2982908276
Short name T419
Test name
Test status
Simulation time 624321969 ps
CPU time 9.59 seconds
Started Jul 26 07:21:52 PM PDT 24
Finished Jul 26 07:22:01 PM PDT 24
Peak memory 215132 kb
Host smart-4dd39bfc-81d6-4f9a-864f-3238355aca9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982908276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2982908276
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.351614748
Short name T838
Test name
Test status
Simulation time 327302222 ps
CPU time 5.4 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 209244 kb
Host smart-72bcfb65-b87a-4c19-a6a7-4d2f22c61f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351614748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.351614748
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4030330251
Short name T316
Test name
Test status
Simulation time 43781774 ps
CPU time 2.14 seconds
Started Jul 26 07:21:45 PM PDT 24
Finished Jul 26 07:21:47 PM PDT 24
Peak memory 218216 kb
Host smart-04113061-6f9b-47ce-bd0b-ae966d8dec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030330251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4030330251
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3289402291
Short name T360
Test name
Test status
Simulation time 325594137 ps
CPU time 3 seconds
Started Jul 26 07:21:49 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 214212 kb
Host smart-12c4cec1-b144-43c7-a585-64e905d4576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289402291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3289402291
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4145653575
Short name T260
Test name
Test status
Simulation time 74344730 ps
CPU time 2.76 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 214204 kb
Host smart-d19abaf9-923b-4b1f-bb27-30ceda8175c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145653575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4145653575
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.889031754
Short name T666
Test name
Test status
Simulation time 333102595 ps
CPU time 4.74 seconds
Started Jul 26 07:21:49 PM PDT 24
Finished Jul 26 07:21:53 PM PDT 24
Peak memory 214128 kb
Host smart-035c772b-dfb1-4e98-a175-b136398a7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889031754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.889031754
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1284095455
Short name T809
Test name
Test status
Simulation time 904051642 ps
CPU time 5.58 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 207276 kb
Host smart-447e97fe-c267-4b5d-ac12-3e266d2c5437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284095455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1284095455
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1927235575
Short name T534
Test name
Test status
Simulation time 893003585 ps
CPU time 6.21 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:53 PM PDT 24
Peak memory 208388 kb
Host smart-8acee1d9-ae42-4262-88f6-7691d6f7f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927235575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1927235575
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.897801110
Short name T810
Test name
Test status
Simulation time 1607716382 ps
CPU time 7.6 seconds
Started Jul 26 07:21:45 PM PDT 24
Finished Jul 26 07:21:53 PM PDT 24
Peak memory 208664 kb
Host smart-25fb1152-ced6-4a36-84fd-b27b21a9b1ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897801110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.897801110
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1532700779
Short name T567
Test name
Test status
Simulation time 669231757 ps
CPU time 5.12 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:53 PM PDT 24
Peak memory 208524 kb
Host smart-5085990f-0c5d-470b-8278-768ad050661f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532700779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1532700779
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2595543115
Short name T846
Test name
Test status
Simulation time 124093358 ps
CPU time 2.43 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 208652 kb
Host smart-08eb2f4c-e354-4102-a0b6-5d42af0d8c30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595543115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2595543115
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.290483038
Short name T616
Test name
Test status
Simulation time 33574923 ps
CPU time 2.48 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 214160 kb
Host smart-002ca998-8122-4e94-8adb-fa6266221e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290483038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.290483038
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4149034262
Short name T835
Test name
Test status
Simulation time 174104283 ps
CPU time 3.76 seconds
Started Jul 26 07:21:48 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 207704 kb
Host smart-29617aca-e3ad-4f07-ae9a-390427e0dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149034262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4149034262
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2308251678
Short name T370
Test name
Test status
Simulation time 778285315 ps
CPU time 23.49 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:22:11 PM PDT 24
Peak memory 222368 kb
Host smart-cc764305-a435-43ff-8271-9446520f7c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308251678 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2308251678
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4007901926
Short name T80
Test name
Test status
Simulation time 998073798 ps
CPU time 9.86 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:57 PM PDT 24
Peak memory 208980 kb
Host smart-877109fd-9e81-4941-89af-ae5a74a370e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007901926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4007901926
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2947940215
Short name T428
Test name
Test status
Simulation time 24050777 ps
CPU time 0.73 seconds
Started Jul 26 07:22:00 PM PDT 24
Finished Jul 26 07:22:01 PM PDT 24
Peak memory 205852 kb
Host smart-bf96b272-954c-4cb7-b246-c8e25cbcdcc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947940215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2947940215
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3976004042
Short name T30
Test name
Test status
Simulation time 65973354 ps
CPU time 2.69 seconds
Started Jul 26 07:21:59 PM PDT 24
Finished Jul 26 07:22:02 PM PDT 24
Peak memory 208804 kb
Host smart-5df133a2-9092-4750-a34d-ebd16ead5397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976004042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3976004042
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2234937044
Short name T713
Test name
Test status
Simulation time 40529102 ps
CPU time 2.14 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 208612 kb
Host smart-c9a0df4c-5ab9-4559-95e7-8bd95d7a056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234937044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2234937044
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3744351897
Short name T706
Test name
Test status
Simulation time 484866515 ps
CPU time 5.12 seconds
Started Jul 26 07:22:02 PM PDT 24
Finished Jul 26 07:22:07 PM PDT 24
Peak memory 219408 kb
Host smart-1e714629-d99e-4116-b6c3-c7002e8307dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744351897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3744351897
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1383315067
Short name T334
Test name
Test status
Simulation time 79162710 ps
CPU time 2.67 seconds
Started Jul 26 07:22:02 PM PDT 24
Finished Jul 26 07:22:04 PM PDT 24
Peak memory 214152 kb
Host smart-21b15b5b-e946-4454-a9c3-947ec192c9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383315067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1383315067
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1828640810
Short name T49
Test name
Test status
Simulation time 224855487 ps
CPU time 3.36 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:50 PM PDT 24
Peak memory 206600 kb
Host smart-eebdadb0-c364-4e23-892e-8506fa0fdaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828640810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1828640810
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1164661378
Short name T548
Test name
Test status
Simulation time 118255169 ps
CPU time 4.89 seconds
Started Jul 26 07:21:47 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 208540 kb
Host smart-c7560e6a-ff65-4177-a887-97be3dd3ac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164661378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1164661378
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1909238550
Short name T436
Test name
Test status
Simulation time 2220852021 ps
CPU time 21.21 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:22:08 PM PDT 24
Peak memory 208076 kb
Host smart-db5af2c3-2328-403e-b2c3-e0612fbf20cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909238550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1909238550
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1306556523
Short name T81
Test name
Test status
Simulation time 78718348 ps
CPU time 2.32 seconds
Started Jul 26 07:21:46 PM PDT 24
Finished Jul 26 07:21:49 PM PDT 24
Peak memory 206840 kb
Host smart-5cdfb943-0012-430d-998f-583d80a9a038
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306556523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1306556523
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2653024394
Short name T831
Test name
Test status
Simulation time 677786647 ps
CPU time 5.7 seconds
Started Jul 26 07:21:50 PM PDT 24
Finished Jul 26 07:21:56 PM PDT 24
Peak memory 207856 kb
Host smart-65581d29-7c2f-47a5-8e37-f522f3e4f29d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653024394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2653024394
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.401793345
Short name T822
Test name
Test status
Simulation time 226863789 ps
CPU time 7.49 seconds
Started Jul 26 07:21:48 PM PDT 24
Finished Jul 26 07:21:55 PM PDT 24
Peak memory 208396 kb
Host smart-d92563c0-830c-4e8b-bb98-a1c4f3a8d467
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401793345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.401793345
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1912498440
Short name T395
Test name
Test status
Simulation time 68756657 ps
CPU time 1.98 seconds
Started Jul 26 07:21:59 PM PDT 24
Finished Jul 26 07:22:02 PM PDT 24
Peak memory 214104 kb
Host smart-89cb8568-70e2-41e0-ad49-5dc3ca5ce264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912498440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1912498440
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1120249665
Short name T620
Test name
Test status
Simulation time 346659992 ps
CPU time 3 seconds
Started Jul 26 07:21:48 PM PDT 24
Finished Jul 26 07:21:52 PM PDT 24
Peak memory 208324 kb
Host smart-3444369b-af1e-4abb-9363-9c442ec4e61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120249665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1120249665
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1027546201
Short name T324
Test name
Test status
Simulation time 966971461 ps
CPU time 16.58 seconds
Started Jul 26 07:22:03 PM PDT 24
Finished Jul 26 07:22:19 PM PDT 24
Peak memory 215444 kb
Host smart-35759fc0-8953-4779-8424-921ba4dd15e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027546201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1027546201
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1659852878
Short name T352
Test name
Test status
Simulation time 1234488860 ps
CPU time 8.7 seconds
Started Jul 26 07:21:59 PM PDT 24
Finished Jul 26 07:22:08 PM PDT 24
Peak memory 214332 kb
Host smart-b193dd67-0a08-425a-92b6-4835f19df933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659852878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1659852878
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3074584987
Short name T460
Test name
Test status
Simulation time 49842633 ps
CPU time 2.23 seconds
Started Jul 26 07:22:01 PM PDT 24
Finished Jul 26 07:22:04 PM PDT 24
Peak memory 209988 kb
Host smart-3c66960f-48ac-4e8e-b002-630d4cf40ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074584987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3074584987
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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