Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4676

1

T2

6

T3

7

T15

8

auto[1]

533

1

T1

2

T2

4

T3

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4676

1

T2

6

T3

7

T15

8

auto[1]

533

1

T1

2

T2

4

T3

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4655

1

T1

2

T2

10

T3

8

auto[1]

554

1

T18

4

T44

2

T138

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4655

1

T1

2

T2

10

T3

8

auto[1]

554

1

T18

4

T44

2

T138

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T17	1		T18	5		T19	2
auto[OpGenId]	1071	1			T1	2		T17	2		T18	12
auto[OpGenSwOut]	1115	1			T3	2		T18	16		T33	6
auto[OpGenHwOut]	2515	1			T2	10		T3	6		T15	8
auto[OpDisable]	71	1			T18	1		T47	1		T48	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T17	1		T18	5		T19	2
auto[OpGenId]	1071	1			T1	2		T17	2		T18	12
auto[OpGenSwOut]	1115	1			T3	2		T18	16		T33	6
auto[OpGenHwOut]	2515	1			T2	10		T3	6		T15	8
auto[OpDisable]	71	1			T18	1		T47	1		T48	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4708

1

T2

10

T3

7

T15

5

auto[1]

501

1

T1

2

T3

1

T15

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4708

1

T2

10

T3

7

T15

5

auto[1]

501

1

T1

2

T3

1

T15

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4901

1

T1

2

T2

10

T3

8

auto[1]

308

1

T19

6

T79

3

T117

11

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1764	1			T1	2		T2	4		T3	2
auto[1]	658	1			T3	2		T15	1		T18	2
auto[2]	659	1			T2	3		T16	2		T18	6
auto[3]	679	1			T3	1		T15	1		T16	1
auto[4]	367	1			T3	1		T15	2		T17	1
auto[5]	368	1			T3	1		T16	1		T18	5
auto[6]	353	1			T2	3		T3	1		T15	1
auto[7]	361	1			T18	1		T19	5		T33	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1449	1			T2	3		T3	3		T15	3
clear_one[1]	658	1			T3	2		T15	1		T18	2
clear_one[2]	659	1			T2	3		T16	2		T18	6
clear_one[3]	679	1			T3	1		T15	1		T16	1
clear_none	1764	1			T1	2		T2	4		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	972	1			T2	2		T3	2		T17	3
auto[StInit]	592	1			T2	1		T3	1		T15	1
auto[StCreatorRootKey]	565	1			T2	1		T3	1		T15	1
auto[StOwnerIntKey]	502	1			T2	1		T3	1		T15	1
auto[StOwnerKey]	481	1			T1	1		T2	1		T3	1
auto[StDisabled]	1838	1			T1	1		T2	4		T3	2
auto[StInvalid]	259	1			T17	3		T36	4		T55	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	972	1			T2	2		T3	2		T17	3
auto[StInit]	592	1			T2	1		T3	1		T15	1
auto[StCreatorRootKey]	565	1			T2	1		T3	1		T15	1
auto[StOwnerIntKey]	502	1			T2	1		T3	1		T15	1
auto[StOwnerKey]	481	1			T1	1		T2	1		T3	1
auto[StDisabled]	1838	1			T1	1		T2	4		T3	2
auto[StInvalid]	259	1			T17	3		T36	4		T55	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T178	1		T225	1		T226	1
auto[0]	auto[StReset]	auto[OpGenId]	163	1			T17	1		T18	2		T36	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	169	1			T18	1		T49	1		T8	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	254	1			T2	2		T3	1		T17	2
auto[0]	auto[StInit]	auto[OpAdvance]	43	1			T18	1		T19	1		T78	1
auto[0]	auto[StInit]	auto[OpGenId]	77	1			T18	1		T19	1		T227	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	78	1			T18	1		T26	1		T135	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	169	1			T15	1		T16	1		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	26	1			T79	1		T27	1		T150	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	48	1			T19	1		T228	1		T150	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	60	1			T18	1		T137	1		T117	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	76	1			T2	1		T18	1		T229	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T19	1		T5	1		T62	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T18	1		T45	1		T32	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T18	1		T33	1		T197	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T27	1		T131	1		T200	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T150	2		T21	1		T61	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T1	1		T230	1		T62	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T184	1		T141	2		T7	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T2	1		T16	1		T201	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	22	1			T26	1		T48	1		T198	1
auto[0]	auto[StDisabled]	auto[OpGenId]	65	1			T1	1		T230	1		T139	4
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T78	1		T150	1		T151	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T3	1		T15	2		T18	2
auto[0]	auto[StDisabled]	auto[OpDisable]	21	1			T18	1		T48	1		T231	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T36	1		T51	1		T232	1
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T233	1		T234	1		T235	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T55	1		T50	1		T236	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	20	1			T237	1		T238	2		T239	1
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T139	1		T66	1		T184	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T194	1		T28	1		T5	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	47	1			T3	1		T44	2		T201	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T125	1		T240	2		T241	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T192	1		T242	1		T243	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T3	1		T7	1		T244	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T245	1		T83	2		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T18	1		T96	1		T37	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T142	1		T247	1		T248	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T249	1		T211	1		T53	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T15	1		T131	1		T132	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T62	1		T178	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T6	1		T66	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T137	1		T61	1		T7	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T138	1		T252	1		T205	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T178	1		T253	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T33	1		T61	1		T7	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T61	1		T199	1		T255	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T138	1		T131	1		T5	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	33	1			T78	1		T27	1		T227	1
auto[1]	auto[StDisabled]	auto[OpGenId]	57	1			T33	1		T48	1		T46	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T18	1		T33	1		T96	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	137	1			T44	1		T48	2		T256	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T257	1		T185	1		T127	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	9	1			T50	1		T258	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T36	1		T260	1		T239	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T49	1		T51	1		T97	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T51	1		T234	1		T261	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T18	1		T69	1		T6	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T48	1		T262	1		T185	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	34	1			T44	1		T61	1		T6	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T83	1		T6	1		T263	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T194	1		T28	1		T264	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T18	1		T83	1		T265	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T2	1		T131	1		T48	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T18	1		T117	1		T5	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T66	1		T266	1		T263	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T262	1		T185	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T16	1		T44	1		T138	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T78	1		T117	2		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T79	1		T227	1		T69	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T66	1		T269	1		T7	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T16	1		T117	2		T201	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T117	1		T48	1		T270	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T79	1		T185	1		T130	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T61	1		T271	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T19	1		T44	1		T117	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T150	1		T273	1		T6	1
auto[2]	auto[StDisabled]	auto[OpGenId]	50	1			T117	2		T48	1		T150	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T18	3		T117	1		T48	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T2	2		T33	1		T79	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T125	1		T52	1		T274	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T238	2		T275	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T55	1		T28	2		T276	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T276	1		T102	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T85	1		T260	1		T234	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T49	1		T5	1		T196	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	15	1			T69	1		T139	1		T66	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	34	1			T18	1		T131	1		T6	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T277	1		T278	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T111	2		T199	1		T221	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T18	1		T33	1		T279	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T201	1		T280	1		T281	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T282	1		T207	1		T223	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T133	1		T283	1		T91	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T27	1		T227	1		T196	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T18	1		T200	1		T256	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T199	1		T66	1		T142	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T18	1		T96	1		T133	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T192	1		T72	1		T185	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T111	1		T180	1		T284	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T185	2		T285	1		T286	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T18	1		T78	1		T198	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T124	1		T214	1		T287	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T3	1		T204	1		T282	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T18	1		T69	1		T66	1
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T18	1		T19	1		T26	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T78	2		T193	1		T228	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T15	1		T16	1		T18	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T61	1		T125	1		T288	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T17	1		T97	1		T234	1
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T237	2		T289	1		T82	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T236	2		T290	1		T291	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T17	1		T292	1		T102	1
auto[4]	auto[StReset]	auto[OpGenId]	5	1			T33	1		T36	2		T6	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T18	1		T6	2		T184	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	26	1			T131	1		T5	1		T86	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T151	1		T293	1		T294	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T86	1		T185	1		T91	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T5	1		T295	1		T105	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T200	1		T127	1		T296	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T297	3		T298	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T18	1		T48	1		T151	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T48	1		T66	1		T125	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T84	1		T299	1		T300	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T151	1		T126	1		T301	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T46	1		T151	1		T66	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T302	1		T130	1		T243	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T15	1		T280	1		T111	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T211	1		T244	1		T303	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T48	1		T304	1		T305	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T18	1		T5	1		T306	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T137	1		T191	1		T205	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T18	1		T151	1		T202	1
auto[4]	auto[StDisabled]	auto[OpGenId]	25	1			T151	1		T5	1		T199	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T18	1		T249	1		T61	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T3	1		T15	1		T44	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T75	1		T244	1		T307	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T55	1		T232	1		T308	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T17	1		T261	1		T309	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T97	1		T102	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T51	1		T235	1		T239	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T97	1		T247	1		T128	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T18	1		T65	1		T311	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T280	1		T312	1		T22	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T83	1		T91	1		T88	1
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T48	1		T311	1		T272	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T313	1		T128	1		T211	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T33	1		T249	1		T314	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T203	1		T128	1		T315	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T27	1		T62	1		T74	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T26	1		T191	1		T111	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T3	1		T316	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T317	1		T315	1		T54	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T298	1		T318	1		T319	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T61	1		T52	1		T220	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T18	1		T228	1		T279	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T105	1		T320	1		T321	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	8	1			T18	1		T228	1		T111	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T18	1		T5	1		T267	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T256	1		T280	1		T322	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T96	1		T5	1		T198	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T33	1		T48	1		T252	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T18	1		T33	1		T137	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T16	1		T138	2		T201	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T60	1		T283	1		T323	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T324	1		T325	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T292	1		T239	1		T275	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T36	1		T50	1		T326	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T36	1		T239	1		T289	1
auto[6]	auto[StReset]	auto[OpGenId]	14	1			T5	1		T7	1		T244	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T38	1		T211	1		T327	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	19	1			T18	1		T8	1		T201	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T140	1		T62	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T328	1		T218	1		T329	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T184	1		T330	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T331	1		T332	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T128	1		T221	1		T335	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T251	1		T336	1		T337	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T322	1		T338	1		T53	2
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T211	1		T241	3		T339	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T185	2		T340	1		T341	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T3	1		T111	1		T342	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T2	1		T132	1		T343	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T199	1		T211	1		T344	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T18	1		T345	1		T346	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T347	1		T62	2		T180	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T15	1		T26	1		T132	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T79	1		T117	1		T5	2
auto[6]	auto[StDisabled]	auto[OpGenId]	24	1			T18	1		T117	1		T61	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T33	1		T202	1		T61	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T2	2		T16	2		T79	2
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T47	1		T348	1		T349	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T308	1		T309	1		T324	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T232	1		T327	1		T261	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T50	1		T350	2		T291	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T97	1		T28	1		T232	1
auto[7]	auto[StReset]	auto[OpGenId]	5	1			T49	1		T6	1		T260	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	15	1			T48	1		T313	1		T127	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	16	1			T6	1		T66	1		T299	1
auto[7]	auto[StInit]	auto[OpAdvance]	6	1			T302	1		T351	1		T352	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T48	1		T126	1		T223	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T221	1		T91	1		T353	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T139	1		T260	1		T354	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T355	2		T353	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T46	1		T343	1		T187	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T356	1		T321	1		T352	3
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T357	1		T6	1		T124	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T199	1		T316	1		T126	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T68	1		T358	1		T359	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T33	1		T48	1		T214	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T18	1		T44	1		T136	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T79	1		T101	1		T360	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T139	1		T66	1		T225	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T69	1		T7	1		T331	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T139	2		T62	1		T361	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T139	3		T199	1		T240	2
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T79	1		T139	3		T61	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T5	2		T245	1		T61	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T19	5		T44	1		T27	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T61	1		T7	1		T362	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T234	1		T102	1		T363	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T85	1		T326	1		T258	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T51	2		T28	1		T364	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T50	1		T260	1		T290	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1449

1

T2

3

T3

3

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

383

1

T3

2

T18

2

T33

3

clear_one[1]

auto[0]

auto[0]

auto[1]

108

1

T15

1

T27

1

T131

2

clear_one[1]

auto[0]

auto[1]

auto[0]

125

1

T44

1

T138

2

T48

1

clear_one[1]

auto[0]

auto[1]

auto[1]

42

1

T252

1

T5

1

T229

1

clear_one[2]

auto[0]

auto[0]

auto[0]

372

1

T2

1

T18

5

T78

1

clear_one[2]

auto[0]

auto[0]

auto[1]

101

1

T19

1

T131

1

T132

1

clear_one[2]

auto[1]

auto[0]

auto[0]

140

1

T2

2

T16

2

T18

1

clear_one[2]

auto[1]

auto[0]

auto[1]

46

1

T150

1

T69

1

T61

2

clear_one[3]

auto[0]

auto[0]

auto[0]

395

1

T15

1

T17

2

T18

5

clear_one[3]

auto[0]

auto[1]

auto[0]

137

1

T44

1

T138

1

T27

1

clear_one[3]

auto[1]

auto[0]

auto[0]

99

1

T3

1

T16

1

T18

2

clear_one[3]

auto[1]

auto[1]

auto[0]

48

1

T18

1

T48

2

T282

4

clear_none

auto[0]

auto[0]

auto[0]

1295

1

T2

2

T3

1

T15

1

clear_none

auto[0]

auto[0]

auto[1]

125

1

T3

1

T15

2

T18

1

clear_none

auto[0]

auto[1]

auto[0]

122

1

T18

2

T136

1

T193

1

clear_none

auto[0]

auto[1]

auto[1]

22

1

T5

1

T229

1

T178

1

clear_none

auto[1]

auto[0]

auto[0]

110

1

T2

2

T16

1

T201

1

clear_none

auto[1]

auto[0]

auto[1]

32

1

T1

2

T19

1

T48

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T18

1

T61

1

T282

2

clear_none

auto[1]

auto[1]

auto[1]

25

1

T5

1

T61

1

T6

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1347	1			T2	3		T3	3		T15	3
clear_all	auto[1]	102	1			T19	3		T79	3		T117	2
clear_one[1]	auto[0]	608	1			T3	2		T15	1		T18	2
clear_one[1]	auto[1]	50	1			T282	3		T178	3		T255	6
clear_one[2]	auto[0]	623	1			T2	3		T16	2		T18	6
clear_one[2]	auto[1]	36	1			T117	9		T150	3		T268	1
clear_one[3]	auto[0]	644	1			T3	1		T15	1		T16	1
clear_one[3]	auto[1]	35	1			T282	4		T141	2		T142	1
clear_none	auto[0]	1679	1			T1	2		T2	4		T3	2
clear_none	auto[1]	85	1			T19	3		T150	3		T139	3