Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10705

1

T1

14

T2

7

T3

12

auto[Attestation]

7112

1

T1

3

T2

3

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2559	1			T1	5		T3	4		T4	4
auto[Aes]	3252	1			T1	2		T2	10		T3	3
auto[Kmac]	3269	1			T1	1		T3	2		T4	4
auto[Otbn]	3203	1			T1	3		T3	5		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7158	1			T1	8		T2	8		T3	8
auto[OpGenId]	5534	1			T1	6		T3	1		T4	7
auto[OpGenSwOut]	5565	1			T1	5		T3	4		T4	14
auto[OpGenHwOut]	6718	1			T1	6		T2	10		T3	10
auto[OpDisable]	129	1			T18	2		T47	1		T48	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10014

1

T1

14

T2

8

T3

8

auto[OpDoneFail]

15090

1

T1

11

T2

10

T3

15

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6148	1			T1	4		T2	3		T3	8
auto[StInit]	3554	1			T1	1		T2	2		T3	2
auto[StCreatorRootKey]	2989	1			T1	5		T2	2		T3	2
auto[StOwnerIntKey]	2612	1			T1	5		T2	2		T3	2
auto[StOwnerKey]	2370	1			T1	3		T2	2		T3	2
auto[StDisabled]	7431	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	313	1			T1	1		T4	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	84	1			T4	1		T18	2		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T18	1		T33	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	77	1			T1	1		T18	3		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T189	1		T134	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	216	1			T4	1		T18	7		T33	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	337	1			T4	2		T17	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	95	1			T18	2		T35	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T18	2		T137	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T1	1		T18	3		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	72	1			T18	1		T19	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	201	1			T3	1		T18	6		T117	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	351	1			T1	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	105	1			T18	1		T26	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	61	1			T34	1		T48	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T4	1		T18	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T48	1		T191	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	177	1			T18	4		T33	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	326	1			T4	3		T17	3		T18	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	90	1			T3	1		T18	2		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T18	1		T33	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T18	1		T137	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	54	1			T4	1		T18	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	209	1			T1	1		T18	6		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T18	3		T48	4		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	119	1			T18	2		T192	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T18	1		T19	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T18	1		T33	2		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T5	1		T111	1		T62	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T4	1		T18	7		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T48	1		T5	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	106	1			T18	4		T27	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	65	1			T18	1		T19	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T3	1		T194	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	76	1			T18	2		T195	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	198	1			T33	2		T78	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	56	1			T18	1		T48	3		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	100	1			T190	1		T45	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T26	2		T27	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T33	1		T150	2		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T18	3		T196	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	204	1			T4	1		T18	6		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T18	1		T48	2		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	93	1			T79	1		T55	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T18	1		T192	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T18	2		T35	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T61	1		T198	1		T199	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	195	1			T18	3		T33	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	243	1			T3	2		T17	1		T18	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T17	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T3	1		T18	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T1	1		T18	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T68	1		T46	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	173	1			T1	1		T18	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	462	1			T2	2		T17	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T2	1		T18	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T2	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T2	1		T18	3		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T18	2		T201	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	265	1			T2	2		T16	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	468	1			T3	1		T17	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T79	1		T26	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T17	2		T18	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T18	1		T35	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	93	1			T18	1		T19	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	260	1			T18	3		T33	1		T79	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	470	1			T1	1		T3	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T15	1		T131	1		T132	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T19	1		T78	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T18	1		T33	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	93	1			T15	1		T33	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	267	1			T3	2		T15	2		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T48	1		T5	2		T61	6
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	84	1			T17	1		T18	3		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T48	1		T202	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T18	4		T48	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T33	1		T203	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	162	1			T1	1		T3	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	41	1			T18	1		T48	2		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T16	1		T18	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T201	1		T200	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T16	1		T34	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	97	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	296	1			T2	2		T16	2		T18	6
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T18	1		T48	5		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T17	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T17	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T44	1		T96	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	84	1			T18	1		T19	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	268	1			T18	2		T79	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T18	1		T48	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T18	1		T135	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T15	1		T18	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T1	1		T15	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T18	1		T131	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	273	1			T15	2		T18	1		T19	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	191	1			T18	3		T27	2		T189	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	634	1			T1	2		T4	3		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	202	1			T1	1		T18	6		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	654	1			T3	1		T4	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	159	1			T4	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	652	1			T1	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T4	1		T18	2		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	645	1			T1	1		T3	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	169	1			T18	2		T19	2		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	375	1			T4	1		T18	12		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	181	1			T3	1		T18	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	381	1			T18	5		T33	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T18	3		T26	2		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	371	1			T4	1		T18	7		T33	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T18	3		T35	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	359	1			T18	4		T33	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T1	1		T3	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	530	1			T1	1		T3	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	255	1			T2	2		T16	1		T18	5
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	848	1			T2	5		T16	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T17	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	859	1			T3	1		T17	3		T18	7
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	257	1			T15	1		T19	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	858	1			T1	1		T3	4		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	166	1			T18	2		T48	2		T203	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	311	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	272	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T2	2		T16	3		T18	8
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T17	1		T18	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	456	1			T17	1		T18	4		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	233	1			T1	1		T15	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	463	1			T15	2		T18	4		T19	2