Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30777

1

T1

28

T2

22

T3

26

auto[1]

296

1

T19

7

T79

3

T117

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30789	1			T1	28		T2	22		T3	26
auto[134217728:268435455]	18	1			T117	2		T141	1		T255	1
auto[268435456:402653183]	10	1			T150	2		T139	1		T392	1
auto[402653184:536870911]	11	1			T19	1		T117	1		T381	1
auto[536870912:671088639]	12	1			T150	1		T141	2		T267	1
auto[671088640:805306367]	15	1			T150	1		T381	1		T380	1
auto[805306368:939524095]	12	1			T117	1		T139	1		T282	1
auto[939524096:1073741823]	7	1			T282	2		T297	2		T225	1
auto[1073741824:1207959551]	13	1			T282	1		T381	1		T141	1
auto[1207959552:1342177279]	12	1			T79	1		T117	1		T139	1
auto[1342177280:1476395007]	8	1			T117	1		T151	1		T139	1
auto[1476395008:1610612735]	6	1			T250	1		T393	1		T226	1
auto[1610612736:1744830463]	9	1			T117	1		T139	1		T240	1
auto[1744830464:1879048191]	12	1			T151	1		T139	1		T250	1
auto[1879048192:2013265919]	6	1			T151	1		T139	2		T297	1
auto[2013265920:2147483647]	12	1			T19	1		T282	1		T178	1
auto[2147483648:2281701375]	8	1			T151	1		T267	1		T392	1
auto[2281701376:2415919103]	11	1			T151	1		T141	1		T355	1
auto[2415919104:2550136831]	5	1			T139	1		T250	1		T333	1
auto[2550136832:2684354559]	10	1			T150	1		T333	1		T225	1
auto[2684354560:2818572287]	3	1			T240	1		T394	1		T346	1
auto[2818572288:2952790015]	9	1			T19	1		T139	1		T355	1
auto[2952790016:3087007743]	3	1			T79	1		T395	1		T396	1
auto[3087007744:3221225471]	14	1			T282	1		T250	2		T393	1
auto[3221225472:3355443199]	7	1			T117	1		T139	1		T380	1
auto[3355443200:3489660927]	5	1			T19	1		T225	1		T226	1
auto[3489660928:3623878655]	6	1			T19	1		T142	1		T355	1
auto[3623878656:3758096383]	6	1			T141	1		T268	1		T397	1
auto[3758096384:3892314111]	8	1			T19	1		T178	1		T268	1
auto[3892314112:4026531839]	11	1			T19	1		T139	1		T141	1
auto[4026531840:4160749567]	5	1			T141	1		T250	1		T397	1
auto[4160749568:4294967295]	10	1			T79	1		T141	2		T255	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30777	1			T1	28		T2	22		T3	26
auto[0:134217727]	auto[1]	12	1			T117	1		T150	1		T139	2
auto[134217728:268435455]	auto[1]	18	1			T117	2		T141	1		T255	1
auto[268435456:402653183]	auto[1]	10	1			T150	2		T139	1		T392	1
auto[402653184:536870911]	auto[1]	11	1			T19	1		T117	1		T381	1
auto[536870912:671088639]	auto[1]	12	1			T150	1		T141	2		T267	1
auto[671088640:805306367]	auto[1]	15	1			T150	1		T381	1		T380	1
auto[805306368:939524095]	auto[1]	12	1			T117	1		T139	1		T282	1
auto[939524096:1073741823]	auto[1]	7	1			T282	2		T297	2		T225	1
auto[1073741824:1207959551]	auto[1]	13	1			T282	1		T381	1		T141	1
auto[1207959552:1342177279]	auto[1]	12	1			T79	1		T117	1		T139	1
auto[1342177280:1476395007]	auto[1]	8	1			T117	1		T151	1		T139	1
auto[1476395008:1610612735]	auto[1]	6	1			T250	1		T393	1		T226	1
auto[1610612736:1744830463]	auto[1]	9	1			T117	1		T139	1		T240	1
auto[1744830464:1879048191]	auto[1]	12	1			T151	1		T139	1		T250	1
auto[1879048192:2013265919]	auto[1]	6	1			T151	1		T139	2		T297	1
auto[2013265920:2147483647]	auto[1]	12	1			T19	1		T282	1		T178	1
auto[2147483648:2281701375]	auto[1]	8	1			T151	1		T267	1		T392	1
auto[2281701376:2415919103]	auto[1]	11	1			T151	1		T141	1		T355	1
auto[2415919104:2550136831]	auto[1]	5	1			T139	1		T250	1		T333	1
auto[2550136832:2684354559]	auto[1]	10	1			T150	1		T333	1		T225	1
auto[2684354560:2818572287]	auto[1]	3	1			T240	1		T394	1		T346	1
auto[2818572288:2952790015]	auto[1]	9	1			T19	1		T139	1		T355	1
auto[2952790016:3087007743]	auto[1]	3	1			T79	1		T395	1		T396	1
auto[3087007744:3221225471]	auto[1]	14	1			T282	1		T250	2		T393	1
auto[3221225472:3355443199]	auto[1]	7	1			T117	1		T139	1		T380	1
auto[3355443200:3489660927]	auto[1]	5	1			T19	1		T225	1		T226	1
auto[3489660928:3623878655]	auto[1]	6	1			T19	1		T142	1		T355	1
auto[3623878656:3758096383]	auto[1]	6	1			T141	1		T268	1		T397	1
auto[3758096384:3892314111]	auto[1]	8	1			T19	1		T178	1		T268	1
auto[3892314112:4026531839]	auto[1]	11	1			T19	1		T139	1		T141	1
auto[4026531840:4160749567]	auto[1]	5	1			T141	1		T250	1		T397	1
auto[4160749568:4294967295]	auto[1]	10	1			T79	1		T141	2		T255	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1530

1

T1

2

T17

7

T18

23

auto[1]

1711

1

T1

2

T17

2

T18

28

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T17	1		T18	3		T78	2
auto[134217728:268435455]	102	1			T18	6		T49	1		T48	2
auto[268435456:402653183]	105	1			T1	1		T18	1		T79	1
auto[402653184:536870911]	100	1			T18	2		T79	1		T55	1
auto[536870912:671088639]	105	1			T17	1		T18	1		T19	1
auto[671088640:805306367]	109	1			T33	1		T78	1		T55	1
auto[805306368:939524095]	102	1			T18	1		T36	1		T50	1
auto[939524096:1073741823]	91	1			T18	1		T27	1		T117	1
auto[1073741824:1207959551]	82	1			T18	2		T56	1		T47	2
auto[1207959552:1342177279]	89	1			T17	1		T18	2		T33	1
auto[1342177280:1476395007]	108	1			T17	1		T18	3		T48	1
auto[1476395008:1610612735]	106	1			T18	1		T26	1		T56	2
auto[1610612736:1744830463]	114	1			T18	2		T49	1		T227	1
auto[1744830464:1879048191]	101	1			T1	1		T17	1		T18	1
auto[1879048192:2013265919]	93	1			T1	1		T17	1		T18	1
auto[2013265920:2147483647]	84	1			T18	1		T33	1		T56	1
auto[2147483648:2281701375]	130	1			T18	3		T55	1		T26	1
auto[2281701376:2415919103]	107	1			T17	1		T18	2		T19	1
auto[2415919104:2550136831]	113	1			T18	1		T48	1		T97	1
auto[2550136832:2684354559]	101	1			T26	1		T117	1		T191	1
auto[2684354560:2818572287]	93	1			T17	1		T18	1		T19	1
auto[2818572288:2952790015]	97	1			T1	1		T18	3		T49	1
auto[2952790016:3087007743]	89	1			T19	1		T48	1		T237	1
auto[3087007744:3221225471]	115	1			T18	2		T78	2		T79	1
auto[3221225472:3355443199]	112	1			T17	1		T18	3		T78	1
auto[3355443200:3489660927]	105	1			T18	1		T27	1		T203	1
auto[3489660928:3623878655]	75	1			T18	1		T33	1		T117	1
auto[3623878656:3758096383]	106	1			T36	1		T49	1		T20	1
auto[3758096384:3892314111]	102	1			T18	2		T48	2		T97	1
auto[3892314112:4026531839]	93	1			T18	3		T27	1		T117	1
auto[4026531840:4160749567]	106	1			T18	1		T78	1		T8	1
auto[4160749568:4294967295]	97	1			T133	1		T50	1		T191	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T17	1		T18	3		T78	2
auto[0:134217727]	auto[1]	58	1			T49	1		T135	1		T192	1
auto[134217728:268435455]	auto[0]	56	1			T18	3		T49	1		T48	2
auto[134217728:268435455]	auto[1]	46	1			T18	3		T45	1		T150	1
auto[268435456:402653183]	auto[0]	55	1			T1	1		T18	1		T79	1
auto[268435456:402653183]	auto[1]	50	1			T56	1		T51	1		T191	1
auto[402653184:536870911]	auto[0]	50	1			T18	2		T79	1		T26	1
auto[402653184:536870911]	auto[1]	50	1			T55	1		T135	1		T45	1
auto[536870912:671088639]	auto[0]	55	1			T19	1		T36	1		T97	1
auto[536870912:671088639]	auto[1]	50	1			T17	1		T18	1		T48	1
auto[671088640:805306367]	auto[0]	49	1			T33	1		T55	1		T45	1
auto[671088640:805306367]	auto[1]	60	1			T78	1		T68	1		T194	1
auto[805306368:939524095]	auto[0]	56	1			T18	1		T48	1		T5	1
auto[805306368:939524095]	auto[1]	46	1			T36	1		T50	1		T191	1
auto[939524096:1073741823]	auto[0]	39	1			T18	1		T117	1		T192	1
auto[939524096:1073741823]	auto[1]	52	1			T27	1		T48	1		T197	1
auto[1073741824:1207959551]	auto[0]	42	1			T18	1		T56	1		T237	1
auto[1073741824:1207959551]	auto[1]	40	1			T18	1		T47	2		T150	1
auto[1207959552:1342177279]	auto[0]	43	1			T17	1		T79	1		T48	1
auto[1207959552:1342177279]	auto[1]	46	1			T18	2		T33	1		T79	1
auto[1342177280:1476395007]	auto[0]	45	1			T17	1		T48	1		T150	1
auto[1342177280:1476395007]	auto[1]	63	1			T18	3		T51	1		T5	1
auto[1476395008:1610612735]	auto[0]	48	1			T18	1		T56	1		T48	1
auto[1476395008:1610612735]	auto[1]	58	1			T26	1		T56	1		T192	1
auto[1610612736:1744830463]	auto[0]	47	1			T194	1		T5	1		T66	3
auto[1610612736:1744830463]	auto[1]	67	1			T18	2		T49	1		T227	1
auto[1744830464:1879048191]	auto[0]	43	1			T17	1		T18	1		T5	1
auto[1744830464:1879048191]	auto[1]	58	1			T1	1		T48	1		T68	1
auto[1879048192:2013265919]	auto[0]	47	1			T17	1		T36	2		T55	1
auto[1879048192:2013265919]	auto[1]	46	1			T1	1		T18	1		T6	1
auto[2013265920:2147483647]	auto[0]	35	1			T48	1		T237	1		T68	1
auto[2013265920:2147483647]	auto[1]	49	1			T18	1		T33	1		T56	1
auto[2147483648:2281701375]	auto[0]	57	1			T18	2		T55	1		T97	3
auto[2147483648:2281701375]	auto[1]	73	1			T18	1		T26	1		T48	1
auto[2281701376:2415919103]	auto[0]	49	1			T17	1		T18	1		T55	1
auto[2281701376:2415919103]	auto[1]	58	1			T18	1		T19	1		T33	1
auto[2415919104:2550136831]	auto[0]	56	1			T97	1		T236	1		T5	1
auto[2415919104:2550136831]	auto[1]	57	1			T18	1		T48	1		T139	1
auto[2550136832:2684354559]	auto[0]	50	1			T26	1		T117	1		T191	1
auto[2550136832:2684354559]	auto[1]	51	1			T68	2		T194	1		T5	3
auto[2684354560:2818572287]	auto[0]	44	1			T36	1		T97	1		T5	2
auto[2684354560:2818572287]	auto[1]	49	1			T17	1		T18	1		T19	1
auto[2818572288:2952790015]	auto[0]	45	1			T1	1		T18	1		T49	1
auto[2818572288:2952790015]	auto[1]	52	1			T18	2		T199	1		T66	1
auto[2952790016:3087007743]	auto[0]	41	1			T237	1		T69	1		T5	1
auto[2952790016:3087007743]	auto[1]	48	1			T19	1		T48	1		T32	1
auto[3087007744:3221225471]	auto[0]	48	1			T18	1		T48	2		T46	1
auto[3087007744:3221225471]	auto[1]	67	1			T18	1		T78	2		T79	1
auto[3221225472:3355443199]	auto[0]	62	1			T17	1		T18	2		T36	1
auto[3221225472:3355443199]	auto[1]	50	1			T18	1		T78	1		T27	1
auto[3355443200:3489660927]	auto[0]	49	1			T28	1		T5	1		T198	1
auto[3355443200:3489660927]	auto[1]	56	1			T18	1		T27	1		T203	1
auto[3489660928:3623878655]	auto[0]	29	1			T33	1		T83	1		T66	1
auto[3489660928:3623878655]	auto[1]	46	1			T18	1		T117	1		T28	1
auto[3623878656:3758096383]	auto[0]	52	1			T36	1		T227	1		T60	2
auto[3623878656:3758096383]	auto[1]	54	1			T49	1		T20	1		T282	1
auto[3758096384:3892314111]	auto[0]	39	1			T48	2		T28	1		T61	2
auto[3758096384:3892314111]	auto[1]	63	1			T18	2		T97	1		T252	1
auto[3892314112:4026531839]	auto[0]	45	1			T18	1		T139	1		T111	1
auto[3892314112:4026531839]	auto[1]	48	1			T18	2		T27	1		T117	1
auto[4026531840:4160749567]	auto[0]	55	1			T18	1		T8	1		T48	2
auto[4026531840:4160749567]	auto[1]	51	1			T78	1		T48	2		T45	1
auto[4160749568:4294967295]	auto[0]	48	1			T191	1		T68	1		T69	1
auto[4160749568:4294967295]	auto[1]	49	1			T133	1		T50	1		T21	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1512

1

T1

2

T17

7

T18

23

auto[1]

1729

1

T1

2

T17

2

T18

28

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T17	1		T18	1		T33	1
auto[134217728:268435455]	98	1			T18	1		T78	1		T36	1
auto[268435456:402653183]	86	1			T18	1		T33	1		T79	1
auto[402653184:536870911]	107	1			T17	1		T18	1		T36	1
auto[536870912:671088639]	107	1			T33	1		T49	1		T26	1
auto[671088640:805306367]	107	1			T18	3		T19	2		T36	1
auto[805306368:939524095]	106	1			T18	3		T45	1		T237	1
auto[939524096:1073741823]	108	1			T18	3		T79	1		T48	2
auto[1073741824:1207959551]	98	1			T18	1		T78	1		T55	1
auto[1207959552:1342177279]	91	1			T27	1		T96	1		T68	1
auto[1342177280:1476395007]	96	1			T18	1		T192	1		T45	1
auto[1476395008:1610612735]	107	1			T17	2		T18	1		T49	1
auto[1610612736:1744830463]	109	1			T18	4		T117	1		T237	1
auto[1744830464:1879048191]	93	1			T18	4		T19	1		T79	1
auto[1879048192:2013265919]	111	1			T18	2		T36	2		T150	1
auto[2013265920:2147483647]	110	1			T1	1		T18	2		T78	1
auto[2147483648:2281701375]	127	1			T18	2		T49	1		T237	1
auto[2281701376:2415919103]	104	1			T1	1		T18	5		T55	1
auto[2415919104:2550136831]	96	1			T1	1		T18	2		T55	1
auto[2550136832:2684354559]	101	1			T17	1		T18	2		T56	1
auto[2684354560:2818572287]	96	1			T18	1		T26	1		T117	1
auto[2818572288:2952790015]	113	1			T17	1		T18	2		T48	1
auto[2952790016:3087007743]	100	1			T19	1		T33	2		T36	1
auto[3087007744:3221225471]	100	1			T1	1		T17	1		T18	1
auto[3221225472:3355443199]	77	1			T18	1		T55	1		T56	1
auto[3355443200:3489660927]	88	1			T18	1		T133	1		T192	1
auto[3489660928:3623878655]	99	1			T18	1		T27	1		T117	1
auto[3623878656:3758096383]	108	1			T18	1		T192	1		T45	1
auto[3758096384:3892314111]	85	1			T17	1		T18	1		T237	1
auto[3892314112:4026531839]	115	1			T17	1		T78	1		T79	1
auto[4026531840:4160749567]	96	1			T18	2		T79	1		T49	1
auto[4160749568:4294967295]	102	1			T18	1		T78	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T33	1		T78	2		T49	1
auto[0:134217727]	auto[1]	57	1			T17	1		T18	1		T5	1
auto[134217728:268435455]	auto[0]	48	1			T18	1		T78	1		T36	1
auto[134217728:268435455]	auto[1]	50	1			T27	1		T50	1		T48	1
auto[268435456:402653183]	auto[0]	42	1			T55	1		T5	1		T66	1
auto[268435456:402653183]	auto[1]	44	1			T18	1		T33	1		T79	1
auto[402653184:536870911]	auto[0]	54	1			T17	1		T18	1		T36	1
auto[402653184:536870911]	auto[1]	53	1			T48	1		T5	1		T198	1
auto[536870912:671088639]	auto[0]	48	1			T49	1		T48	1		T97	1
auto[536870912:671088639]	auto[1]	59	1			T33	1		T26	1		T47	1
auto[671088640:805306367]	auto[0]	43	1			T18	1		T36	1		T26	1
auto[671088640:805306367]	auto[1]	64	1			T18	2		T19	2		T68	1
auto[805306368:939524095]	auto[0]	50	1			T18	1		T237	1		T150	1
auto[805306368:939524095]	auto[1]	56	1			T18	2		T45	1		T388	1
auto[939524096:1073741823]	auto[0]	50	1			T48	2		T97	2		T227	1
auto[939524096:1073741823]	auto[1]	58	1			T18	3		T79	1		T45	1
auto[1073741824:1207959551]	auto[0]	49	1			T18	1		T78	1		T55	1
auto[1073741824:1207959551]	auto[1]	49	1			T151	1		T5	2		T245	1
auto[1207959552:1342177279]	auto[0]	39	1			T96	1		T5	1		T206	1
auto[1207959552:1342177279]	auto[1]	52	1			T27	1		T68	1		T5	1
auto[1342177280:1476395007]	auto[0]	43	1			T45	1		T191	1		T236	1
auto[1342177280:1476395007]	auto[1]	53	1			T18	1		T192	1		T197	1
auto[1476395008:1610612735]	auto[0]	50	1			T17	2		T18	1		T49	1
auto[1476395008:1610612735]	auto[1]	57	1			T45	1		T5	2		T61	1
auto[1610612736:1744830463]	auto[0]	50	1			T18	2		T97	1		T28	1
auto[1610612736:1744830463]	auto[1]	59	1			T18	2		T117	1		T237	1
auto[1744830464:1879048191]	auto[0]	43	1			T18	2		T150	1		T5	1
auto[1744830464:1879048191]	auto[1]	50	1			T18	2		T19	1		T79	1
auto[1879048192:2013265919]	auto[0]	51	1			T18	1		T36	1		T28	1
auto[1879048192:2013265919]	auto[1]	60	1			T18	1		T36	1		T150	1
auto[2013265920:2147483647]	auto[0]	59	1			T1	1		T18	1		T48	1
auto[2013265920:2147483647]	auto[1]	51	1			T18	1		T78	1		T56	1
auto[2147483648:2281701375]	auto[0]	55	1			T18	1		T237	1		T97	1
auto[2147483648:2281701375]	auto[1]	72	1			T18	1		T49	1		T203	1
auto[2281701376:2415919103]	auto[0]	54	1			T1	1		T18	4		T26	1
auto[2281701376:2415919103]	auto[1]	50	1			T18	1		T55	1		T27	1
auto[2415919104:2550136831]	auto[0]	43	1			T55	1		T5	2		T61	2
auto[2415919104:2550136831]	auto[1]	53	1			T1	1		T18	2		T48	1
auto[2550136832:2684354559]	auto[0]	45	1			T17	1		T18	1		T68	1
auto[2550136832:2684354559]	auto[1]	56	1			T18	1		T56	1		T47	1
auto[2684354560:2818572287]	auto[0]	42	1			T117	1		T56	1		T237	1
auto[2684354560:2818572287]	auto[1]	54	1			T18	1		T26	1		T48	1
auto[2818572288:2952790015]	auto[0]	62	1			T17	1		T48	1		T97	1
auto[2818572288:2952790015]	auto[1]	51	1			T18	2		T5	1		T9	1
auto[2952790016:3087007743]	auto[0]	50	1			T33	1		T36	1		T68	1
auto[2952790016:3087007743]	auto[1]	50	1			T19	1		T33	1		T49	1
auto[3087007744:3221225471]	auto[0]	42	1			T17	1		T48	1		T237	1
auto[3087007744:3221225471]	auto[1]	58	1			T1	1		T18	1		T135	1
auto[3221225472:3355443199]	auto[0]	39	1			T55	1		T56	1		T48	2
auto[3221225472:3355443199]	auto[1]	38	1			T18	1		T5	1		T245	1
auto[3355443200:3489660927]	auto[0]	35	1			T18	1		T237	1		T68	1
auto[3355443200:3489660927]	auto[1]	53	1			T133	1		T192	1		T48	1
auto[3489660928:3623878655]	auto[0]	46	1			T18	1		T117	1		T48	2
auto[3489660928:3623878655]	auto[1]	53	1			T27	1		T48	1		T191	1
auto[3623878656:3758096383]	auto[0]	50	1			T18	1		T61	2		T111	1
auto[3623878656:3758096383]	auto[1]	58	1			T192	1		T45	1		T237	1
auto[3758096384:3892314111]	auto[0]	44	1			T237	1		T227	1		T194	1
auto[3758096384:3892314111]	auto[1]	41	1			T17	1		T18	1		T51	1
auto[3892314112:4026531839]	auto[0]	54	1			T17	1		T36	1		T48	1
auto[3892314112:4026531839]	auto[1]	61	1			T78	1		T79	1		T36	1
auto[4026531840:4160749567]	auto[0]	44	1			T18	1		T49	1		T5	1
auto[4026531840:4160749567]	auto[1]	52	1			T18	1		T79	1		T48	1
auto[4160749568:4294967295]	auto[0]	45	1			T18	1		T97	1		T227	1
auto[4160749568:4294967295]	auto[1]	57	1			T78	1		T48	1		T5	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1510

1

T1

2

T17

7

T18

21

auto[1]

1731

1

T1

2

T17

2

T18

30

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T1	1		T17	1		T78	1
auto[134217728:268435455]	107	1			T18	1		T78	1		T79	1
auto[268435456:402653183]	95	1			T18	1		T36	1		T26	1
auto[402653184:536870911]	103	1			T18	3		T78	1		T49	1
auto[536870912:671088639]	86	1			T18	1		T78	1		T48	2
auto[671088640:805306367]	104	1			T18	1		T49	1		T48	3
auto[805306368:939524095]	80	1			T17	1		T79	1		T192	1
auto[939524096:1073741823]	100	1			T78	1		T36	1		T55	1
auto[1073741824:1207959551]	107	1			T18	2		T8	1		T48	1
auto[1207959552:1342177279]	106	1			T18	2		T79	1		T398	1
auto[1342177280:1476395007]	111	1			T33	1		T48	1		T150	1
auto[1476395008:1610612735]	104	1			T17	1		T18	1		T78	1
auto[1610612736:1744830463]	100	1			T18	5		T36	1		T26	1
auto[1744830464:1879048191]	94	1			T1	1		T17	1		T18	1
auto[1879048192:2013265919]	98	1			T18	3		T48	1		T203	1
auto[2013265920:2147483647]	93	1			T18	1		T48	1		T97	1
auto[2147483648:2281701375]	99	1			T18	1		T33	1		T27	1
auto[2281701376:2415919103]	115	1			T18	3		T33	1		T36	1
auto[2415919104:2550136831]	110	1			T27	1		T56	1		T135	1
auto[2550136832:2684354559]	106	1			T18	2		T36	1		T237	3
auto[2684354560:2818572287]	87	1			T17	1		T18	1		T19	1
auto[2818572288:2952790015]	98	1			T17	1		T48	1		T20	1
auto[2952790016:3087007743]	104	1			T1	2		T18	1		T19	1
auto[3087007744:3221225471]	115	1			T17	1		T18	1		T33	1
auto[3221225472:3355443199]	102	1			T17	2		T18	4		T79	1
auto[3355443200:3489660927]	85	1			T18	2		T19	1		T36	1
auto[3489660928:3623878655]	104	1			T18	4		T117	1		T56	1
auto[3623878656:3758096383]	100	1			T18	4		T55	1		T49	2
auto[3758096384:3892314111]	107	1			T18	1		T49	1		T26	1
auto[3892314112:4026531839]	106	1			T18	2		T19	1		T33	1
auto[4026531840:4160749567]	102	1			T18	3		T27	1		T48	3
auto[4160749568:4294967295]	111	1			T55	1		T237	1		T68	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T1	1		T17	1		T237	1
auto[0:134217727]	auto[1]	56	1			T78	1		T79	1		T68	1
auto[134217728:268435455]	auto[0]	45	1			T18	1		T79	1		T97	1
auto[134217728:268435455]	auto[1]	62	1			T78	1		T49	1		T117	1
auto[268435456:402653183]	auto[0]	48	1			T26	1		T117	1		T56	1
auto[268435456:402653183]	auto[1]	47	1			T18	1		T36	1		T48	1
auto[402653184:536870911]	auto[0]	57	1			T18	2		T78	1		T49	1
auto[402653184:536870911]	auto[1]	46	1			T18	1		T135	1		T47	1
auto[536870912:671088639]	auto[0]	44	1			T78	1		T191	1		T236	1
auto[536870912:671088639]	auto[1]	42	1			T18	1		T48	2		T83	1
auto[671088640:805306367]	auto[0]	47	1			T49	1		T48	1		T45	1
auto[671088640:805306367]	auto[1]	57	1			T18	1		T48	2		T45	1
auto[805306368:939524095]	auto[0]	33	1			T17	1		T79	1		T48	1
auto[805306368:939524095]	auto[1]	47	1			T192	1		T45	1		T97	1
auto[939524096:1073741823]	auto[0]	54	1			T36	1		T55	1		T48	1
auto[939524096:1073741823]	auto[1]	46	1			T78	1		T51	1		T97	1
auto[1073741824:1207959551]	auto[0]	50	1			T8	1		T48	1		T150	1
auto[1073741824:1207959551]	auto[1]	57	1			T18	2		T21	1		T111	1
auto[1207959552:1342177279]	auto[0]	39	1			T398	1		T5	1		T139	1
auto[1207959552:1342177279]	auto[1]	67	1			T18	2		T79	1		T5	2
auto[1342177280:1476395007]	auto[0]	42	1			T33	1		T5	1		T61	1
auto[1342177280:1476395007]	auto[1]	69	1			T48	1		T150	1		T398	1
auto[1476395008:1610612735]	auto[0]	52	1			T48	2		T45	1		T237	1
auto[1476395008:1610612735]	auto[1]	52	1			T17	1		T18	1		T78	1
auto[1610612736:1744830463]	auto[0]	41	1			T18	4		T36	1		T27	1
auto[1610612736:1744830463]	auto[1]	59	1			T18	1		T26	1		T192	1
auto[1744830464:1879048191]	auto[0]	45	1			T17	1		T18	1		T36	1
auto[1744830464:1879048191]	auto[1]	49	1			T1	1		T192	1		T5	2
auto[1879048192:2013265919]	auto[0]	48	1			T18	1		T48	1		T68	2
auto[1879048192:2013265919]	auto[1]	50	1			T18	2		T203	1		T398	1
auto[2013265920:2147483647]	auto[0]	41	1			T97	1		T68	1		T236	1
auto[2013265920:2147483647]	auto[1]	52	1			T18	1		T48	1		T194	1
auto[2147483648:2281701375]	auto[0]	46	1			T18	1		T60	1		T61	1
auto[2147483648:2281701375]	auto[1]	53	1			T33	1		T27	1		T50	1
auto[2281701376:2415919103]	auto[0]	55	1			T18	1		T150	1		T5	1
auto[2281701376:2415919103]	auto[1]	60	1			T18	2		T33	1		T36	1
auto[2415919104:2550136831]	auto[0]	51	1			T48	1		T237	1		T150	1
auto[2415919104:2550136831]	auto[1]	59	1			T27	1		T56	1		T135	1
auto[2550136832:2684354559]	auto[0]	55	1			T18	1		T36	1		T237	3
auto[2550136832:2684354559]	auto[1]	51	1			T18	1		T197	1		T9	1
auto[2684354560:2818572287]	auto[0]	38	1			T17	1		T78	1		T97	1
auto[2684354560:2818572287]	auto[1]	49	1			T18	1		T19	1		T51	1
auto[2818572288:2952790015]	auto[0]	44	1			T48	1		T5	1		T204	1
auto[2818572288:2952790015]	auto[1]	54	1			T17	1		T20	1		T21	1
auto[2952790016:3087007743]	auto[0]	52	1			T1	1		T55	1		T48	1
auto[2952790016:3087007743]	auto[1]	52	1			T1	1		T18	1		T19	1
auto[3087007744:3221225471]	auto[0]	56	1			T17	1		T18	1		T36	1
auto[3087007744:3221225471]	auto[1]	59	1			T33	1		T26	1		T48	1
auto[3221225472:3355443199]	auto[0]	42	1			T17	2		T18	3		T69	1
auto[3221225472:3355443199]	auto[1]	60	1			T18	1		T79	1		T96	1
auto[3355443200:3489660927]	auto[0]	31	1			T18	1		T19	1		T36	1
auto[3355443200:3489660927]	auto[1]	54	1			T18	1		T133	1		T50	1
auto[3489660928:3623878655]	auto[0]	43	1			T18	1		T56	1		T48	2
auto[3489660928:3623878655]	auto[1]	61	1			T18	3		T117	1		T237	1
auto[3623878656:3758096383]	auto[0]	56	1			T18	1		T49	1		T68	1
auto[3623878656:3758096383]	auto[1]	44	1			T18	3		T55	1		T49	1
auto[3758096384:3892314111]	auto[0]	52	1			T139	1		T61	1		T6	1
auto[3758096384:3892314111]	auto[1]	55	1			T18	1		T49	1		T26	1
auto[3892314112:4026531839]	auto[0]	58	1			T55	1		T45	1		T97	2
auto[3892314112:4026531839]	auto[1]	48	1			T18	2		T19	1		T33	1
auto[4026531840:4160749567]	auto[0]	50	1			T18	2		T69	1		T5	1
auto[4026531840:4160749567]	auto[1]	52	1			T18	1		T27	1		T48	3
auto[4160749568:4294967295]	auto[0]	49	1			T55	1		T68	1		T28	1
auto[4160749568:4294967295]	auto[1]	62	1			T237	1		T194	1		T69	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1524

1

T1

2

T17

7

T18

22

auto[1]

1718

1

T1

2

T17

2

T18

29

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	84	1			T18	1		T19	1		T33	1
auto[134217728:268435455]	108	1			T18	1		T78	2		T36	2
auto[268435456:402653183]	97	1			T17	1		T18	2		T192	1
auto[402653184:536870911]	109	1			T18	1		T36	1		T48	2
auto[536870912:671088639]	103	1			T18	1		T78	2		T79	1
auto[671088640:805306367]	107	1			T18	2		T33	1		T79	1
auto[805306368:939524095]	91	1			T18	1		T19	1		T45	1
auto[939524096:1073741823]	99	1			T17	1		T18	1		T19	1
auto[1073741824:1207959551]	117	1			T78	2		T48	1		T51	1
auto[1207959552:1342177279]	105	1			T17	1		T18	2		T33	1
auto[1342177280:1476395007]	115	1			T18	1		T26	1		T191	1
auto[1476395008:1610612735]	101	1			T18	3		T48	1		T97	1
auto[1610612736:1744830463]	110	1			T1	1		T18	3		T33	1
auto[1744830464:1879048191]	122	1			T1	1		T18	2		T79	1
auto[1879048192:2013265919]	86	1			T18	1		T27	1		T192	1
auto[2013265920:2147483647]	97	1			T117	1		T48	2		T20	1
auto[2147483648:2281701375]	84	1			T18	1		T36	1		T49	1
auto[2281701376:2415919103]	100	1			T18	1		T27	2		T96	1
auto[2415919104:2550136831]	98	1			T18	1		T36	1		T135	1
auto[2550136832:2684354559]	84	1			T17	2		T18	3		T36	1
auto[2684354560:2818572287]	83	1			T17	1		T18	1		T49	2
auto[2818572288:2952790015]	102	1			T1	1		T18	3		T135	1
auto[2952790016:3087007743]	125	1			T18	1		T79	1		T252	1
auto[3087007744:3221225471]	97	1			T17	1		T18	1		T78	1
auto[3221225472:3355443199]	114	1			T18	3		T55	1		T48	1
auto[3355443200:3489660927]	92	1			T18	2		T19	1		T33	1
auto[3489660928:3623878655]	95	1			T1	1		T36	1		T55	1
auto[3623878656:3758096383]	96	1			T17	1		T18	2		T79	1
auto[3758096384:3892314111]	121	1			T17	1		T18	6		T117	1
auto[3892314112:4026531839]	94	1			T18	1		T117	1		T47	1
auto[4026531840:4160749567]	102	1			T55	1		T133	1		T50	1
auto[4160749568:4294967295]	104	1			T18	3		T56	1		T252	1