Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2867

1

T1

4

T17

9

T18

44

auto[1]

294

1

T19

5

T79

7

T117

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T17	1		T36	1		T27	1
auto[134217728:268435455]	114	1			T17	2		T18	3		T78	1
auto[268435456:402653183]	99	1			T17	1		T18	3		T48	1
auto[402653184:536870911]	110	1			T18	1		T19	1		T26	1
auto[536870912:671088639]	110	1			T18	2		T78	2		T79	1
auto[671088640:805306367]	101	1			T18	1		T19	2		T36	1
auto[805306368:939524095]	104	1			T18	1		T19	1		T78	1
auto[939524096:1073741823]	99	1			T18	3		T79	1		T117	1
auto[1073741824:1207959551]	92	1			T17	1		T117	2		T45	1
auto[1207959552:1342177279]	96	1			T18	2		T117	1		T133	1
auto[1342177280:1476395007]	108	1			T17	1		T18	1		T26	1
auto[1476395008:1610612735]	77	1			T18	1		T19	1		T55	1
auto[1610612736:1744830463]	104	1			T18	1		T117	1		T56	1
auto[1744830464:1879048191]	105	1			T19	1		T79	1		T48	1
auto[1879048192:2013265919]	96	1			T78	1		T50	1		T237	1
auto[2013265920:2147483647]	99	1			T17	2		T18	2		T48	1
auto[2147483648:2281701375]	106	1			T1	2		T18	1		T79	1
auto[2281701376:2415919103]	100	1			T33	1		T192	2		T48	1
auto[2415919104:2550136831]	102	1			T18	3		T97	1		T46	1
auto[2550136832:2684354559]	97	1			T18	2		T27	1		T48	1
auto[2684354560:2818572287]	107	1			T18	1		T33	1		T78	1
auto[2818572288:2952790015]	115	1			T18	2		T19	2		T78	1
auto[2952790016:3087007743]	93	1			T18	2		T36	1		T26	1
auto[3087007744:3221225471]	97	1			T33	1		T27	1		T48	1
auto[3221225472:3355443199]	97	1			T17	1		T18	3		T79	1
auto[3355443200:3489660927]	90	1			T1	1		T18	3		T49	1
auto[3489660928:3623878655]	102	1			T1	1		T18	1		T33	1
auto[3623878656:3758096383]	94	1			T79	1		T48	1		T150	3
auto[3758096384:3892314111]	79	1			T18	1		T19	1		T27	1
auto[3892314112:4026531839]	96	1			T18	1		T33	1		T79	1
auto[4026531840:4160749567]	95	1			T18	2		T79	1		T36	2
auto[4160749568:4294967295]	81	1			T18	1		T49	1		T236	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	86	1			T17	1		T36	1		T27	1
auto[0:134217727]	auto[1]	10	1			T151	1		T139	1		T282	1
auto[134217728:268435455]	auto[0]	106	1			T17	2		T18	3		T78	1
auto[134217728:268435455]	auto[1]	8	1			T150	1		T282	1		T395	1
auto[268435456:402653183]	auto[0]	96	1			T17	1		T18	3		T48	1
auto[268435456:402653183]	auto[1]	3	1			T402	1		T346	1		T344	1
auto[402653184:536870911]	auto[0]	100	1			T18	1		T26	1		T56	1
auto[402653184:536870911]	auto[1]	10	1			T19	1		T151	3		T250	2
auto[536870912:671088639]	auto[0]	96	1			T18	2		T78	2		T55	2
auto[536870912:671088639]	auto[1]	14	1			T79	1		T178	1		T255	1
auto[671088640:805306367]	auto[0]	89	1			T18	1		T36	1		T26	1
auto[671088640:805306367]	auto[1]	12	1			T19	2		T117	1		T150	1
auto[805306368:939524095]	auto[0]	93	1			T18	1		T19	1		T78	1
auto[805306368:939524095]	auto[1]	11	1			T178	2		T250	1		T392	1
auto[939524096:1073741823]	auto[0]	90	1			T18	3		T79	1		T117	1
auto[939524096:1073741823]	auto[1]	9	1			T150	1		T151	1		T141	1
auto[1073741824:1207959551]	auto[0]	79	1			T17	1		T45	1		T237	1
auto[1073741824:1207959551]	auto[1]	13	1			T117	2		T141	1		T267	1
auto[1207959552:1342177279]	auto[0]	88	1			T18	2		T133	1		T48	1
auto[1207959552:1342177279]	auto[1]	8	1			T117	1		T150	1		T151	1
auto[1342177280:1476395007]	auto[0]	94	1			T17	1		T18	1		T26	1
auto[1342177280:1476395007]	auto[1]	14	1			T150	1		T151	1		T139	1
auto[1476395008:1610612735]	auto[0]	70	1			T18	1		T19	1		T55	1
auto[1476395008:1610612735]	auto[1]	7	1			T402	1		T333	1		T225	2
auto[1610612736:1744830463]	auto[0]	99	1			T18	1		T117	1		T56	1
auto[1610612736:1744830463]	auto[1]	5	1			T282	1		T178	1		T250	1
auto[1744830464:1879048191]	auto[0]	97	1			T79	1		T48	1		T45	1
auto[1744830464:1879048191]	auto[1]	8	1			T19	1		T139	1		T381	1
auto[1879048192:2013265919]	auto[0]	87	1			T78	1		T50	1		T237	1
auto[1879048192:2013265919]	auto[1]	9	1			T150	1		T151	2		T255	2
auto[2013265920:2147483647]	auto[0]	92	1			T17	2		T18	2		T48	1
auto[2013265920:2147483647]	auto[1]	7	1			T150	1		T282	1		T383	1
auto[2147483648:2281701375]	auto[0]	101	1			T1	2		T18	1		T79	1
auto[2147483648:2281701375]	auto[1]	5	1			T355	1		T250	1		T297	1
auto[2281701376:2415919103]	auto[0]	92	1			T33	1		T192	2		T48	1
auto[2281701376:2415919103]	auto[1]	8	1			T139	1		T141	1		T333	2
auto[2415919104:2550136831]	auto[0]	94	1			T18	3		T97	1		T46	1
auto[2415919104:2550136831]	auto[1]	8	1			T380	1		T240	1		T254	1
auto[2550136832:2684354559]	auto[0]	84	1			T18	2		T27	1		T48	1
auto[2550136832:2684354559]	auto[1]	13	1			T150	1		T151	1		T139	2
auto[2684354560:2818572287]	auto[0]	90	1			T18	1		T33	1		T78	1
auto[2684354560:2818572287]	auto[1]	17	1			T79	2		T141	1		T255	1
auto[2818572288:2952790015]	auto[0]	101	1			T18	2		T19	2		T78	1
auto[2818572288:2952790015]	auto[1]	14	1			T79	1		T151	1		T139	1
auto[2952790016:3087007743]	auto[0]	88	1			T18	2		T36	1		T26	1
auto[2952790016:3087007743]	auto[1]	5	1			T250	1		T393	1		T254	1
auto[3087007744:3221225471]	auto[0]	91	1			T33	1		T27	1		T48	1
auto[3087007744:3221225471]	auto[1]	6	1			T139	1		T250	1		T240	1
auto[3221225472:3355443199]	auto[0]	91	1			T17	1		T18	3		T36	1
auto[3221225472:3355443199]	auto[1]	6	1			T79	1		T255	1		T355	1
auto[3355443200:3489660927]	auto[0]	79	1			T1	1		T18	3		T49	1
auto[3355443200:3489660927]	auto[1]	11	1			T282	2		T402	1		T225	1
auto[3489660928:3623878655]	auto[0]	93	1			T1	1		T18	1		T33	1
auto[3489660928:3623878655]	auto[1]	9	1			T79	1		T117	1		T141	1
auto[3623878656:3758096383]	auto[0]	80	1			T79	1		T48	1		T150	1
auto[3623878656:3758096383]	auto[1]	14	1			T150	2		T178	1		T141	1
auto[3758096384:3892314111]	auto[0]	73	1			T18	1		T27	1		T56	1
auto[3758096384:3892314111]	auto[1]	6	1			T19	1		T402	1		T297	1
auto[3892314112:4026531839]	auto[0]	84	1			T18	1		T33	1		T8	1
auto[3892314112:4026531839]	auto[1]	12	1			T79	1		T117	1		T255	1
auto[4026531840:4160749567]	auto[0]	90	1			T18	2		T79	1		T36	2
auto[4026531840:4160749567]	auto[1]	5	1			T282	1		T241	2		T382	1
auto[4160749568:4294967295]	auto[0]	74	1			T18	1		T49	1		T236	1
auto[4160749568:4294967295]	auto[1]	7	1			T139	1		T392	1		T297	1