Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.19 98.28 100.00 99.02 98.41 91.22


Total test records in report: 1075
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T1006 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4065121780 Jul 27 06:34:40 PM PDT 24 Jul 27 06:34:41 PM PDT 24 155474166 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1908425792 Jul 27 06:34:29 PM PDT 24 Jul 27 06:34:30 PM PDT 24 36940183 ps
T1008 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2101155376 Jul 27 06:34:38 PM PDT 24 Jul 27 06:34:41 PM PDT 24 99917791 ps
T1009 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2916686321 Jul 27 06:34:46 PM PDT 24 Jul 27 06:34:53 PM PDT 24 1311889788 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1183913027 Jul 27 06:34:31 PM PDT 24 Jul 27 06:34:38 PM PDT 24 219640233 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3802058621 Jul 27 06:34:42 PM PDT 24 Jul 27 06:34:43 PM PDT 24 48290553 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3959550069 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:49 PM PDT 24 132680703 ps
T1013 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1119488586 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:48 PM PDT 24 19886224 ps
T155 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2414961267 Jul 27 06:34:46 PM PDT 24 Jul 27 06:34:51 PM PDT 24 102674539 ps
T1014 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3812894251 Jul 27 06:35:04 PM PDT 24 Jul 27 06:35:05 PM PDT 24 18206533 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3295939558 Jul 27 06:34:15 PM PDT 24 Jul 27 06:34:16 PM PDT 24 13606651 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2950438413 Jul 27 06:34:31 PM PDT 24 Jul 27 06:34:35 PM PDT 24 458245581 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.460661619 Jul 27 06:34:49 PM PDT 24 Jul 27 06:34:55 PM PDT 24 218776155 ps
T1018 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3944600305 Jul 27 06:34:57 PM PDT 24 Jul 27 06:35:02 PM PDT 24 340620111 ps
T1019 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3142677907 Jul 27 06:34:49 PM PDT 24 Jul 27 06:34:52 PM PDT 24 160972469 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.936824722 Jul 27 06:34:41 PM PDT 24 Jul 27 06:34:44 PM PDT 24 416651166 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.689134143 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:49 PM PDT 24 21775281 ps
T1022 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2093098656 Jul 27 06:34:55 PM PDT 24 Jul 27 06:34:55 PM PDT 24 11316468 ps
T1023 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2407824684 Jul 27 06:35:16 PM PDT 24 Jul 27 06:35:17 PM PDT 24 45380763 ps
T1024 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3908789046 Jul 27 06:34:42 PM PDT 24 Jul 27 06:34:47 PM PDT 24 584699166 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2494739669 Jul 27 06:34:52 PM PDT 24 Jul 27 06:34:56 PM PDT 24 288434482 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2156797610 Jul 27 06:34:30 PM PDT 24 Jul 27 06:34:31 PM PDT 24 11802320 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2767036269 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:48 PM PDT 24 14770583 ps
T1028 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2689096956 Jul 27 06:34:56 PM PDT 24 Jul 27 06:34:59 PM PDT 24 508784905 ps
T1029 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1248718945 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:53 PM PDT 24 91585747 ps
T1030 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2680864538 Jul 27 06:35:16 PM PDT 24 Jul 27 06:35:17 PM PDT 24 10983025 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1034696555 Jul 27 06:35:02 PM PDT 24 Jul 27 06:35:03 PM PDT 24 80726006 ps
T1032 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1144548508 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:51 PM PDT 24 303007414 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1262693948 Jul 27 06:34:17 PM PDT 24 Jul 27 06:34:19 PM PDT 24 26142757 ps
T1034 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3491152048 Jul 27 06:35:01 PM PDT 24 Jul 27 06:35:03 PM PDT 24 193781048 ps
T1035 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.938153489 Jul 27 06:34:38 PM PDT 24 Jul 27 06:34:39 PM PDT 24 91338954 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3493486361 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:49 PM PDT 24 363539136 ps
T1037 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.510842695 Jul 27 06:35:04 PM PDT 24 Jul 27 06:35:05 PM PDT 24 7597192 ps
T1038 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3634980461 Jul 27 06:34:41 PM PDT 24 Jul 27 06:34:43 PM PDT 24 80913641 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.502030755 Jul 27 06:34:46 PM PDT 24 Jul 27 06:34:51 PM PDT 24 185955009 ps
T1040 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.730035308 Jul 27 06:34:41 PM PDT 24 Jul 27 06:34:43 PM PDT 24 757377948 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3371870475 Jul 27 06:34:13 PM PDT 24 Jul 27 06:34:24 PM PDT 24 436716691 ps
T1042 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2396681537 Jul 27 06:34:46 PM PDT 24 Jul 27 06:34:48 PM PDT 24 322792269 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2110324678 Jul 27 06:34:48 PM PDT 24 Jul 27 06:34:49 PM PDT 24 23557066 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3102195835 Jul 27 06:34:36 PM PDT 24 Jul 27 06:34:37 PM PDT 24 31936888 ps
T1045 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2333966163 Jul 27 06:34:41 PM PDT 24 Jul 27 06:34:44 PM PDT 24 406473946 ps
T1046 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2795161896 Jul 27 06:34:33 PM PDT 24 Jul 27 06:34:40 PM PDT 24 261016504 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.238138221 Jul 27 06:34:36 PM PDT 24 Jul 27 06:34:38 PM PDT 24 164528155 ps
T1048 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1948282650 Jul 27 06:34:48 PM PDT 24 Jul 27 06:34:49 PM PDT 24 97048230 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1609719607 Jul 27 06:34:49 PM PDT 24 Jul 27 06:34:53 PM PDT 24 68375287 ps
T1050 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3311019596 Jul 27 06:34:58 PM PDT 24 Jul 27 06:35:00 PM PDT 24 125406663 ps
T1051 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.729389529 Jul 27 06:34:56 PM PDT 24 Jul 27 06:34:57 PM PDT 24 23718456 ps
T160 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2861689985 Jul 27 06:34:42 PM PDT 24 Jul 27 06:34:49 PM PDT 24 277037666 ps
T1052 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3634381082 Jul 27 06:34:30 PM PDT 24 Jul 27 06:34:33 PM PDT 24 127817515 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.260545875 Jul 27 06:35:02 PM PDT 24 Jul 27 06:35:04 PM PDT 24 138072253 ps
T1054 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.783582757 Jul 27 06:34:46 PM PDT 24 Jul 27 06:34:48 PM PDT 24 39535116 ps
T171 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3035670724 Jul 27 06:34:56 PM PDT 24 Jul 27 06:34:59 PM PDT 24 113861249 ps
T1055 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.113010966 Jul 27 06:34:40 PM PDT 24 Jul 27 06:34:48 PM PDT 24 556802066 ps
T1056 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1388733152 Jul 27 06:35:03 PM PDT 24 Jul 27 06:35:04 PM PDT 24 58241064 ps
T164 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.147310991 Jul 27 06:34:50 PM PDT 24 Jul 27 06:34:53 PM PDT 24 159800192 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1800049361 Jul 27 06:34:40 PM PDT 24 Jul 27 06:34:41 PM PDT 24 64649798 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3231771967 Jul 27 06:34:53 PM PDT 24 Jul 27 06:34:54 PM PDT 24 102949788 ps
T1059 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2119967985 Jul 27 06:34:34 PM PDT 24 Jul 27 06:34:36 PM PDT 24 104848336 ps
T1060 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1788483363 Jul 27 06:35:16 PM PDT 24 Jul 27 06:35:17 PM PDT 24 23050975 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4218887277 Jul 27 06:34:29 PM PDT 24 Jul 27 06:34:35 PM PDT 24 253760995 ps
T1062 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2186145458 Jul 27 06:35:02 PM PDT 24 Jul 27 06:35:05 PM PDT 24 1266436437 ps
T1063 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.787783470 Jul 27 06:34:48 PM PDT 24 Jul 27 06:34:50 PM PDT 24 49966358 ps
T1064 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3725581140 Jul 27 06:34:42 PM PDT 24 Jul 27 06:34:43 PM PDT 24 48249333 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1149820899 Jul 27 06:34:17 PM PDT 24 Jul 27 06:34:17 PM PDT 24 14823199 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1980901239 Jul 27 06:34:30 PM PDT 24 Jul 27 06:34:39 PM PDT 24 196031584 ps
T1067 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1908356976 Jul 27 06:34:33 PM PDT 24 Jul 27 06:34:35 PM PDT 24 718636237 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3324975195 Jul 27 06:34:49 PM PDT 24 Jul 27 06:34:49 PM PDT 24 10910386 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.35891304 Jul 27 06:34:31 PM PDT 24 Jul 27 06:34:34 PM PDT 24 108489590 ps
T370 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1112352727 Jul 27 06:34:28 PM PDT 24 Jul 27 06:34:34 PM PDT 24 413693180 ps
T1070 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3345599962 Jul 27 06:34:47 PM PDT 24 Jul 27 06:34:52 PM PDT 24 132533863 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3274209755 Jul 27 06:34:29 PM PDT 24 Jul 27 06:34:30 PM PDT 24 54684709 ps
T1072 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.979400166 Jul 27 06:34:12 PM PDT 24 Jul 27 06:34:16 PM PDT 24 274838088 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2166310665 Jul 27 06:34:56 PM PDT 24 Jul 27 06:35:03 PM PDT 24 207684722 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4229402957 Jul 27 06:34:58 PM PDT 24 Jul 27 06:35:13 PM PDT 24 1889369124 ps
T1075 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.947193240 Jul 27 06:35:14 PM PDT 24 Jul 27 06:35:15 PM PDT 24 29337220 ps

Test location /workspace/coverage/default/30.keymgr_stress_all.1999779677
Short name T18
Test name
Test status
Simulation time 1457219784 ps
CPU time 51.17 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:42:17 PM PDT 24
Peak memory 215228 kb
Host smart-0825e163-5214-4882-ae5f-c8e8a9482193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999779677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1999779677
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4165531794
Short name T5
Test name
Test status
Simulation time 4550236587 ps
CPU time 40.46 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:42:23 PM PDT 24
Peak memory 222464 kb
Host smart-81610bfd-3a56-483c-b0da-b7a9067ce2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165531794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4165531794
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2377653057
Short name T124
Test name
Test status
Simulation time 902286995 ps
CPU time 14.17 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 222372 kb
Host smart-cd11f25b-3d8f-48e7-9420-cce5c426e88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377653057 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2377653057
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.59378880
Short name T12
Test name
Test status
Simulation time 441879465 ps
CPU time 13.18 seconds
Started Jul 27 05:40:18 PM PDT 24
Finished Jul 27 05:40:32 PM PDT 24
Peak memory 238104 kb
Host smart-17b4d863-edfe-4a04-a45f-c80f0de27b85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59378880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.59378880
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2231155504
Short name T17
Test name
Test status
Simulation time 151665897 ps
CPU time 3.05 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 222124 kb
Host smart-b1f17e36-c1e1-4fa9-8bfb-7067156d445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231155504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2231155504
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.995310817
Short name T139
Test name
Test status
Simulation time 8125231585 ps
CPU time 116.51 seconds
Started Jul 27 05:41:39 PM PDT 24
Finished Jul 27 05:43:35 PM PDT 24
Peak memory 218920 kb
Host smart-ad030f4a-8978-4f4b-8874-c437bf60a7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995310817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.995310817
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1200907963
Short name T8
Test name
Test status
Simulation time 478596814 ps
CPU time 2.47 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 222536 kb
Host smart-67ecf06d-2db2-496a-82f2-021e05b9840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200907963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1200907963
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4101877929
Short name T97
Test name
Test status
Simulation time 684196305 ps
CPU time 4.45 seconds
Started Jul 27 05:40:58 PM PDT 24
Finished Jul 27 05:41:02 PM PDT 24
Peak memory 214048 kb
Host smart-9e350922-c3c9-4d3f-8168-2e9c51b997e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101877929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4101877929
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.69683039
Short name T114
Test name
Test status
Simulation time 1418141007 ps
CPU time 10.02 seconds
Started Jul 27 06:34:39 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 220232 kb
Host smart-01fac589-ff29-41f5-a190-6cdfce39e0d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69683039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.69683039
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3179922345
Short name T6
Test name
Test status
Simulation time 1636003929 ps
CPU time 19.49 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 223008 kb
Host smart-51e9acba-19c3-45a9-8787-d6cb6c695d2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179922345 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3179922345
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4009984321
Short name T61
Test name
Test status
Simulation time 6704039528 ps
CPU time 57.5 seconds
Started Jul 27 05:41:12 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 222368 kb
Host smart-15ecab43-7841-41ca-a79a-7a7b21cd1ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009984321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4009984321
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1844455444
Short name T225
Test name
Test status
Simulation time 1613752294 ps
CPU time 11.9 seconds
Started Jul 27 05:41:59 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 214172 kb
Host smart-b10f024e-11be-494f-b5a2-665b122d860e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844455444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1844455444
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3264606184
Short name T83
Test name
Test status
Simulation time 353626559 ps
CPU time 3.67 seconds
Started Jul 27 05:40:26 PM PDT 24
Finished Jul 27 05:40:29 PM PDT 24
Peak memory 208780 kb
Host smart-ebfa1ea3-b980-49bb-9669-99a49ca75f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264606184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3264606184
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3765814127
Short name T141
Test name
Test status
Simulation time 291047413 ps
CPU time 7.92 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 215156 kb
Host smart-df4aba94-ea2f-4e91-bfda-9ddba3faee1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765814127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3765814127
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2552034964
Short name T19
Test name
Test status
Simulation time 233135683 ps
CPU time 12.68 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:17 PM PDT 24
Peak memory 214144 kb
Host smart-0bbf4154-4fa9-4343-8786-03d0739e74cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552034964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2552034964
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3990427911
Short name T48
Test name
Test status
Simulation time 24772616114 ps
CPU time 35.26 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:41:15 PM PDT 24
Peak memory 221304 kb
Host smart-89f297f0-ac1d-4e9f-9b3d-c433af94d061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990427911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3990427911
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1288475924
Short name T161
Test name
Test status
Simulation time 347497215 ps
CPU time 4.2 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 213848 kb
Host smart-d3391811-94f5-4dbc-a302-7a35025426aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288475924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1288475924
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.746606920
Short name T40
Test name
Test status
Simulation time 52467569 ps
CPU time 2.18 seconds
Started Jul 27 05:40:02 PM PDT 24
Finished Jul 27 05:40:04 PM PDT 24
Peak memory 209668 kb
Host smart-8b8e2242-0271-41ba-bed9-382e49447dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746606920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.746606920
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3988212991
Short name T352
Test name
Test status
Simulation time 752888191 ps
CPU time 42.43 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:42:33 PM PDT 24
Peak memory 215316 kb
Host smart-e306702c-d277-4700-aa6b-67c280298501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988212991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3988212991
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4015441524
Short name T185
Test name
Test status
Simulation time 32801077898 ps
CPU time 61.53 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 215824 kb
Host smart-6153d7a9-ab80-4ef3-aa4c-3761fa198125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015441524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4015441524
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.276273087
Short name T344
Test name
Test status
Simulation time 282358672 ps
CPU time 7.65 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:17 PM PDT 24
Peak memory 222220 kb
Host smart-58107b36-d2df-4772-b28f-ccfa63673a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276273087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.276273087
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2791642965
Short name T38
Test name
Test status
Simulation time 60148305 ps
CPU time 2.61 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 214124 kb
Host smart-b97b0c8e-8f23-495b-8923-5f8df279e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791642965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2791642965
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2941201002
Short name T56
Test name
Test status
Simulation time 376451832 ps
CPU time 5.12 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 217592 kb
Host smart-e1c913d7-6fd9-4632-a45a-a0d6310e1e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941201002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2941201002
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.435623140
Short name T23
Test name
Test status
Simulation time 54913406 ps
CPU time 1.5 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:19 PM PDT 24
Peak memory 214404 kb
Host smart-b17fa621-d1d4-44a3-8faa-74cd3dd8c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435623140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.435623140
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.877089110
Short name T151
Test name
Test status
Simulation time 61872976 ps
CPU time 4.11 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 215260 kb
Host smart-c215b5d3-ff7e-4831-a407-b7c291622a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877089110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.877089110
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4007200826
Short name T24
Test name
Test status
Simulation time 134847931 ps
CPU time 4.74 seconds
Started Jul 27 05:40:29 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 209040 kb
Host smart-2af53bda-f97b-4608-92f8-7aeaf6d2f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007200826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4007200826
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2971696855
Short name T31
Test name
Test status
Simulation time 104930908 ps
CPU time 4.74 seconds
Started Jul 27 05:41:20 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 215472 kb
Host smart-83230f05-9f37-496e-a219-ff0f3b933cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971696855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2971696855
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.273361481
Short name T62
Test name
Test status
Simulation time 3236692121 ps
CPU time 32.06 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 214944 kb
Host smart-cff50222-f530-4327-aed1-7fed5ddf4892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273361481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.273361481
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1908381153
Short name T7
Test name
Test status
Simulation time 6177264428 ps
CPU time 72.16 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:43:25 PM PDT 24
Peak memory 216624 kb
Host smart-817a94eb-c3a0-47f1-a948-7eb5942cc0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908381153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1908381153
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.942603584
Short name T79
Test name
Test status
Simulation time 56325528 ps
CPU time 4.28 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 214136 kb
Host smart-31a4cf69-10cf-468d-8a26-dca00559c1a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942603584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.942603584
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2364800712
Short name T123
Test name
Test status
Simulation time 637099172 ps
CPU time 2.76 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 214156 kb
Host smart-915dae4a-9d10-4d29-8eb7-2d9f28e47a20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364800712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2364800712
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2473765848
Short name T22
Test name
Test status
Simulation time 174018910 ps
CPU time 6.68 seconds
Started Jul 27 05:42:16 PM PDT 24
Finished Jul 27 05:42:23 PM PDT 24
Peak memory 210416 kb
Host smart-952f0d41-9018-43e3-a184-aa65d84d7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473765848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2473765848
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.185700534
Short name T758
Test name
Test status
Simulation time 329233833 ps
CPU time 4.58 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 214212 kb
Host smart-26497741-6a00-40b3-928b-4a89c6a597ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185700534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.185700534
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2414961267
Short name T155
Test name
Test status
Simulation time 102674539 ps
CPU time 4.23 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 213976 kb
Host smart-bbedeff0-4092-4ea8-924c-7f2dd658f54a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414961267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2414961267
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.532401188
Short name T424
Test name
Test status
Simulation time 19997237 ps
CPU time 0.98 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:39 PM PDT 24
Peak memory 205908 kb
Host smart-246c4b68-7a26-4f46-91e7-7efaf756fcec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532401188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.532401188
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1833453724
Short name T241
Test name
Test status
Simulation time 2001768883 ps
CPU time 101.4 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:42:28 PM PDT 24
Peak memory 215808 kb
Host smart-56b6d5b4-6867-4656-9453-255b7ac443d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833453724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1833453724
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1290629718
Short name T53
Test name
Test status
Simulation time 17388059875 ps
CPU time 66.51 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:42:02 PM PDT 24
Peak memory 215540 kb
Host smart-c48b6000-d451-4cf3-8ac1-d19089007ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290629718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1290629718
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1544157399
Short name T68
Test name
Test status
Simulation time 102833436 ps
CPU time 5.48 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:15 PM PDT 24
Peak memory 210236 kb
Host smart-d975fcfe-6b6a-4735-beb4-cb1a5267ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544157399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1544157399
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1510225928
Short name T324
Test name
Test status
Simulation time 764043403 ps
CPU time 4.66 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 220776 kb
Host smart-aac0290d-b4a8-457b-b455-2ec19a774f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510225928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1510225928
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2326086779
Short name T353
Test name
Test status
Simulation time 206728287 ps
CPU time 10.33 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 214848 kb
Host smart-429a997a-2333-4aba-97b9-00c0068972f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326086779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2326086779
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.218777311
Short name T250
Test name
Test status
Simulation time 2619112427 ps
CPU time 29.78 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 214944 kb
Host smart-36d96d3b-aa96-410b-b6e0-e90b289656c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218777311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.218777311
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2667233516
Short name T158
Test name
Test status
Simulation time 275190530 ps
CPU time 10.7 seconds
Started Jul 27 06:34:53 PM PDT 24
Finished Jul 27 06:35:04 PM PDT 24
Peak memory 213948 kb
Host smart-0f34c259-bacc-446c-a733-230a12a9a025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667233516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2667233516
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3539419815
Short name T82
Test name
Test status
Simulation time 596153358 ps
CPU time 3.59 seconds
Started Jul 27 05:40:35 PM PDT 24
Finished Jul 27 05:40:39 PM PDT 24
Peak memory 221244 kb
Host smart-7296b661-6854-4868-b60a-6b1144ab43a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539419815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3539419815
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3364526439
Short name T111
Test name
Test status
Simulation time 441700432 ps
CPU time 19.57 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 222408 kb
Host smart-0bf00d70-16fc-4340-b1b5-46472b88f617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364526439 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3364526439
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3797828176
Short name T106
Test name
Test status
Simulation time 47061703 ps
CPU time 2.84 seconds
Started Jul 27 05:42:08 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 222464 kb
Host smart-b4d553e5-8051-4354-8ac7-efe5add888c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797828176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3797828176
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1744957124
Short name T234
Test name
Test status
Simulation time 507332684 ps
CPU time 3.32 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 214088 kb
Host smart-21fd3a46-45ea-4e58-8440-cc0af9e8efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744957124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1744957124
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3161124970
Short name T223
Test name
Test status
Simulation time 90864100 ps
CPU time 4.47 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:07 PM PDT 24
Peak memory 221672 kb
Host smart-64904e4a-014b-4016-92e6-ac2bd8451875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161124970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3161124970
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2096048000
Short name T333
Test name
Test status
Simulation time 148238880 ps
CPU time 7.65 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:56 PM PDT 24
Peak memory 215228 kb
Host smart-2d1702c4-bd39-4554-bea1-6b0d2d8c8e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096048000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2096048000
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2366689014
Short name T326
Test name
Test status
Simulation time 216016121 ps
CPU time 4.16 seconds
Started Jul 27 05:41:06 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 215584 kb
Host smart-6614776f-2ada-4a5c-bd54-defb2e04f48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366689014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2366689014
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.669040848
Short name T346
Test name
Test status
Simulation time 2699779088 ps
CPU time 131.96 seconds
Started Jul 27 05:42:30 PM PDT 24
Finished Jul 27 05:44:42 PM PDT 24
Peak memory 215372 kb
Host smart-ee7c8356-d52e-4bf1-9361-4d5e7c35c43b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669040848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.669040848
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3246351371
Short name T166
Test name
Test status
Simulation time 129756475 ps
CPU time 5.7 seconds
Started Jul 27 06:34:51 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 213836 kb
Host smart-02c30a39-017f-4f9d-8a6f-85dd7e9d3d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246351371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3246351371
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1432968748
Short name T157
Test name
Test status
Simulation time 1260546553 ps
CPU time 5.73 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:44 PM PDT 24
Peak memory 213900 kb
Host smart-44a24eea-5ca9-4b26-8b2a-e0e20243f5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432968748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1432968748
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.491521309
Short name T314
Test name
Test status
Simulation time 1080731210 ps
CPU time 2.94 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:02 PM PDT 24
Peak memory 208484 kb
Host smart-0e6ab768-4432-4c20-b347-54623b091f99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491521309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.491521309
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3933808981
Short name T218
Test name
Test status
Simulation time 6801240509 ps
CPU time 52.27 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 221380 kb
Host smart-e7e7838b-b735-4fc6-81e8-4a2e53d44b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933808981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3933808981
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.485533301
Short name T54
Test name
Test status
Simulation time 1532262151 ps
CPU time 30.03 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:31 PM PDT 24
Peak memory 215308 kb
Host smart-e924b7f5-0b72-444f-88fe-c30aae15344d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485533301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.485533301
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2754018361
Short name T371
Test name
Test status
Simulation time 370458554 ps
CPU time 6.33 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:16 PM PDT 24
Peak memory 210716 kb
Host smart-05393b97-0067-4e84-84a2-bb03f4536f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754018361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2754018361
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.684570711
Short name T125
Test name
Test status
Simulation time 935896066 ps
CPU time 16.81 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 222172 kb
Host smart-5e01f7ad-22ad-4b5c-bdc7-847409b818c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684570711 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.684570711
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3553387062
Short name T661
Test name
Test status
Simulation time 166243880 ps
CPU time 6.58 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 213988 kb
Host smart-27b6f01c-bd83-4f4a-8971-de14a09002f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553387062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3553387062
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.753712787
Short name T282
Test name
Test status
Simulation time 577996842 ps
CPU time 9.43 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:38 PM PDT 24
Peak memory 214088 kb
Host smart-b896d413-30aa-46c8-91d7-bee301aa7930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753712787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.753712787
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3035670724
Short name T171
Test name
Test status
Simulation time 113861249 ps
CPU time 3.33 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 205748 kb
Host smart-4d77ac54-1748-4ce2-a3ce-64e193ee3e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035670724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3035670724
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2919237198
Short name T109
Test name
Test status
Simulation time 111205827 ps
CPU time 2.18 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:53 PM PDT 24
Peak memory 216904 kb
Host smart-8c40313f-a1a0-42e2-86e5-a6e4a3d41d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919237198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2919237198
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1166405133
Short name T110
Test name
Test status
Simulation time 139705988 ps
CPU time 2.66 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 222424 kb
Host smart-656579c3-1bc5-45e6-a1db-f3bb8a025f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166405133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1166405133
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3728671759
Short name T878
Test name
Test status
Simulation time 407879742 ps
CPU time 8.54 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 214032 kb
Host smart-6ae2aeb4-4fa1-40a9-bf77-5aea70f9d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728671759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3728671759
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_random.276624844
Short name T203
Test name
Test status
Simulation time 758958587 ps
CPU time 6.97 seconds
Started Jul 27 05:40:44 PM PDT 24
Finished Jul 27 05:40:51 PM PDT 24
Peak memory 207648 kb
Host smart-44248d25-23c6-4c69-9609-2f6f22eb56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276624844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.276624844
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2064889462
Short name T316
Test name
Test status
Simulation time 27028575 ps
CPU time 2.18 seconds
Started Jul 27 05:40:43 PM PDT 24
Finished Jul 27 05:40:46 PM PDT 24
Peak memory 209848 kb
Host smart-e1d348cb-8bfb-4368-89a3-dc902db9c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064889462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2064889462
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1884546809
Short name T320
Test name
Test status
Simulation time 8107097718 ps
CPU time 21.64 seconds
Started Jul 27 05:40:47 PM PDT 24
Finished Jul 27 05:41:09 PM PDT 24
Peak memory 215508 kb
Host smart-de716439-fa8e-4206-999a-a7df416bb0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884546809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1884546809
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2097019667
Short name T44
Test name
Test status
Simulation time 96930595 ps
CPU time 2.08 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:53 PM PDT 24
Peak memory 208428 kb
Host smart-c5370ba3-c2ac-4f98-8d70-45cacdbbc1b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097019667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2097019667
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3553897354
Short name T330
Test name
Test status
Simulation time 110668872 ps
CPU time 3.33 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 214152 kb
Host smart-170c2648-9218-4677-9663-f0f8ba63a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553897354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3553897354
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1442452860
Short name T298
Test name
Test status
Simulation time 241071070 ps
CPU time 3.01 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 207508 kb
Host smart-3291532a-d338-4de9-84ac-bb6c4a7e35a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442452860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1442452860
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3466761422
Short name T243
Test name
Test status
Simulation time 167519682 ps
CPU time 3.25 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 209880 kb
Host smart-d88c0967-f820-47ca-9d51-008ad87292e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466761422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3466761422
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1745313327
Short name T239
Test name
Test status
Simulation time 853602194 ps
CPU time 3.05 seconds
Started Jul 27 05:42:26 PM PDT 24
Finished Jul 27 05:42:29 PM PDT 24
Peak memory 214124 kb
Host smart-8bee9f99-d70e-4e26-9950-8807f21effd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745313327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1745313327
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3037909990
Short name T211
Test name
Test status
Simulation time 6584019955 ps
CPU time 128.72 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:44:37 PM PDT 24
Peak memory 222368 kb
Host smart-80cb8684-46fa-4128-be6c-4e44d376b8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037909990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3037909990
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.908130872
Short name T168
Test name
Test status
Simulation time 108187079 ps
CPU time 3.2 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 213912 kb
Host smart-35806ee4-a643-4883-a783-84a056ee8f85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908130872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.908130872
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2176666260
Short name T167
Test name
Test status
Simulation time 175651195 ps
CPU time 5.06 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 213816 kb
Host smart-f1bf4aba-1147-4a77-9ccc-3a5d4edeb391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176666260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2176666260
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3421992134
Short name T159
Test name
Test status
Simulation time 394143986 ps
CPU time 7.13 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:55 PM PDT 24
Peak memory 213924 kb
Host smart-7e715f25-2448-44c1-847b-1597f61e2d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421992134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3421992134
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2903517379
Short name T80
Test name
Test status
Simulation time 327283885 ps
CPU time 4.21 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 209324 kb
Host smart-20b84b9f-15ba-49b2-807a-eaab4b654f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903517379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2903517379
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.506270701
Short name T107
Test name
Test status
Simulation time 38719565 ps
CPU time 2.38 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 218248 kb
Host smart-fdabc067-b502-4826-8bde-b3f36939597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506270701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.506270701
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2137884252
Short name T222
Test name
Test status
Simulation time 48322061 ps
CPU time 3.08 seconds
Started Jul 27 05:40:01 PM PDT 24
Finished Jul 27 05:40:05 PM PDT 24
Peak memory 221668 kb
Host smart-06a36dd7-bc5d-4dd3-9bce-515149ba43e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137884252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2137884252
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2805437912
Short name T35
Test name
Test status
Simulation time 1518193846 ps
CPU time 3.98 seconds
Started Jul 27 05:40:18 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 210364 kb
Host smart-13f0fdb5-db46-4860-bbc1-bed8ec106062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805437912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2805437912
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_sideload.742081059
Short name T623
Test name
Test status
Simulation time 536549332 ps
CPU time 4.34 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 208236 kb
Host smart-e3da3330-6833-4efb-a32e-392d35a2f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742081059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.742081059
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1555359046
Short name T175
Test name
Test status
Simulation time 626737638 ps
CPU time 21.74 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 222076 kb
Host smart-8a7dfbca-842c-44b3-a58b-880f1693ef56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555359046 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1555359046
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1288200953
Short name T248
Test name
Test status
Simulation time 86951986 ps
CPU time 3.75 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:56 PM PDT 24
Peak memory 208732 kb
Host smart-b9895b73-9101-4885-aedb-689ea840cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288200953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1288200953
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.436189172
Short name T34
Test name
Test status
Simulation time 58560752 ps
CPU time 2.32 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 209948 kb
Host smart-c3044728-cd1e-4409-9208-21dc70e39d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436189172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.436189172
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2385971240
Short name T219
Test name
Test status
Simulation time 198884835 ps
CPU time 2.71 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 216472 kb
Host smart-50234c28-4dc2-4782-95f2-0a0711e57c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385971240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2385971240
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2422900948
Short name T394
Test name
Test status
Simulation time 94400274 ps
CPU time 3.41 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 214156 kb
Host smart-6b965cdc-f3e2-4e02-965c-eb3d3c91d829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422900948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2422900948
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3877535138
Short name T238
Test name
Test status
Simulation time 128204346 ps
CPU time 5.23 seconds
Started Jul 27 05:40:54 PM PDT 24
Finished Jul 27 05:40:59 PM PDT 24
Peak memory 214076 kb
Host smart-0a783722-472f-4095-be67-a7631da30562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877535138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3877535138
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3780566288
Short name T50
Test name
Test status
Simulation time 26296607 ps
CPU time 1.81 seconds
Started Jul 27 05:41:12 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 214236 kb
Host smart-de83e5c0-feb8-4db0-b01d-f8b421c4a193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780566288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3780566288
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.323515775
Short name T278
Test name
Test status
Simulation time 1135805606 ps
CPU time 10.25 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:11 PM PDT 24
Peak memory 214084 kb
Host smart-effb3617-24a1-41ef-9e0d-1ec816aaa02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323515775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.323515775
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1036588551
Short name T336
Test name
Test status
Simulation time 271045969 ps
CPU time 8.13 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:19 PM PDT 24
Peak memory 214096 kb
Host smart-74e33856-bc7f-4b25-84e9-867af57e7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036588551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1036588551
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.446006863
Short name T209
Test name
Test status
Simulation time 559659287 ps
CPU time 26.91 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 216832 kb
Host smart-7696d166-2884-45fd-9a4d-8d5a5481d592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446006863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.446006863
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1653309298
Short name T334
Test name
Test status
Simulation time 138781550 ps
CPU time 2.43 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 208256 kb
Host smart-6ae5e5d3-dea8-420d-a09e-4097947b3fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653309298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1653309298
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2628397423
Short name T618
Test name
Test status
Simulation time 131084204 ps
CPU time 4.21 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 214108 kb
Host smart-79820abd-bb65-4961-bf7e-6cd5bc3093fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628397423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2628397423
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2037222839
Short name T213
Test name
Test status
Simulation time 1179788671 ps
CPU time 8.92 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 220680 kb
Host smart-409c7b52-6a2d-405c-b16d-3d883d64690d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037222839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2037222839
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3230760990
Short name T224
Test name
Test status
Simulation time 1169375711 ps
CPU time 18.05 seconds
Started Jul 27 05:42:43 PM PDT 24
Finished Jul 27 05:43:02 PM PDT 24
Peak memory 220888 kb
Host smart-a4dff7c4-c5bf-44ef-b502-dde26a6d00ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230760990 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3230760990
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4291861172
Short name T81
Test name
Test status
Simulation time 1583345443 ps
CPU time 21.27 seconds
Started Jul 27 05:40:30 PM PDT 24
Finished Jul 27 05:40:52 PM PDT 24
Peak memory 214096 kb
Host smart-7958a222-93d0-480e-8e60-ad3a0bba630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291861172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4291861172
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1834017400
Short name T221
Test name
Test status
Simulation time 443295644 ps
CPU time 25.86 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:58 PM PDT 24
Peak memory 220824 kb
Host smart-356a4eb8-0a79-4929-8516-125f9642bfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834017400 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1834017400
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1596841031
Short name T108
Test name
Test status
Simulation time 197516310 ps
CPU time 6.31 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:31 PM PDT 24
Peak memory 218108 kb
Host smart-234117b8-f07c-4da5-bd76-c81a459d83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596841031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1596841031
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4037490144
Short name T939
Test name
Test status
Simulation time 765171560 ps
CPU time 11.59 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 205752 kb
Host smart-9f0ff4ff-2676-4cea-8468-5da1e9f1d472
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037490144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
037490144
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.891755877
Short name T923
Test name
Test status
Simulation time 324863691 ps
CPU time 12.16 seconds
Started Jul 27 06:34:15 PM PDT 24
Finished Jul 27 06:34:27 PM PDT 24
Peak memory 205776 kb
Host smart-70639167-a2a1-4762-aab8-3f2e463ce6da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891755877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.891755877
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1298167732
Short name T176
Test name
Test status
Simulation time 141096863 ps
CPU time 1.16 seconds
Started Jul 27 06:34:14 PM PDT 24
Finished Jul 27 06:34:15 PM PDT 24
Peak memory 205704 kb
Host smart-a76b390e-099f-4214-bf90-43ece903f9a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298167732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
298167732
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2988199742
Short name T915
Test name
Test status
Simulation time 80282910 ps
CPU time 1.49 seconds
Started Jul 27 06:34:34 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 214012 kb
Host smart-71744365-e96a-414a-81e9-4eb529222b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988199742 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2988199742
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3295939558
Short name T1015
Test name
Test status
Simulation time 13606651 ps
CPU time 1 seconds
Started Jul 27 06:34:15 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 205684 kb
Host smart-38b89337-ddf8-4f84-9569-d421e7b2a56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295939558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3295939558
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1149820899
Short name T1065
Test name
Test status
Simulation time 14823199 ps
CPU time 0.7 seconds
Started Jul 27 06:34:17 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 205528 kb
Host smart-45e85892-fedc-4093-ad10-ca2e12efd531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149820899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1149820899
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2950438413
Short name T1016
Test name
Test status
Simulation time 458245581 ps
CPU time 3.76 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 205748 kb
Host smart-d40ddd44-6962-4fe6-83f8-e6cfbf863d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950438413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2950438413
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2163213438
Short name T116
Test name
Test status
Simulation time 51106245 ps
CPU time 1.68 seconds
Started Jul 27 06:34:14 PM PDT 24
Finished Jul 27 06:34:15 PM PDT 24
Peak memory 214112 kb
Host smart-9aefd961-9f44-4918-8c87-49bc30bcd18d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163213438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2163213438
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3371870475
Short name T1041
Test name
Test status
Simulation time 436716691 ps
CPU time 11.07 seconds
Started Jul 27 06:34:13 PM PDT 24
Finished Jul 27 06:34:24 PM PDT 24
Peak memory 220300 kb
Host smart-6ec58284-1eb4-4624-9811-7d91407c328b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371870475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3371870475
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1262693948
Short name T1033
Test name
Test status
Simulation time 26142757 ps
CPU time 2.12 seconds
Started Jul 27 06:34:17 PM PDT 24
Finished Jul 27 06:34:19 PM PDT 24
Peak memory 214020 kb
Host smart-5dfacc6e-a2e6-405e-8d6f-d239db20c2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262693948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1262693948
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.979400166
Short name T1072
Test name
Test status
Simulation time 274838088 ps
CPU time 3.57 seconds
Started Jul 27 06:34:12 PM PDT 24
Finished Jul 27 06:34:16 PM PDT 24
Peak memory 213844 kb
Host smart-8d69d3c8-7647-451e-b8c7-16bc95ed0a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979400166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
979400166
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1980901239
Short name T1066
Test name
Test status
Simulation time 196031584 ps
CPU time 7.99 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:39 PM PDT 24
Peak memory 205716 kb
Host smart-c58c414b-f4db-4133-b7a5-4494f21f78c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980901239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
980901239
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1223016341
Short name T152
Test name
Test status
Simulation time 2216505871 ps
CPU time 16.17 seconds
Started Jul 27 06:34:32 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205868 kb
Host smart-1c05b77a-dab9-4ce9-b7ec-f4ade96cf9bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223016341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
223016341
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2007547498
Short name T957
Test name
Test status
Simulation time 13352001 ps
CPU time 1.01 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:32 PM PDT 24
Peak memory 205640 kb
Host smart-dafae393-001b-4f47-b7e8-4d690800d4b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007547498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
007547498
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3128196123
Short name T924
Test name
Test status
Simulation time 114351886 ps
CPU time 1.88 seconds
Started Jul 27 06:34:34 PM PDT 24
Finished Jul 27 06:34:36 PM PDT 24
Peak memory 214004 kb
Host smart-0d97b435-beaa-4f4f-a769-47b3f5580af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128196123 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3128196123
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.173848699
Short name T911
Test name
Test status
Simulation time 16047517 ps
CPU time 0.97 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:30 PM PDT 24
Peak memory 205668 kb
Host smart-377e6c5e-f537-4047-9f3d-e8928786f292
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173848699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.173848699
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2156797610
Short name T1026
Test name
Test status
Simulation time 11802320 ps
CPU time 0.72 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:31 PM PDT 24
Peak memory 205516 kb
Host smart-07d12f63-d3ea-4aea-a641-f1e36828df56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156797610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2156797610
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3933994081
Short name T982
Test name
Test status
Simulation time 46057042 ps
CPU time 1.93 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:31 PM PDT 24
Peak memory 205788 kb
Host smart-1412d8d2-08c9-4c99-9c75-12fa3625f2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933994081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3933994081
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2119967985
Short name T1059
Test name
Test status
Simulation time 104848336 ps
CPU time 1.79 seconds
Started Jul 27 06:34:34 PM PDT 24
Finished Jul 27 06:34:36 PM PDT 24
Peak memory 214108 kb
Host smart-919ab33d-c979-4516-8924-c6e24498eff0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119967985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2119967985
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2795161896
Short name T1046
Test name
Test status
Simulation time 261016504 ps
CPU time 6.9 seconds
Started Jul 27 06:34:33 PM PDT 24
Finished Jul 27 06:34:40 PM PDT 24
Peak memory 214212 kb
Host smart-64a571a0-0978-4b0a-902a-17ea2e6fb0d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795161896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2795161896
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1850315511
Short name T918
Test name
Test status
Simulation time 329593979 ps
CPU time 3.27 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 216020 kb
Host smart-c9d0eee0-32ed-4098-915d-5c3401ac1090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850315511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1850315511
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1112352727
Short name T370
Test name
Test status
Simulation time 413693180 ps
CPU time 6.33 seconds
Started Jul 27 06:34:28 PM PDT 24
Finished Jul 27 06:34:34 PM PDT 24
Peak memory 213988 kb
Host smart-8d4eafb2-9c98-40b9-b31a-f7b405adbbad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112352727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1112352727
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2793484647
Short name T928
Test name
Test status
Simulation time 352648010 ps
CPU time 2.08 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 214036 kb
Host smart-7c82cb09-a44f-40e8-a79a-d7f545964e49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793484647 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2793484647
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3495125716
Short name T966
Test name
Test status
Simulation time 32166542 ps
CPU time 1.63 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 205748 kb
Host smart-02e50f53-971e-489b-b4ac-80d1fc5d0f73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495125716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3495125716
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2767036269
Short name T1027
Test name
Test status
Simulation time 14770583 ps
CPU time 0.84 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205652 kb
Host smart-284eb26a-8096-449f-926f-3f5e5b0c8f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767036269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2767036269
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2778825422
Short name T144
Test name
Test status
Simulation time 40247916 ps
CPU time 2.11 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 205732 kb
Host smart-b26a8863-ae92-4615-b48a-c2fe51d6f19a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778825422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2778825422
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3142677907
Short name T1019
Test name
Test status
Simulation time 160972469 ps
CPU time 2.06 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 214168 kb
Host smart-a7b1241a-4118-4c0b-9818-04df43bd7e9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142677907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3142677907
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.27936665
Short name T960
Test name
Test status
Simulation time 1444549997 ps
CPU time 8.45 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 214192 kb
Host smart-6c9c50e8-d269-44dd-adbc-0970f4779682
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27936665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_shadow_reg_errors_with_csr_rw.27936665
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1548284402
Short name T977
Test name
Test status
Simulation time 69233317 ps
CPU time 1.92 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 213872 kb
Host smart-ef5db1a3-e7f3-4083-861c-83adf397c732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548284402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1548284402
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.147310991
Short name T164
Test name
Test status
Simulation time 159800192 ps
CPU time 2.39 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 214032 kb
Host smart-cdea1d91-03bf-4c1d-85b7-d2e3b63d13d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147310991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.147310991
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3859957250
Short name T379
Test name
Test status
Simulation time 86207340 ps
CPU time 1.5 seconds
Started Jul 27 06:34:45 PM PDT 24
Finished Jul 27 06:34:47 PM PDT 24
Peak memory 217204 kb
Host smart-d5b8992c-1161-4799-9be8-85bd1bafea22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859957250 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3859957250
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.454716886
Short name T951
Test name
Test status
Simulation time 60902711 ps
CPU time 0.97 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 205472 kb
Host smart-2ab9d1e3-249f-4bc2-a7e1-bdf12832e6aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454716886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.454716886
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.36002864
Short name T922
Test name
Test status
Simulation time 134601365 ps
CPU time 0.72 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 205400 kb
Host smart-83079b97-97d9-4c8f-ae6d-21e532475ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36002864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.36002864
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3959550069
Short name T1012
Test name
Test status
Simulation time 132680703 ps
CPU time 2.21 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 205688 kb
Host smart-1a2f4d40-43a9-4aca-8fc8-09a4726ead43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959550069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3959550069
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1959601865
Short name T963
Test name
Test status
Simulation time 71687372 ps
CPU time 1.52 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 214176 kb
Host smart-6d7e7312-f041-4970-8fca-4b5c30e6e568
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959601865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1959601865
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.460661619
Short name T1017
Test name
Test status
Simulation time 218776155 ps
CPU time 6.28 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:55 PM PDT 24
Peak memory 214192 kb
Host smart-bac941c1-abca-4ade-bec2-516c046d24a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460661619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.460661619
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1282580341
Short name T910
Test name
Test status
Simulation time 100696292 ps
CPU time 1.86 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 214008 kb
Host smart-cfdf9a2f-c9dc-45be-bd63-8a227c48b5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282580341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1282580341
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2527810933
Short name T933
Test name
Test status
Simulation time 181057016 ps
CPU time 1.63 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 213988 kb
Host smart-d6634aba-2149-40fa-8f53-e62ea5d81fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527810933 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2527810933
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.787783470
Short name T1063
Test name
Test status
Simulation time 49966358 ps
CPU time 1.36 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 205740 kb
Host smart-76602bf3-6148-40e6-998b-b9428f44a5fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787783470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.787783470
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3426918251
Short name T919
Test name
Test status
Simulation time 41303924 ps
CPU time 0.77 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:47 PM PDT 24
Peak memory 205464 kb
Host smart-dd0bdd11-5729-4689-94e8-2d4643222227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426918251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3426918251
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.783582757
Short name T1054
Test name
Test status
Simulation time 39535116 ps
CPU time 1.4 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205656 kb
Host smart-1df3dc10-6f46-4bf3-9e00-744fbb863354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783582757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.783582757
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3493486361
Short name T1036
Test name
Test status
Simulation time 363539136 ps
CPU time 2.51 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 214184 kb
Host smart-d61eac17-27c5-479e-939a-d4e97d838542
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493486361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3493486361
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1144548508
Short name T1032
Test name
Test status
Simulation time 303007414 ps
CPU time 3.76 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 214116 kb
Host smart-7714e91e-d14e-4e55-ba84-b7ee9265f75f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144548508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1144548508
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2110324678
Short name T1043
Test name
Test status
Simulation time 23557066 ps
CPU time 1.5 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 213960 kb
Host smart-7b20d2cd-11d0-43ca-afe4-e7d69c667de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110324678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2110324678
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2845323275
Short name T378
Test name
Test status
Simulation time 95464451 ps
CPU time 5.16 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 213992 kb
Host smart-e0b9834e-ee5c-4d7c-ac05-fc6ff02cf72f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845323275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2845323275
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2413220595
Short name T956
Test name
Test status
Simulation time 91770641 ps
CPU time 1.21 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205784 kb
Host smart-69ea575e-f5c9-40d3-bfaa-d045ba840907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413220595 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2413220595
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2518939820
Short name T974
Test name
Test status
Simulation time 47781424 ps
CPU time 1.19 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 205704 kb
Host smart-81801290-59be-4b63-adb0-a3e9cdc32b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518939820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2518939820
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3324975195
Short name T1068
Test name
Test status
Simulation time 10910386 ps
CPU time 0.7 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 205444 kb
Host smart-820861a5-cb03-494f-8eaa-906c07c3ab4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324975195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3324975195
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3071337348
Short name T1000
Test name
Test status
Simulation time 447531081 ps
CPU time 4.18 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 205836 kb
Host smart-baabe5df-2a35-4655-a554-f699e64093fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071337348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3071337348
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3435041358
Short name T946
Test name
Test status
Simulation time 319326964 ps
CPU time 2.96 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 214104 kb
Host smart-e7606830-a12f-4cae-b890-1e3b9e98733b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435041358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3435041358
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2494739669
Short name T1025
Test name
Test status
Simulation time 288434482 ps
CPU time 3.78 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:56 PM PDT 24
Peak memory 214172 kb
Host smart-1cc1a8c3-6fe6-4d81-a40a-016a62eadb87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494739669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2494739669
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.375310155
Short name T984
Test name
Test status
Simulation time 102532120 ps
CPU time 1.9 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 216076 kb
Host smart-fe12375f-fc9b-4ccb-9877-c36424ae537b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375310155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.375310155
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.291042797
Short name T154
Test name
Test status
Simulation time 155897672 ps
CPU time 5.59 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:56 PM PDT 24
Peak memory 213940 kb
Host smart-34c6bef9-928f-498f-acf9-a2356203c425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291042797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.291042797
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3214890575
Short name T927
Test name
Test status
Simulation time 489479599 ps
CPU time 2.11 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 213996 kb
Host smart-3b2893a2-0c69-4902-8053-b3f7dda3b780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214890575 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3214890575
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.826995976
Short name T975
Test name
Test status
Simulation time 15355731 ps
CPU time 1.06 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 205720 kb
Host smart-ecfcdd4b-0b5e-4837-b56a-9325974c8f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826995976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.826995976
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3320602111
Short name T1002
Test name
Test status
Simulation time 12311468 ps
CPU time 0.74 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 205528 kb
Host smart-adfd8b19-8b70-4d56-bf27-8c1cc5b3b69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320602111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3320602111
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2632631550
Short name T987
Test name
Test status
Simulation time 23296979 ps
CPU time 1.67 seconds
Started Jul 27 06:34:51 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 205712 kb
Host smart-355aeed5-c762-48a3-be7d-8edb79d0348c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632631550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2632631550
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2396681537
Short name T1042
Test name
Test status
Simulation time 322792269 ps
CPU time 1.95 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 214208 kb
Host smart-4fe2a930-f0a9-43e8-957d-390b3562c71c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396681537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2396681537
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1609719607
Short name T1049
Test name
Test status
Simulation time 68375287 ps
CPU time 3.42 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 214216 kb
Host smart-60d878aa-9261-4a33-9e8c-613cdb6aaad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609719607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1609719607
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.549367366
Short name T962
Test name
Test status
Simulation time 848193479 ps
CPU time 1.48 seconds
Started Jul 27 06:34:51 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 213996 kb
Host smart-5e93349d-b717-4b35-ae2d-f6d09eb4ac6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549367366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.549367366
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1948282650
Short name T1048
Test name
Test status
Simulation time 97048230 ps
CPU time 1.09 seconds
Started Jul 27 06:34:48 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 205728 kb
Host smart-c4aa6ef7-4034-4ecb-aceb-682dae4576be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948282650 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1948282650
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2027572276
Short name T936
Test name
Test status
Simulation time 22530632 ps
CPU time 1 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205656 kb
Host smart-2eb15af9-b036-43b2-bfd3-2786c271f005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027572276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2027572276
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3677963929
Short name T940
Test name
Test status
Simulation time 36002265 ps
CPU time 0.81 seconds
Started Jul 27 06:34:52 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 205488 kb
Host smart-a8fc5549-c410-4529-a04a-2f780b5e33ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677963929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3677963929
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3033106084
Short name T146
Test name
Test status
Simulation time 41582150 ps
CPU time 1.62 seconds
Started Jul 27 06:34:49 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 205644 kb
Host smart-f904983b-3f7a-443a-8253-68b3dbaff7e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033106084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3033106084
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1306439297
Short name T119
Test name
Test status
Simulation time 80748348 ps
CPU time 1.91 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 214264 kb
Host smart-021e473f-518a-430a-95b7-cbc9b39d21b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306439297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1306439297
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2916686321
Short name T1009
Test name
Test status
Simulation time 1311889788 ps
CPU time 6.55 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 214252 kb
Host smart-0c61cd71-73e0-468d-b41a-724b36f9a058
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916686321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2916686321
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3345599962
Short name T1070
Test name
Test status
Simulation time 132533863 ps
CPU time 4.73 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 213880 kb
Host smart-df1a6639-21b6-4ebc-91e8-e04fda4be99d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345599962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3345599962
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3491152048
Short name T1034
Test name
Test status
Simulation time 193781048 ps
CPU time 2.17 seconds
Started Jul 27 06:35:01 PM PDT 24
Finished Jul 27 06:35:03 PM PDT 24
Peak memory 213920 kb
Host smart-09b183b5-a7f8-4060-9da5-2589fa13bb60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491152048 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3491152048
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3440037092
Short name T997
Test name
Test status
Simulation time 22581816 ps
CPU time 1.02 seconds
Started Jul 27 06:34:53 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 205828 kb
Host smart-e9d32460-09e0-4191-9a9e-879a0a383476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440037092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3440037092
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.181913418
Short name T912
Test name
Test status
Simulation time 49382614 ps
CPU time 0.74 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:34:58 PM PDT 24
Peak memory 205428 kb
Host smart-f0cd6cbb-91b4-451f-be4e-28223da9a174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181913418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.181913418
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.216834159
Short name T955
Test name
Test status
Simulation time 83023188 ps
CPU time 1.32 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 205680 kb
Host smart-3af84bf3-1d5a-4375-a145-4ca53fcc84ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216834159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.216834159
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3627013586
Short name T989
Test name
Test status
Simulation time 91958477 ps
CPU time 3.15 seconds
Started Jul 27 06:34:54 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 214180 kb
Host smart-772c410b-a3c7-4568-919c-1fd1f545fcd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627013586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3627013586
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3944600305
Short name T1018
Test name
Test status
Simulation time 340620111 ps
CPU time 4.69 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:35:02 PM PDT 24
Peak memory 214128 kb
Host smart-4b6c6e6b-233c-49db-99cc-6bc83ddaf6b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944600305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3944600305
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.252612556
Short name T979
Test name
Test status
Simulation time 203602164 ps
CPU time 1.82 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 215992 kb
Host smart-5210e910-8727-407e-a00f-d2d01db103b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252612556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.252612556
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2186145458
Short name T1062
Test name
Test status
Simulation time 1266436437 ps
CPU time 3.57 seconds
Started Jul 27 06:35:02 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 213920 kb
Host smart-19224d1a-6800-4ae1-96c0-43cf6849a5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186145458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2186145458
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3231771967
Short name T1058
Test name
Test status
Simulation time 102949788 ps
CPU time 1.43 seconds
Started Jul 27 06:34:53 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 205748 kb
Host smart-060cf009-a6cc-477e-a9a6-dda3ec480e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231771967 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3231771967
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1321486953
Short name T993
Test name
Test status
Simulation time 13253634 ps
CPU time 0.9 seconds
Started Jul 27 06:34:58 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 205596 kb
Host smart-5766ba57-0d3d-456f-99bd-66816a3e8767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321486953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1321486953
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3197498461
Short name T941
Test name
Test status
Simulation time 11360386 ps
CPU time 0.7 seconds
Started Jul 27 06:34:55 PM PDT 24
Finished Jul 27 06:34:56 PM PDT 24
Peak memory 205392 kb
Host smart-d96a7361-0cd8-46b2-b219-7c46ba6d6da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197498461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3197498461
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1552847852
Short name T145
Test name
Test status
Simulation time 66460691 ps
CPU time 2.27 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 205680 kb
Host smart-6e847c25-ecb3-4abd-a26a-daa0bcf4035f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552847852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1552847852
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4229402957
Short name T1074
Test name
Test status
Simulation time 1889369124 ps
CPU time 15.25 seconds
Started Jul 27 06:34:58 PM PDT 24
Finished Jul 27 06:35:13 PM PDT 24
Peak memory 214172 kb
Host smart-bb1e993b-2844-4521-bde8-b716d61b443c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229402957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4229402957
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.260545875
Short name T1053
Test name
Test status
Simulation time 138072253 ps
CPU time 2.28 seconds
Started Jul 27 06:35:02 PM PDT 24
Finished Jul 27 06:35:04 PM PDT 24
Peak memory 217080 kb
Host smart-c7803c01-4b65-414f-80cb-fde0121d045e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260545875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.260545875
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3311019596
Short name T1050
Test name
Test status
Simulation time 125406663 ps
CPU time 2.01 seconds
Started Jul 27 06:34:58 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 214008 kb
Host smart-63055590-2f58-4172-b875-e06c3c9ab5df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311019596 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3311019596
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.297628058
Short name T148
Test name
Test status
Simulation time 32304652 ps
CPU time 1.34 seconds
Started Jul 27 06:34:59 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 205780 kb
Host smart-79f8f15a-28fb-45b2-b437-31c829be39bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297628058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.297628058
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.729389529
Short name T1051
Test name
Test status
Simulation time 23718456 ps
CPU time 0.74 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 205516 kb
Host smart-e2a9ca29-2a93-40b0-b1b0-8e270f1e53b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729389529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.729389529
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.976608833
Short name T932
Test name
Test status
Simulation time 120220543 ps
CPU time 2.21 seconds
Started Jul 27 06:34:54 PM PDT 24
Finished Jul 27 06:34:56 PM PDT 24
Peak memory 205708 kb
Host smart-a79c8a51-6661-41cb-b4fe-6200aff5dacd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976608833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.976608833
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3415909915
Short name T121
Test name
Test status
Simulation time 40946561 ps
CPU time 1.35 seconds
Started Jul 27 06:34:55 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 214208 kb
Host smart-eb2ddcec-3f46-4701-a79d-efecf0758036
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415909915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3415909915
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2166310665
Short name T1073
Test name
Test status
Simulation time 207684722 ps
CPU time 7.09 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:35:03 PM PDT 24
Peak memory 214128 kb
Host smart-976a7ea0-f2ce-49f3-b428-c9f94b781622
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166310665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2166310665
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2956247947
Short name T942
Test name
Test status
Simulation time 393799603 ps
CPU time 1.63 seconds
Started Jul 27 06:34:55 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 213896 kb
Host smart-7bfe0613-2952-41ca-a04b-b3433d79ce84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956247947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2956247947
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3828300296
Short name T177
Test name
Test status
Simulation time 218612284 ps
CPU time 2.47 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 213956 kb
Host smart-d015bfee-d59e-48b3-9127-6f18a47b6514
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828300296 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3828300296
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3242300751
Short name T952
Test name
Test status
Simulation time 19578548 ps
CPU time 0.9 seconds
Started Jul 27 06:34:58 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 205508 kb
Host smart-977d71a0-48ac-4970-8e28-c530a927a90f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242300751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3242300751
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.551560926
Short name T931
Test name
Test status
Simulation time 13705566 ps
CPU time 0.85 seconds
Started Jul 27 06:34:59 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 205540 kb
Host smart-0ad3a7ea-42fa-41e8-b65e-d7f089bd74ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551560926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.551560926
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1034696555
Short name T1031
Test name
Test status
Simulation time 80726006 ps
CPU time 1.65 seconds
Started Jul 27 06:35:02 PM PDT 24
Finished Jul 27 06:35:03 PM PDT 24
Peak memory 205664 kb
Host smart-ee6ed463-4690-4eae-b7eb-0f30fde9cbec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034696555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1034696555
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2689096956
Short name T1028
Test name
Test status
Simulation time 508784905 ps
CPU time 2.49 seconds
Started Jul 27 06:34:56 PM PDT 24
Finished Jul 27 06:34:59 PM PDT 24
Peak memory 214196 kb
Host smart-7ef48ae0-5bbf-4083-9e62-d99f180dbe4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689096956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2689096956
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.304831655
Short name T113
Test name
Test status
Simulation time 735695001 ps
CPU time 4.53 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:35:01 PM PDT 24
Peak memory 214256 kb
Host smart-17111c8b-e1de-4d2f-9e5d-322700588b67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304831655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.304831655
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3237371256
Short name T945
Test name
Test status
Simulation time 552500187 ps
CPU time 3.26 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 213936 kb
Host smart-ffd8c23e-ae1e-4090-b1bc-94a14925fbe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237371256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3237371256
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1183913027
Short name T1010
Test name
Test status
Simulation time 219640233 ps
CPU time 7.15 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 205648 kb
Host smart-74299a8d-dc21-493f-bed5-c31f5c82aa42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183913027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
183913027
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2537460688
Short name T930
Test name
Test status
Simulation time 1809258203 ps
CPU time 6.04 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 205656 kb
Host smart-63ba8d61-9e47-4255-abfa-f381a37bea0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537460688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
537460688
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.852717496
Short name T914
Test name
Test status
Simulation time 37953530 ps
CPU time 0.87 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:30 PM PDT 24
Peak memory 205496 kb
Host smart-bef0e715-9873-4a9a-908e-2cfa58ceff88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852717496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.852717496
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.35891304
Short name T1069
Test name
Test status
Simulation time 108489590 ps
CPU time 2.32 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:34 PM PDT 24
Peak memory 213904 kb
Host smart-9648fb86-fe6e-477e-a3db-67067e891519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891304 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.35891304
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1908425792
Short name T1007
Test name
Test status
Simulation time 36940183 ps
CPU time 0.98 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:30 PM PDT 24
Peak memory 205492 kb
Host smart-6d695f15-8654-48b9-88ab-e45c27cffc5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908425792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1908425792
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.47691910
Short name T929
Test name
Test status
Simulation time 13840867 ps
CPU time 0.88 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:30 PM PDT 24
Peak memory 205668 kb
Host smart-f62b87f9-bf9e-4258-886c-7cead4260d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47691910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.47691910
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1908356976
Short name T1067
Test name
Test status
Simulation time 718636237 ps
CPU time 2.01 seconds
Started Jul 27 06:34:33 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 205660 kb
Host smart-48e4098e-3bb8-4c35-89b3-ee1aadfa013a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908356976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1908356976
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1033827619
Short name T122
Test name
Test status
Simulation time 154682369 ps
CPU time 1.89 seconds
Started Jul 27 06:34:35 PM PDT 24
Finished Jul 27 06:34:37 PM PDT 24
Peak memory 214068 kb
Host smart-00cc6eef-e6a2-4a95-a40e-75b2f1e22d80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033827619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1033827619
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3645295599
Short name T999
Test name
Test status
Simulation time 300388242 ps
CPU time 6.97 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 214224 kb
Host smart-ed24288a-cd1d-47db-92dc-1ae9a53b9f9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645295599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3645295599
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1790685585
Short name T1005
Test name
Test status
Simulation time 98638579 ps
CPU time 3.77 seconds
Started Jul 27 06:34:32 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 222052 kb
Host smart-bfeba434-52cc-4546-ba42-b2f6a7508835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790685585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1790685585
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1172527824
Short name T162
Test name
Test status
Simulation time 1203020292 ps
CPU time 3.33 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 214776 kb
Host smart-c1abc71e-5b4c-4c52-813a-a4ebcec78866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172527824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1172527824
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2093098656
Short name T1022
Test name
Test status
Simulation time 11316468 ps
CPU time 0.75 seconds
Started Jul 27 06:34:55 PM PDT 24
Finished Jul 27 06:34:55 PM PDT 24
Peak memory 205444 kb
Host smart-e742e7c3-8749-460b-9e7f-222c8876c554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093098656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2093098656
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3592443522
Short name T947
Test name
Test status
Simulation time 13907440 ps
CPU time 0.92 seconds
Started Jul 27 06:35:04 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 205668 kb
Host smart-57557908-5cec-42c7-bfca-d23b59483ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592443522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3592443522
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3921331694
Short name T949
Test name
Test status
Simulation time 12863964 ps
CPU time 0.88 seconds
Started Jul 27 06:34:57 PM PDT 24
Finished Jul 27 06:34:58 PM PDT 24
Peak memory 205456 kb
Host smart-b792c3f5-b159-4dc5-96ca-2767b1ec44d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921331694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3921331694
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1388733152
Short name T1056
Test name
Test status
Simulation time 58241064 ps
CPU time 0.74 seconds
Started Jul 27 06:35:03 PM PDT 24
Finished Jul 27 06:35:04 PM PDT 24
Peak memory 205516 kb
Host smart-ebcdbfe3-d1ee-4e72-926a-25703d48d27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388733152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1388733152
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.510842695
Short name T1037
Test name
Test status
Simulation time 7597192 ps
CPU time 0.8 seconds
Started Jul 27 06:35:04 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 205444 kb
Host smart-4908fae8-b7c0-4319-bb5a-822cb103a70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510842695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.510842695
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3812894251
Short name T1014
Test name
Test status
Simulation time 18206533 ps
CPU time 0.72 seconds
Started Jul 27 06:35:04 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 205532 kb
Host smart-a14e3624-f7b5-4dd6-a972-d7795d95bc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812894251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3812894251
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1876392851
Short name T971
Test name
Test status
Simulation time 10637602 ps
CPU time 0.83 seconds
Started Jul 27 06:35:05 PM PDT 24
Finished Jul 27 06:35:06 PM PDT 24
Peak memory 205504 kb
Host smart-06c22037-01ef-43ce-862b-c6712f06f69e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876392851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1876392851
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3673948206
Short name T961
Test name
Test status
Simulation time 26960684 ps
CPU time 0.76 seconds
Started Jul 27 06:35:05 PM PDT 24
Finished Jul 27 06:35:06 PM PDT 24
Peak memory 205432 kb
Host smart-b6c10465-5e3f-4210-b975-b9f8b4be8297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673948206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3673948206
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.964824136
Short name T938
Test name
Test status
Simulation time 43596884 ps
CPU time 0.69 seconds
Started Jul 27 06:35:06 PM PDT 24
Finished Jul 27 06:35:07 PM PDT 24
Peak memory 205520 kb
Host smart-b477e576-31c5-4eef-adf8-b0270d513cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964824136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.964824136
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1359666597
Short name T953
Test name
Test status
Simulation time 28081465 ps
CPU time 0.76 seconds
Started Jul 27 06:35:03 PM PDT 24
Finished Jul 27 06:35:04 PM PDT 24
Peak memory 205516 kb
Host smart-897ba9d4-80be-4864-808f-84d81fc22abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359666597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1359666597
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4218887277
Short name T1061
Test name
Test status
Simulation time 253760995 ps
CPU time 5.8 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 205712 kb
Host smart-0d9d42ed-a9f1-49f8-9f5a-86d193ef2c8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218887277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
218887277
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1291004591
Short name T992
Test name
Test status
Simulation time 261297467 ps
CPU time 7.77 seconds
Started Jul 27 06:34:36 PM PDT 24
Finished Jul 27 06:34:44 PM PDT 24
Peak memory 205724 kb
Host smart-f1958fb7-84d1-4166-85a0-9ff7a023b5ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291004591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
291004591
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3274209755
Short name T1071
Test name
Test status
Simulation time 54684709 ps
CPU time 1.03 seconds
Started Jul 27 06:34:29 PM PDT 24
Finished Jul 27 06:34:30 PM PDT 24
Peak memory 205660 kb
Host smart-30a18681-0dfd-4e2a-b9b2-1ecd8910cb96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274209755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
274209755
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3714029488
Short name T1001
Test name
Test status
Simulation time 135110975 ps
CPU time 1.48 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 214008 kb
Host smart-ed83e238-f8ce-42a1-8f43-d6e50ecc0e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714029488 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3714029488
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.464204659
Short name T948
Test name
Test status
Simulation time 55730777 ps
CPU time 1.63 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:32 PM PDT 24
Peak memory 205608 kb
Host smart-cd414c75-1f9c-49da-8615-593a4858931b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464204659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.464204659
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3548725377
Short name T967
Test name
Test status
Simulation time 46363921 ps
CPU time 0.78 seconds
Started Jul 27 06:34:37 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 205452 kb
Host smart-c82ffaa1-b507-46a3-b7ca-69f01d655ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548725377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3548725377
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2322802710
Short name T143
Test name
Test status
Simulation time 32688566 ps
CPU time 2.42 seconds
Started Jul 27 06:34:35 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 205740 kb
Host smart-b4cf861f-8233-4469-8ca8-4223c0120b6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322802710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2322802710
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1738337254
Short name T983
Test name
Test status
Simulation time 688596689 ps
CPU time 3.58 seconds
Started Jul 27 06:34:32 PM PDT 24
Finished Jul 27 06:34:36 PM PDT 24
Peak memory 214104 kb
Host smart-d2a69c5b-f817-4c30-9903-0384b6621b13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738337254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1738337254
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3458186097
Short name T980
Test name
Test status
Simulation time 259874226 ps
CPU time 8.85 seconds
Started Jul 27 06:34:31 PM PDT 24
Finished Jul 27 06:34:40 PM PDT 24
Peak memory 214120 kb
Host smart-2d8bca67-c88e-4004-9cfc-a7fb685d4a42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458186097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3458186097
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3634381082
Short name T1052
Test name
Test status
Simulation time 127817515 ps
CPU time 3.09 seconds
Started Jul 27 06:34:30 PM PDT 24
Finished Jul 27 06:34:33 PM PDT 24
Peak memory 216128 kb
Host smart-2a667c5c-d950-4859-816e-a79ca94cb0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634381082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3634381082
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3103835796
Short name T994
Test name
Test status
Simulation time 67128719 ps
CPU time 0.76 seconds
Started Jul 27 06:35:04 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 205516 kb
Host smart-64cac4f6-1a45-4493-bfe3-37422e6a5385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103835796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3103835796
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1471623086
Short name T926
Test name
Test status
Simulation time 34504900 ps
CPU time 0.81 seconds
Started Jul 27 06:35:06 PM PDT 24
Finished Jul 27 06:35:07 PM PDT 24
Peak memory 205508 kb
Host smart-d22b6e6a-b6e5-4031-888a-be5b2a8c6c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471623086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1471623086
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1065182329
Short name T921
Test name
Test status
Simulation time 76659630 ps
CPU time 0.74 seconds
Started Jul 27 06:35:05 PM PDT 24
Finished Jul 27 06:35:06 PM PDT 24
Peak memory 205504 kb
Host smart-cb281440-36d1-47a9-95de-a6461ca25ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065182329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1065182329
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.884938272
Short name T964
Test name
Test status
Simulation time 18323004 ps
CPU time 0.72 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205516 kb
Host smart-d4949c00-5d7c-4526-af03-537bf2dfdfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884938272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.884938272
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2680864538
Short name T1030
Test name
Test status
Simulation time 10983025 ps
CPU time 0.84 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205520 kb
Host smart-ae9170c9-d683-4f9b-bb14-d6229eef3479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680864538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2680864538
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2903215579
Short name T950
Test name
Test status
Simulation time 26913819 ps
CPU time 0.79 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205420 kb
Host smart-515d67ab-b862-4e50-be8c-99ac00abab51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903215579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2903215579
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2174448393
Short name T917
Test name
Test status
Simulation time 15525476 ps
CPU time 0.78 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205464 kb
Host smart-2947121d-9021-4e15-85ac-8a8d66abb8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174448393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2174448393
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4057769394
Short name T920
Test name
Test status
Simulation time 9281893 ps
CPU time 0.74 seconds
Started Jul 27 06:35:17 PM PDT 24
Finished Jul 27 06:35:18 PM PDT 24
Peak memory 205524 kb
Host smart-b7460c36-4158-4689-9f3c-88e82fec1fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057769394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4057769394
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.352472247
Short name T925
Test name
Test status
Simulation time 75137887 ps
CPU time 0.7 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205504 kb
Host smart-96123488-3ae4-4ea0-9939-210812eff10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352472247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.352472247
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3798378696
Short name T986
Test name
Test status
Simulation time 13020992 ps
CPU time 0.76 seconds
Started Jul 27 06:35:17 PM PDT 24
Finished Jul 27 06:35:18 PM PDT 24
Peak memory 205528 kb
Host smart-8bf5f65b-fdd3-47ce-bf78-0bf0855ddbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798378696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3798378696
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.113010966
Short name T1055
Test name
Test status
Simulation time 556802066 ps
CPU time 7.79 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205760 kb
Host smart-89a28a7c-8c8b-4fc1-82a2-f88c3fd6d6cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113010966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.113010966
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4083849911
Short name T959
Test name
Test status
Simulation time 447406900 ps
CPU time 12.26 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 205604 kb
Host smart-33b3808c-eaf0-4460-b9be-50f3208ceb95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083849911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4
083849911
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.689134143
Short name T1021
Test name
Test status
Simulation time 21775281 ps
CPU time 1.23 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 205724 kb
Host smart-a49b58c7-87d4-43c6-a8c8-a21efa1ab75f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689134143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.689134143
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3109548006
Short name T153
Test name
Test status
Simulation time 144935256 ps
CPU time 1.89 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 213960 kb
Host smart-d621adff-bed0-4eed-a37f-c4f747b3b75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109548006 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3109548006
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4065121780
Short name T1006
Test name
Test status
Simulation time 155474166 ps
CPU time 1.19 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 205708 kb
Host smart-02871b34-6053-4f8c-91be-6ab5a9711a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065121780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4065121780
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3917419344
Short name T998
Test name
Test status
Simulation time 16369233 ps
CPU time 0.95 seconds
Started Jul 27 06:34:39 PM PDT 24
Finished Jul 27 06:34:40 PM PDT 24
Peak memory 205676 kb
Host smart-abfefc38-08a2-455b-8f05-c66c6acda1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917419344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3917419344
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2743094441
Short name T968
Test name
Test status
Simulation time 25562070 ps
CPU time 1.73 seconds
Started Jul 27 06:34:37 PM PDT 24
Finished Jul 27 06:34:39 PM PDT 24
Peak memory 205700 kb
Host smart-7628c479-06a2-4b07-b118-5b20d3012958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743094441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2743094441
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.238138221
Short name T1047
Test name
Test status
Simulation time 164528155 ps
CPU time 2.04 seconds
Started Jul 27 06:34:36 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 214112 kb
Host smart-5e533be4-d3d7-4cc1-9027-0ff06d8eab66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238138221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.238138221
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3711498853
Short name T1003
Test name
Test status
Simulation time 90316403 ps
CPU time 3.78 seconds
Started Jul 27 06:34:37 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 214208 kb
Host smart-4aa51c71-d4a7-4a29-84e9-6122514165a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711498853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3711498853
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.21049195
Short name T954
Test name
Test status
Simulation time 481899330 ps
CPU time 4.6 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 213940 kb
Host smart-cb910257-ea8f-42a6-ade1-242aadcc4acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21049195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.21049195
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2407824684
Short name T1023
Test name
Test status
Simulation time 45380763 ps
CPU time 0.69 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205400 kb
Host smart-dbd5781c-ad55-41b5-8931-db2817400f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407824684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2407824684
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1788483363
Short name T1060
Test name
Test status
Simulation time 23050975 ps
CPU time 0.68 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205488 kb
Host smart-2df5ccc2-8b32-4d33-b434-6ebf8f2943c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788483363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1788483363
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.199750348
Short name T988
Test name
Test status
Simulation time 18496808 ps
CPU time 0.92 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:35:16 PM PDT 24
Peak memory 205664 kb
Host smart-8e3aecf4-6566-4fb2-9a45-5d3247d54534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199750348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.199750348
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1236734954
Short name T981
Test name
Test status
Simulation time 30929783 ps
CPU time 0.7 seconds
Started Jul 27 06:35:16 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 205508 kb
Host smart-e950ebe2-88e2-44e2-ad5b-19dbed1089d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236734954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1236734954
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1972165230
Short name T909
Test name
Test status
Simulation time 13889594 ps
CPU time 0.74 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205524 kb
Host smart-a3ede5ea-3940-4043-8ce3-fe42088a29b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972165230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1972165230
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1924010761
Short name T916
Test name
Test status
Simulation time 16770704 ps
CPU time 0.75 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205388 kb
Host smart-8e24e251-407a-4dca-8b48-1e6f1edcb8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924010761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1924010761
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.947193240
Short name T1075
Test name
Test status
Simulation time 29337220 ps
CPU time 0.7 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205408 kb
Host smart-641984c9-efe7-4674-a956-65f11ab24699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947193240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.947193240
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.735673320
Short name T976
Test name
Test status
Simulation time 11984572 ps
CPU time 0.85 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:35:16 PM PDT 24
Peak memory 205480 kb
Host smart-062ac8c8-7da5-44be-9d30-8941daf174dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735673320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.735673320
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3073742368
Short name T913
Test name
Test status
Simulation time 47871877 ps
CPU time 0.76 seconds
Started Jul 27 06:35:15 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205568 kb
Host smart-7c8c72a9-59f2-42ad-bc63-b4845c8fadba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073742368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3073742368
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2550243058
Short name T958
Test name
Test status
Simulation time 19448397 ps
CPU time 0.69 seconds
Started Jul 27 06:35:14 PM PDT 24
Finished Jul 27 06:35:15 PM PDT 24
Peak memory 205460 kb
Host smart-73804008-0bd0-4825-9d22-dd19828c1f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550243058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2550243058
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3634980461
Short name T1038
Test name
Test status
Simulation time 80913641 ps
CPU time 1.56 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 205824 kb
Host smart-c7d9e63e-e0e8-492d-b716-eb7f14438b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634980461 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3634980461
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2904873477
Short name T944
Test name
Test status
Simulation time 96216456 ps
CPU time 1.06 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:42 PM PDT 24
Peak memory 205656 kb
Host smart-a8ad6ccd-bd6d-41a1-953b-464d9832abd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904873477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2904873477
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2878640902
Short name T934
Test name
Test status
Simulation time 136912960 ps
CPU time 0.73 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:38 PM PDT 24
Peak memory 205492 kb
Host smart-5a1b8aad-e27a-41f3-95a8-a6a70c570349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878640902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2878640902
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1800049361
Short name T1057
Test name
Test status
Simulation time 64649798 ps
CPU time 1.62 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 205724 kb
Host smart-296fb45f-b012-4ed5-867d-ba3c0f0070a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800049361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1800049361
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2101155376
Short name T1008
Test name
Test status
Simulation time 99917791 ps
CPU time 3.02 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 214164 kb
Host smart-577b8991-9f4c-4940-bbc4-d846dcdb099a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101155376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2101155376
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2427373968
Short name T970
Test name
Test status
Simulation time 690281008 ps
CPU time 5.08 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 214140 kb
Host smart-cfe81b70-2580-4e62-a6a4-15e9bbe5b690
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427373968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2427373968
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3908789046
Short name T1024
Test name
Test status
Simulation time 584699166 ps
CPU time 5.25 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:47 PM PDT 24
Peak memory 216212 kb
Host smart-5b84a649-ef66-4960-a622-9ccb693f47ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908789046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3908789046
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.754256313
Short name T156
Test name
Test status
Simulation time 633955361 ps
CPU time 10.8 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 213876 kb
Host smart-311338a1-805b-4ce7-b71e-4c006fb46a24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754256313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
754256313
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.543079893
Short name T995
Test name
Test status
Simulation time 45057647 ps
CPU time 2.04 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 213992 kb
Host smart-feb53b99-9d2e-4985-a4aa-f587648e1e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543079893 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.543079893
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.859192579
Short name T973
Test name
Test status
Simulation time 29143377 ps
CPU time 1.57 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:42 PM PDT 24
Peak memory 205676 kb
Host smart-a282c673-997f-433c-a54f-def05a34fc46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859192579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.859192579
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.938153489
Short name T1035
Test name
Test status
Simulation time 91338954 ps
CPU time 0.76 seconds
Started Jul 27 06:34:38 PM PDT 24
Finished Jul 27 06:34:39 PM PDT 24
Peak memory 205520 kb
Host smart-3e51e822-42d4-4947-913d-84db51206d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938153489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.938153489
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1699719063
Short name T972
Test name
Test status
Simulation time 18883110 ps
CPU time 1.53 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 205668 kb
Host smart-3a4f76d9-1c7c-4e8c-aef0-14627a562ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699719063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1699719063
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1423961199
Short name T996
Test name
Test status
Simulation time 127366694 ps
CPU time 3.96 seconds
Started Jul 27 06:34:37 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 214200 kb
Host smart-6452127f-5bab-4ebe-8b3d-b93c99a1da3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423961199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1423961199
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2176144976
Short name T965
Test name
Test status
Simulation time 457081073 ps
CPU time 4.29 seconds
Started Jul 27 06:34:37 PM PDT 24
Finished Jul 27 06:34:42 PM PDT 24
Peak memory 214140 kb
Host smart-168de8d9-d739-4cbe-a85d-cb3b6d374e47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176144976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2176144976
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1754523161
Short name T935
Test name
Test status
Simulation time 260294366 ps
CPU time 4.97 seconds
Started Jul 27 06:34:40 PM PDT 24
Finished Jul 27 06:34:45 PM PDT 24
Peak memory 216180 kb
Host smart-9ebdc6a8-04c7-4696-8c24-0353b8c96d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754523161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1754523161
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2861689985
Short name T160
Test name
Test status
Simulation time 277037666 ps
CPU time 7.31 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 213908 kb
Host smart-addc84d4-e19c-4419-810f-9d4751400411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861689985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2861689985
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3780498712
Short name T985
Test name
Test status
Simulation time 50609684 ps
CPU time 1.7 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 214044 kb
Host smart-f3a4ca69-6277-47ae-9c80-57a0f23bcc78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780498712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3780498712
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3102195835
Short name T1044
Test name
Test status
Simulation time 31936888 ps
CPU time 0.94 seconds
Started Jul 27 06:34:36 PM PDT 24
Finished Jul 27 06:34:37 PM PDT 24
Peak memory 205564 kb
Host smart-4d2413d2-22c7-467e-9822-d28590e29c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102195835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3102195835
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3725581140
Short name T1064
Test name
Test status
Simulation time 48249333 ps
CPU time 0.88 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 205508 kb
Host smart-c4353227-71d8-425c-bb4c-e39b0da90de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725581140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3725581140
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3571315341
Short name T149
Test name
Test status
Simulation time 130985555 ps
CPU time 2.21 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 205704 kb
Host smart-727e3f8f-e226-46b0-bc6e-218d09e0319f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571315341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3571315341
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1921570629
Short name T118
Test name
Test status
Simulation time 244786074 ps
CPU time 2.68 seconds
Started Jul 27 06:34:39 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 214184 kb
Host smart-cf2fdf11-22c8-4aa1-9e41-0570e7668608
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921570629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1921570629
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1977535242
Short name T115
Test name
Test status
Simulation time 343520683 ps
CPU time 6.99 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 214208 kb
Host smart-6eb31d7c-a0ac-47c4-b170-e0ca7e764e0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977535242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1977535242
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3840334463
Short name T978
Test name
Test status
Simulation time 116408456 ps
CPU time 3.09 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:44 PM PDT 24
Peak memory 213956 kb
Host smart-afa76f20-ac3b-4ebb-a4a5-17a36268b2d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840334463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3840334463
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2681363240
Short name T991
Test name
Test status
Simulation time 103875630 ps
CPU time 1.66 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:49 PM PDT 24
Peak memory 213984 kb
Host smart-8765e886-8206-4a5f-ae1b-4f93ece4b09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681363240 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2681363240
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1078385847
Short name T943
Test name
Test status
Simulation time 26922630 ps
CPU time 1.04 seconds
Started Jul 27 06:34:39 PM PDT 24
Finished Jul 27 06:34:40 PM PDT 24
Peak memory 205748 kb
Host smart-938edd73-14f2-41a4-89d8-e803f904892b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078385847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1078385847
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3802058621
Short name T1011
Test name
Test status
Simulation time 48290553 ps
CPU time 0.78 seconds
Started Jul 27 06:34:42 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 205516 kb
Host smart-2f7bfbfd-c85e-42a7-8e71-298e50348cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802058621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3802058621
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2333966163
Short name T1045
Test name
Test status
Simulation time 406473946 ps
CPU time 2.22 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:44 PM PDT 24
Peak memory 205660 kb
Host smart-eff275dc-1f08-43bb-88dc-91080e890e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333966163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2333966163
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.730035308
Short name T1040
Test name
Test status
Simulation time 757377948 ps
CPU time 2.05 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 214224 kb
Host smart-7c0c6bbc-d308-4700-911e-e032265b827b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730035308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.730035308
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1886169561
Short name T990
Test name
Test status
Simulation time 358764217 ps
CPU time 1.89 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 213908 kb
Host smart-c64a8f8f-149e-446d-905a-313f77a750d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886169561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1886169561
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.936824722
Short name T1020
Test name
Test status
Simulation time 416651166 ps
CPU time 3.35 seconds
Started Jul 27 06:34:41 PM PDT 24
Finished Jul 27 06:34:44 PM PDT 24
Peak memory 213832 kb
Host smart-65b30337-5628-4601-9fc6-28986069a169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936824722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
936824722
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4203075526
Short name T937
Test name
Test status
Simulation time 381001111 ps
CPU time 1.37 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205764 kb
Host smart-c9f57464-db17-492b-a9ee-4b1b7be0923e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203075526 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4203075526
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2271751576
Short name T1004
Test name
Test status
Simulation time 17838533 ps
CPU time 1.15 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205668 kb
Host smart-ba7cd860-25dd-41b9-ab1c-fcf5d44361f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271751576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2271751576
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1119488586
Short name T1013
Test name
Test status
Simulation time 19886224 ps
CPU time 0.82 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 205512 kb
Host smart-074d98b7-af5d-40f0-979a-3a4fdd4e692d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119488586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1119488586
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.579597217
Short name T147
Test name
Test status
Simulation time 33522523 ps
CPU time 2.3 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 205764 kb
Host smart-c390bc6c-2e83-46f1-87bc-e057e8b419da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579597217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.579597217
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2215637098
Short name T120
Test name
Test status
Simulation time 342179700 ps
CPU time 3.43 seconds
Started Jul 27 06:34:51 PM PDT 24
Finished Jul 27 06:34:54 PM PDT 24
Peak memory 214224 kb
Host smart-c8156c25-775b-4efe-845e-789c1e28d9cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215637098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2215637098
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.502030755
Short name T1039
Test name
Test status
Simulation time 185955009 ps
CPU time 5.01 seconds
Started Jul 27 06:34:46 PM PDT 24
Finished Jul 27 06:34:51 PM PDT 24
Peak memory 214092 kb
Host smart-cae506c7-9827-48b6-ace3-34c5898db243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502030755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.502030755
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1138653766
Short name T969
Test name
Test status
Simulation time 203284364 ps
CPU time 2.21 seconds
Started Jul 27 06:34:50 PM PDT 24
Finished Jul 27 06:34:52 PM PDT 24
Peak memory 216036 kb
Host smart-f23b6a3d-91d7-44dc-9a2f-d81900753bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138653766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1138653766
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1248718945
Short name T1029
Test name
Test status
Simulation time 91585747 ps
CPU time 5.17 seconds
Started Jul 27 06:34:47 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 213952 kb
Host smart-7c4d4e8d-2f31-46a4-bcaf-990f956e8e76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248718945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1248718945
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1934517605
Short name T458
Test name
Test status
Simulation time 8580243 ps
CPU time 0.83 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:09 PM PDT 24
Peak memory 205816 kb
Host smart-4a3cbedd-6192-45ff-adf7-ce5aedf20e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934517605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1934517605
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1699353810
Short name T382
Test name
Test status
Simulation time 60058305 ps
CPU time 3.88 seconds
Started Jul 27 05:40:04 PM PDT 24
Finished Jul 27 05:40:08 PM PDT 24
Peak memory 215336 kb
Host smart-1a83e9de-9cde-4b2d-9274-470496a98133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699353810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1699353810
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3953496878
Short name T522
Test name
Test status
Simulation time 6350196931 ps
CPU time 54.45 seconds
Started Jul 27 05:40:06 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 218248 kb
Host smart-3197164d-2208-4ee4-9a74-6e0a9a858b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953496878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3953496878
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1269185921
Short name T290
Test name
Test status
Simulation time 81085653 ps
CPU time 2.04 seconds
Started Jul 27 05:40:01 PM PDT 24
Finished Jul 27 05:40:04 PM PDT 24
Peak memory 214160 kb
Host smart-66501a2c-d76a-43f9-a338-5bcc8931c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269185921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1269185921
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3075180682
Short name T85
Test name
Test status
Simulation time 559250448 ps
CPU time 12.21 seconds
Started Jul 27 05:40:00 PM PDT 24
Finished Jul 27 05:40:12 PM PDT 24
Peak memory 214064 kb
Host smart-f7e46572-0876-4a11-9341-640e3fda954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075180682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3075180682
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1775855241
Short name T524
Test name
Test status
Simulation time 39352641 ps
CPU time 1.88 seconds
Started Jul 27 05:40:05 PM PDT 24
Finished Jul 27 05:40:07 PM PDT 24
Peak memory 209628 kb
Host smart-e970bb2a-5723-467b-a257-97998e94ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775855241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1775855241
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.540015571
Short name T263
Test name
Test status
Simulation time 1258877254 ps
CPU time 40.97 seconds
Started Jul 27 05:39:59 PM PDT 24
Finished Jul 27 05:40:40 PM PDT 24
Peak memory 214172 kb
Host smart-ac9e71d9-f41c-48a2-b78a-0030dfdd9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540015571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.540015571
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.821221098
Short name T13
Test name
Test status
Simulation time 778235821 ps
CPU time 6.82 seconds
Started Jul 27 05:40:19 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 230568 kb
Host smart-ddb1f90a-0140-4f11-8f53-562af5478d16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821221098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.821221098
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2323418856
Short name T626
Test name
Test status
Simulation time 3077935319 ps
CPU time 22.33 seconds
Started Jul 27 05:40:02 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 207808 kb
Host smart-72004835-f204-4bc7-a85f-6be682e87c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323418856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2323418856
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4008508394
Short name T354
Test name
Test status
Simulation time 392915319 ps
CPU time 3.78 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 208308 kb
Host smart-abcae946-4d6a-47a6-9be0-467ba0f79cb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008508394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4008508394
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2744615159
Short name T136
Test name
Test status
Simulation time 275456912 ps
CPU time 3.98 seconds
Started Jul 27 05:40:01 PM PDT 24
Finished Jul 27 05:40:05 PM PDT 24
Peak memory 206644 kb
Host smart-71da822e-7776-4156-aceb-890974ba909b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744615159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2744615159
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3167359969
Short name T561
Test name
Test status
Simulation time 41295902 ps
CPU time 1.75 seconds
Started Jul 27 05:40:04 PM PDT 24
Finished Jul 27 05:40:06 PM PDT 24
Peak memory 207180 kb
Host smart-aef22766-e6fb-4584-8173-391bb402fe52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167359969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3167359969
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1459550124
Short name T516
Test name
Test status
Simulation time 229627169 ps
CPU time 3.82 seconds
Started Jul 27 05:40:04 PM PDT 24
Finished Jul 27 05:40:08 PM PDT 24
Peak memory 209660 kb
Host smart-91cce33b-1a3f-4f81-ac87-eabde11c2948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459550124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1459550124
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1293270093
Short name T4
Test name
Test status
Simulation time 88949722 ps
CPU time 3.69 seconds
Started Jul 27 05:40:04 PM PDT 24
Finished Jul 27 05:40:08 PM PDT 24
Peak memory 208488 kb
Host smart-51e8bb61-d7cc-441d-885a-2d45ae8fe183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293270093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1293270093
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4074101034
Short name T319
Test name
Test status
Simulation time 2107785807 ps
CPU time 35.62 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 222232 kb
Host smart-8ffa4638-7fc5-48c6-9b0d-3a1fae570a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074101034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4074101034
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3400434649
Short name T586
Test name
Test status
Simulation time 802319923 ps
CPU time 14.99 seconds
Started Jul 27 05:39:59 PM PDT 24
Finished Jul 27 05:40:14 PM PDT 24
Peak memory 218064 kb
Host smart-3e10d425-0a31-4db4-9e51-24342f11ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400434649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3400434649
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2085957205
Short name T576
Test name
Test status
Simulation time 22345586 ps
CPU time 0.72 seconds
Started Jul 27 05:40:06 PM PDT 24
Finished Jul 27 05:40:07 PM PDT 24
Peak memory 205824 kb
Host smart-9d3a95b4-93ec-4ba8-af5b-08e281687c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085957205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2085957205
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3024029708
Short name T866
Test name
Test status
Simulation time 302599522 ps
CPU time 3.71 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 209700 kb
Host smart-8d1cc597-6795-4b31-80a5-00964d9aa112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024029708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3024029708
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.389519090
Short name T348
Test name
Test status
Simulation time 129915895 ps
CPU time 3.38 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 208664 kb
Host smart-8ab200b1-5524-409a-8314-394b2408ccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389519090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.389519090
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2825902147
Short name T551
Test name
Test status
Simulation time 167240147 ps
CPU time 6.51 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:15 PM PDT 24
Peak memory 214100 kb
Host smart-f75b40cd-0ef8-48ce-96e6-aaf488e2aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825902147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2825902147
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2024810790
Short name T403
Test name
Test status
Simulation time 64832977 ps
CPU time 2.56 seconds
Started Jul 27 05:40:10 PM PDT 24
Finished Jul 27 05:40:13 PM PDT 24
Peak memory 214756 kb
Host smart-da3645c6-0c9d-4561-aad6-a2f3fbbc27b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024810790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2024810790
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3628796703
Short name T521
Test name
Test status
Simulation time 258376657 ps
CPU time 3.43 seconds
Started Jul 27 05:40:13 PM PDT 24
Finished Jul 27 05:40:17 PM PDT 24
Peak memory 209172 kb
Host smart-adf0d9d6-4da1-44e6-8f91-094814d4339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628796703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3628796703
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1096172992
Short name T11
Test name
Test status
Simulation time 985822498 ps
CPU time 11.69 seconds
Started Jul 27 05:40:13 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 237920 kb
Host smart-0d0f65eb-2228-48ae-81f1-8e23a10efbc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096172992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1096172992
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2103197286
Short name T99
Test name
Test status
Simulation time 1096536942 ps
CPU time 3.14 seconds
Started Jul 27 05:40:09 PM PDT 24
Finished Jul 27 05:40:12 PM PDT 24
Peak memory 207912 kb
Host smart-4f65bfa6-7e70-41c3-b92d-23afa5cb7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103197286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2103197286
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2300179853
Short name T873
Test name
Test status
Simulation time 1087058205 ps
CPU time 4.48 seconds
Started Jul 27 05:40:06 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 206680 kb
Host smart-f83caf42-742b-4a46-9f38-c64264bd2f70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300179853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2300179853
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3899849421
Short name T842
Test name
Test status
Simulation time 2568339361 ps
CPU time 28.19 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 206868 kb
Host smart-a6009935-3810-4947-b5d9-20d0dab034d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899849421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3899849421
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3192392057
Short name T895
Test name
Test status
Simulation time 197765570 ps
CPU time 2.56 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:16 PM PDT 24
Peak memory 208260 kb
Host smart-ec367c4e-e901-4928-ac46-e2182bf43c9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192392057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3192392057
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.504725522
Short name T676
Test name
Test status
Simulation time 34415556 ps
CPU time 2.16 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:10 PM PDT 24
Peak memory 214060 kb
Host smart-cda24b8a-114a-441b-86f0-4d52b87c6fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504725522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.504725522
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1389146102
Short name T408
Test name
Test status
Simulation time 342730660 ps
CPU time 3.96 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 208516 kb
Host smart-41feebd7-2fb5-4536-97e2-fc02c6dd3059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389146102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1389146102
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3657100146
Short name T699
Test name
Test status
Simulation time 1613373676 ps
CPU time 24.9 seconds
Started Jul 27 05:40:05 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 216844 kb
Host smart-516c975e-7f7c-4785-8758-61a5ffcdf3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657100146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3657100146
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.848893480
Short name T359
Test name
Test status
Simulation time 33642588 ps
CPU time 2.68 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 207984 kb
Host smart-cfef461b-ed68-409d-a7c0-cb4c24b508d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848893480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.848893480
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4068035277
Short name T599
Test name
Test status
Simulation time 73993179 ps
CPU time 0.77 seconds
Started Jul 27 05:40:44 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 205792 kb
Host smart-00da0236-0f1d-4b4f-b60e-bf872b41701b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068035277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4068035277
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2970466678
Short name T29
Test name
Test status
Simulation time 105796325 ps
CPU time 2.65 seconds
Started Jul 27 05:40:31 PM PDT 24
Finished Jul 27 05:40:33 PM PDT 24
Peak memory 217824 kb
Host smart-cced85ec-cdc7-4ce3-8e29-0bbfbd5c71f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970466678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2970466678
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1085319862
Short name T892
Test name
Test status
Simulation time 341206935 ps
CPU time 2.87 seconds
Started Jul 27 05:40:31 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 209100 kb
Host smart-42669dce-fe12-4bd7-ba8f-756ab18f57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085319862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1085319862
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2722991674
Short name T325
Test name
Test status
Simulation time 295013829 ps
CPU time 2.5 seconds
Started Jul 27 05:40:33 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 213976 kb
Host smart-77ee0199-778c-4906-a528-782520cf8257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722991674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2722991674
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.602116755
Short name T555
Test name
Test status
Simulation time 109671455 ps
CPU time 2.66 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:41 PM PDT 24
Peak memory 207536 kb
Host smart-81dc25b3-cc7d-4308-9f74-2bf8a0e6d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602116755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.602116755
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.856909351
Short name T755
Test name
Test status
Simulation time 49219729 ps
CPU time 3.29 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 208152 kb
Host smart-13b80c13-0d4b-4798-ac6e-c75b51de7520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856909351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.856909351
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.348587212
Short name T659
Test name
Test status
Simulation time 1353959211 ps
CPU time 28.53 seconds
Started Jul 27 05:40:34 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 208676 kb
Host smart-f98e6d4e-62b9-40b2-aa87-232527d02e8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348587212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.348587212
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2741247843
Short name T791
Test name
Test status
Simulation time 209447989 ps
CPU time 3 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 206860 kb
Host smart-da5ac0a5-33cd-4ff9-9a0e-b52b47913020
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741247843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2741247843
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1958255117
Short name T695
Test name
Test status
Simulation time 176505463 ps
CPU time 5.83 seconds
Started Jul 27 05:40:31 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 206864 kb
Host smart-ecf8fb85-a1d8-4c6e-a6f6-f45e76a263c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958255117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1958255117
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4280636789
Short name T293
Test name
Test status
Simulation time 42060645 ps
CPU time 2.79 seconds
Started Jul 27 05:40:34 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 209248 kb
Host smart-6220acab-1ac0-4090-bee1-05e9130863ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280636789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4280636789
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1554334928
Short name T663
Test name
Test status
Simulation time 224039076 ps
CPU time 2.63 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 206564 kb
Host smart-851dc3be-f387-4ea5-b098-c43a15f9b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554334928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1554334928
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3713398598
Short name T475
Test name
Test status
Simulation time 34833830 ps
CPU time 2.24 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:40:41 PM PDT 24
Peak memory 206744 kb
Host smart-5e7f694d-5195-4ffe-8b35-f4f3573ade30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713398598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3713398598
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1614708419
Short name T342
Test name
Test status
Simulation time 1425660239 ps
CPU time 15.93 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 208940 kb
Host smart-0fcffd4b-51f5-4f79-8690-e169378ac74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614708419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1614708419
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2146913061
Short name T837
Test name
Test status
Simulation time 36003767 ps
CPU time 1.84 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 209704 kb
Host smart-d8cb9c5e-15bd-41cc-aaf9-0e6fcb5d39e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146913061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2146913061
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4144495669
Short name T405
Test name
Test status
Simulation time 42640701 ps
CPU time 3.29 seconds
Started Jul 27 05:40:36 PM PDT 24
Finished Jul 27 05:40:40 PM PDT 24
Peak memory 215340 kb
Host smart-095bcf0d-ed6c-4885-9d73-2073233eab43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144495669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4144495669
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2179590346
Short name T875
Test name
Test status
Simulation time 2950085006 ps
CPU time 7.64 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 221732 kb
Host smart-62918aba-221f-4c6b-9f91-4812bd9880af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179590346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2179590346
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3620791539
Short name T492
Test name
Test status
Simulation time 227943035 ps
CPU time 2.81 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:40:41 PM PDT 24
Peak memory 214296 kb
Host smart-7bed1942-76b6-413c-833b-22fa7a184119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620791539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3620791539
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.79852749
Short name T259
Test name
Test status
Simulation time 547253691 ps
CPU time 4.07 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 214112 kb
Host smart-f9d4bb19-dd5b-4607-9839-250e877d42b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79852749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.79852749
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3790978790
Short name T653
Test name
Test status
Simulation time 322325095 ps
CPU time 6.32 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:44 PM PDT 24
Peak memory 218384 kb
Host smart-5833d8dc-1cb5-4212-92d0-34332fe57acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790978790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3790978790
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.239375945
Short name T554
Test name
Test status
Simulation time 162725008 ps
CPU time 2.62 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:44 PM PDT 24
Peak memory 207732 kb
Host smart-7d3a2eb8-21a0-4d54-b15d-a156af9f4702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239375945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.239375945
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2156188238
Short name T542
Test name
Test status
Simulation time 127310587 ps
CPU time 2.3 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:02 PM PDT 24
Peak memory 206460 kb
Host smart-ac90e932-aae0-4649-a318-eb74cd67c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156188238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2156188238
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1876719784
Short name T740
Test name
Test status
Simulation time 37675055 ps
CPU time 2.58 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 208724 kb
Host smart-a9762c3f-4ba4-4822-83c5-7872bbdc519c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876719784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1876719784
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.559742347
Short name T782
Test name
Test status
Simulation time 63093784 ps
CPU time 3.07 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 208400 kb
Host smart-75b32a8b-df63-41ae-b22c-aee30e126928
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559742347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.559742347
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1406317561
Short name T398
Test name
Test status
Simulation time 1441757321 ps
CPU time 15.47 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 220132 kb
Host smart-62b0d0c0-4d1c-462f-8c82-4a0f165118e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406317561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1406317561
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.929383674
Short name T594
Test name
Test status
Simulation time 20791205 ps
CPU time 1.68 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:44 PM PDT 24
Peak memory 206420 kb
Host smart-e96612b5-c10e-4cab-a431-e46324fac8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929383674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.929383674
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.204480839
Short name T321
Test name
Test status
Simulation time 274777162 ps
CPU time 9.5 seconds
Started Jul 27 05:40:50 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 218012 kb
Host smart-219d91f3-f21b-4865-ba8d-4412cbb76015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204480839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.204480839
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1985763218
Short name T905
Test name
Test status
Simulation time 35145796 ps
CPU time 1.51 seconds
Started Jul 27 05:40:49 PM PDT 24
Finished Jul 27 05:40:51 PM PDT 24
Peak memory 209532 kb
Host smart-0c473150-9cab-45d0-a124-643b330a6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985763218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1985763218
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1688407593
Short name T843
Test name
Test status
Simulation time 53176969 ps
CPU time 0.88 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 205836 kb
Host smart-c07004f5-69b1-438c-8e5d-7b1680a52c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688407593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1688407593
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.972334950
Short name T749
Test name
Test status
Simulation time 581483035 ps
CPU time 12.93 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:58 PM PDT 24
Peak memory 214696 kb
Host smart-9bb9baf6-c62e-4bed-a6c6-b135dace4f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972334950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.972334950
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2478544769
Short name T850
Test name
Test status
Simulation time 274979979 ps
CPU time 4.22 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:47 PM PDT 24
Peak memory 210140 kb
Host smart-916bde98-2dbb-4eaa-a9d6-1c12ec62e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478544769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2478544769
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1977357183
Short name T696
Test name
Test status
Simulation time 266282551 ps
CPU time 4.18 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 214140 kb
Host smart-36fb906a-ddd6-4509-add4-95f9396c9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977357183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1977357183
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1111964550
Short name T768
Test name
Test status
Simulation time 54622665 ps
CPU time 3.28 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 219588 kb
Host smart-f81813c5-6858-4aa1-8ee8-d93340c08e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111964550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1111964550
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2508046319
Short name T101
Test name
Test status
Simulation time 236299567 ps
CPU time 4.33 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:46 PM PDT 24
Peak memory 214196 kb
Host smart-d869c269-4984-4123-8d43-cde970fd3acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508046319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2508046319
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3169292501
Short name T183
Test name
Test status
Simulation time 102778699 ps
CPU time 3.2 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 206660 kb
Host smart-d80f61cf-96e9-4a08-b590-fc1b83457370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169292501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3169292501
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.245989133
Short name T547
Test name
Test status
Simulation time 139142881 ps
CPU time 3.53 seconds
Started Jul 27 05:40:43 PM PDT 24
Finished Jul 27 05:40:46 PM PDT 24
Peak memory 208032 kb
Host smart-9b5b858f-f6a6-4889-977a-30a9fa67799d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245989133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.245989133
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3627307162
Short name T546
Test name
Test status
Simulation time 38503983 ps
CPU time 1.71 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 206920 kb
Host smart-47b5fd77-a3c9-460d-a398-ce512e4afd39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627307162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3627307162
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.779837032
Short name T793
Test name
Test status
Simulation time 186353840 ps
CPU time 2.55 seconds
Started Jul 27 05:40:47 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 206756 kb
Host smart-736a2136-75af-4ff6-a4fe-e7cf8003ae22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779837032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.779837032
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3100544486
Short name T479
Test name
Test status
Simulation time 126452244 ps
CPU time 2.65 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 206632 kb
Host smart-b12a2f8d-9141-439f-97dc-d0df9e06e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100544486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3100544486
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3423943534
Short name T537
Test name
Test status
Simulation time 116499647 ps
CPU time 3.62 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 208428 kb
Host smart-1411ef8b-6f5c-4532-85de-ce21ac15050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423943534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3423943534
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2429391581
Short name T769
Test name
Test status
Simulation time 56941322 ps
CPU time 2.17 seconds
Started Jul 27 05:40:40 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 209976 kb
Host smart-50da0f73-46be-4e8e-83c6-889de7f3a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429391581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2429391581
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3648225765
Short name T754
Test name
Test status
Simulation time 13893028 ps
CPU time 0.89 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 205884 kb
Host smart-33b0b70d-5698-47ca-9519-42fc8de59132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648225765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3648225765
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1826583913
Short name T383
Test name
Test status
Simulation time 37680265 ps
CPU time 2.7 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:44 PM PDT 24
Peak memory 214140 kb
Host smart-f77504ec-8235-4045-8038-d75f00657e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826583913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1826583913
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1162457625
Short name T212
Test name
Test status
Simulation time 415107712 ps
CPU time 8.66 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 218040 kb
Host smart-d53f9088-8cfd-4b3c-9f25-dcb029bd832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162457625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1162457625
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2056268883
Short name T643
Test name
Test status
Simulation time 273741133 ps
CPU time 3.39 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 208168 kb
Host smart-d9818bdf-2586-4fa6-a0fd-1d8c4e573106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056268883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2056268883
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4119523054
Short name T844
Test name
Test status
Simulation time 616569391 ps
CPU time 4.15 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:46 PM PDT 24
Peak memory 208484 kb
Host smart-e715ed08-0674-4502-942b-096ed473b14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119523054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4119523054
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1862104443
Short name T654
Test name
Test status
Simulation time 205715043 ps
CPU time 7.43 seconds
Started Jul 27 05:40:41 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 222156 kb
Host smart-336b08df-a28a-4fb7-ad4d-7c998ee821f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862104443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1862104443
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2511538641
Short name T425
Test name
Test status
Simulation time 202458104 ps
CPU time 2.89 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 218424 kb
Host smart-9019677d-1639-422d-b300-fc8a23235da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511538641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2511538641
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.660654370
Short name T105
Test name
Test status
Simulation time 4999289645 ps
CPU time 55.77 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 218304 kb
Host smart-5449e05e-7a68-43bc-8b55-a496e37a62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660654370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.660654370
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1022839635
Short name T3
Test name
Test status
Simulation time 312172203 ps
CPU time 3.34 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:56 PM PDT 24
Peak memory 208816 kb
Host smart-c51b0142-b64d-4a8d-9a8f-59ef330c61d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022839635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1022839635
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2625580831
Short name T756
Test name
Test status
Simulation time 52034083 ps
CPU time 2.79 seconds
Started Jul 27 05:40:44 PM PDT 24
Finished Jul 27 05:40:47 PM PDT 24
Peak memory 208596 kb
Host smart-857759d9-9c06-4af0-a222-4f68587f83c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625580831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2625580831
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2440873747
Short name T595
Test name
Test status
Simulation time 153109442 ps
CPU time 2.72 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 208628 kb
Host smart-6fe32da2-baff-4040-a6f5-3e05652ea573
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440873747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2440873747
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3024497298
Short name T634
Test name
Test status
Simulation time 34583069 ps
CPU time 2.16 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 206488 kb
Host smart-c3937b8e-bea0-478c-b8d9-405f84ccaac1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024497298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3024497298
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2955725192
Short name T620
Test name
Test status
Simulation time 137391763 ps
CPU time 3.33 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:46 PM PDT 24
Peak memory 209844 kb
Host smart-ce337292-3db1-4630-a39d-fc1cc8468148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955725192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2955725192
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2318281012
Short name T788
Test name
Test status
Simulation time 71655560 ps
CPU time 2.04 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 206760 kb
Host smart-806c9a96-b334-433f-a2dc-db80b91b0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318281012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2318281012
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2059087265
Short name T636
Test name
Test status
Simulation time 404337814 ps
CPU time 15.03 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:16 PM PDT 24
Peak memory 222388 kb
Host smart-edbd50b9-5684-46a5-9c46-84b3b9eadd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059087265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2059087265
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2192299322
Short name T229
Test name
Test status
Simulation time 223786011 ps
CPU time 3.94 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:40:43 PM PDT 24
Peak memory 207456 kb
Host smart-3572f943-9caf-40dc-8780-a909e9eab77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192299322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2192299322
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1962666564
Short name T798
Test name
Test status
Simulation time 419436218 ps
CPU time 1.91 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 209812 kb
Host smart-359d753e-fe97-4cad-a4d2-90e614a54893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962666564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1962666564
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2037002999
Short name T834
Test name
Test status
Simulation time 15223892 ps
CPU time 0.75 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:52 PM PDT 24
Peak memory 205752 kb
Host smart-5d893342-42c4-4d16-a41d-d7b76aecbe82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037002999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2037002999
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1008360098
Short name T25
Test name
Test status
Simulation time 218435327 ps
CPU time 2.22 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:40:58 PM PDT 24
Peak memory 218632 kb
Host smart-112c8002-299d-413f-87b5-fed360a36a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008360098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1008360098
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3146990110
Short name T835
Test name
Test status
Simulation time 1320247101 ps
CPU time 23.31 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:23 PM PDT 24
Peak memory 209744 kb
Host smart-3b237ee9-acc7-4aa5-9fc3-3e242fd19ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146990110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3146990110
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3017615394
Short name T51
Test name
Test status
Simulation time 213457709 ps
CPU time 2.65 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 214176 kb
Host smart-fffe96c6-91ee-4488-9d86-c1a9b8365083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017615394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3017615394
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.201855226
Short name T172
Test name
Test status
Simulation time 130551041 ps
CPU time 5.29 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:41:02 PM PDT 24
Peak memory 222260 kb
Host smart-05e29009-0b04-4980-99ed-61c0b8dc607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201855226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.201855226
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1444168546
Short name T750
Test name
Test status
Simulation time 1565077485 ps
CPU time 5.74 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 218048 kb
Host smart-e9c593e4-d73a-468b-8609-81a909700d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444168546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1444168546
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.449571445
Short name T279
Test name
Test status
Simulation time 199427103 ps
CPU time 2.35 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:51 PM PDT 24
Peak memory 208388 kb
Host smart-d32c1794-6d2a-4031-91eb-58cbe81091da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449571445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.449571445
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2128285112
Short name T606
Test name
Test status
Simulation time 706544172 ps
CPU time 4.96 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:50 PM PDT 24
Peak memory 208712 kb
Host smart-ad2be4fa-6621-46d1-9d7a-6eee9f45a024
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128285112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2128285112
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1062591737
Short name T633
Test name
Test status
Simulation time 19277217 ps
CPU time 1.79 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 206860 kb
Host smart-638a4d0d-76eb-4c41-9f27-b14d27f18aa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062591737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1062591737
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.645624351
Short name T789
Test name
Test status
Simulation time 76419955 ps
CPU time 3.14 seconds
Started Jul 27 05:40:58 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 206896 kb
Host smart-2e9a5259-657b-4eb3-a888-5af64e89a2d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645624351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.645624351
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1862296722
Short name T752
Test name
Test status
Simulation time 28862406 ps
CPU time 1.77 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 208640 kb
Host smart-6c73baf8-7e45-49d9-b0fb-d1f5fec60c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862296722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1862296722
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2705062955
Short name T817
Test name
Test status
Simulation time 167046235 ps
CPU time 4.74 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 207948 kb
Host smart-f7968f9f-ad92-4841-b5a6-64a903f43a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705062955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2705062955
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2817911686
Short name T900
Test name
Test status
Simulation time 1086575740 ps
CPU time 11.78 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 222320 kb
Host smart-00336e6d-dbaf-4355-ac4b-9a02953ed1d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817911686 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2817911686
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.873546287
Short name T894
Test name
Test status
Simulation time 470013020 ps
CPU time 4.9 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 210216 kb
Host smart-5584568a-7bbc-48e8-aeb2-2f66c73079f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873546287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.873546287
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.343707018
Short name T545
Test name
Test status
Simulation time 37971935 ps
CPU time 2.16 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 209768 kb
Host smart-cc562543-4d3c-4499-86e3-48fe605404f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343707018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.343707018
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1863108657
Short name T731
Test name
Test status
Simulation time 10114756 ps
CPU time 0.7 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:40:47 PM PDT 24
Peak memory 205844 kb
Host smart-af6069a7-a7ea-4e32-887c-c6fd6b2de032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863108657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1863108657
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4131138397
Short name T240
Test name
Test status
Simulation time 182637686 ps
CPU time 3.75 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 214128 kb
Host smart-d708d787-b0d1-4fdd-95dd-78c0909794f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131138397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4131138397
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2979444018
Short name T737
Test name
Test status
Simulation time 1493152531 ps
CPU time 4.7 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:40:51 PM PDT 24
Peak memory 222472 kb
Host smart-c2703e78-88ba-4ca4-9653-ee95deea1da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979444018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2979444018
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.576288832
Short name T307
Test name
Test status
Simulation time 56871249 ps
CPU time 1.72 seconds
Started Jul 27 05:40:54 PM PDT 24
Finished Jul 27 05:40:56 PM PDT 24
Peak memory 214164 kb
Host smart-9d9e4e07-9007-42be-b7bb-37f7c9578011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576288832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.576288832
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3526164247
Short name T86
Test name
Test status
Simulation time 459079771 ps
CPU time 4.71 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:53 PM PDT 24
Peak memory 220552 kb
Host smart-daebbdea-e481-4347-a025-c42ce65b4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526164247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3526164247
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1692864686
Short name T784
Test name
Test status
Simulation time 618557943 ps
CPU time 12.15 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 222216 kb
Host smart-06d937e7-8eff-47c3-a821-4798c12d6fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692864686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1692864686
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.402257910
Short name T792
Test name
Test status
Simulation time 36162861 ps
CPU time 2.54 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:40:58 PM PDT 24
Peak memory 219656 kb
Host smart-92839fe6-6e31-49fe-a9a6-00283588ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402257910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.402257910
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3174758816
Short name T98
Test name
Test status
Simulation time 259845146 ps
CPU time 7.31 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 208280 kb
Host smart-f8c5bfa6-47ad-4eef-a434-f549e8992ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174758816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3174758816
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.255351851
Short name T311
Test name
Test status
Simulation time 136989252 ps
CPU time 2.66 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 208372 kb
Host smart-c505cb0c-e50b-4761-85fb-48008d5b11d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255351851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.255351851
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.836928869
Short name T462
Test name
Test status
Simulation time 75330792 ps
CPU time 3.2 seconds
Started Jul 27 05:40:44 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 208016 kb
Host smart-5a0dbf2c-a8de-485d-a0c6-14a6471c59de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836928869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.836928869
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.451503869
Short name T628
Test name
Test status
Simulation time 65753888 ps
CPU time 3.28 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 208396 kb
Host smart-45fe2a6c-68af-418c-91e8-a5f8b44e6bb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451503869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.451503869
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1719768078
Short name T893
Test name
Test status
Simulation time 1985408784 ps
CPU time 4.92 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 206708 kb
Host smart-2061bc02-12db-4088-9264-957060c78e73
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719768078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1719768078
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.542202948
Short name T840
Test name
Test status
Simulation time 66753206 ps
CPU time 3.21 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 208408 kb
Host smart-6924f256-74ab-41b7-a94d-028ef2c9bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542202948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.542202948
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.754530809
Short name T126
Test name
Test status
Simulation time 3770650341 ps
CPU time 20.84 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 222412 kb
Host smart-ce57404b-e8f1-4d95-88c3-d712e99ccd25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754530809 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.754530809
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.969639422
Short name T568
Test name
Test status
Simulation time 82759664 ps
CPU time 4.02 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:52 PM PDT 24
Peak memory 208816 kb
Host smart-3df9db51-69e7-4431-8459-bb61d6bfb47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969639422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.969639422
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4148441223
Short name T415
Test name
Test status
Simulation time 82325412 ps
CPU time 0.76 seconds
Started Jul 27 05:40:54 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 205884 kb
Host smart-7cb09a7f-2904-4b8a-a5be-0cff422cc56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148441223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4148441223
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1461257729
Short name T742
Test name
Test status
Simulation time 106084037 ps
CPU time 2.97 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 215604 kb
Host smart-b8080073-3d95-4b7e-bd65-9173f6b0be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461257729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1461257729
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2578606930
Short name T745
Test name
Test status
Simulation time 73300352 ps
CPU time 3.58 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 214132 kb
Host smart-711f42ca-15e5-4905-bff2-6c92dfa37e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578606930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2578606930
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3154707304
Short name T679
Test name
Test status
Simulation time 38706086 ps
CPU time 2.63 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 211376 kb
Host smart-b2b25f11-4810-4a8f-be4e-22ea88cbbd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154707304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3154707304
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3324085399
Short name T210
Test name
Test status
Simulation time 311467395 ps
CPU time 2.55 seconds
Started Jul 27 05:40:45 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 214996 kb
Host smart-cf6c611c-7e3c-43e2-bb1a-8141c967cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324085399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3324085399
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4241194664
Short name T429
Test name
Test status
Simulation time 341998107 ps
CPU time 4.64 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:40:50 PM PDT 24
Peak memory 209268 kb
Host smart-d6afc10a-ed00-41a6-8dff-ebfd6ad1d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241194664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4241194664
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1823536892
Short name T790
Test name
Test status
Simulation time 118307769 ps
CPU time 5.28 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:53 PM PDT 24
Peak memory 206720 kb
Host smart-f858a156-e67d-41e1-a4a0-d935ba2e5065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823536892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1823536892
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4046443342
Short name T464
Test name
Test status
Simulation time 782962703 ps
CPU time 17.29 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:19 PM PDT 24
Peak memory 208140 kb
Host smart-d026b077-8820-4f76-9335-3e952a68b034
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046443342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4046443342
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.147179792
Short name T825
Test name
Test status
Simulation time 322038555 ps
CPU time 8.58 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 208488 kb
Host smart-2ac723d5-9d55-4e9b-8733-ee14b1c5cf19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147179792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.147179792
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1349724732
Short name T385
Test name
Test status
Simulation time 235780113 ps
CPU time 2.45 seconds
Started Jul 27 05:40:47 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 208884 kb
Host smart-13a112b6-6bcd-4018-8421-9232d0e2cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349724732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1349724732
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.163219620
Short name T648
Test name
Test status
Simulation time 92662080 ps
CPU time 2.23 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:50 PM PDT 24
Peak memory 207768 kb
Host smart-401edf46-ec81-4f5f-b4d3-8bf9d3df7297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163219620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.163219620
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2164378975
Short name T52
Test name
Test status
Simulation time 842734066 ps
CPU time 27.74 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 217048 kb
Host smart-88ab8e56-81c3-4726-8b82-a85cc357da9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164378975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2164378975
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2794049001
Short name T526
Test name
Test status
Simulation time 746799309 ps
CPU time 7.76 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 207280 kb
Host smart-64377841-df00-404c-b9ca-cc702903db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794049001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2794049001
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1352846353
Short name T707
Test name
Test status
Simulation time 88529927 ps
CPU time 3.4 seconds
Started Jul 27 05:40:48 PM PDT 24
Finished Jul 27 05:40:51 PM PDT 24
Peak memory 210372 kb
Host smart-1ae964e3-9613-4404-a7af-6d292525a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352846353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1352846353
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1336460096
Short name T569
Test name
Test status
Simulation time 9683522 ps
CPU time 0.72 seconds
Started Jul 27 05:40:58 PM PDT 24
Finished Jul 27 05:40:59 PM PDT 24
Peak memory 205844 kb
Host smart-4acbb2b1-4af9-4eeb-a441-263e45cd149f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336460096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1336460096
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2025595899
Short name T877
Test name
Test status
Simulation time 136901507 ps
CPU time 2.75 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 215200 kb
Host smart-5149debe-a5e9-43a0-9974-15f63ac2a99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025595899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2025595899
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.59058848
Short name T468
Test name
Test status
Simulation time 42511753 ps
CPU time 2.07 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 214160 kb
Host smart-e07e0fbe-749a-433e-a943-3ca003174c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59058848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.59058848
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2009045724
Short name T88
Test name
Test status
Simulation time 520791072 ps
CPU time 6.62 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 214132 kb
Host smart-06d5e42c-f73e-44d5-914e-521a56ecd7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009045724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2009045724
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3131792716
Short name T232
Test name
Test status
Simulation time 56428754 ps
CPU time 2.26 seconds
Started Jul 27 05:40:58 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 214060 kb
Host smart-492a846c-1b2a-4b47-823e-571a02bef55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131792716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3131792716
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3662329898
Short name T45
Test name
Test status
Simulation time 73150274 ps
CPU time 3.6 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 214228 kb
Host smart-b934fbf2-5483-47ec-badd-e3ef49dabf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662329898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3662329898
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1216801201
Short name T227
Test name
Test status
Simulation time 75847239 ps
CPU time 3.79 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 207624 kb
Host smart-7ee15c3f-0047-4759-ab49-b439e975d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216801201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1216801201
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3055708727
Short name T706
Test name
Test status
Simulation time 84973133 ps
CPU time 3.62 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:40:56 PM PDT 24
Peak memory 208532 kb
Host smart-c25afe88-7177-47a9-9e9a-005d37a8ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055708727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3055708727
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1746266894
Short name T332
Test name
Test status
Simulation time 4168298485 ps
CPU time 14 seconds
Started Jul 27 05:40:54 PM PDT 24
Finished Jul 27 05:41:08 PM PDT 24
Peak memory 208856 kb
Host smart-e4e59957-09ef-4bba-8b0a-3bd61b4a0ac4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746266894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1746266894
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4220204492
Short name T256
Test name
Test status
Simulation time 100155150 ps
CPU time 3.45 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 206820 kb
Host smart-3a01faed-faf4-4b16-aa3d-a3d9a0552c1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220204492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4220204492
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.340902043
Short name T863
Test name
Test status
Simulation time 45238426 ps
CPU time 2.53 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 208388 kb
Host smart-f2cf21a9-e303-43fe-9193-853ef524f9be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340902043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.340902043
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2734635820
Short name T593
Test name
Test status
Simulation time 120098837 ps
CPU time 3.01 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 210188 kb
Host smart-3618ddce-b273-463f-bef4-ad06587186e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734635820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2734635820
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1771603011
Short name T567
Test name
Test status
Simulation time 338850906 ps
CPU time 7.15 seconds
Started Jul 27 05:40:51 PM PDT 24
Finished Jul 27 05:40:58 PM PDT 24
Peak memory 208364 kb
Host smart-fc74cd38-f616-43dd-9f8b-a62ed1cebafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771603011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1771603011
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3860743907
Short name T867
Test name
Test status
Simulation time 313275339 ps
CPU time 12.73 seconds
Started Jul 27 05:40:58 PM PDT 24
Finished Jul 27 05:41:11 PM PDT 24
Peak memory 220244 kb
Host smart-cb57d78c-8151-46da-a8e4-3beeebb6c085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860743907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3860743907
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2375963354
Short name T349
Test name
Test status
Simulation time 4088313022 ps
CPU time 24.45 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 221300 kb
Host smart-9b491a9c-0153-4372-9ac7-4e4c0aa1cf6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375963354 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2375963354
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3923885644
Short name T488
Test name
Test status
Simulation time 413624641 ps
CPU time 13.26 seconds
Started Jul 27 05:40:52 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 218216 kb
Host smart-9c1b10a1-0499-4180-8d95-2e72072b2e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923885644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3923885644
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2797613391
Short name T787
Test name
Test status
Simulation time 61887039 ps
CPU time 2.38 seconds
Started Jul 27 05:40:54 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 210076 kb
Host smart-1c57001b-8660-4a5d-9ac1-9d21f707a164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797613391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2797613391
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2831139907
Short name T800
Test name
Test status
Simulation time 14042888 ps
CPU time 0.76 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 205836 kb
Host smart-ab09fdb6-fe1c-4243-9512-44bef989887a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831139907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2831139907
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2138175906
Short name T76
Test name
Test status
Simulation time 49106803 ps
CPU time 2.02 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 207476 kb
Host smart-f4e70f51-6d9f-4582-9d13-c64688a333bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138175906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2138175906
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.981323359
Short name T611
Test name
Test status
Simulation time 36488050 ps
CPU time 2.47 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 221156 kb
Host smart-6c5c4433-f5d4-4bec-bf5c-a7b947985b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981323359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.981323359
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1272117770
Short name T813
Test name
Test status
Simulation time 78399412 ps
CPU time 4.14 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 209832 kb
Host smart-39b157ff-de25-49ae-a57d-8d4c0bb12d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272117770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1272117770
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1302590523
Short name T469
Test name
Test status
Simulation time 3513588150 ps
CPU time 62.62 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:42:03 PM PDT 24
Peak memory 209008 kb
Host smart-406c93f2-df8f-4ff6-8710-f05fda0be7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302590523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1302590523
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1604701737
Short name T228
Test name
Test status
Simulation time 99654428 ps
CPU time 2.59 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 206552 kb
Host smart-e4d920e9-4e6b-4811-83cf-5feca194cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604701737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1604701737
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.948243672
Short name T904
Test name
Test status
Simulation time 79174604 ps
CPU time 2.46 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 206680 kb
Host smart-afc32495-de46-449d-830c-c8152edaa9c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948243672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.948243672
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.243060800
Short name T869
Test name
Test status
Simulation time 215831782 ps
CPU time 3.34 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:01 PM PDT 24
Peak memory 207340 kb
Host smart-95c6deb4-9991-4a5e-ae97-0e9e83e826eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243060800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.243060800
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2546338825
Short name T132
Test name
Test status
Simulation time 70845661 ps
CPU time 3.3 seconds
Started Jul 27 05:40:56 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 208636 kb
Host smart-d687d063-afec-4cec-ae24-18a5ca479b89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546338825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2546338825
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2062718108
Short name T467
Test name
Test status
Simulation time 38025860 ps
CPU time 1.66 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 207424 kb
Host smart-8294a5c6-9897-4bf4-9b79-59d95d59bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062718108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2062718108
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3016394182
Short name T518
Test name
Test status
Simulation time 547505049 ps
CPU time 3.84 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 208276 kb
Host smart-b8485ea6-cf95-436f-b063-e04c3a45b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016394182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3016394182
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3334111196
Short name T896
Test name
Test status
Simulation time 1422673949 ps
CPU time 11.04 seconds
Started Jul 27 05:40:59 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 215736 kb
Host smart-7875a846-8c0a-4f1c-8fd1-e9305b19d936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334111196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3334111196
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2928538541
Short name T747
Test name
Test status
Simulation time 216680411 ps
CPU time 8.63 seconds
Started Jul 27 05:41:05 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 208480 kb
Host smart-e84a46cb-aabe-4e4e-8b95-d58453c1d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928538541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2928538541
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1685161648
Short name T376
Test name
Test status
Simulation time 37847071 ps
CPU time 2.08 seconds
Started Jul 27 05:40:53 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 209492 kb
Host smart-bcb4ed83-5747-4ad2-9ca6-2e6b28a91e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685161648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1685161648
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.723685328
Short name T640
Test name
Test status
Simulation time 50629609 ps
CPU time 0.81 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:02 PM PDT 24
Peak memory 205872 kb
Host smart-aed1c5f2-e2b1-4104-a5b5-79e9be7915f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723685328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.723685328
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.306240114
Short name T604
Test name
Test status
Simulation time 91852841 ps
CPU time 4.73 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:23 PM PDT 24
Peak memory 222524 kb
Host smart-9747da65-4779-4be7-8d58-8e759b7ed3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306240114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.306240114
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2814404905
Short name T874
Test name
Test status
Simulation time 505063264 ps
CPU time 4.87 seconds
Started Jul 27 05:41:12 PM PDT 24
Finished Jul 27 05:41:17 PM PDT 24
Peak memory 218040 kb
Host smart-dd2d5a37-0931-4542-adfd-2742c9896f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814404905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2814404905
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1953155727
Short name T621
Test name
Test status
Simulation time 177357138 ps
CPU time 3.65 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 214120 kb
Host smart-4de2fa89-97c9-4915-a87e-a808dc5b02c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953155727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1953155727
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.165579611
Short name T697
Test name
Test status
Simulation time 221020885 ps
CPU time 2.53 seconds
Started Jul 27 05:41:13 PM PDT 24
Finished Jul 27 05:41:16 PM PDT 24
Peak memory 214052 kb
Host smart-431d98a8-c885-46cb-95ce-db2b0861a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165579611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.165579611
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.314310341
Short name T876
Test name
Test status
Simulation time 257924663 ps
CPU time 3.04 seconds
Started Jul 27 05:41:07 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 214264 kb
Host smart-eba40f49-83e2-4e41-94b1-c5a388ca56ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314310341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.314310341
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2350415379
Short name T753
Test name
Test status
Simulation time 764484030 ps
CPU time 13.92 seconds
Started Jul 27 05:41:12 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 218084 kb
Host smart-d79b994b-e498-4215-a7a3-bd82087c6ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350415379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2350415379
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2984843059
Short name T184
Test name
Test status
Simulation time 434841181 ps
CPU time 3.71 seconds
Started Jul 27 05:40:55 PM PDT 24
Finished Jul 27 05:40:59 PM PDT 24
Peak memory 208524 kb
Host smart-4710815a-2be4-459a-937c-f83083bf4be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984843059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2984843059
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1810908044
Short name T501
Test name
Test status
Simulation time 407445437 ps
CPU time 5.71 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 208632 kb
Host smart-13c1d5e8-e70f-4702-b053-f6aa40593d62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810908044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1810908044
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2330066801
Short name T856
Test name
Test status
Simulation time 312433274 ps
CPU time 2.52 seconds
Started Jul 27 05:40:57 PM PDT 24
Finished Jul 27 05:41:00 PM PDT 24
Peak memory 206740 kb
Host smart-8ad1a529-e53e-48ca-8422-c4fa45030d68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330066801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2330066801
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3380237503
Short name T503
Test name
Test status
Simulation time 474525453 ps
CPU time 12.4 seconds
Started Jul 27 05:41:00 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 208692 kb
Host smart-20fd2318-14c1-402e-b640-c0a4ef506c04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380237503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3380237503
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4136833570
Short name T536
Test name
Test status
Simulation time 110443078 ps
CPU time 1.92 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 209644 kb
Host smart-e6d099ec-7876-4336-9021-37ce603c4223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136833570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4136833570
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2285725259
Short name T864
Test name
Test status
Simulation time 473037185 ps
CPU time 3.25 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 208504 kb
Host smart-ae01052e-5c15-46c7-a87b-6cb4e129a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285725259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2285725259
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.888260233
Short name T127
Test name
Test status
Simulation time 2903129482 ps
CPU time 23.13 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 222352 kb
Host smart-8f0e99fd-593c-473f-b827-500acda9c39e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888260233 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.888260233
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1431454437
Short name T712
Test name
Test status
Simulation time 38436695 ps
CPU time 2.78 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 218116 kb
Host smart-60ae1f0f-ec15-4762-8041-e892a28e839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431454437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1431454437
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3591524963
Short name T743
Test name
Test status
Simulation time 127964105 ps
CPU time 1.6 seconds
Started Jul 27 05:41:07 PM PDT 24
Finished Jul 27 05:41:09 PM PDT 24
Peak memory 210076 kb
Host smart-2fcb412b-dadc-4537-bd45-8e8bb90afb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591524963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3591524963
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.137640494
Short name T470
Test name
Test status
Simulation time 14268246 ps
CPU time 0.96 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:09 PM PDT 24
Peak memory 205864 kb
Host smart-bd9b86b9-6da6-4c20-b12e-e60cb1466c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137640494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.137640494
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3925274496
Short name T117
Test name
Test status
Simulation time 1179362958 ps
CPU time 30.79 seconds
Started Jul 27 05:40:11 PM PDT 24
Finished Jul 27 05:40:41 PM PDT 24
Peak memory 214192 kb
Host smart-e0a84d2e-1af2-46bb-963f-5293ef698506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925274496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3925274496
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.99647755
Short name T20
Test name
Test status
Simulation time 85241378 ps
CPU time 3.34 seconds
Started Jul 27 05:40:11 PM PDT 24
Finished Jul 27 05:40:14 PM PDT 24
Peak memory 219472 kb
Host smart-34964c8e-f923-4e3b-a78d-55065c7ea3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99647755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.99647755
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2588940969
Short name T422
Test name
Test status
Simulation time 55744165 ps
CPU time 1.76 seconds
Started Jul 27 05:40:13 PM PDT 24
Finished Jul 27 05:40:15 PM PDT 24
Peak memory 206980 kb
Host smart-71ee9126-8a79-45aa-b5eb-703bdc782c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588940969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2588940969
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.34423360
Short name T781
Test name
Test status
Simulation time 408674825 ps
CPU time 8.88 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 209564 kb
Host smart-daab3e4d-33d8-419a-8a45-391c680aa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34423360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.34423360
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.364320118
Short name T292
Test name
Test status
Simulation time 260777729 ps
CPU time 2.81 seconds
Started Jul 27 05:40:10 PM PDT 24
Finished Jul 27 05:40:13 PM PDT 24
Peak memory 214100 kb
Host smart-94e0f13f-b1ab-4e22-a2a9-6ac5ec9f533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364320118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.364320118
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4101768192
Short name T763
Test name
Test status
Simulation time 55801071 ps
CPU time 2.56 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:17 PM PDT 24
Peak memory 214116 kb
Host smart-e43affc0-a79d-4dd6-9845-534b3a21c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101768192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4101768192
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2756999882
Short name T420
Test name
Test status
Simulation time 54617916 ps
CPU time 3.4 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 209892 kb
Host smart-d089b823-e9f5-41d4-b0a4-ade9be96c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756999882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2756999882
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.46762554
Short name T42
Test name
Test status
Simulation time 441966707 ps
CPU time 8.83 seconds
Started Jul 27 05:40:12 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 230588 kb
Host smart-e28019b1-170e-40d7-b5ae-b605bba83547
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46762554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.46762554
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2541029444
Short name T686
Test name
Test status
Simulation time 230418414 ps
CPU time 3.18 seconds
Started Jul 27 05:40:08 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 208268 kb
Host smart-ad48274e-de58-4523-b72c-3a2c40c7ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541029444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2541029444
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3680632881
Short name T357
Test name
Test status
Simulation time 143286537 ps
CPU time 2.67 seconds
Started Jul 27 05:40:10 PM PDT 24
Finished Jul 27 05:40:13 PM PDT 24
Peak memory 206676 kb
Host smart-34187c43-4e01-43be-a1c1-01c5bb3f348c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680632881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3680632881
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3286193845
Short name T603
Test name
Test status
Simulation time 235372418 ps
CPU time 3.41 seconds
Started Jul 27 05:40:11 PM PDT 24
Finished Jul 27 05:40:14 PM PDT 24
Peak memory 206752 kb
Host smart-a9c5f198-6ed9-43c8-94a0-c4d2b8f679d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286193845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3286193845
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.341014461
Short name T879
Test name
Test status
Simulation time 1860334806 ps
CPU time 4.98 seconds
Started Jul 27 05:40:20 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 208828 kb
Host smart-000a38de-34c1-4f93-9dd3-e5719e61e5a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341014461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.341014461
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2382092811
Short name T295
Test name
Test status
Simulation time 1807475902 ps
CPU time 12.95 seconds
Started Jul 27 05:40:10 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 214080 kb
Host smart-5f0bde64-6800-452d-98cf-74a4d6e8330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382092811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2382092811
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.90686349
Short name T739
Test name
Test status
Simulation time 118125544 ps
CPU time 2.36 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:09 PM PDT 24
Peak memory 206404 kb
Host smart-67698136-b976-4fe3-a299-5e57699084ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90686349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.90686349
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3180758123
Short name T253
Test name
Test status
Simulation time 207250301 ps
CPU time 9.45 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:17 PM PDT 24
Peak memory 221216 kb
Host smart-82011df3-80bc-4896-b732-a3c382dd6268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180758123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3180758123
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1784391608
Short name T865
Test name
Test status
Simulation time 621767707 ps
CPU time 17.91 seconds
Started Jul 27 05:40:07 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 220504 kb
Host smart-bff8291e-0c93-436c-9597-86862c2360e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784391608 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1784391608
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.4169185027
Short name T610
Test name
Test status
Simulation time 626221889 ps
CPU time 6.93 seconds
Started Jul 27 05:40:06 PM PDT 24
Finished Jul 27 05:40:13 PM PDT 24
Peak memory 214124 kb
Host smart-ef0f943f-a188-44e5-af01-e2dfd0cdc6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169185027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4169185027
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1351712175
Short name T165
Test name
Test status
Simulation time 116238961 ps
CPU time 3.06 seconds
Started Jul 27 05:40:04 PM PDT 24
Finished Jul 27 05:40:07 PM PDT 24
Peak memory 210068 kb
Host smart-4ce20502-d165-44c8-8be9-5b7d35d6d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351712175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1351712175
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2155094577
Short name T509
Test name
Test status
Simulation time 46155019 ps
CPU time 0.88 seconds
Started Jul 27 05:41:13 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 205856 kb
Host smart-27fd472a-ca4a-4f5e-bf5a-b2492559b789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155094577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2155094577
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2577309252
Short name T401
Test name
Test status
Simulation time 48087871 ps
CPU time 3.43 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:08 PM PDT 24
Peak memory 214840 kb
Host smart-1c9ed141-9dc0-451d-8865-4deb90dde992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577309252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2577309252
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2213722802
Short name T709
Test name
Test status
Simulation time 283414857 ps
CPU time 3.87 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 218164 kb
Host smart-a47b87be-2326-40cc-bb78-f2c077cf7688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213722802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2213722802
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2817685715
Short name T839
Test name
Test status
Simulation time 87729791 ps
CPU time 4.05 seconds
Started Jul 27 05:41:16 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 222136 kb
Host smart-823ac80d-dca1-4127-be07-da770800567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817685715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2817685715
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1759493011
Short name T819
Test name
Test status
Simulation time 113955740 ps
CPU time 4.97 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:08 PM PDT 24
Peak memory 214152 kb
Host smart-211136a3-2e8d-4695-808e-79fb08bc3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759493011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1759493011
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2799837959
Short name T500
Test name
Test status
Simulation time 263620647 ps
CPU time 4.98 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:09 PM PDT 24
Peak memory 209920 kb
Host smart-0adba18d-1a8e-4d7a-9531-b991f569e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799837959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2799837959
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.867420041
Short name T318
Test name
Test status
Simulation time 122825233 ps
CPU time 1.95 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 207488 kb
Host smart-03a9df44-17ba-4a4e-acd5-de631d20d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867420041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.867420041
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2260883286
Short name T16
Test name
Test status
Simulation time 94134699 ps
CPU time 2.69 seconds
Started Jul 27 05:41:03 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 207940 kb
Host smart-74a740de-1325-42b2-8f5e-a561bbfcd553
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260883286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2260883286
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3335102102
Short name T797
Test name
Test status
Simulation time 29898799 ps
CPU time 1.92 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:03 PM PDT 24
Peak memory 206764 kb
Host smart-6c28cf58-1e0b-41fb-95e0-07db3ee52655
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335102102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3335102102
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3840822100
Short name T437
Test name
Test status
Simulation time 69668854 ps
CPU time 3.12 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 207052 kb
Host smart-72357987-6474-426d-8818-87824ea2e068
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840822100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3840822100
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2993560979
Short name T858
Test name
Test status
Simulation time 68658197 ps
CPU time 3.26 seconds
Started Jul 27 05:41:03 PM PDT 24
Finished Jul 27 05:41:07 PM PDT 24
Peak memory 214068 kb
Host smart-d81aefb4-24bb-4c8c-8420-0ad083a2ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993560979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2993560979
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.109518370
Short name T760
Test name
Test status
Simulation time 352091572 ps
CPU time 5.7 seconds
Started Jul 27 05:41:02 PM PDT 24
Finished Jul 27 05:41:08 PM PDT 24
Peak memory 206844 kb
Host smart-59726896-b7c9-434a-b291-7efb4ea2fcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109518370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.109518370
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4008960038
Short name T345
Test name
Test status
Simulation time 445001270 ps
CPU time 14.49 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 208324 kb
Host smart-95b7ba64-0502-4dab-90e1-13dd374eee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008960038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4008960038
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.687200279
Short name T373
Test name
Test status
Simulation time 203011457 ps
CPU time 4.08 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 210316 kb
Host smart-9ed605f7-3b3c-4bc8-9e21-eab29dff8160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687200279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.687200279
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3455493246
Short name T829
Test name
Test status
Simulation time 15660582 ps
CPU time 0.77 seconds
Started Jul 27 05:41:15 PM PDT 24
Finished Jul 27 05:41:16 PM PDT 24
Peak memory 205904 kb
Host smart-c66fa77c-df97-409c-8c3c-372a27dbe59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455493246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3455493246
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.428351553
Short name T270
Test name
Test status
Simulation time 51507509 ps
CPU time 3.55 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 214052 kb
Host smart-70b6a6d2-a270-4a15-8d69-0db00d615146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428351553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.428351553
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.477814675
Short name T528
Test name
Test status
Simulation time 210650888 ps
CPU time 3.04 seconds
Started Jul 27 05:41:07 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 209136 kb
Host smart-ebcb91ea-15ab-430d-a7b4-658baff0612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477814675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.477814675
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4293671672
Short name T681
Test name
Test status
Simulation time 114124656 ps
CPU time 2.92 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 218000 kb
Host smart-6e44c54c-063a-4589-b43a-fd3c4db9adf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293671672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4293671672
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.6473766
Short name T235
Test name
Test status
Simulation time 136035829 ps
CPU time 2.44 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 214040 kb
Host smart-4c17b7b0-cfac-4419-ac70-b3f4ac531da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6473766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.6473766
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3658874533
Short name T596
Test name
Test status
Simulation time 108039830 ps
CPU time 4.17 seconds
Started Jul 27 05:41:06 PM PDT 24
Finished Jul 27 05:41:11 PM PDT 24
Peak memory 220432 kb
Host smart-8c9231bc-f56c-4ffe-a4db-4574b8ffc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658874533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3658874533
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.688067585
Short name T341
Test name
Test status
Simulation time 51044016 ps
CPU time 3.23 seconds
Started Jul 27 05:41:01 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 214208 kb
Host smart-4c08c0ca-60ab-483c-beaa-ee694d2c3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688067585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.688067585
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3965227243
Short name T182
Test name
Test status
Simulation time 213325495 ps
CPU time 3.12 seconds
Started Jul 27 05:41:04 PM PDT 24
Finished Jul 27 05:41:07 PM PDT 24
Peak memory 208084 kb
Host smart-17bbb0e5-d3e0-4f7b-9dfb-98bcab538538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965227243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3965227243
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1398004962
Short name T730
Test name
Test status
Simulation time 1755352586 ps
CPU time 40.4 seconds
Started Jul 27 05:41:12 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 208900 kb
Host smart-e80172a5-6378-4290-a3a5-3a9f00357c2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398004962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1398004962
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3972031754
Short name T444
Test name
Test status
Simulation time 302380165 ps
CPU time 3.56 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 206808 kb
Host smart-903c8f73-fca3-4585-8769-8d2ba690e9ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972031754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3972031754
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.923561535
Short name T897
Test name
Test status
Simulation time 132299395 ps
CPU time 2.63 seconds
Started Jul 27 05:41:03 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 208392 kb
Host smart-a1676402-1cc9-4254-b8dd-8159c6695efc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923561535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.923561535
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1791134978
Short name T808
Test name
Test status
Simulation time 47239183 ps
CPU time 1.88 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:10 PM PDT 24
Peak memory 208940 kb
Host smart-8489e025-d943-438b-9960-de9d74867fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791134978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1791134978
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3361754734
Short name T903
Test name
Test status
Simulation time 14852771 ps
CPU time 0.81 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:11 PM PDT 24
Peak memory 205912 kb
Host smart-bea4b5f4-3ab0-467e-9b6e-fa07a8aafdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361754734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3361754734
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2789688655
Short name T407
Test name
Test status
Simulation time 312760254 ps
CPU time 4.77 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 214900 kb
Host smart-4b16d548-af33-4a8b-b68b-b7ced0b91e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789688655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2789688655
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1443491543
Short name T21
Test name
Test status
Simulation time 65840515 ps
CPU time 3.56 seconds
Started Jul 27 05:41:15 PM PDT 24
Finished Jul 27 05:41:19 PM PDT 24
Peak memory 209900 kb
Host smart-2a25f03c-32a1-4be2-b217-d9db117e61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443491543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1443491543
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1710515044
Short name T693
Test name
Test status
Simulation time 1184425511 ps
CPU time 9.01 seconds
Started Jul 27 05:41:15 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 214020 kb
Host smart-dc8a8971-af0b-4fc1-a4dd-6eddd144eaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710515044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1710515044
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.83091636
Short name T338
Test name
Test status
Simulation time 47563100 ps
CPU time 2.94 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 214112 kb
Host smart-29f87cd7-ee34-46d5-90c2-b625877a0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83091636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.83091636
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_random.1370997046
Short name T734
Test name
Test status
Simulation time 761939398 ps
CPU time 9.08 seconds
Started Jul 27 05:41:16 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 208404 kb
Host smart-297090ce-a9f0-4ac6-8b24-cbe034707384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370997046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1370997046
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.993939231
Short name T247
Test name
Test status
Simulation time 743259023 ps
CPU time 21.21 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 208860 kb
Host smart-4243fc59-1a07-4753-b10f-2dc6351b227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993939231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.993939231
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2294040787
Short name T625
Test name
Test status
Simulation time 39927259 ps
CPU time 1.72 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 206732 kb
Host smart-0f57bebd-2483-4861-8303-d0594728c321
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294040787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2294040787
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2004618536
Short name T861
Test name
Test status
Simulation time 71030045 ps
CPU time 2.61 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 208588 kb
Host smart-e8ef316e-ce27-4a1d-81fa-679840d6b0df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004618536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2004618536
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.759611046
Short name T583
Test name
Test status
Simulation time 328568357 ps
CPU time 4.23 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:15 PM PDT 24
Peak memory 208420 kb
Host smart-6d69d9b8-dc4a-4f22-bf66-04268600a443
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759611046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.759611046
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1873249482
Short name T812
Test name
Test status
Simulation time 513604929 ps
CPU time 17.37 seconds
Started Jul 27 05:41:15 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 220080 kb
Host smart-e9a7c38c-41e5-4c83-8b15-958b12741db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873249482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1873249482
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1699872442
Short name T821
Test name
Test status
Simulation time 294802035 ps
CPU time 3.66 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 207640 kb
Host smart-684ba4dc-ecd9-4751-bb1f-6be4fd5d790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699872442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1699872442
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3378736716
Short name T777
Test name
Test status
Simulation time 2461518108 ps
CPU time 29.01 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 222408 kb
Host smart-590c6d8d-d6ab-42c0-95eb-caea5d5eeb0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378736716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3378736716
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2789528512
Short name T684
Test name
Test status
Simulation time 71169289 ps
CPU time 2.67 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 208096 kb
Host smart-912de1cb-8d75-483a-8388-f82ff115505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789528512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2789528512
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.399094741
Short name T490
Test name
Test status
Simulation time 129837380 ps
CPU time 4.23 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 210192 kb
Host smart-20d6e866-6446-46a9-a54f-6cb9c33f92e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399094741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.399094741
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2336541907
Short name T508
Test name
Test status
Simulation time 44346370 ps
CPU time 0.76 seconds
Started Jul 27 05:41:06 PM PDT 24
Finished Jul 27 05:41:07 PM PDT 24
Peak memory 205868 kb
Host smart-6430f721-5b63-4c1f-8dc8-435ccd1c6155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336541907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2336541907
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1350313277
Short name T37
Test name
Test status
Simulation time 82777083 ps
CPU time 1.97 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 208488 kb
Host smart-924ffc9e-8723-42a0-83f3-eadb8b0c7801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350313277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1350313277
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.892534450
Short name T525
Test name
Test status
Simulation time 259395526 ps
CPU time 2.34 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:11 PM PDT 24
Peak memory 207624 kb
Host smart-947b7bdd-45c4-4364-acba-9da8f0369200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892534450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.892534450
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3348003268
Short name T309
Test name
Test status
Simulation time 114026314 ps
CPU time 2.55 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 214116 kb
Host smart-6f8e1982-9006-4a79-939c-369569137128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348003268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3348003268
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3972367145
Short name T601
Test name
Test status
Simulation time 123092585 ps
CPU time 2.55 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 214852 kb
Host smart-c6f128df-1e14-4a26-a824-44dc1241abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972367145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3972367145
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.393207173
Short name T140
Test name
Test status
Simulation time 131720156 ps
CPU time 3.84 seconds
Started Jul 27 05:41:13 PM PDT 24
Finished Jul 27 05:41:17 PM PDT 24
Peak memory 214140 kb
Host smart-510c9f09-7b90-40e8-b5f0-ee11ceb75c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393207173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.393207173
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2193203298
Short name T294
Test name
Test status
Simulation time 149013119 ps
CPU time 2.61 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 214028 kb
Host smart-aaedcc56-729a-4b0c-834a-daee541a667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193203298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2193203298
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3191177038
Short name T419
Test name
Test status
Simulation time 63454179 ps
CPU time 2.41 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 207024 kb
Host smart-bc85c7e3-449e-433e-ae9c-5bb024959f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191177038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3191177038
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1442779425
Short name T432
Test name
Test status
Simulation time 121136086 ps
CPU time 4 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 206844 kb
Host smart-3a1547c4-ab7c-4ecb-a99f-f5e3552f0a44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442779425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1442779425
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.677346982
Short name T281
Test name
Test status
Simulation time 35951694 ps
CPU time 2.43 seconds
Started Jul 27 05:41:11 PM PDT 24
Finished Jul 27 05:41:14 PM PDT 24
Peak memory 207260 kb
Host smart-06e51db0-45b2-4d38-9e41-d13623b52e7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677346982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.677346982
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1015885361
Short name T533
Test name
Test status
Simulation time 72512353 ps
CPU time 1.8 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:20 PM PDT 24
Peak memory 206792 kb
Host smart-8cffcb18-0cff-4421-a24c-1032c8621a82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015885361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1015885361
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3437072434
Short name T683
Test name
Test status
Simulation time 71981302 ps
CPU time 3.19 seconds
Started Jul 27 05:41:14 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 214104 kb
Host smart-768a39b1-e446-41ee-a51a-0ecc5ac2f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437072434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3437072434
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2334254733
Short name T557
Test name
Test status
Simulation time 377730286 ps
CPU time 2.72 seconds
Started Jul 27 05:41:13 PM PDT 24
Finished Jul 27 05:41:16 PM PDT 24
Peak memory 206700 kb
Host smart-e12d109a-d8a4-48a8-afe2-5b5ed1c1cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334254733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2334254733
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3603142021
Short name T356
Test name
Test status
Simulation time 6391727486 ps
CPU time 44 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 216900 kb
Host smart-753a0d13-81a5-4c9d-8f86-1b5301d627e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603142021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3603142021
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.702894013
Short name T375
Test name
Test status
Simulation time 216762409 ps
CPU time 2.46 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:26 PM PDT 24
Peak memory 209920 kb
Host smart-afca626d-72f8-4274-bb4f-2db0ce1bc50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702894013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.702894013
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1604943184
Short name T575
Test name
Test status
Simulation time 36324258 ps
CPU time 1.07 seconds
Started Jul 27 05:41:16 PM PDT 24
Finished Jul 27 05:41:17 PM PDT 24
Peak memory 205816 kb
Host smart-d5f89182-693e-4918-8b41-3229fd95e79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604943184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1604943184
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2121628854
Short name T719
Test name
Test status
Simulation time 79984443 ps
CPU time 3.75 seconds
Started Jul 27 05:41:14 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 221716 kb
Host smart-d6eb4ffa-7949-47a4-a88d-166793b9b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121628854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2121628854
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3869481386
Short name T574
Test name
Test status
Simulation time 3475819416 ps
CPU time 18.26 seconds
Started Jul 27 05:41:13 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 218196 kb
Host smart-f0cade21-095e-420f-acc1-593ba06556f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869481386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3869481386
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.404733489
Short name T838
Test name
Test status
Simulation time 214986412 ps
CPU time 2.38 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 214072 kb
Host smart-b87eecc2-06c1-4f00-b335-e32dad89894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404733489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.404733489
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2299659978
Short name T870
Test name
Test status
Simulation time 31458041 ps
CPU time 2.09 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 221284 kb
Host smart-e58c6b4a-7a55-4e90-8f6a-1b84d2357484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299659978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2299659978
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1100179573
Short name T484
Test name
Test status
Simulation time 99430235 ps
CPU time 3.73 seconds
Started Jul 27 05:41:14 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 216952 kb
Host smart-2d97aa7d-cf56-4317-8fcc-a54b0d9f550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100179573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1100179573
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.490928197
Short name T194
Test name
Test status
Simulation time 431488627 ps
CPU time 5.69 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:15 PM PDT 24
Peak memory 218168 kb
Host smart-44ecc867-6e2e-4428-bc71-7e447f17a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490928197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.490928197
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1230628961
Short name T181
Test name
Test status
Simulation time 138114375 ps
CPU time 3.13 seconds
Started Jul 27 05:41:10 PM PDT 24
Finished Jul 27 05:41:13 PM PDT 24
Peak memory 206604 kb
Host smart-bdfeb194-ced4-4efb-9662-de41b321864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230628961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1230628961
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3804163983
Short name T565
Test name
Test status
Simulation time 377606520 ps
CPU time 4.14 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 208572 kb
Host smart-277ac1aa-eb17-4424-85b5-6d4d56df9ddd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804163983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3804163983
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.905263377
Short name T711
Test name
Test status
Simulation time 125361255 ps
CPU time 2.27 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:20 PM PDT 24
Peak memory 206820 kb
Host smart-665e7299-ffb8-4eae-9fae-193a42f54a11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905263377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.905263377
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2616287974
Short name T860
Test name
Test status
Simulation time 620606402 ps
CPU time 14.8 seconds
Started Jul 27 05:41:08 PM PDT 24
Finished Jul 27 05:41:23 PM PDT 24
Peak memory 208752 kb
Host smart-3fcd5cd3-91a3-4d10-ba31-c322508baaeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616287974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2616287974
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4211776695
Short name T460
Test name
Test status
Simulation time 37209017 ps
CPU time 2 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 207288 kb
Host smart-cb185ed9-b9be-4aa4-8283-9ac70f6ec74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211776695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4211776695
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4208340090
Short name T587
Test name
Test status
Simulation time 86498501 ps
CPU time 2.53 seconds
Started Jul 27 05:41:09 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 206548 kb
Host smart-29330734-c946-4a18-be90-110118953be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208340090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4208340090
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3112347219
Short name T305
Test name
Test status
Simulation time 44418302851 ps
CPU time 263.08 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:45:45 PM PDT 24
Peak memory 218596 kb
Host smart-2a3c16d8-4681-4530-b132-ebf2835c8b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112347219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3112347219
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2334121072
Short name T796
Test name
Test status
Simulation time 847421429 ps
CPU time 22.46 seconds
Started Jul 27 05:41:11 PM PDT 24
Finished Jul 27 05:41:33 PM PDT 24
Peak memory 214096 kb
Host smart-b54b3fbf-6dbb-4354-9b3d-8dea432a41d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334121072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2334121072
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.871211355
Short name T657
Test name
Test status
Simulation time 105551619 ps
CPU time 2.57 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:20 PM PDT 24
Peak memory 209604 kb
Host smart-df0acab7-b79d-44d0-9043-d9761b6c4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871211355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.871211355
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2895290951
Short name T14
Test name
Test status
Simulation time 67249500 ps
CPU time 0.78 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:26 PM PDT 24
Peak memory 205796 kb
Host smart-f754266b-69aa-4101-9785-abcd31f3576d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895290951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2895290951
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1843861489
Short name T404
Test name
Test status
Simulation time 392185603 ps
CPU time 20.6 seconds
Started Jul 27 05:41:19 PM PDT 24
Finished Jul 27 05:41:40 PM PDT 24
Peak memory 214276 kb
Host smart-f9741777-c3e4-4a79-851e-75fb8b09d6c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843861489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1843861489
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.502512265
Short name T770
Test name
Test status
Simulation time 131936897 ps
CPU time 2.04 seconds
Started Jul 27 05:41:17 PM PDT 24
Finished Jul 27 05:41:20 PM PDT 24
Peak memory 216432 kb
Host smart-c9e808c4-ca89-4213-af74-4d3db1a8f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502512265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.502512265
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3905844696
Short name T814
Test name
Test status
Simulation time 137150398 ps
CPU time 5.11 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:28 PM PDT 24
Peak memory 209464 kb
Host smart-49d4cedb-02c5-40db-b3cb-70f353f873d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905844696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3905844696
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2507267240
Short name T748
Test name
Test status
Simulation time 52974769 ps
CPU time 2.96 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:26 PM PDT 24
Peak memory 215240 kb
Host smart-b44ed27e-69eb-4a2a-b57a-5c443c945d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507267240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2507267240
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2913396613
Short name T310
Test name
Test status
Simulation time 115194407 ps
CPU time 5.39 seconds
Started Jul 27 05:41:17 PM PDT 24
Finished Jul 27 05:41:22 PM PDT 24
Peak memory 222252 kb
Host smart-dd28210b-8282-4a57-a212-d4d3d82efb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913396613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2913396613
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.723284882
Short name T59
Test name
Test status
Simulation time 70841162 ps
CPU time 3.09 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 209744 kb
Host smart-68ee8883-2ad0-4e97-8432-f29a5c352d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723284882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.723284882
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.169174669
Short name T671
Test name
Test status
Simulation time 106888330 ps
CPU time 5.09 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 209120 kb
Host smart-a6f59c4f-c891-4042-aea4-297b806120a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169174669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.169174669
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4249870404
Short name T284
Test name
Test status
Simulation time 1601887030 ps
CPU time 4.67 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:23 PM PDT 24
Peak memory 206764 kb
Host smart-0b44dbbe-1c15-497b-ad17-3feea81e4bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249870404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4249870404
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2087826641
Short name T629
Test name
Test status
Simulation time 49797003 ps
CPU time 2.72 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 206696 kb
Host smart-68147a1e-ce50-4731-b6f5-20b3b72568c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087826641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2087826641
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4035071157
Short name T452
Test name
Test status
Simulation time 2208888117 ps
CPU time 7.36 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 208548 kb
Host smart-83ad3217-943d-4b26-9d46-e502cc9ec7e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035071157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4035071157
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1795859685
Short name T573
Test name
Test status
Simulation time 396330229 ps
CPU time 3.62 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:22 PM PDT 24
Peak memory 206964 kb
Host smart-9868494a-dcc6-4734-a6fe-a37bb65247c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795859685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1795859685
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3049100182
Short name T783
Test name
Test status
Simulation time 687339172 ps
CPU time 5.17 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:28 PM PDT 24
Peak memory 207840 kb
Host smart-6823c251-98ff-4411-8428-6c30d76f82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049100182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3049100182
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.870418151
Short name T505
Test name
Test status
Simulation time 4847968612 ps
CPU time 26.71 seconds
Started Jul 27 05:41:20 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 208112 kb
Host smart-57421847-a35a-4747-802c-49ab3d6c2d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870418151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.870418151
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.322381115
Short name T33
Test name
Test status
Simulation time 110395515 ps
CPU time 6.3 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 219436 kb
Host smart-8c67cf5b-90db-4d3e-b68b-77b12660f1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322381115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.322381115
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1183274451
Short name T544
Test name
Test status
Simulation time 415039642 ps
CPU time 3.94 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 214100 kb
Host smart-199c69a8-5904-41da-af9d-eae81b0f4b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183274451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1183274451
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3131305273
Short name T872
Test name
Test status
Simulation time 11750119 ps
CPU time 0.72 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:26 PM PDT 24
Peak memory 205820 kb
Host smart-555f8844-caa8-4963-a70f-f4555d29c8af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131305273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3131305273
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4129068375
Short name T268
Test name
Test status
Simulation time 26978859 ps
CPU time 2.56 seconds
Started Jul 27 05:41:28 PM PDT 24
Finished Jul 27 05:41:31 PM PDT 24
Peak memory 214156 kb
Host smart-d954c321-30ee-491f-b8f6-db718c6e09b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129068375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4129068375
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1084090596
Short name T391
Test name
Test status
Simulation time 19248524 ps
CPU time 1.52 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 207716 kb
Host smart-192731c2-d220-4b2b-a4eb-a29e62ea7242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084090596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1084090596
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3689758419
Short name T847
Test name
Test status
Simulation time 220215321 ps
CPU time 6 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 214100 kb
Host smart-b3e465ec-7c55-421d-bb71-2c4ef1afc9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689758419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3689758419
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2042049980
Short name T809
Test name
Test status
Simulation time 41996241 ps
CPU time 2.29 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 213992 kb
Host smart-1b478094-f7d2-4be1-90f1-9bfa51da883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042049980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2042049980
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.3889334954
Short name T198
Test name
Test status
Simulation time 233568013 ps
CPU time 4.92 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 209028 kb
Host smart-8ec29029-96e5-4cd5-bf72-74fbf5b716f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889334954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3889334954
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2308756626
Short name T550
Test name
Test status
Simulation time 2868074821 ps
CPU time 49.55 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 208736 kb
Host smart-15e42b95-9f5f-4ae7-a49d-a2de7eaa7ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308756626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2308756626
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1655846541
Short name T651
Test name
Test status
Simulation time 750848405 ps
CPU time 5.84 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 207928 kb
Host smart-dadcad3b-93b7-499a-a442-635c2d9072f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655846541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1655846541
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3772969579
Short name T410
Test name
Test status
Simulation time 1004321850 ps
CPU time 4.73 seconds
Started Jul 27 05:41:17 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 207172 kb
Host smart-e9a83019-06b9-40ac-ab1c-0059146465d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772969579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3772969579
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1040680185
Short name T578
Test name
Test status
Simulation time 55612305 ps
CPU time 2.35 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 206788 kb
Host smart-86e6f1b3-55d1-44c4-82a8-aa642dbf28f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040680185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1040680185
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1170680422
Short name T548
Test name
Test status
Simulation time 25694623 ps
CPU time 1.91 seconds
Started Jul 27 05:41:16 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 206904 kb
Host smart-d6df5a5c-33a8-4ac9-a345-69a76af699d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170680422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1170680422
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.286022479
Short name T426
Test name
Test status
Simulation time 89859473 ps
CPU time 3.37 seconds
Started Jul 27 05:41:18 PM PDT 24
Finished Jul 27 05:41:22 PM PDT 24
Peak memory 208080 kb
Host smart-efbeee14-233b-48ac-a7ba-4141eb7aee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286022479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.286022479
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2755590668
Short name T466
Test name
Test status
Simulation time 1286999785 ps
CPU time 40.5 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 208864 kb
Host smart-daf7e4b6-5e1a-47e5-8682-40c4b7a46dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755590668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2755590668
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2633465391
Short name T372
Test name
Test status
Simulation time 65408713 ps
CPU time 1.87 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 209632 kb
Host smart-23429370-89c2-4317-8e8e-18dfb5936007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633465391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2633465391
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.339878566
Short name T738
Test name
Test status
Simulation time 330162977 ps
CPU time 0.83 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 205796 kb
Host smart-e4aaf3f0-cb02-4bc8-95e6-71c30d9d4b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339878566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.339878566
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1231141013
Short name T380
Test name
Test status
Simulation time 47994179 ps
CPU time 3.02 seconds
Started Jul 27 05:41:35 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 214200 kb
Host smart-87a7bc34-3784-46a9-ab15-01a5fb1e3581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231141013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1231141013
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2677163442
Short name T801
Test name
Test status
Simulation time 65236302 ps
CPU time 2.78 seconds
Started Jul 27 05:41:27 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 214052 kb
Host smart-a7682dea-8e4b-4cae-b4d2-ebd92f1a4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677163442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2677163442
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2230365125
Short name T504
Test name
Test status
Simulation time 4814533448 ps
CPU time 20.84 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 220040 kb
Host smart-c239b7cb-43c8-4727-af81-8d94e2a8dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230365125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2230365125
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.146601055
Short name T87
Test name
Test status
Simulation time 116555259 ps
CPU time 4.84 seconds
Started Jul 27 05:41:29 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 209400 kb
Host smart-cba4e54e-dfd9-4569-8c0e-101fa724a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146601055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.146601055
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2774526485
Short name T351
Test name
Test status
Simulation time 46696992 ps
CPU time 3.23 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:37 PM PDT 24
Peak memory 214048 kb
Host smart-c160c78d-a4cc-4b94-bb8e-3378d74ae120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774526485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2774526485
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2669332654
Short name T447
Test name
Test status
Simulation time 259934746 ps
CPU time 2.9 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 209760 kb
Host smart-bb7332f8-34ef-4268-ad85-824bceba39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669332654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2669332654
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2414909099
Short name T529
Test name
Test status
Simulation time 79401974 ps
CPU time 3.94 seconds
Started Jul 27 05:41:17 PM PDT 24
Finished Jul 27 05:41:21 PM PDT 24
Peak memory 208844 kb
Host smart-2dee49c2-b264-4d10-8f1e-81b57200f0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414909099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2414909099
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4244262936
Short name T249
Test name
Test status
Simulation time 235390656 ps
CPU time 5.88 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 208348 kb
Host smart-ac27effd-c846-4cac-bcea-60b0dfdb89e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244262936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4244262936
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3442088656
Short name T512
Test name
Test status
Simulation time 39214900 ps
CPU time 2.34 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 206740 kb
Host smart-d9698feb-29f6-44b8-91a3-31c93d6e171a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442088656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3442088656
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3985034691
Short name T497
Test name
Test status
Simulation time 49046202 ps
CPU time 2.33 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 206576 kb
Host smart-53741631-cfab-4855-8871-4b4b36acca7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985034691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3985034691
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4236819423
Short name T472
Test name
Test status
Simulation time 100995330 ps
CPU time 1.84 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 206828 kb
Host smart-25822318-2b47-4f57-ae5d-7145fc3c2b62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236819423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4236819423
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2440324091
Short name T133
Test name
Test status
Simulation time 56771150 ps
CPU time 2.61 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 209976 kb
Host smart-4b4063c7-2366-4c34-a8d9-b6909563ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440324091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2440324091
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2704934258
Short name T698
Test name
Test status
Simulation time 11954950487 ps
CPU time 44.27 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 207956 kb
Host smart-1396124d-a533-4d19-ace3-0b7666dbb727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704934258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2704934258
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3998618852
Short name T187
Test name
Test status
Simulation time 95538723 ps
CPU time 3.54 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:28 PM PDT 24
Peak memory 208260 kb
Host smart-14b8e7be-8c85-459f-89fc-79ac84900d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998618852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3998618852
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3699114717
Short name T197
Test name
Test status
Simulation time 89255850 ps
CPU time 3.68 seconds
Started Jul 27 05:41:33 PM PDT 24
Finished Jul 27 05:41:37 PM PDT 24
Peak memory 207824 kb
Host smart-1a4ccf42-3046-4a39-8e3c-f8321627860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699114717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3699114717
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1294981998
Short name T662
Test name
Test status
Simulation time 45822285 ps
CPU time 2.14 seconds
Started Jul 27 05:41:22 PM PDT 24
Finished Jul 27 05:41:25 PM PDT 24
Peak memory 209852 kb
Host smart-69aad5fe-447d-4e8a-8f61-98fa0605e517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294981998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1294981998
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.531940679
Short name T454
Test name
Test status
Simulation time 205194318 ps
CPU time 0.75 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 205872 kb
Host smart-037a77ef-aeed-459b-afbb-51b7df57b378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531940679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.531940679
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1211090486
Short name T178
Test name
Test status
Simulation time 559722078 ps
CPU time 5.84 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 214052 kb
Host smart-a8b7f6c0-92af-43d0-9500-206a1e8fee0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211090486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1211090486
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.394354746
Short name T715
Test name
Test status
Simulation time 207409990 ps
CPU time 5.66 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 222516 kb
Host smart-e3cea4ae-c604-42bc-bb76-1180ae454c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394354746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.394354746
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1360984427
Short name T732
Test name
Test status
Simulation time 456715030 ps
CPU time 3.22 seconds
Started Jul 27 05:41:30 PM PDT 24
Finished Jul 27 05:41:33 PM PDT 24
Peak memory 214148 kb
Host smart-8a3d1d4d-ad8f-4a5b-847a-d216f7db3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360984427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1360984427
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3192175251
Short name T560
Test name
Test status
Simulation time 198620656 ps
CPU time 7.03 seconds
Started Jul 27 05:41:27 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 208948 kb
Host smart-8b382595-f986-4885-b2a4-28b5bd1c0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192175251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3192175251
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3108758118
Short name T28
Test name
Test status
Simulation time 11243625605 ps
CPU time 18.35 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 222248 kb
Host smart-2782e892-8e8c-4936-bce5-770a39627f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108758118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3108758118
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.250616192
Short name T907
Test name
Test status
Simulation time 321864962 ps
CPU time 4.05 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:38 PM PDT 24
Peak memory 214092 kb
Host smart-eb36f904-5c9b-455a-9374-59a8f642dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250616192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.250616192
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2969936926
Short name T303
Test name
Test status
Simulation time 283960580 ps
CPU time 8.49 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:33 PM PDT 24
Peak memory 214120 kb
Host smart-3220c9db-b9fc-400e-8f3e-df0c49670c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969936926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2969936926
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1018487263
Short name T779
Test name
Test status
Simulation time 1153820911 ps
CPU time 20.85 seconds
Started Jul 27 05:41:33 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 208276 kb
Host smart-fa91cf22-4744-4a82-a56e-5054e2856ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018487263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1018487263
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3373204398
Short name T701
Test name
Test status
Simulation time 82544825 ps
CPU time 1.81 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 206708 kb
Host smart-a2c67ff8-d135-4d09-a54e-032f13ff00c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373204398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3373204398
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.710675586
Short name T868
Test name
Test status
Simulation time 182242045 ps
CPU time 4.98 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 208372 kb
Host smart-60c7a7d9-f92a-4335-b50b-9253531d17ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710675586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.710675586
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3819098548
Short name T851
Test name
Test status
Simulation time 1173551079 ps
CPU time 11.74 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:41:37 PM PDT 24
Peak memory 208224 kb
Host smart-276aaef4-0ab8-459f-914f-1b4dbdc7c67b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819098548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3819098548
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2008061513
Short name T442
Test name
Test status
Simulation time 690321783 ps
CPU time 11.37 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:41:37 PM PDT 24
Peak memory 208516 kb
Host smart-e6aca976-dc59-414d-a900-357f23810fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008061513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2008061513
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3492443121
Short name T531
Test name
Test status
Simulation time 1086115812 ps
CPU time 6.85 seconds
Started Jul 27 05:41:29 PM PDT 24
Finished Jul 27 05:41:36 PM PDT 24
Peak memory 208684 kb
Host smart-20fccdcf-3e61-4bd6-b53b-c12657afd391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492443121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3492443121
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2034770897
Short name T836
Test name
Test status
Simulation time 24684238262 ps
CPU time 169.46 seconds
Started Jul 27 05:41:28 PM PDT 24
Finished Jul 27 05:44:17 PM PDT 24
Peak memory 222316 kb
Host smart-03299c2b-9902-4a12-9196-2e1e50846284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034770897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2034770897
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1059507728
Short name T511
Test name
Test status
Simulation time 285746236 ps
CPU time 7.83 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 222400 kb
Host smart-2debb926-3e2c-4ae2-9762-94b9ddae65df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059507728 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1059507728
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1167446653
Short name T302
Test name
Test status
Simulation time 695250361 ps
CPU time 7.99 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:33 PM PDT 24
Peak memory 218052 kb
Host smart-7ebbd2de-3134-4f53-8346-bbc4b3f20625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167446653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1167446653
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3303486001
Short name T532
Test name
Test status
Simulation time 40658334 ps
CPU time 1.69 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 208388 kb
Host smart-762d669e-0899-4645-824c-08ff9a5f65ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303486001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3303486001
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.746348421
Short name T761
Test name
Test status
Simulation time 23857662 ps
CPU time 0.74 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:32 PM PDT 24
Peak memory 205880 kb
Host smart-de94add0-3b4c-4630-b954-ef588c9a7761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746348421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.746348421
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2588061129
Short name T393
Test name
Test status
Simulation time 3780868019 ps
CPU time 12.61 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 214152 kb
Host smart-47d9ac62-3a40-49b7-a3fc-c236ce49ba1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588061129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2588061129
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.316795584
Short name T208
Test name
Test status
Simulation time 245266457 ps
CPU time 3.65 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:38 PM PDT 24
Peak memory 214336 kb
Host smart-22fe115b-3900-4857-8e65-55d748c64929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316795584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.316795584
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3370431752
Short name T645
Test name
Test status
Simulation time 169898395 ps
CPU time 4.99 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 209376 kb
Host smart-9135ed10-3ac9-4ccf-a2dc-31005a2c3985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370431752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3370431752
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2447155340
Short name T885
Test name
Test status
Simulation time 530300334 ps
CPU time 17.1 seconds
Started Jul 27 05:41:30 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 214156 kb
Host smart-8b016048-7e40-420b-a8d2-8ca4b436f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447155340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2447155340
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3293331712
Short name T36
Test name
Test status
Simulation time 147735659 ps
CPU time 6.19 seconds
Started Jul 27 05:41:29 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 222172 kb
Host smart-2b0eacc7-b270-4ffa-890a-4d2d6494c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293331712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3293331712
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4221602537
Short name T520
Test name
Test status
Simulation time 714417339 ps
CPU time 3.79 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 214156 kb
Host smart-d2a7293b-6724-4344-a634-ad60b6904c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221602537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4221602537
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3841250173
Short name T538
Test name
Test status
Simulation time 404728453 ps
CPU time 4.87 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:28 PM PDT 24
Peak memory 206652 kb
Host smart-7a82bf82-4bde-4e4b-9b3b-3227baf17363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841250173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3841250173
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2559014811
Short name T751
Test name
Test status
Simulation time 178429702 ps
CPU time 2.77 seconds
Started Jul 27 05:41:26 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 206596 kb
Host smart-4ce92036-ae95-4999-b86f-8c730399f9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559014811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2559014811
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1346540258
Short name T519
Test name
Test status
Simulation time 393277124 ps
CPU time 8.2 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:40 PM PDT 24
Peak memory 207888 kb
Host smart-88321a9a-1521-4a46-9c96-a3dc0ede0ae6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346540258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1346540258
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4081726208
Short name T675
Test name
Test status
Simulation time 497061919 ps
CPU time 3.2 seconds
Started Jul 27 05:41:23 PM PDT 24
Finished Jul 27 05:41:26 PM PDT 24
Peak memory 208888 kb
Host smart-30317a5c-38e6-4265-9120-7a7ccd2856e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081726208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4081726208
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1080023061
Short name T702
Test name
Test status
Simulation time 57629640 ps
CPU time 2.74 seconds
Started Jul 27 05:41:24 PM PDT 24
Finished Jul 27 05:41:27 PM PDT 24
Peak memory 207868 kb
Host smart-8d9a420f-f9e2-4447-a7db-4e78935101f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080023061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1080023061
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3373279510
Short name T300
Test name
Test status
Simulation time 115647066 ps
CPU time 4.44 seconds
Started Jul 27 05:41:25 PM PDT 24
Finished Jul 27 05:41:30 PM PDT 24
Peak memory 209572 kb
Host smart-fa5a23be-bdc0-46c2-8498-c649b3622711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373279510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3373279510
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.448657156
Short name T456
Test name
Test status
Simulation time 831377111 ps
CPU time 19.92 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 208608 kb
Host smart-c80bca68-bfb0-4e15-9590-76496735660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448657156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.448657156
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2879617787
Short name T614
Test name
Test status
Simulation time 3340181744 ps
CPU time 21.45 seconds
Started Jul 27 05:41:27 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 218036 kb
Host smart-796d04ab-55da-4cd0-8e71-2c9bcaa9fd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879617787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2879617787
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.959492604
Short name T112
Test name
Test status
Simulation time 74544587 ps
CPU time 2.08 seconds
Started Jul 27 05:41:36 PM PDT 24
Finished Jul 27 05:41:38 PM PDT 24
Peak memory 209664 kb
Host smart-ed56da1d-a850-4d59-80fa-e1ff7d3352f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959492604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.959492604
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.46707743
Short name T642
Test name
Test status
Simulation time 7476644 ps
CPU time 0.76 seconds
Started Jul 27 05:40:19 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 205776 kb
Host smart-93a5a327-8a74-49e2-a41e-2104936a5efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46707743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.46707743
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.274262123
Short name T226
Test name
Test status
Simulation time 4034861301 ps
CPU time 11.53 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 214172 kb
Host smart-c7b4b770-6873-440f-8222-f942c84bf94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274262123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.274262123
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1395310663
Short name T10
Test name
Test status
Simulation time 1386031920 ps
CPU time 8.82 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 214508 kb
Host smart-e0896834-3e24-4abe-9808-9a119651f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395310663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1395310663
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.750450558
Short name T563
Test name
Test status
Simulation time 78853157 ps
CPU time 1.86 seconds
Started Jul 27 05:40:11 PM PDT 24
Finished Jul 27 05:40:13 PM PDT 24
Peak memory 214208 kb
Host smart-ea62e724-6c12-4693-bb8f-f82a3dfca0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750450558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.750450558
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3490084144
Short name T350
Test name
Test status
Simulation time 194716600 ps
CPU time 2.51 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:18 PM PDT 24
Peak memory 214148 kb
Host smart-73d448e9-2613-4a9c-b775-9ba00895e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490084144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3490084144
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1747359674
Short name T237
Test name
Test status
Simulation time 202880739 ps
CPU time 4.03 seconds
Started Jul 27 05:40:17 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 222168 kb
Host smart-f72757ed-937d-448b-a4e1-3e8a4f16f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747359674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1747359674
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3610241755
Short name T728
Test name
Test status
Simulation time 195464918 ps
CPU time 2.07 seconds
Started Jul 27 05:40:18 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 214156 kb
Host smart-58123e08-f38b-4534-b165-7b729328bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610241755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3610241755
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3032492774
Short name T507
Test name
Test status
Simulation time 1640788638 ps
CPU time 22.33 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 207700 kb
Host smart-5bb99dd3-6522-4c10-91db-e8bb5f01fc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032492774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3032492774
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.82491164
Short name T43
Test name
Test status
Simulation time 772072101 ps
CPU time 17.24 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:32 PM PDT 24
Peak memory 232492 kb
Host smart-9554a1d6-97b9-4a51-bdcf-cf8980a7aabb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82491164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.82491164
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1002186884
Short name T539
Test name
Test status
Simulation time 538034979 ps
CPU time 5.54 seconds
Started Jul 27 05:40:17 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 207772 kb
Host smart-ef7cb777-add6-4cb4-abda-72b5eb118f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002186884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1002186884
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2308699908
Short name T461
Test name
Test status
Simulation time 99059020 ps
CPU time 3.26 seconds
Started Jul 27 05:40:19 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 206720 kb
Host smart-d0746174-6702-4ae2-8fe2-1017c71e98a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308699908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2308699908
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3899641130
Short name T848
Test name
Test status
Simulation time 347392742 ps
CPU time 1.99 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:17 PM PDT 24
Peak memory 206724 kb
Host smart-37d743bd-e173-4160-80ca-e1b3c2551f9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899641130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3899641130
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3203037179
Short name T506
Test name
Test status
Simulation time 1447235798 ps
CPU time 33.28 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 208508 kb
Host smart-bb7070b8-c92d-493b-b67e-d0a20cfcff76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203037179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3203037179
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2970193316
Short name T264
Test name
Test status
Simulation time 24819985 ps
CPU time 2.12 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 209504 kb
Host smart-5e327d71-9ce2-4782-93fa-fd9d9e97fd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970193316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2970193316
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1013683688
Short name T494
Test name
Test status
Simulation time 89504910 ps
CPU time 2.41 seconds
Started Jul 27 05:40:13 PM PDT 24
Finished Jul 27 05:40:15 PM PDT 24
Peak memory 206588 kb
Host smart-b326111b-3681-44bf-9b38-b3ce0d36cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013683688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1013683688
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4217631266
Short name T186
Test name
Test status
Simulation time 241975859 ps
CPU time 6.18 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 208652 kb
Host smart-be0f6a31-5ebf-43da-afbe-5a893a2ab00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217631266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4217631266
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.711608376
Short name T647
Test name
Test status
Simulation time 68417498 ps
CPU time 4.58 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 214184 kb
Host smart-6b730141-a0d8-4036-8c56-bf243620a76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711608376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.711608376
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.4153742854
Short name T369
Test name
Test status
Simulation time 117118946 ps
CPU time 1.72 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:18 PM PDT 24
Peak memory 209596 kb
Host smart-4960c61a-aa17-4613-ad10-1f0d42227277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153742854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4153742854
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3926352482
Short name T871
Test name
Test status
Simulation time 99541801 ps
CPU time 0.73 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 205836 kb
Host smart-ef1a429a-98f2-40ff-aa84-1ed41b0f50b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926352482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3926352482
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2436320727
Short name T267
Test name
Test status
Simulation time 29115994 ps
CPU time 2.45 seconds
Started Jul 27 05:41:37 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 214100 kb
Host smart-857ce1b4-1853-4ade-8746-a6e576df10f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436320727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2436320727
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3542779501
Short name T67
Test name
Test status
Simulation time 677056594 ps
CPU time 4.29 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 214196 kb
Host smart-ef332c5b-4d34-4edd-b593-ca72de8529e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542779501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3542779501
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2308231771
Short name T242
Test name
Test status
Simulation time 86455035 ps
CPU time 1.83 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 217900 kb
Host smart-2b5637e9-1cb6-4c8f-9fb2-dfc423c87b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308231771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2308231771
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.978553692
Short name T833
Test name
Test status
Simulation time 118759233 ps
CPU time 4.04 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 214084 kb
Host smart-8ed55d13-ed09-4211-b357-831842211350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978553692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.978553692
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1142118332
Short name T477
Test name
Test status
Simulation time 585141440 ps
CPU time 3.42 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 214048 kb
Host smart-999401f1-86e8-408c-8ccb-529c49f3ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142118332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1142118332
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1047232421
Short name T207
Test name
Test status
Simulation time 147804397 ps
CPU time 3.06 seconds
Started Jul 27 05:41:32 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 214124 kb
Host smart-83fce042-2061-4adf-8469-051f7494ac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047232421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1047232421
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3210062303
Short name T857
Test name
Test status
Simulation time 1134257384 ps
CPU time 8.54 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 222288 kb
Host smart-a4ba9a61-bc53-4d50-915a-ecc8924f996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210062303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3210062303
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3772279299
Short name T853
Test name
Test status
Simulation time 828545910 ps
CPU time 5 seconds
Started Jul 27 05:41:38 PM PDT 24
Finished Jul 27 05:41:43 PM PDT 24
Peak memory 207248 kb
Host smart-699057e5-4447-47b3-b950-c6525f6e8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772279299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3772279299
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1475678893
Short name T589
Test name
Test status
Simulation time 679983008 ps
CPU time 3 seconds
Started Jul 27 05:41:33 PM PDT 24
Finished Jul 27 05:41:36 PM PDT 24
Peak memory 206612 kb
Host smart-b6cfe733-abe6-4025-8a6b-459baeb189c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475678893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1475678893
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2327931086
Short name T572
Test name
Test status
Simulation time 133582212 ps
CPU time 2.43 seconds
Started Jul 27 05:41:39 PM PDT 24
Finished Jul 27 05:41:42 PM PDT 24
Peak memory 206892 kb
Host smart-8c200951-921a-4e6c-96e8-2bb425d36e86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327931086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2327931086
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3119177170
Short name T280
Test name
Test status
Simulation time 7393526869 ps
CPU time 20.03 seconds
Started Jul 27 05:41:32 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 208584 kb
Host smart-b73f1659-2bf9-4ee4-946b-c28bb28b52ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119177170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3119177170
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2017695976
Short name T592
Test name
Test status
Simulation time 805315702 ps
CPU time 6.31 seconds
Started Jul 27 05:41:32 PM PDT 24
Finished Jul 27 05:41:39 PM PDT 24
Peak memory 218252 kb
Host smart-c34d5ea7-f6c3-4fad-ae9e-21176f804580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017695976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2017695976
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2631995151
Short name T534
Test name
Test status
Simulation time 608731219 ps
CPU time 2.5 seconds
Started Jul 27 05:41:38 PM PDT 24
Finished Jul 27 05:41:41 PM PDT 24
Peak memory 206624 kb
Host smart-ad73976d-521b-4af4-8661-5245a1710f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631995151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2631995151
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4189522834
Short name T416
Test name
Test status
Simulation time 5622953122 ps
CPU time 23.42 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:42:05 PM PDT 24
Peak memory 214228 kb
Host smart-70e17e10-e40f-4d73-aca6-a7042a15d421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189522834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4189522834
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.857637534
Short name T609
Test name
Test status
Simulation time 916935743 ps
CPU time 6.89 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 210388 kb
Host smart-72a8381e-ec28-49f0-add5-7647b8498669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857637534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.857637534
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.192573162
Short name T616
Test name
Test status
Simulation time 19476779 ps
CPU time 0.74 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:46 PM PDT 24
Peak memory 205828 kb
Host smart-874eef17-9ac1-4dca-8bea-4e4c155a3190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192573162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.192573162
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2789815612
Short name T257
Test name
Test status
Simulation time 106153847 ps
CPU time 3.43 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 214152 kb
Host smart-5e4fa248-82f9-4a55-8f89-c453ffe2132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789815612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2789815612
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2516776095
Short name T27
Test name
Test status
Simulation time 540760525 ps
CPU time 7.88 seconds
Started Jul 27 05:41:36 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 214064 kb
Host smart-69105f32-eb89-4c88-a9b7-b20fa8b4adab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516776095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2516776095
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1436676075
Short name T612
Test name
Test status
Simulation time 97114258 ps
CPU time 3.45 seconds
Started Jul 27 05:41:39 PM PDT 24
Finished Jul 27 05:41:42 PM PDT 24
Peak memory 214104 kb
Host smart-c2318bc8-6954-4ce8-b27d-cde8957bbcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436676075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1436676075
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1993715297
Short name T806
Test name
Test status
Simulation time 78415492 ps
CPU time 3.32 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 214140 kb
Host smart-b858656a-82b1-42a0-be55-bebb6ef285ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993715297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1993715297
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3421407250
Short name T517
Test name
Test status
Simulation time 3333184910 ps
CPU time 35.14 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:42:07 PM PDT 24
Peak memory 209024 kb
Host smart-7234e5f0-a4e0-4bb9-90a4-d0f101b78411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421407250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3421407250
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2646991032
Short name T855
Test name
Test status
Simulation time 247320876 ps
CPU time 4.01 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 208288 kb
Host smart-7abc5d40-5a68-43a2-9e6c-9e5e70aeb5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646991032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2646991032
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2347755402
Short name T581
Test name
Test status
Simulation time 662302261 ps
CPU time 4.02 seconds
Started Jul 27 05:41:37 PM PDT 24
Finished Jul 27 05:41:42 PM PDT 24
Peak memory 206824 kb
Host smart-69eef447-1753-4d6f-abbe-a67470efef5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347755402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2347755402
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2964552095
Short name T527
Test name
Test status
Simulation time 172886542 ps
CPU time 5.02 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 208440 kb
Host smart-c0bd5ac6-fc98-464d-bc26-f3e57b500c00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964552095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2964552095
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1221422888
Short name T724
Test name
Test status
Simulation time 422090768 ps
CPU time 7.8 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 207848 kb
Host smart-92f5a28b-e2d9-43ba-a306-7101f6fa3ef3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221422888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1221422888
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4276651057
Short name T399
Test name
Test status
Simulation time 245875562 ps
CPU time 4.26 seconds
Started Jul 27 05:41:30 PM PDT 24
Finished Jul 27 05:41:35 PM PDT 24
Peak memory 209264 kb
Host smart-ce896a3a-f997-40db-a897-6453278039b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276651057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4276651057
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3489426061
Short name T635
Test name
Test status
Simulation time 19894983 ps
CPU time 1.74 seconds
Started Jul 27 05:41:40 PM PDT 24
Finished Jul 27 05:41:42 PM PDT 24
Peak memory 206952 kb
Host smart-0c6e6383-e089-4415-aafd-229221df2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489426061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3489426061
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.322649597
Short name T244
Test name
Test status
Simulation time 664247560 ps
CPU time 23.4 seconds
Started Jul 27 05:41:31 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 215064 kb
Host smart-03a56675-bf97-4c9e-82b2-60003050cc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322649597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.322649597
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1616370796
Short name T577
Test name
Test status
Simulation time 6410391879 ps
CPU time 34.08 seconds
Started Jul 27 05:41:32 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 214156 kb
Host smart-31eed93b-5914-4862-b1d2-2b5679a4afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616370796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1616370796
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2586537246
Short name T765
Test name
Test status
Simulation time 192137054 ps
CPU time 3.69 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 210228 kb
Host smart-96f4b1be-196d-407a-b445-e034ad085a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586537246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2586537246
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.254379266
Short name T414
Test name
Test status
Simulation time 43489694 ps
CPU time 0.79 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 205756 kb
Host smart-54519e52-7f02-4ad4-bf63-cdc5d045968a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254379266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.254379266
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.955592475
Short name T727
Test name
Test status
Simulation time 573683934 ps
CPU time 4.57 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:46 PM PDT 24
Peak memory 209732 kb
Host smart-014f3925-abbe-49f7-bc88-3dcd2a7db8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955592475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.955592475
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2920350838
Short name T47
Test name
Test status
Simulation time 196077442 ps
CPU time 2.16 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 214180 kb
Host smart-bd0f83a0-f01d-4025-9fbe-f6d6e8491b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920350838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2920350838
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3138033966
Short name T92
Test name
Test status
Simulation time 110803117 ps
CPU time 2.98 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 214116 kb
Host smart-318151bf-7a67-4afc-aed2-9ca9b45164a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138033966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3138033966
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3857468484
Short name T261
Test name
Test status
Simulation time 803630414 ps
CPU time 5.46 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 214124 kb
Host smart-f327ef17-f2be-4c84-950a-247360cec2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857468484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3857468484
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3917615587
Short name T807
Test name
Test status
Simulation time 45780897 ps
CPU time 2.66 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 215836 kb
Host smart-d874a900-ebcc-4992-8f7a-01f2af0ac42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917615587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3917615587
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1417747451
Short name T590
Test name
Test status
Simulation time 4334925914 ps
CPU time 29.45 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 209336 kb
Host smart-3f14b81d-e3cb-4c15-bbb8-05cc7df26fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417747451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1417747451
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.373165390
Short name T418
Test name
Test status
Simulation time 3648069450 ps
CPU time 15.78 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:42:03 PM PDT 24
Peak memory 207712 kb
Host smart-ca593fa1-ca78-4613-9fd8-324c2a7bb68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373165390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.373165390
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2100554520
Short name T721
Test name
Test status
Simulation time 128947710 ps
CPU time 4.84 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 208576 kb
Host smart-d80d93ee-f267-48b0-a31d-ba4b2f6953b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100554520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2100554520
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3505009384
Short name T431
Test name
Test status
Simulation time 106105743 ps
CPU time 2.98 seconds
Started Jul 27 05:41:35 PM PDT 24
Finished Jul 27 05:41:38 PM PDT 24
Peak memory 208220 kb
Host smart-73fab764-6a13-4c57-b9c9-bf440748e7e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505009384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3505009384
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4185157200
Short name T901
Test name
Test status
Simulation time 54406596 ps
CPU time 2.89 seconds
Started Jul 27 05:41:41 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 206924 kb
Host smart-37d5e98e-3b7e-4442-a403-ab79e4b8d87e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185157200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4185157200
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2417587522
Short name T358
Test name
Test status
Simulation time 1908684346 ps
CPU time 4.16 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 209720 kb
Host smart-3eafe9b7-cde2-4f73-bddb-d9b63b4a8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417587522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2417587522
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.389375960
Short name T646
Test name
Test status
Simulation time 108302250 ps
CPU time 2.74 seconds
Started Jul 27 05:41:34 PM PDT 24
Finished Jul 27 05:41:37 PM PDT 24
Peak memory 206768 kb
Host smart-2c2a49c1-43f1-494d-b6e0-b1c55e9eae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389375960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.389375960
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1512277120
Short name T889
Test name
Test status
Simulation time 2512598008 ps
CPU time 54.5 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 208396 kb
Host smart-fdf60cff-da3f-48d9-b594-6e5d5ebbf858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512277120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1512277120
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1942121356
Short name T785
Test name
Test status
Simulation time 271864887 ps
CPU time 2.88 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:46 PM PDT 24
Peak memory 210416 kb
Host smart-46e2b6e8-5330-4bda-873f-7938cf363fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942121356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1942121356
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4187421083
Short name T427
Test name
Test status
Simulation time 20757529 ps
CPU time 0.84 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:44 PM PDT 24
Peak memory 205772 kb
Host smart-cd107ffd-11e4-47ff-a8f2-fbeb36dbc74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187421083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4187421083
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.475875241
Short name T254
Test name
Test status
Simulation time 390526975 ps
CPU time 21.88 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 222136 kb
Host smart-6ac15556-fe4f-45d5-871a-8863f70fb1e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475875241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.475875241
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1704250765
Short name T75
Test name
Test status
Simulation time 265243351 ps
CPU time 8.18 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 208736 kb
Host smart-246f3c1e-d0c2-4c71-8ad7-ba6f41ba3009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704250765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1704250765
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4276998766
Short name T91
Test name
Test status
Simulation time 87266253 ps
CPU time 4.19 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 220092 kb
Host smart-9df7ed2d-ee0a-42cc-beaf-2746c2ebb016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276998766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4276998766
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2055193798
Short name T233
Test name
Test status
Simulation time 122757333 ps
CPU time 3.53 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 222172 kb
Host smart-cf8c92d5-9c88-4c95-923c-768cefbc5ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055193798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2055193798
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.1350896039
Short name T703
Test name
Test status
Simulation time 201113870 ps
CPU time 2.64 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 207628 kb
Host smart-f2e146bd-bc58-42fc-857c-dc9531ecacc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350896039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1350896039
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1580109275
Short name T824
Test name
Test status
Simulation time 108299837 ps
CPU time 3.61 seconds
Started Jul 27 05:41:38 PM PDT 24
Finished Jul 27 05:41:42 PM PDT 24
Peak memory 208392 kb
Host smart-eee28efa-d91f-4342-bbb9-16c61dce3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580109275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1580109275
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3818934005
Short name T474
Test name
Test status
Simulation time 25370798 ps
CPU time 2.08 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:46 PM PDT 24
Peak memory 208872 kb
Host smart-949f7785-82fc-43ff-90e9-e42e814dc959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818934005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3818934005
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3577983769
Short name T884
Test name
Test status
Simulation time 240319387 ps
CPU time 2.18 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 206788 kb
Host smart-30c8a764-a6b7-4890-bdb3-9fdbbe4d0a40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577983769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3577983769
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1581108740
Short name T131
Test name
Test status
Simulation time 46798950 ps
CPU time 2.58 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 208388 kb
Host smart-3c9c90ac-472d-41c6-a82f-4e51baff4311
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581108740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1581108740
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3161898469
Short name T328
Test name
Test status
Simulation time 112642500 ps
CPU time 3.94 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 210076 kb
Host smart-a6272573-a19b-4b96-b9d4-2eba28f9a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161898469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3161898469
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1740966843
Short name T134
Test name
Test status
Simulation time 235342355 ps
CPU time 3.33 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:41:48 PM PDT 24
Peak memory 208500 kb
Host smart-36395ce9-4dc0-4d79-b087-173301484f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740966843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1740966843
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3911915866
Short name T216
Test name
Test status
Simulation time 190177359 ps
CPU time 5.15 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 220616 kb
Host smart-f3a2be33-d2e2-4fbc-b3f4-df35e033f4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911915866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3911915866
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4203027979
Short name T564
Test name
Test status
Simulation time 588080077 ps
CPU time 5.13 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 209828 kb
Host smart-b078b273-c850-47fd-9ad5-7b37b0bf7e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203027979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4203027979
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1642545294
Short name T605
Test name
Test status
Simulation time 61893557 ps
CPU time 2.19 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 209620 kb
Host smart-a3bfc606-b73d-4e27-ba7e-45f839089e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642545294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1642545294
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1342092686
Short name T762
Test name
Test status
Simulation time 60949218 ps
CPU time 0.96 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:46 PM PDT 24
Peak memory 205984 kb
Host smart-83a7b1ed-c179-420f-b608-9035fc309115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342092686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1342092686
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.476696482
Short name T355
Test name
Test status
Simulation time 264151510 ps
CPU time 14.2 seconds
Started Jul 27 05:41:43 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 214264 kb
Host smart-6d9a291e-308e-4c88-911d-74bf65587250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476696482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.476696482
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4209858645
Short name T802
Test name
Test status
Simulation time 201949766 ps
CPU time 2.35 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 208132 kb
Host smart-075a2618-78d3-43d4-92af-35c3463352bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209858645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4209858645
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2331003834
Short name T744
Test name
Test status
Simulation time 444819165 ps
CPU time 3.49 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:48 PM PDT 24
Peak memory 208600 kb
Host smart-a4bd1f7e-5761-4863-b438-d673be69d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331003834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2331003834
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.124365564
Short name T308
Test name
Test status
Simulation time 133975124 ps
CPU time 3.12 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 214176 kb
Host smart-46926e03-e85c-4ab0-ac1e-53034f550e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124365564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.124365564
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1859498468
Short name T811
Test name
Test status
Simulation time 450188303 ps
CPU time 2.65 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 214108 kb
Host smart-8c31c84e-7a7d-4e66-83c7-1f56fab63612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859498468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1859498468
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.445552296
Short name T317
Test name
Test status
Simulation time 773976987 ps
CPU time 6.79 seconds
Started Jul 27 05:41:38 PM PDT 24
Finished Jul 27 05:41:45 PM PDT 24
Peak memory 209324 kb
Host smart-558a696f-7748-494c-bda9-f8e0586562b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445552296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.445552296
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.378449425
Short name T265
Test name
Test status
Simulation time 4062731415 ps
CPU time 14.38 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 208660 kb
Host smart-b13da434-4a4e-45d0-9c57-cf6bf11b2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378449425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.378449425
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3161190473
Short name T908
Test name
Test status
Simulation time 6262442384 ps
CPU time 23.87 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 207728 kb
Host smart-2861ab78-1190-482b-84d1-bb0e1992adb8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161190473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3161190473
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4072025323
Short name T708
Test name
Test status
Simulation time 113015483 ps
CPU time 2.84 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:41:47 PM PDT 24
Peak memory 206648 kb
Host smart-bb042737-5a58-4420-814e-31062282fb86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072025323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4072025323
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.580099990
Short name T854
Test name
Test status
Simulation time 612067593 ps
CPU time 5.02 seconds
Started Jul 27 05:41:44 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 208516 kb
Host smart-1db9847a-8962-460b-86b7-231d7808c510
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580099990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.580099990
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4146907110
Short name T660
Test name
Test status
Simulation time 127875708 ps
CPU time 1.74 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:48 PM PDT 24
Peak memory 207964 kb
Host smart-a1827386-cf70-4041-a838-786b05baf43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146907110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4146907110
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.557879399
Short name T435
Test name
Test status
Simulation time 514825206 ps
CPU time 4.3 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 207748 kb
Host smart-32bad1c4-462c-4e34-8a9c-d7d2bf3ea8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557879399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.557879399
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2842673064
Short name T773
Test name
Test status
Simulation time 16724337340 ps
CPU time 364.3 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:47:50 PM PDT 24
Peak memory 217748 kb
Host smart-be4c2a73-8c7a-4155-8f49-e7391c1a904a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842673064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2842673064
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1307582378
Short name T174
Test name
Test status
Simulation time 1393929188 ps
CPU time 8.03 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 219368 kb
Host smart-d90fd69e-3bac-47e3-a17e-057b2bd88cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307582378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1307582378
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3178663237
Short name T582
Test name
Test status
Simulation time 406993160 ps
CPU time 6.24 seconds
Started Jul 27 05:41:42 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 209024 kb
Host smart-766cfe2d-480d-4dd5-858d-54a45b3bebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178663237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3178663237
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3603253744
Short name T549
Test name
Test status
Simulation time 90264327 ps
CPU time 2.49 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:48 PM PDT 24
Peak memory 209792 kb
Host smart-d30052ba-087e-477d-b174-e3e3f002696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603253744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3603253744
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1895531758
Short name T436
Test name
Test status
Simulation time 33725309 ps
CPU time 0.71 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 205828 kb
Host smart-8629f003-0e89-47b1-9a7e-f02d9075f62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895531758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1895531758
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4157019851
Short name T627
Test name
Test status
Simulation time 42036017 ps
CPU time 2.73 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 209028 kb
Host smart-d459539d-a9a0-48ab-9030-8b6d391a853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157019851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4157019851
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1553341613
Short name T658
Test name
Test status
Simulation time 197553393 ps
CPU time 2.48 seconds
Started Jul 27 05:41:46 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 218132 kb
Host smart-1fa588ac-ac31-4b9d-8459-bba7359e5350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553341613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1553341613
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1272717878
Short name T615
Test name
Test status
Simulation time 33360539 ps
CPU time 2.35 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 215280 kb
Host smart-bd4a5fa6-b7a4-4224-b3b9-275c668c5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272717878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1272717878
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3191921132
Short name T794
Test name
Test status
Simulation time 56900058 ps
CPU time 1.9 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 214116 kb
Host smart-72c93796-0a67-43e3-8b72-e2bf056de0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191921132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3191921132
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2355090577
Short name T58
Test name
Test status
Simulation time 70549797 ps
CPU time 2.65 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 217644 kb
Host smart-2a63995c-000c-4398-b31a-1aa3566e2c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355090577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2355090577
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2383282909
Short name T204
Test name
Test status
Simulation time 1035319288 ps
CPU time 6.4 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 218100 kb
Host smart-b7ce04ea-4218-4f15-b106-6207eb5c9c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383282909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2383282909
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1436048608
Short name T513
Test name
Test status
Simulation time 106671235 ps
CPU time 2.16 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 206640 kb
Host smart-e2f8300a-0491-476b-921c-206a6af0e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436048608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1436048608
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1179874792
Short name T428
Test name
Test status
Simulation time 113315985 ps
CPU time 3.26 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 208580 kb
Host smart-9086070e-91a4-42b4-8fff-80b23a262d8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179874792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1179874792
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1043623175
Short name T687
Test name
Test status
Simulation time 244783890 ps
CPU time 6.84 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 208808 kb
Host smart-9c95a76c-c869-46ae-966a-06c35204d37d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043623175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1043623175
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1133993877
Short name T489
Test name
Test status
Simulation time 517174624 ps
CPU time 3.99 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 207248 kb
Host smart-f11ed3f0-c035-4b2f-a6e3-2395171f05c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133993877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1133993877
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3906896627
Short name T192
Test name
Test status
Simulation time 316681667 ps
CPU time 2.75 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 209192 kb
Host smart-3f57c786-5116-4f03-a512-84b95844fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906896627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3906896627
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.659641105
Short name T189
Test name
Test status
Simulation time 43173333 ps
CPU time 2.28 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:41:49 PM PDT 24
Peak memory 208332 kb
Host smart-775c6a62-bbb9-4c97-bf30-edf29977fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659641105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.659641105
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1648690624
Short name T214
Test name
Test status
Simulation time 1058878721 ps
CPU time 22.01 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:42:17 PM PDT 24
Peak memory 215096 kb
Host smart-dae1eb31-e758-4c81-905b-cab1f50c6b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648690624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1648690624
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2366790827
Short name T129
Test name
Test status
Simulation time 1116060061 ps
CPU time 9.21 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 222208 kb
Host smart-857212de-2860-4e28-b674-3d00d7b8fb3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366790827 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2366790827
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.796394809
Short name T1
Test name
Test status
Simulation time 243941300 ps
CPU time 5.56 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 214128 kb
Host smart-e5a6e4e3-23e1-47f7-bf99-eb2c2960e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796394809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.796394809
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1922882632
Short name T502
Test name
Test status
Simulation time 42010002 ps
CPU time 2.06 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 209824 kb
Host smart-30e23846-408a-440e-95e7-55fd83c547f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922882632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1922882632
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1927276546
Short name T799
Test name
Test status
Simulation time 64714425 ps
CPU time 0.7 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 205812 kb
Host smart-79b00cfa-7001-465a-a00d-3d5208be7ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927276546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1927276546
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2970153934
Short name T381
Test name
Test status
Simulation time 35429239 ps
CPU time 3.06 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 214084 kb
Host smart-705b94e8-8d7d-4ab1-a382-be6d6ed5b617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970153934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2970153934
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2225183454
Short name T339
Test name
Test status
Simulation time 329314656 ps
CPU time 3.03 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:52 PM PDT 24
Peak memory 208120 kb
Host smart-5177048f-1139-46f5-885b-f4b420295718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225183454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2225183454
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2817169469
Short name T231
Test name
Test status
Simulation time 46205690 ps
CPU time 1.94 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 208772 kb
Host smart-737210a0-4fac-4dc8-9359-8b7b5a8fff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817169469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2817169469
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.950860475
Short name T720
Test name
Test status
Simulation time 220384523 ps
CPU time 3.3 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 214948 kb
Host smart-74b845fc-06f8-48a4-b657-61f51ff86591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950860475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.950860475
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2754475310
Short name T291
Test name
Test status
Simulation time 214372772 ps
CPU time 3.77 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 214104 kb
Host smart-2570d34a-63f4-4d0f-a32e-819f05f27e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754475310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2754475310
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2431996103
Short name T215
Test name
Test status
Simulation time 104904772 ps
CPU time 4.76 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 215636 kb
Host smart-d6a4cbd6-a36e-490f-acdc-c4b87f354684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431996103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2431996103
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2195506300
Short name T852
Test name
Test status
Simulation time 370056314 ps
CPU time 5.63 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 208156 kb
Host smart-a1e6f557-72f8-45e9-b2ba-e3d1cd386951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195506300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2195506300
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.387998119
Short name T196
Test name
Test status
Simulation time 1601884634 ps
CPU time 39.44 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:42:30 PM PDT 24
Peak memory 208784 kb
Host smart-d8f19680-3219-4519-ada7-caa005ec1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387998119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.387998119
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2016993552
Short name T200
Test name
Test status
Simulation time 238119418 ps
CPU time 3.63 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 208472 kb
Host smart-a702b817-5fad-4180-84dc-356c8035c0f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016993552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2016993552
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3353442622
Short name T361
Test name
Test status
Simulation time 277055056 ps
CPU time 5.98 seconds
Started Jul 27 05:41:45 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 208464 kb
Host smart-2c69b8a3-4c70-4481-a8a4-679dc1ff80ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353442622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3353442622
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2557409111
Short name T15
Test name
Test status
Simulation time 237870313 ps
CPU time 5.04 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:55 PM PDT 24
Peak memory 208004 kb
Host smart-fdc8a9fb-7f00-4ba8-a6f4-b69df728bcc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557409111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2557409111
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_smoke.646073815
Short name T667
Test name
Test status
Simulation time 125996023 ps
CPU time 2.51 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:51 PM PDT 24
Peak memory 208380 kb
Host smart-2f028a7f-1235-443e-b8e4-effcfc78aca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646073815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.646073815
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2061296429
Short name T478
Test name
Test status
Simulation time 2675134698 ps
CPU time 16.61 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 208012 kb
Host smart-bf6d9871-e037-454d-9e30-4719e78294a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061296429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2061296429
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4123024333
Short name T445
Test name
Test status
Simulation time 1362676517 ps
CPU time 4.04 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 209672 kb
Host smart-3cb73618-c134-438e-b73b-814e921f45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123024333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4123024333
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2394629636
Short name T631
Test name
Test status
Simulation time 47903110 ps
CPU time 2.02 seconds
Started Jul 27 05:41:50 PM PDT 24
Finished Jul 27 05:41:53 PM PDT 24
Peak memory 209620 kb
Host smart-27172af5-875e-420f-a3a1-1bf72dd513ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394629636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2394629636
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.50183081
Short name T622
Test name
Test status
Simulation time 23949596 ps
CPU time 0.74 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 205844 kb
Host smart-d2ec29e6-dd0b-48e6-87fd-4d03981a10bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50183081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.50183081
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2803732360
Short name T392
Test name
Test status
Simulation time 510327332 ps
CPU time 7.31 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 214104 kb
Host smart-b36b94eb-eda1-45ff-9949-db0a674e2ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803732360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2803732360
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2265537859
Short name T70
Test name
Test status
Simulation time 54074431 ps
CPU time 2.5 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 209984 kb
Host smart-16bc562a-6721-45c2-88aa-2e64484ab8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265537859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2265537859
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3403048318
Short name T306
Test name
Test status
Simulation time 636523326 ps
CPU time 5.96 seconds
Started Jul 27 05:41:51 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 218128 kb
Host smart-bfa077ec-127c-4970-ba34-d3eb46253e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403048318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3403048318
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4218418016
Short name T523
Test name
Test status
Simulation time 227199081 ps
CPU time 5.45 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 220140 kb
Host smart-2561e8a0-9494-4cad-9ec7-0f1dd5226b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218418016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4218418016
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.713094881
Short name T173
Test name
Test status
Simulation time 36055632 ps
CPU time 2.58 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 219544 kb
Host smart-00ed4d7f-8dc8-4f4e-9b52-eb2cdfe70e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713094881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.713094881
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3434231727
Short name T670
Test name
Test status
Simulation time 110154142 ps
CPU time 5.06 seconds
Started Jul 27 05:41:49 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 214112 kb
Host smart-27a3ef46-4d64-4b26-abc5-c32a4fb27520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434231727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3434231727
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1236340142
Short name T137
Test name
Test status
Simulation time 848213949 ps
CPU time 6.29 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:42:01 PM PDT 24
Peak memory 208332 kb
Host smart-1d23ec2d-b96d-448a-a1a5-0105ae1d6f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236340142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1236340142
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.142994160
Short name T205
Test name
Test status
Simulation time 72938766 ps
CPU time 2.22 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 206728 kb
Host smart-4b323b61-2cc6-44ef-970f-43a73eb079d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142994160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.142994160
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4013237919
Short name T510
Test name
Test status
Simulation time 31341879 ps
CPU time 2.26 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 206796 kb
Host smart-c54f1b56-456f-4ce7-a80c-cb14f1e4b412
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013237919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4013237919
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.349893433
Short name T898
Test name
Test status
Simulation time 891861187 ps
CPU time 6.52 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 206836 kb
Host smart-bbb788cc-a843-4345-afc1-342938e5d8d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349893433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.349893433
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1494888359
Short name T786
Test name
Test status
Simulation time 1112186940 ps
CPU time 16.51 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 207772 kb
Host smart-176e2b43-d890-44fd-8e76-239956bc6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494888359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1494888359
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2562717463
Short name T619
Test name
Test status
Simulation time 20328188 ps
CPU time 1.73 seconds
Started Jul 27 05:41:48 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 206596 kb
Host smart-42e5f1f9-214d-4205-9815-d6c7230bc470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562717463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2562717463
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3678740118
Short name T315
Test name
Test status
Simulation time 197126932 ps
CPU time 3.09 seconds
Started Jul 27 05:41:47 PM PDT 24
Finished Jul 27 05:41:50 PM PDT 24
Peak memory 207776 kb
Host smart-6d35af83-e602-4a4d-83dd-4ca3439599fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678740118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3678740118
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.288954639
Short name T804
Test name
Test status
Simulation time 458540275 ps
CPU time 2.7 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 209952 kb
Host smart-56346450-bb6c-4644-97d2-2881935d8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288954639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.288954639
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4143655930
Short name T602
Test name
Test status
Simulation time 11453573 ps
CPU time 0.87 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:54 PM PDT 24
Peak memory 205868 kb
Host smart-094e548d-ce65-44e4-b53f-bbd77d408299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143655930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4143655930
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2010590408
Short name T255
Test name
Test status
Simulation time 2433376889 ps
CPU time 61.65 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:42:56 PM PDT 24
Peak memory 214236 kb
Host smart-0ea99e7e-9171-4759-b2ab-483d437367e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010590408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2010590408
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1844234914
Short name T457
Test name
Test status
Simulation time 364269135 ps
CPU time 4.37 seconds
Started Jul 27 05:41:59 PM PDT 24
Finished Jul 27 05:42:03 PM PDT 24
Peak memory 209024 kb
Host smart-2c546793-f7d9-40f7-aedc-e5f83d58a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844234914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1844234914
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2863935549
Short name T694
Test name
Test status
Simulation time 183316187 ps
CPU time 2.26 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 207080 kb
Host smart-8bbd98ef-3e0b-455b-83dd-2ddd2070934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863935549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2863935549
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2501290954
Short name T363
Test name
Test status
Simulation time 67619237 ps
CPU time 3.18 seconds
Started Jul 27 05:42:00 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 214120 kb
Host smart-021f671a-87c2-426a-aca9-dd21b923f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501290954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2501290954
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4039955960
Short name T49
Test name
Test status
Simulation time 48752278 ps
CPU time 2.83 seconds
Started Jul 27 05:41:57 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 222292 kb
Host smart-e8bdce2e-bb6e-4977-b2b1-2668a1bf5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039955960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4039955960
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2660505596
Short name T818
Test name
Test status
Simulation time 135237215 ps
CPU time 3.45 seconds
Started Jul 27 05:42:09 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 218904 kb
Host smart-c121c243-a4cd-4daa-bb03-9c7102aecef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660505596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2660505596
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1537983206
Short name T607
Test name
Test status
Simulation time 1180434357 ps
CPU time 8.61 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:42:01 PM PDT 24
Peak memory 222268 kb
Host smart-b49021fb-e749-422b-b14c-1587d442c854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537983206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1537983206
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1545887310
Short name T685
Test name
Test status
Simulation time 203474208 ps
CPU time 1.77 seconds
Started Jul 27 05:42:03 PM PDT 24
Finished Jul 27 05:42:05 PM PDT 24
Peak memory 206828 kb
Host smart-4943489c-a8fc-4d04-8ffd-51cffde0cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545887310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1545887310
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3779881478
Short name T845
Test name
Test status
Simulation time 812923696 ps
CPU time 4.41 seconds
Started Jul 27 05:42:00 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 206872 kb
Host smart-8f7ffe6c-103f-4a79-b483-3a17a56ce7f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779881478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3779881478
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3031017683
Short name T386
Test name
Test status
Simulation time 766893834 ps
CPU time 4.78 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 208752 kb
Host smart-019789d8-91c1-40ea-b7d9-eb7457ec4af9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031017683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3031017683
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.674098915
Short name T312
Test name
Test status
Simulation time 80996018 ps
CPU time 3.69 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 208468 kb
Host smart-c5377ec6-4e99-48a0-b437-e1d313c8c80f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674098915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.674098915
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3543058339
Short name T726
Test name
Test status
Simulation time 37703663 ps
CPU time 1.81 seconds
Started Jul 27 05:42:06 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 215316 kb
Host smart-64617866-16df-4eb7-8439-b8ab2dd7e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543058339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3543058339
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.673300299
Short name T641
Test name
Test status
Simulation time 1165830568 ps
CPU time 3.67 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 208652 kb
Host smart-0ece7732-8aae-4f6d-bd35-81d65848b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673300299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.673300299
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1197166210
Short name T46
Test name
Test status
Simulation time 2530360350 ps
CPU time 24.42 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 216804 kb
Host smart-40a7f996-c0a9-4a31-b7ea-637bf2408f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197166210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1197166210
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1356375005
Short name T96
Test name
Test status
Simulation time 189804912 ps
CPU time 6.48 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 219028 kb
Host smart-012609b9-9b8e-41e7-b42b-069a7d78995f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356375005 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1356375005
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4006251500
Short name T103
Test name
Test status
Simulation time 297497256 ps
CPU time 4.04 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 206892 kb
Host smart-fc7336e2-1ad2-4137-8c95-5ece19e3f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006251500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4006251500
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1767201803
Short name T498
Test name
Test status
Simulation time 55275290 ps
CPU time 2.38 seconds
Started Jul 27 05:42:06 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 209852 kb
Host smart-151b8d35-6b55-4c31-90d7-5f79dcc35d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767201803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1767201803
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3160666711
Short name T832
Test name
Test status
Simulation time 70373445 ps
CPU time 0.86 seconds
Started Jul 27 05:41:59 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 205852 kb
Host smart-6897776b-ce7a-4742-8cb2-f8be6cddc500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160666711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3160666711
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4193458706
Short name T39
Test name
Test status
Simulation time 186169638 ps
CPU time 3.43 seconds
Started Jul 27 05:41:52 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 218220 kb
Host smart-918a0b64-3918-4d44-9535-5f0978cb2122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193458706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4193458706
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1491073217
Short name T72
Test name
Test status
Simulation time 28888001 ps
CPU time 1.93 seconds
Started Jul 27 05:42:03 PM PDT 24
Finished Jul 27 05:42:05 PM PDT 24
Peak memory 208884 kb
Host smart-ed69dde2-6193-456d-9625-f13aa1bfce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491073217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1491073217
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1267870184
Short name T89
Test name
Test status
Simulation time 5750445378 ps
CPU time 23.73 seconds
Started Jul 27 05:41:59 PM PDT 24
Finished Jul 27 05:42:23 PM PDT 24
Peak memory 222420 kb
Host smart-f68b3839-6f3f-4775-a641-35d06681cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267870184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1267870184
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.21945427
Short name T258
Test name
Test status
Simulation time 259406547 ps
CPU time 1.99 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:07 PM PDT 24
Peak memory 214120 kb
Host smart-c94496a1-c175-4acf-bc2b-1c0e89623ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21945427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.21945427
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.593870034
Short name T217
Test name
Test status
Simulation time 109059478 ps
CPU time 4.95 seconds
Started Jul 27 05:42:06 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 219824 kb
Host smart-6d1b3c8a-4340-4ce8-8e92-98a54746fbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593870034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.593870034
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3271017086
Short name T191
Test name
Test status
Simulation time 2433924033 ps
CPU time 5.66 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 207344 kb
Host smart-5afbf8d8-cf3f-4af4-8367-1fe2b3e21831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271017086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3271017086
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2579972490
Short name T271
Test name
Test status
Simulation time 434046821 ps
CPU time 3.99 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 206748 kb
Host smart-81082acd-c7ac-4536-b260-9d5818db0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579972490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2579972490
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1711355172
Short name T771
Test name
Test status
Simulation time 103121513 ps
CPU time 3.53 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 208004 kb
Host smart-44326926-35ee-4e85-a74a-4dcbc3d39de6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711355172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1711355172
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2583105472
Short name T390
Test name
Test status
Simulation time 259610776 ps
CPU time 3.28 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 207936 kb
Host smart-87c32f2f-28c3-49a8-91c0-8c54225e76d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583105472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2583105472
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.108193190
Short name T585
Test name
Test status
Simulation time 66417126 ps
CPU time 2.26 seconds
Started Jul 27 05:42:01 PM PDT 24
Finished Jul 27 05:42:03 PM PDT 24
Peak memory 206660 kb
Host smart-ac4702fb-f76b-416d-a249-378d23e85e4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108193190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.108193190
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.174949610
Short name T624
Test name
Test status
Simulation time 98905519 ps
CPU time 2.74 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 214248 kb
Host smart-5d32a6d1-a32f-4746-96bb-672402451ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174949610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.174949610
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3633227019
Short name T487
Test name
Test status
Simulation time 57774294 ps
CPU time 2.52 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 208328 kb
Host smart-ef270b81-1fc7-498c-a0f1-22b33813738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633227019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3633227019
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.355726023
Short name T304
Test name
Test status
Simulation time 762582888 ps
CPU time 19.32 seconds
Started Jul 27 05:42:01 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 214548 kb
Host smart-9861a5e3-efeb-49d2-9410-99c588122360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355726023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.355726023
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3721976403
Short name T579
Test name
Test status
Simulation time 383544042 ps
CPU time 5.45 seconds
Started Jul 27 05:41:53 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 209748 kb
Host smart-154a5843-ceca-4005-b33c-0390a83b5380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721976403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3721976403
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.296901038
Short name T57
Test name
Test status
Simulation time 183603448 ps
CPU time 2.09 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:56 PM PDT 24
Peak memory 209756 kb
Host smart-e793042b-beab-49f7-8895-47f352856dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296901038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.296901038
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2349374152
Short name T433
Test name
Test status
Simulation time 15350287 ps
CPU time 0.73 seconds
Started Jul 27 05:40:15 PM PDT 24
Finished Jul 27 05:40:16 PM PDT 24
Peak memory 205768 kb
Host smart-85e5c747-4ddc-45b5-8173-c8190320c3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349374152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2349374152
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.241066496
Short name T142
Test name
Test status
Simulation time 73954537 ps
CPU time 2.94 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 215228 kb
Host smart-87d08200-31cf-4bf1-a0f4-515d34fcc2cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241066496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.241066496
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3777644195
Short name T32
Test name
Test status
Simulation time 366058703 ps
CPU time 2.61 seconds
Started Jul 27 05:40:20 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 221084 kb
Host smart-7810b7e0-b1e6-4111-963f-8867559603ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777644195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3777644195
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.378641465
Short name T412
Test name
Test status
Simulation time 68328919 ps
CPU time 2.14 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 208916 kb
Host smart-9253426f-f252-42ad-8808-f7ea983546fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378641465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.378641465
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1630091907
Short name T287
Test name
Test status
Simulation time 391779269 ps
CPU time 6.14 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 214136 kb
Host smart-2397c1d7-1a75-41f1-9827-aa0c9de9b818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630091907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1630091907
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2991864558
Short name T389
Test name
Test status
Simulation time 261366546 ps
CPU time 3.44 seconds
Started Jul 27 05:40:14 PM PDT 24
Finished Jul 27 05:40:18 PM PDT 24
Peak memory 209276 kb
Host smart-619c6cf4-2dc9-45b2-94f3-a888f0fbc825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991864558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2991864558
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1658508493
Short name T388
Test name
Test status
Simulation time 416051338 ps
CPU time 5.36 seconds
Started Jul 27 05:40:18 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 207448 kb
Host smart-157bb8c6-dd5a-4b74-9f0b-fa7a2ad0c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658508493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1658508493
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3584580239
Short name T776
Test name
Test status
Simulation time 284681679 ps
CPU time 2.92 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 206636 kb
Host smart-221ed148-80c3-4dd2-adb0-62c306a80a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584580239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3584580239
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3804448647
Short name T421
Test name
Test status
Simulation time 1085038089 ps
CPU time 3.27 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 206716 kb
Host smart-c01536d4-cc40-4420-b08e-c1079927ca6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804448647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3804448647
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4212380241
Short name T296
Test name
Test status
Simulation time 56048254 ps
CPU time 2.2 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 207196 kb
Host smart-da7faace-a316-4af4-9032-ce75926b9b90
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212380241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4212380241
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4084626444
Short name T700
Test name
Test status
Simulation time 42762839 ps
CPU time 2.48 seconds
Started Jul 27 05:40:26 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 206584 kb
Host smart-533a41bb-acaf-4667-8268-6f4865005f78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084626444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4084626444
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1054240866
Short name T710
Test name
Test status
Simulation time 150262617 ps
CPU time 2.81 seconds
Started Jul 27 05:40:17 PM PDT 24
Finished Jul 27 05:40:20 PM PDT 24
Peak memory 207896 kb
Host smart-4607a027-1f27-47e9-b5bf-cb5a92e18038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054240866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1054240866
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4213536191
Short name T440
Test name
Test status
Simulation time 889776567 ps
CPU time 5.99 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 206636 kb
Host smart-e1ab5eb7-c702-405a-85d4-39eaeb69be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213536191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4213536191
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2451415751
Short name T463
Test name
Test status
Simulation time 45834972 ps
CPU time 2.22 seconds
Started Jul 27 05:40:16 PM PDT 24
Finished Jul 27 05:40:19 PM PDT 24
Peak memory 209652 kb
Host smart-b4a79a3e-30b0-4f52-b60e-60a8b771caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451415751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2451415751
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1126658641
Short name T409
Test name
Test status
Simulation time 19512660 ps
CPU time 0.87 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 205728 kb
Host smart-ddc3b35e-62c2-40b6-abcf-1034007529a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126658641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1126658641
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1455894462
Short name T396
Test name
Test status
Simulation time 200433714 ps
CPU time 3.53 seconds
Started Jul 27 05:41:57 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 214176 kb
Host smart-d13afd65-3d23-4686-beb1-189c00a886bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455894462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1455894462
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1086660802
Short name T716
Test name
Test status
Simulation time 130447500 ps
CPU time 3.9 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 220584 kb
Host smart-f7125131-3655-4d1e-8970-068fb3abe687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086660802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1086660802
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1812119485
Short name T673
Test name
Test status
Simulation time 136427263 ps
CPU time 3.93 seconds
Started Jul 27 05:41:55 PM PDT 24
Finished Jul 27 05:41:59 PM PDT 24
Peak memory 209500 kb
Host smart-6b4f4749-6e35-4ed3-afc4-4a8ef72250ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812119485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1812119485
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1483024088
Short name T90
Test name
Test status
Simulation time 947692641 ps
CPU time 11.83 seconds
Started Jul 27 05:41:56 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 214092 kb
Host smart-cdb8ad78-5d74-4fbe-834f-a0b55b700dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483024088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1483024088
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3973449909
Short name T364
Test name
Test status
Simulation time 950070544 ps
CPU time 8.19 seconds
Started Jul 27 05:41:56 PM PDT 24
Finished Jul 27 05:42:05 PM PDT 24
Peak memory 219680 kb
Host smart-419c9c48-a814-4281-8be3-2b5b8f5f9691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973449909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3973449909
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1655604064
Short name T335
Test name
Test status
Simulation time 401656529 ps
CPU time 3.54 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 208440 kb
Host smart-c5ae52a4-a361-4efe-b6c6-b79c3ece5299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655604064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1655604064
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.667069218
Short name T400
Test name
Test status
Simulation time 117412727 ps
CPU time 3.96 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 207564 kb
Host smart-514ca6df-9117-40a0-93da-31edabf6bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667069218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.667069218
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1942995915
Short name T558
Test name
Test status
Simulation time 204677386 ps
CPU time 2.92 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 206896 kb
Host smart-c2a8ad3f-dd0a-4d81-8026-db7a11514932
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942995915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1942995915
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1220368285
Short name T613
Test name
Test status
Simulation time 36255840 ps
CPU time 2.56 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 206752 kb
Host smart-7fdf6070-c5cb-466a-883b-da166a51c06d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220368285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1220368285
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2115899271
Short name T733
Test name
Test status
Simulation time 1530031288 ps
CPU time 17.74 seconds
Started Jul 27 05:41:57 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 208532 kb
Host smart-58dbec2e-91fe-45d0-97cf-25efb8161997
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115899271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2115899271
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1403906067
Short name T862
Test name
Test status
Simulation time 60189422 ps
CPU time 1.81 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 209004 kb
Host smart-eb7511bb-c775-4d22-b70c-25327c43757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403906067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1403906067
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2566091808
Short name T717
Test name
Test status
Simulation time 64546604 ps
CPU time 2.69 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:41:57 PM PDT 24
Peak memory 205900 kb
Host smart-2ac59dc4-c070-497a-9453-f5e303dc48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566091808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2566091808
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1965052743
Short name T880
Test name
Test status
Simulation time 492726558 ps
CPU time 7.41 seconds
Started Jul 27 05:42:04 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 218576 kb
Host smart-32e57e12-4042-4ab0-9a3b-724cb058884f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965052743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1965052743
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2023361958
Short name T130
Test name
Test status
Simulation time 293722491 ps
CPU time 11.49 seconds
Started Jul 27 05:41:54 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 222236 kb
Host smart-5cb1ce84-5cf2-4e88-a4f2-d571b3a84fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023361958 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2023361958
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.385789297
Short name T795
Test name
Test status
Simulation time 2747306355 ps
CPU time 35.23 seconds
Started Jul 27 05:41:56 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 208880 kb
Host smart-3483e62a-1c35-431b-90c1-8cf22bdcb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385789297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.385789297
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.620441476
Short name T169
Test name
Test status
Simulation time 56046148 ps
CPU time 1.82 seconds
Started Jul 27 05:42:04 PM PDT 24
Finished Jul 27 05:42:06 PM PDT 24
Peak memory 209684 kb
Host smart-d41f32be-d431-4f8a-bc30-3e9982ec188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620441476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.620441476
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.969919284
Short name T764
Test name
Test status
Simulation time 48854954 ps
CPU time 0.93 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 205944 kb
Host smart-e0ba450b-2239-4d4a-8772-cd109da79100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969919284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.969919284
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2949681307
Short name T274
Test name
Test status
Simulation time 794033205 ps
CPU time 6.48 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 208932 kb
Host smart-cd5132c2-a67e-4358-a232-905f1e54b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949681307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2949681307
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3463888015
Short name T774
Test name
Test status
Simulation time 114675348 ps
CPU time 5.2 seconds
Started Jul 27 05:42:15 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 214032 kb
Host smart-f498addf-843c-4d8d-8073-84f80e1daed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463888015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3463888015
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3682711761
Short name T778
Test name
Test status
Simulation time 436542435 ps
CPU time 5.41 seconds
Started Jul 27 05:42:06 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 222140 kb
Host smart-9746429c-d86a-41d9-9c97-94607f2d515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682711761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3682711761
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.603636710
Short name T347
Test name
Test status
Simulation time 91369746 ps
CPU time 3.79 seconds
Started Jul 27 05:42:09 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 208984 kb
Host smart-ce769262-97d4-43d8-82fc-044c0c4880a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603636710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.603636710
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.788871727
Short name T273
Test name
Test status
Simulation time 569651817 ps
CPU time 4.13 seconds
Started Jul 27 05:42:06 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 207376 kb
Host smart-a7844b62-6b52-4ff8-b7d7-4a88d10492e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788871727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.788871727
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2302120441
Short name T193
Test name
Test status
Simulation time 125853917 ps
CPU time 2.79 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:23 PM PDT 24
Peak memory 206708 kb
Host smart-7c5c2200-5f11-4e3f-81cf-2c44ded72846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302120441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2302120441
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2880738590
Short name T438
Test name
Test status
Simulation time 110167204 ps
CPU time 3.81 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 208376 kb
Host smart-d313c93b-21f3-4b92-99d2-0fd0d0f4f113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880738590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2880738590
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.973405566
Short name T888
Test name
Test status
Simulation time 1267847653 ps
CPU time 4.1 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 206752 kb
Host smart-ef71b256-2802-4445-802a-28a6219eeb56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973405566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.973405566
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.77985248
Short name T644
Test name
Test status
Simulation time 452316407 ps
CPU time 6 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:17 PM PDT 24
Peak memory 208584 kb
Host smart-18c53ced-56d1-4e6f-b5fc-8e525cc0aa9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77985248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.77985248
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.613602586
Short name T453
Test name
Test status
Simulation time 75688252 ps
CPU time 2.53 seconds
Started Jul 27 05:42:09 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 207960 kb
Host smart-bc81a0df-2d14-4c6a-8858-04adf2f665c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613602586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.613602586
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2102137998
Short name T387
Test name
Test status
Simulation time 3294411501 ps
CPU time 33.53 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 208456 kb
Host smart-130bf371-c41f-45d5-9775-6f3562903aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102137998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2102137998
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2981690662
Short name T199
Test name
Test status
Simulation time 621932350 ps
CPU time 17.02 seconds
Started Jul 27 05:41:59 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 222160 kb
Host smart-4b1aeafc-b69d-4c03-8abe-3f55672dee73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981690662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2981690662
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3428253389
Short name T540
Test name
Test status
Simulation time 53775592 ps
CPU time 3.01 seconds
Started Jul 27 05:42:01 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 208484 kb
Host smart-a3da4a9f-82c4-40bb-b154-4ab5b33c506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428253389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3428253389
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1145168435
Short name T64
Test name
Test status
Simulation time 2175772519 ps
CPU time 21.29 seconds
Started Jul 27 05:42:02 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 211008 kb
Host smart-0e00a341-67c5-42a3-8aee-ea2a23838b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145168435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1145168435
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2435080724
Short name T94
Test name
Test status
Simulation time 35543366 ps
CPU time 0.85 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 205812 kb
Host smart-0d075299-85ba-488c-be63-4c4b98459384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435080724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2435080724
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2967934297
Short name T297
Test name
Test status
Simulation time 3342608929 ps
CPU time 46.28 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:53 PM PDT 24
Peak memory 214372 kb
Host smart-4bca24ab-15a4-4140-87fd-0c9e1ef378fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967934297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2967934297
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2539648708
Short name T530
Test name
Test status
Simulation time 100915100 ps
CPU time 3 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:08 PM PDT 24
Peak memory 214364 kb
Host smart-1978d190-ccbb-4d26-b084-36b6380ef207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539648708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2539648708
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1808826576
Short name T331
Test name
Test status
Simulation time 1147572033 ps
CPU time 12.66 seconds
Started Jul 27 05:42:08 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 214244 kb
Host smart-38d656ae-373a-43ac-a4eb-8d8dd33f6978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808826576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1808826576
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4040453348
Short name T826
Test name
Test status
Simulation time 98873109 ps
CPU time 2.23 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 214244 kb
Host smart-0bed7eae-13f0-41f3-828c-03ee40d5be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040453348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4040453348
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1269590899
Short name T277
Test name
Test status
Simulation time 99899177 ps
CPU time 3.68 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 222024 kb
Host smart-394bedcb-1151-41d7-96dd-5f3a174cbde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269590899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1269590899
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4082952495
Short name T384
Test name
Test status
Simulation time 513057249 ps
CPU time 5.95 seconds
Started Jul 27 05:42:09 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 220044 kb
Host smart-e2ff6706-d612-437d-b88b-30e0b74498e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082952495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4082952495
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.836996479
Short name T476
Test name
Test status
Simulation time 99784836 ps
CPU time 3.24 seconds
Started Jul 27 05:42:18 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 208444 kb
Host smart-55cad7a1-4ede-48b5-a936-387929ef8e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836996479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.836996479
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4097258751
Short name T652
Test name
Test status
Simulation time 124127771 ps
CPU time 3.7 seconds
Started Jul 27 05:42:08 PM PDT 24
Finished Jul 27 05:42:17 PM PDT 24
Peak memory 206656 kb
Host smart-39e21518-82ac-421f-8d7c-8507bbbb2492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097258751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4097258751
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3921559485
Short name T449
Test name
Test status
Simulation time 114318723 ps
CPU time 2.98 seconds
Started Jul 27 05:42:01 PM PDT 24
Finished Jul 27 05:42:04 PM PDT 24
Peak memory 208380 kb
Host smart-4e24d112-921c-4138-b162-57749aa86217
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921559485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3921559485
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.568436679
Short name T246
Test name
Test status
Simulation time 249997989 ps
CPU time 4.78 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 208180 kb
Host smart-1056e6b0-65f9-49d7-a077-253ebf05f319
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568436679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.568436679
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.965106423
Short name T655
Test name
Test status
Simulation time 161531164 ps
CPU time 2.47 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 207060 kb
Host smart-f3974342-2788-400c-8ae8-2d3713af5a5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965106423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.965106423
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2466999656
Short name T735
Test name
Test status
Simulation time 113386836 ps
CPU time 2.14 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 208096 kb
Host smart-d6a4d15b-983b-49f6-ae0f-33be37955f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466999656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2466999656
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3097135157
Short name T591
Test name
Test status
Simulation time 33631161 ps
CPU time 2.3 seconds
Started Jul 27 05:42:22 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 207108 kb
Host smart-7c9727d1-4fac-4b6f-bf1d-45cd1705cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097135157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3097135157
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4279794158
Short name T329
Test name
Test status
Simulation time 1027640773 ps
CPU time 42.37 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:54 PM PDT 24
Peak memory 221680 kb
Host smart-59355397-44c8-4802-a575-a7c8d2e8219a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279794158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4279794158
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1671197561
Short name T299
Test name
Test status
Simulation time 9746611397 ps
CPU time 81.02 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:43:41 PM PDT 24
Peak memory 214128 kb
Host smart-abd67a30-251a-47b2-a99d-cc8a49ed251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671197561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1671197561
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4162751867
Short name T374
Test name
Test status
Simulation time 106307647 ps
CPU time 2.87 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:10 PM PDT 24
Peak memory 210040 kb
Host smart-3e6c09e6-f530-4ef6-8677-df4d919d46aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162751867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4162751867
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3830170271
Short name T95
Test name
Test status
Simulation time 19186516 ps
CPU time 0.83 seconds
Started Jul 27 05:42:19 PM PDT 24
Finished Jul 27 05:42:19 PM PDT 24
Peak memory 205848 kb
Host smart-add60004-7ac0-4459-86c2-71d0243f095d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830170271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3830170271
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.53874929
Short name T828
Test name
Test status
Simulation time 156790100 ps
CPU time 8.54 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 215656 kb
Host smart-582ffc3a-f1ef-4180-8633-d0036286f40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53874929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.53874929
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4148703884
Short name T60
Test name
Test status
Simulation time 129278212 ps
CPU time 3.33 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 208808 kb
Host smart-bc9d99ac-4bf9-4888-9ef3-9fa4d5f14d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148703884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4148703884
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.88759047
Short name T365
Test name
Test status
Simulation time 75209181 ps
CPU time 3.65 seconds
Started Jul 27 05:42:21 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 214148 kb
Host smart-ca829de4-35ed-4e00-8cc1-aebd5f2e3db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88759047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.88759047
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1503011855
Short name T664
Test name
Test status
Simulation time 37211640 ps
CPU time 2.41 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 220856 kb
Host smart-38e47449-cae4-4f1c-9f9d-027158e34c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503011855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1503011855
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1583445103
Short name T65
Test name
Test status
Simulation time 431662372 ps
CPU time 4.88 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 214136 kb
Host smart-86a8eb59-826b-4381-893b-0945c3666344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583445103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1583445103
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1544839887
Short name T448
Test name
Test status
Simulation time 918046893 ps
CPU time 27.11 seconds
Started Jul 27 05:42:12 PM PDT 24
Finished Jul 27 05:42:40 PM PDT 24
Peak memory 209616 kb
Host smart-f6ee2595-7b59-41fb-bf6c-892c12b32ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544839887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1544839887
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1228220374
Short name T262
Test name
Test status
Simulation time 451687019 ps
CPU time 5.36 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 208236 kb
Host smart-58656ca5-e524-4ed3-9042-22cf621d9943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228220374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1228220374
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3021534080
Short name T514
Test name
Test status
Simulation time 7485128444 ps
CPU time 47.57 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:58 PM PDT 24
Peak memory 208728 kb
Host smart-23b0b806-f257-49f2-a88d-3a4d4b5a9cd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021534080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3021534080
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1843572159
Short name T665
Test name
Test status
Simulation time 915073028 ps
CPU time 23.3 seconds
Started Jul 27 05:42:01 PM PDT 24
Finished Jul 27 05:42:25 PM PDT 24
Peak memory 208040 kb
Host smart-5521717d-3581-4ea4-b82b-cd322f011157
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843572159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1843572159
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.627544339
Short name T859
Test name
Test status
Simulation time 440896120 ps
CPU time 4.02 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:17 PM PDT 24
Peak memory 208328 kb
Host smart-961614e8-3582-4e3c-8c52-4137d58981fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627544339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.627544339
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2095910574
Short name T135
Test name
Test status
Simulation time 81437339 ps
CPU time 2.25 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:19 PM PDT 24
Peak memory 208712 kb
Host smart-1d34c35d-76f7-4498-81b3-cfe25ea47ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095910574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2095910574
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3906582562
Short name T515
Test name
Test status
Simulation time 172842545 ps
CPU time 4.52 seconds
Started Jul 27 05:42:09 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 208272 kb
Host smart-a12258bc-c7aa-4218-a3aa-d2b540aafbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906582562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3906582562
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1328897045
Short name T301
Test name
Test status
Simulation time 131991540 ps
CPU time 2.88 seconds
Started Jul 27 05:42:15 PM PDT 24
Finished Jul 27 05:42:18 PM PDT 24
Peak memory 209072 kb
Host smart-fc5bf0b4-dc51-40bc-9815-f795a926a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328897045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1328897045
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1556152348
Short name T690
Test name
Test status
Simulation time 410401307 ps
CPU time 3.97 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 210160 kb
Host smart-193680a8-70e1-4252-be5d-9390b5e31eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556152348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1556152348
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2358951824
Short name T597
Test name
Test status
Simulation time 38676399 ps
CPU time 0.75 seconds
Started Jul 27 05:42:12 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 205860 kb
Host smart-d8cce5b1-db88-4bb1-93d4-456457ed1862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358951824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2358951824
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.400920442
Short name T402
Test name
Test status
Simulation time 53782066 ps
CPU time 4 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 214140 kb
Host smart-555ca85c-38c7-4f96-b98a-b94391fc632f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400920442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.400920442
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2022996116
Short name T362
Test name
Test status
Simulation time 61013005 ps
CPU time 1.25 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 207248 kb
Host smart-116309c9-bf6b-4d55-861f-9a36e8af7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022996116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2022996116
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.430073594
Short name T830
Test name
Test status
Simulation time 1356462167 ps
CPU time 20.84 seconds
Started Jul 27 05:42:16 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 214076 kb
Host smart-6e4d666e-84f0-4d8c-a460-412d6201b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430073594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.430073594
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.469217652
Short name T102
Test name
Test status
Simulation time 158280007 ps
CPU time 2.43 seconds
Started Jul 27 05:42:12 PM PDT 24
Finished Jul 27 05:42:14 PM PDT 24
Peak memory 222148 kb
Host smart-78f6afdd-2cc5-4584-bc83-42ff65b9aede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469217652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.469217652
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2429025630
Short name T69
Test name
Test status
Simulation time 134432576 ps
CPU time 3.59 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 210324 kb
Host smart-e54abc3f-7ee4-4113-8a12-02d584e29709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429025630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2429025630
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.785609542
Short name T677
Test name
Test status
Simulation time 8769916877 ps
CPU time 55.38 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:43:06 PM PDT 24
Peak memory 207304 kb
Host smart-2caa8e00-c906-490c-9845-ecf24b4854ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785609542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.785609542
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3136422956
Short name T680
Test name
Test status
Simulation time 139566800 ps
CPU time 4.49 seconds
Started Jul 27 05:42:07 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 208248 kb
Host smart-bcd94f57-62df-4327-963e-ecc7a1277435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136422956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3136422956
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3205197309
Short name T495
Test name
Test status
Simulation time 54165402 ps
CPU time 2.47 seconds
Started Jul 27 05:42:05 PM PDT 24
Finished Jul 27 05:42:07 PM PDT 24
Peak memory 206808 kb
Host smart-cdb39962-4e7a-4411-a34d-a3f602db8a23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205197309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3205197309
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2967012339
Short name T443
Test name
Test status
Simulation time 692507659 ps
CPU time 5.57 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 207840 kb
Host smart-7f5f89b6-2c6e-40d9-8d07-08489d09a351
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967012339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2967012339
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4104507876
Short name T423
Test name
Test status
Simulation time 311235754 ps
CPU time 2.91 seconds
Started Jul 27 05:42:08 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 208516 kb
Host smart-ed462a96-b0cb-4acd-badd-ccc623edbabf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104507876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4104507876
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1057402290
Short name T692
Test name
Test status
Simulation time 2518128551 ps
CPU time 17.31 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 208104 kb
Host smart-de138469-0998-4c8c-b117-f9e89f55e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057402290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1057402290
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2883308777
Short name T482
Test name
Test status
Simulation time 1013467023 ps
CPU time 22.67 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:33 PM PDT 24
Peak memory 207648 kb
Host smart-1faf4fed-95d0-44fd-ae9e-7f9b9de7e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883308777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2883308777
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1541608018
Short name T77
Test name
Test status
Simulation time 3083295618 ps
CPU time 20.56 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:40 PM PDT 24
Peak memory 222428 kb
Host smart-7963e80e-6404-4676-8694-e95f433a51d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541608018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1541608018
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.60505821
Short name T337
Test name
Test status
Simulation time 84035911 ps
CPU time 3.89 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 218212 kb
Host smart-083993d6-5276-434c-98e8-4351fd3849ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60505821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.60505821
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3184780234
Short name T163
Test name
Test status
Simulation time 56523928 ps
CPU time 2.85 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 209660 kb
Host smart-39bce3b0-1c55-42b2-951d-7af069e5ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184780234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3184780234
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2666669788
Short name T713
Test name
Test status
Simulation time 16509305 ps
CPU time 0.81 seconds
Started Jul 27 05:42:14 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 205852 kb
Host smart-887fbf35-8d61-4f29-9d0f-bc1dbd2cfce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666669788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2666669788
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2890441321
Short name T827
Test name
Test status
Simulation time 974023658 ps
CPU time 42.51 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:56 PM PDT 24
Peak memory 214448 kb
Host smart-cb0f6288-b3b3-420b-98ed-340574ea80bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890441321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2890441321
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2440321373
Short name T30
Test name
Test status
Simulation time 91971439 ps
CPU time 3.97 seconds
Started Jul 27 05:42:08 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 213996 kb
Host smart-bede1eab-44c9-421f-b624-60484bcde75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440321373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2440321373
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3218451258
Short name T775
Test name
Test status
Simulation time 83960998 ps
CPU time 2.28 seconds
Started Jul 27 05:42:16 PM PDT 24
Finished Jul 27 05:42:18 PM PDT 24
Peak memory 208656 kb
Host smart-c04ef6c3-d6e5-4330-b852-156b0f096478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218451258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3218451258
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1390135867
Short name T600
Test name
Test status
Simulation time 204672295 ps
CPU time 2.99 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 214172 kb
Host smart-0ef65684-a391-42da-b4d5-00ac90379651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390135867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1390135867
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1653596038
Short name T236
Test name
Test status
Simulation time 270239101 ps
CPU time 3.43 seconds
Started Jul 27 05:42:11 PM PDT 24
Finished Jul 27 05:42:15 PM PDT 24
Peak memory 214004 kb
Host smart-5ead0b06-6f3a-43e7-8648-1137e14f096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653596038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1653596038
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1432677387
Short name T496
Test name
Test status
Simulation time 287459422 ps
CPU time 3.68 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 209360 kb
Host smart-c6c23061-e3eb-4183-9de3-1a6cf858a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432677387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1432677387
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3037720360
Short name T820
Test name
Test status
Simulation time 7107319334 ps
CPU time 45.84 seconds
Started Jul 27 05:42:12 PM PDT 24
Finished Jul 27 05:42:58 PM PDT 24
Peak memory 208312 kb
Host smart-37f3f7d5-dfa1-4433-af21-7a5a822a876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037720360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3037720360
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.591311447
Short name T343
Test name
Test status
Simulation time 129405167 ps
CPU time 2.56 seconds
Started Jul 27 05:42:25 PM PDT 24
Finished Jul 27 05:42:28 PM PDT 24
Peak memory 206540 kb
Host smart-f718492c-75af-4797-be6c-dfe0110eafd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591311447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.591311447
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2601976287
Short name T493
Test name
Test status
Simulation time 332136275 ps
CPU time 4.53 seconds
Started Jul 27 05:42:14 PM PDT 24
Finished Jul 27 05:42:19 PM PDT 24
Peak memory 208484 kb
Host smart-095747be-82eb-4284-8798-9321a1086a5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601976287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2601976287
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1720072549
Short name T822
Test name
Test status
Simulation time 86965789 ps
CPU time 2.88 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:16 PM PDT 24
Peak memory 206768 kb
Host smart-c2a50955-f5e7-4619-a970-9581e43c37d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720072549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1720072549
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1015717669
Short name T669
Test name
Test status
Simulation time 465459104 ps
CPU time 15.76 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 208344 kb
Host smart-07077554-f879-4243-ae0e-0b9210d751d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015717669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1015717669
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.328534351
Short name T882
Test name
Test status
Simulation time 493159954 ps
CPU time 3.74 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 207684 kb
Host smart-5602d5c5-174d-454e-9857-8c721d422ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328534351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.328534351
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2635243493
Short name T805
Test name
Test status
Simulation time 265124743 ps
CPU time 2.81 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 208112 kb
Host smart-d687506d-0f09-4ba0-a836-7c4059200046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635243493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2635243493
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2646756785
Short name T617
Test name
Test status
Simulation time 106513572 ps
CPU time 4.69 seconds
Started Jul 27 05:42:13 PM PDT 24
Finished Jul 27 05:42:18 PM PDT 24
Peak memory 210036 kb
Host smart-211ee6ac-d7ea-4bb6-b211-3434eae0f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646756785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2646756785
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.209694519
Short name T485
Test name
Test status
Simulation time 43192910 ps
CPU time 1.95 seconds
Started Jul 27 05:42:10 PM PDT 24
Finished Jul 27 05:42:12 PM PDT 24
Peak memory 209752 kb
Host smart-605dab85-7adb-48a3-9f92-f784d1032350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209694519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.209694519
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3197866726
Short name T637
Test name
Test status
Simulation time 11243242 ps
CPU time 0.72 seconds
Started Jul 27 05:42:31 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 205836 kb
Host smart-fd6bb2fe-99c1-46e5-89fc-6f12011a8127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197866726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3197866726
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.14627853
Short name T150
Test name
Test status
Simulation time 132925454 ps
CPU time 4.94 seconds
Started Jul 27 05:42:21 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 214716 kb
Host smart-9e1d6b89-e40c-4c6a-babe-17e4ae67b5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14627853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.14627853
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.712307858
Short name T465
Test name
Test status
Simulation time 1538205770 ps
CPU time 24.7 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:53 PM PDT 24
Peak memory 209376 kb
Host smart-6da0296f-e0c8-4a2b-bc2b-de39c23a7f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712307858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.712307858
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1020508082
Short name T93
Test name
Test status
Simulation time 562812652 ps
CPU time 5.8 seconds
Started Jul 27 05:42:21 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 214360 kb
Host smart-a77b20d2-d562-47d9-b842-a6e4841c177d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020508082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1020508082
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2335685917
Short name T656
Test name
Test status
Simulation time 110579377 ps
CPU time 2.4 seconds
Started Jul 27 05:42:25 PM PDT 24
Finished Jul 27 05:42:27 PM PDT 24
Peak memory 214048 kb
Host smart-dc8ef186-aa72-4c35-838b-6673fd60d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335685917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2335685917
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2643948605
Short name T251
Test name
Test status
Simulation time 127076829 ps
CPU time 3.36 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 217860 kb
Host smart-bf66e17e-43be-40a9-99e4-df8798f2dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643948605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2643948605
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1806882978
Short name T313
Test name
Test status
Simulation time 7641309441 ps
CPU time 75.56 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:43:35 PM PDT 24
Peak memory 209696 kb
Host smart-9123fdc4-3bed-4f07-b3f5-075db4a9c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806882978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1806882978
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2506670915
Short name T741
Test name
Test status
Simulation time 194951783 ps
CPU time 2.27 seconds
Started Jul 27 05:42:30 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 206668 kb
Host smart-6b5fa42a-ee2e-4378-84f8-cef8788982a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506670915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2506670915
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.661411814
Short name T439
Test name
Test status
Simulation time 33108022 ps
CPU time 2.15 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 206756 kb
Host smart-ec1bf530-d9eb-41d6-a93a-bbb95b003750
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661411814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.661411814
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.4204378908
Short name T570
Test name
Test status
Simulation time 160810239 ps
CPU time 2.71 seconds
Started Jul 27 05:42:32 PM PDT 24
Finished Jul 27 05:42:35 PM PDT 24
Peak memory 208576 kb
Host smart-fa18a434-b206-4770-a55c-93772b069364
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204378908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.4204378908
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3498586170
Short name T757
Test name
Test status
Simulation time 683411573 ps
CPU time 3.08 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:31 PM PDT 24
Peak memory 208272 kb
Host smart-55a32815-d463-45dd-8bd8-4faec3f0b89b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498586170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3498586170
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2882667868
Short name T780
Test name
Test status
Simulation time 118535935 ps
CPU time 1.73 seconds
Started Jul 27 05:42:20 PM PDT 24
Finished Jul 27 05:42:22 PM PDT 24
Peak memory 207340 kb
Host smart-d1a17ace-928c-4142-9051-18bc73dcf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882667868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2882667868
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.734017291
Short name T417
Test name
Test status
Simulation time 72205586 ps
CPU time 1.86 seconds
Started Jul 27 05:42:24 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 208568 kb
Host smart-08fd7a37-6f02-41ab-9c48-549445bcae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734017291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.734017291
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3999074143
Short name T66
Test name
Test status
Simulation time 756827899 ps
CPU time 36.93 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:43:06 PM PDT 24
Peak memory 215848 kb
Host smart-03877608-6775-4bb6-b57f-24a0ba4481ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999074143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3999074143
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1181522220
Short name T340
Test name
Test status
Simulation time 4234953260 ps
CPU time 13.85 seconds
Started Jul 27 05:42:17 PM PDT 24
Finished Jul 27 05:42:31 PM PDT 24
Peak memory 222384 kb
Host smart-75d22e7e-9b14-4796-b37f-ec4b63abbcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181522220 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1181522220
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4034075624
Short name T608
Test name
Test status
Simulation time 368398840 ps
CPU time 6.8 seconds
Started Jul 27 05:42:34 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 209824 kb
Host smart-bb84281b-1837-4458-8972-c16fb9c0c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034075624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4034075624
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1131876467
Short name T170
Test name
Test status
Simulation time 362330316 ps
CPU time 3.15 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 209980 kb
Host smart-b5a2a6e8-635c-4622-b7a8-dd5f055fbc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131876467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1131876467
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2741581972
Short name T899
Test name
Test status
Simulation time 22916962 ps
CPU time 0.75 seconds
Started Jul 27 05:42:40 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 205784 kb
Host smart-6fc9cdd3-6d74-4ed2-869e-fc1c31f04120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741581972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2741581972
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.135533089
Short name T9
Test name
Test status
Simulation time 140755631 ps
CPU time 4.95 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:33 PM PDT 24
Peak memory 222576 kb
Host smart-32f2610f-9e76-4f62-a60d-4d9fd5b75f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135533089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.135533089
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.230707069
Short name T266
Test name
Test status
Simulation time 54160953 ps
CPU time 3.58 seconds
Started Jul 27 05:42:31 PM PDT 24
Finished Jul 27 05:42:35 PM PDT 24
Peak memory 217948 kb
Host smart-0dabc8f4-c361-4107-8ac6-ea0208db6adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230707069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.230707069
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3224610050
Short name T84
Test name
Test status
Simulation time 39542179 ps
CPU time 2.96 seconds
Started Jul 27 05:42:23 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 214300 kb
Host smart-bbd8ec90-3a9e-4886-87a0-509cbde10662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224610050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3224610050
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.995703631
Short name T260
Test name
Test status
Simulation time 61803622 ps
CPU time 3.63 seconds
Started Jul 27 05:42:39 PM PDT 24
Finished Jul 27 05:42:43 PM PDT 24
Peak memory 222104 kb
Host smart-d7aa8e60-a037-4e84-b487-4ff145e51132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995703631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.995703631
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1072220932
Short name T480
Test name
Test status
Simulation time 45884346 ps
CPU time 3.16 seconds
Started Jul 27 05:42:32 PM PDT 24
Finished Jul 27 05:42:36 PM PDT 24
Peak memory 222244 kb
Host smart-889aa705-dc5e-4846-bcc5-ead16f3665a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072220932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1072220932
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2164880007
Short name T269
Test name
Test status
Simulation time 3305843028 ps
CPU time 47.53 seconds
Started Jul 27 05:42:36 PM PDT 24
Finished Jul 27 05:43:23 PM PDT 24
Peak memory 208572 kb
Host smart-5e53d4b7-c467-4bc7-a647-55cf7fdaa3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164880007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2164880007
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1766888414
Short name T650
Test name
Test status
Simulation time 28476522 ps
CPU time 2.08 seconds
Started Jul 27 05:42:18 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 208372 kb
Host smart-c31bebff-d00f-4cbd-9f0e-8aac5fd2e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766888414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1766888414
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3883716884
Short name T705
Test name
Test status
Simulation time 530286732 ps
CPU time 4.95 seconds
Started Jul 27 05:42:19 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 207988 kb
Host smart-2a3e9ca2-876a-4739-9f8b-12e3cec31c71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883716884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3883716884
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1276015343
Short name T138
Test name
Test status
Simulation time 220667992 ps
CPU time 7.67 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:36 PM PDT 24
Peak memory 206948 kb
Host smart-4f62fc3a-7579-45fd-9e82-844387a328e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276015343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1276015343
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.105224400
Short name T766
Test name
Test status
Simulation time 1679625221 ps
CPU time 4.9 seconds
Started Jul 27 05:42:30 PM PDT 24
Finished Jul 27 05:42:35 PM PDT 24
Peak memory 207720 kb
Host smart-7c796ac4-dc8b-438f-9ea7-a493a1f5faae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105224400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.105224400
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1650662346
Short name T483
Test name
Test status
Simulation time 126594836 ps
CPU time 5.03 seconds
Started Jul 27 05:42:27 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 218032 kb
Host smart-ededeb76-3e5e-40ee-83fc-40a7e08f1761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650662346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1650662346
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3865718116
Short name T668
Test name
Test status
Simulation time 446835887 ps
CPU time 3.37 seconds
Started Jul 27 05:42:16 PM PDT 24
Finished Jul 27 05:42:20 PM PDT 24
Peak memory 208260 kb
Host smart-fa217f53-a3ed-4bc5-a41f-08f64e6f1444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865718116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3865718116
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.560949476
Short name T722
Test name
Test status
Simulation time 13857805274 ps
CPU time 87.19 seconds
Started Jul 27 05:42:25 PM PDT 24
Finished Jul 27 05:43:53 PM PDT 24
Peak memory 216520 kb
Host smart-041a623b-b295-4cf5-82b0-8b5497865fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560949476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.560949476
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.962493568
Short name T78
Test name
Test status
Simulation time 167784078 ps
CPU time 4.93 seconds
Started Jul 27 05:42:36 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 209268 kb
Host smart-a7d65f81-56d3-419c-855c-496003ef732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962493568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.962493568
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2542706289
Short name T674
Test name
Test status
Simulation time 64659875 ps
CPU time 2.08 seconds
Started Jul 27 05:42:26 PM PDT 24
Finished Jul 27 05:42:28 PM PDT 24
Peak memory 210064 kb
Host smart-359db0fa-9d1d-4877-8d0a-93761a337446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542706289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2542706289
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.673018664
Short name T767
Test name
Test status
Simulation time 28614416 ps
CPU time 0.78 seconds
Started Jul 27 05:42:46 PM PDT 24
Finished Jul 27 05:42:47 PM PDT 24
Peak memory 205784 kb
Host smart-305458a7-f21e-4185-a546-afb7986e6f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673018664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.673018664
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3379178446
Short name T810
Test name
Test status
Simulation time 225100592 ps
CPU time 2.07 seconds
Started Jul 27 05:42:50 PM PDT 24
Finished Jul 27 05:42:53 PM PDT 24
Peak memory 210512 kb
Host smart-0c85333d-afc9-4131-b096-8e52b18adf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379178446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3379178446
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3563332074
Short name T288
Test name
Test status
Simulation time 1363699368 ps
CPU time 8.43 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 208716 kb
Host smart-358e90dc-46a4-4bbc-ae00-3355eb4d90eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563332074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3563332074
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1374101892
Short name T688
Test name
Test status
Simulation time 127667884 ps
CPU time 2.75 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:31 PM PDT 24
Peak memory 222160 kb
Host smart-0e57839f-4013-42ab-848b-3da772c454da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374101892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1374101892
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3618088862
Short name T584
Test name
Test status
Simulation time 43415757 ps
CPU time 2.69 seconds
Started Jul 27 05:42:32 PM PDT 24
Finished Jul 27 05:42:35 PM PDT 24
Peak memory 215060 kb
Host smart-e98b5009-7fe1-441f-bcac-8216a6959c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618088862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3618088862
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3241023668
Short name T580
Test name
Test status
Simulation time 68177316 ps
CPU time 4.54 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:34 PM PDT 24
Peak memory 214148 kb
Host smart-c3e9dee1-8750-4fb2-aa86-23866bd389c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241023668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3241023668
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1017725730
Short name T180
Test name
Test status
Simulation time 101049792 ps
CPU time 2.67 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 206628 kb
Host smart-9466e639-68e8-4437-b3b1-b6730a39275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017725730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1017725730
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.897865283
Short name T723
Test name
Test status
Simulation time 528183861 ps
CPU time 3.44 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:32 PM PDT 24
Peak memory 208800 kb
Host smart-35543493-e68d-499e-a97a-93a75f6fade0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897865283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.897865283
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4126047868
Short name T100
Test name
Test status
Simulation time 371857685 ps
CPU time 3.53 seconds
Started Jul 27 05:42:25 PM PDT 24
Finished Jul 27 05:42:29 PM PDT 24
Peak memory 206616 kb
Host smart-e278293c-7ad8-4839-94a9-449b725ce659
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126047868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4126047868
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3297023083
Short name T446
Test name
Test status
Simulation time 119788428 ps
CPU time 2.85 seconds
Started Jul 27 05:42:34 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 208364 kb
Host smart-45c61d24-0071-45b9-b181-2d3a6ee7828d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297023083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3297023083
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.962462242
Short name T535
Test name
Test status
Simulation time 147984466 ps
CPU time 3.41 seconds
Started Jul 27 05:42:30 PM PDT 24
Finished Jul 27 05:42:34 PM PDT 24
Peak memory 208568 kb
Host smart-20615972-00c3-4028-98af-ebe1ffbf4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962462242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.962462242
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3615483504
Short name T441
Test name
Test status
Simulation time 719960582 ps
CPU time 3.86 seconds
Started Jul 27 05:42:40 PM PDT 24
Finished Jul 27 05:42:44 PM PDT 24
Peak memory 208128 kb
Host smart-360ba3b3-cc70-48ec-8c2d-7e18278eeb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615483504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3615483504
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.370039806
Short name T759
Test name
Test status
Simulation time 464859447 ps
CPU time 17.91 seconds
Started Jul 27 05:42:36 PM PDT 24
Finished Jul 27 05:42:54 PM PDT 24
Peak memory 221436 kb
Host smart-d2315e4d-c902-4a7d-915f-be0343c98828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370039806 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.370039806
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2456529515
Short name T272
Test name
Test status
Simulation time 69887974 ps
CPU time 3.24 seconds
Started Jul 27 05:42:30 PM PDT 24
Finished Jul 27 05:42:34 PM PDT 24
Peak memory 214076 kb
Host smart-9d28d4e3-8519-4963-8686-a05aefe38ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456529515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2456529515
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1086843445
Short name T823
Test name
Test status
Simulation time 594724879 ps
CPU time 7.03 seconds
Started Jul 27 05:42:40 PM PDT 24
Finished Jul 27 05:42:48 PM PDT 24
Peak memory 210768 kb
Host smart-8512b766-4fc2-4709-ba1c-b137e7783005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086843445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1086843445
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1246281206
Short name T411
Test name
Test status
Simulation time 37887410 ps
CPU time 0.76 seconds
Started Jul 27 05:42:25 PM PDT 24
Finished Jul 27 05:42:26 PM PDT 24
Peak memory 206048 kb
Host smart-02dd4b5d-fe27-4294-9dff-ee0fa727e439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246281206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1246281206
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.165638270
Short name T395
Test name
Test status
Simulation time 567384028 ps
CPU time 5.58 seconds
Started Jul 27 05:42:41 PM PDT 24
Finished Jul 27 05:42:47 PM PDT 24
Peak memory 215280 kb
Host smart-37b317ce-8207-41d5-96ac-63117800dfd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165638270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.165638270
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2438017677
Short name T71
Test name
Test status
Simulation time 734820496 ps
CPU time 3.64 seconds
Started Jul 27 05:42:34 PM PDT 24
Finished Jul 27 05:42:37 PM PDT 24
Peak memory 214200 kb
Host smart-1eb6fd5a-8fae-4098-8c19-2be3ac3a986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438017677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2438017677
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1619182207
Short name T849
Test name
Test status
Simulation time 70469075 ps
CPU time 2.39 seconds
Started Jul 27 05:42:26 PM PDT 24
Finished Jul 27 05:42:29 PM PDT 24
Peak memory 208236 kb
Host smart-f2e0395e-91a5-42e9-ad09-c8a50d25c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619182207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1619182207
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1759408808
Short name T275
Test name
Test status
Simulation time 95893654 ps
CPU time 4.15 seconds
Started Jul 27 05:42:36 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 214440 kb
Host smart-74e68b8c-2556-415a-b895-c70f674e0358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759408808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1759408808
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2957590644
Short name T286
Test name
Test status
Simulation time 859511506 ps
CPU time 8.16 seconds
Started Jul 27 05:42:26 PM PDT 24
Finished Jul 27 05:42:34 PM PDT 24
Peak memory 208772 kb
Host smart-518e48c1-0165-462d-a92d-6bb3e1202c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957590644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2957590644
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3202813272
Short name T206
Test name
Test status
Simulation time 118572802 ps
CPU time 1.79 seconds
Started Jul 27 05:42:29 PM PDT 24
Finished Jul 27 05:42:31 PM PDT 24
Peak memory 222212 kb
Host smart-b374bd54-509b-454e-acc9-9b91e882e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202813272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3202813272
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2747743574
Short name T360
Test name
Test status
Simulation time 435772947 ps
CPU time 5.44 seconds
Started Jul 27 05:42:27 PM PDT 24
Finished Jul 27 05:42:33 PM PDT 24
Peak memory 209868 kb
Host smart-3f97f909-c0ee-4ea8-8956-69da1cd3f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747743574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2747743574
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.922745142
Short name T638
Test name
Test status
Simulation time 209423155 ps
CPU time 3.17 seconds
Started Jul 27 05:42:24 PM PDT 24
Finished Jul 27 05:42:27 PM PDT 24
Peak memory 206688 kb
Host smart-71b719d9-093b-4086-83eb-a03788cf43ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922745142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.922745142
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1999421237
Short name T201
Test name
Test status
Simulation time 250687037 ps
CPU time 3.41 seconds
Started Jul 27 05:42:31 PM PDT 24
Finished Jul 27 05:42:34 PM PDT 24
Peak memory 208892 kb
Host smart-9b530329-8536-4ec9-8f45-48ba227742c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999421237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1999421237
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.677276146
Short name T559
Test name
Test status
Simulation time 6648383489 ps
CPU time 39.39 seconds
Started Jul 27 05:42:27 PM PDT 24
Finished Jul 27 05:43:07 PM PDT 24
Peak memory 208528 kb
Host smart-cd273a0b-cf6e-48e2-8770-a5fdda1fbe9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677276146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.677276146
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1454133196
Short name T322
Test name
Test status
Simulation time 356657406 ps
CPU time 3.38 seconds
Started Jul 27 05:42:41 PM PDT 24
Finished Jul 27 05:42:44 PM PDT 24
Peak memory 206912 kb
Host smart-71348646-764c-42c5-91c9-2996c4bdfa29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454133196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1454133196
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.587609472
Short name T649
Test name
Test status
Simulation time 20211208 ps
CPU time 1.64 seconds
Started Jul 27 05:42:34 PM PDT 24
Finished Jul 27 05:42:36 PM PDT 24
Peak memory 215256 kb
Host smart-92cc7b36-2c64-4d5f-9166-e204fd5e4c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587609472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.587609472
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4265261659
Short name T678
Test name
Test status
Simulation time 47114651 ps
CPU time 2.29 seconds
Started Jul 27 05:42:39 PM PDT 24
Finished Jul 27 05:42:41 PM PDT 24
Peak memory 206744 kb
Host smart-5b0f5866-ba68-4be5-8c80-8a0a38bd1467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265261659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4265261659
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1221108246
Short name T481
Test name
Test status
Simulation time 396951000 ps
CPU time 13.92 seconds
Started Jul 27 05:42:50 PM PDT 24
Finished Jul 27 05:43:05 PM PDT 24
Peak memory 220920 kb
Host smart-b74e0ace-88b3-4939-86e3-052bfeec7c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221108246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1221108246
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1689489637
Short name T815
Test name
Test status
Simulation time 5529972477 ps
CPU time 27.08 seconds
Started Jul 27 05:42:28 PM PDT 24
Finished Jul 27 05:42:56 PM PDT 24
Peak memory 209064 kb
Host smart-9929ecd0-a243-454c-8032-c046a5fa8964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689489637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1689489637
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3041739447
Short name T41
Test name
Test status
Simulation time 194342416 ps
CPU time 1.93 seconds
Started Jul 27 05:42:41 PM PDT 24
Finished Jul 27 05:42:43 PM PDT 24
Peak memory 209700 kb
Host smart-c389905d-ca99-4f2f-92b1-91e3d689fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041739447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3041739447
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4005224322
Short name T499
Test name
Test status
Simulation time 75832997 ps
CPU time 1.3 seconds
Started Jul 27 05:40:26 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 205840 kb
Host smart-3c66864b-ec47-46c6-83cb-e2df4a6fe477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005224322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4005224322
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1670334333
Short name T406
Test name
Test status
Simulation time 109866211 ps
CPU time 6.16 seconds
Started Jul 27 05:40:28 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 214152 kb
Host smart-c70bd7dc-e402-4718-b030-de964e6bffa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670334333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1670334333
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.988293651
Short name T736
Test name
Test status
Simulation time 190695554 ps
CPU time 5.48 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 209520 kb
Host smart-cbcc1af7-9080-4928-945e-6853a77d55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988293651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.988293651
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4130307220
Short name T890
Test name
Test status
Simulation time 208710483 ps
CPU time 2.91 seconds
Started Jul 27 05:40:26 PM PDT 24
Finished Jul 27 05:40:29 PM PDT 24
Peak memory 208252 kb
Host smart-71b1fb43-fe75-40e4-92c8-3536edac8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130307220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4130307220
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3232730679
Short name T571
Test name
Test status
Simulation time 147828474 ps
CPU time 5.81 seconds
Started Jul 27 05:40:29 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 221684 kb
Host smart-f373bac5-dd06-46bb-9dfc-1401d4990d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232730679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3232730679
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1262018915
Short name T891
Test name
Test status
Simulation time 62637097 ps
CPU time 2.98 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 215572 kb
Host smart-6c02a17d-e6c8-4c04-847f-4773ca5cc172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262018915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1262018915
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1077271706
Short name T245
Test name
Test status
Simulation time 87893435 ps
CPU time 3.94 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 209664 kb
Host smart-2a74278e-e5e0-471a-98df-068fa55f97a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077271706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1077271706
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.986270515
Short name T230
Test name
Test status
Simulation time 5828726316 ps
CPU time 24.61 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:49 PM PDT 24
Peak memory 207748 kb
Host smart-4929dc9f-72ab-4ce3-ad5a-7d844c64b6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986270515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.986270515
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3016197456
Short name T2
Test name
Test status
Simulation time 1001730422 ps
CPU time 3.14 seconds
Started Jul 27 05:40:18 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 208424 kb
Host smart-f118b786-a945-419f-895a-c96b1021582c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016197456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3016197456
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.67128195
Short name T632
Test name
Test status
Simulation time 3595401790 ps
CPU time 24.68 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 208112 kb
Host smart-697d4ddb-483e-4461-ad89-e151c4ca186d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67128195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.67128195
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2442650348
Short name T430
Test name
Test status
Simulation time 1740635285 ps
CPU time 18.86 seconds
Started Jul 27 05:40:19 PM PDT 24
Finished Jul 27 05:40:38 PM PDT 24
Peak memory 208436 kb
Host smart-8c070098-e044-4ed0-b833-f14edfb0f081
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442650348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2442650348
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3765006933
Short name T588
Test name
Test status
Simulation time 739114451 ps
CPU time 5.23 seconds
Started Jul 27 05:40:25 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 214164 kb
Host smart-a7c7bcaa-f5c3-4e9a-aa97-ebebaa2e47b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765006933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3765006933
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1465266083
Short name T553
Test name
Test status
Simulation time 95794409 ps
CPU time 2.69 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:24 PM PDT 24
Peak memory 208124 kb
Host smart-79f8b6df-bd3b-4132-93ee-87df68648735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465266083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1465266083
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.586432285
Short name T666
Test name
Test status
Simulation time 289199189 ps
CPU time 4.75 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:29 PM PDT 24
Peak memory 218068 kb
Host smart-657930cf-a44b-408d-9a04-7cf713451830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586432285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.586432285
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2031427349
Short name T128
Test name
Test status
Simulation time 1130668523 ps
CPU time 10.63 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:33 PM PDT 24
Peak memory 222432 kb
Host smart-545ff765-8821-434d-bd77-ed326dff264d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031427349 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2031427349
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1046495286
Short name T473
Test name
Test status
Simulation time 1201972727 ps
CPU time 7.13 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:29 PM PDT 24
Peak memory 208636 kb
Host smart-87074e97-2e68-4b85-9c71-11a7bffc8cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046495286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1046495286
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1137454089
Short name T368
Test name
Test status
Simulation time 882119919 ps
CPU time 13.72 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 210280 kb
Host smart-740c699f-e762-42b0-8a0e-06156d8050c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137454089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1137454089
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.111511921
Short name T718
Test name
Test status
Simulation time 59781395 ps
CPU time 0.72 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 205760 kb
Host smart-c2fcb24e-b630-4364-ba7f-e032f34fa194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111511921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.111511921
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1234175391
Short name T881
Test name
Test status
Simulation time 351943433 ps
CPU time 3.65 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 214376 kb
Host smart-b32767cc-cc66-46af-9ad7-1d2f789d8b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234175391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1234175391
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.627226099
Short name T451
Test name
Test status
Simulation time 569978956 ps
CPU time 2.09 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 214104 kb
Host smart-3465f5fe-84cc-40ac-9db9-5c08c64d809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627226099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.627226099
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3408975415
Short name T289
Test name
Test status
Simulation time 326208740 ps
CPU time 3.83 seconds
Started Jul 27 05:40:26 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 205840 kb
Host smart-5bf736d1-6187-4cf7-b87c-98016fed5d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408975415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3408975415
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3386786002
Short name T883
Test name
Test status
Simulation time 71674277 ps
CPU time 2.19 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 207988 kb
Host smart-b3a8d5e4-a517-4fea-806a-04dee29cd3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386786002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3386786002
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.147330005
Short name T746
Test name
Test status
Simulation time 115638787 ps
CPU time 4.34 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 207224 kb
Host smart-cfbd6ecc-a471-47ff-80a9-303029c99f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147330005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.147330005
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4263054547
Short name T179
Test name
Test status
Simulation time 206102875 ps
CPU time 3 seconds
Started Jul 27 05:40:30 PM PDT 24
Finished Jul 27 05:40:33 PM PDT 24
Peak memory 207452 kb
Host smart-ac1550b4-184b-4642-8a98-498432329a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263054547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4263054547
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1721901684
Short name T486
Test name
Test status
Simulation time 242594831 ps
CPU time 3.36 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:27 PM PDT 24
Peak memory 206784 kb
Host smart-5c336b6f-130c-4129-9d65-0e53da14894e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721901684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1721901684
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3677439759
Short name T691
Test name
Test status
Simulation time 335476411 ps
CPU time 3.27 seconds
Started Jul 27 05:40:28 PM PDT 24
Finished Jul 27 05:40:31 PM PDT 24
Peak memory 206620 kb
Host smart-75a690ae-39bc-4ab0-821e-b3cb93a85df1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677439759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3677439759
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1277513476
Short name T639
Test name
Test status
Simulation time 44718343 ps
CPU time 2.41 seconds
Started Jul 27 05:40:29 PM PDT 24
Finished Jul 27 05:40:31 PM PDT 24
Peak memory 206628 kb
Host smart-ebda636b-b5a9-422b-9ce9-f3fd5f1d04c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277513476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1277513476
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.142861651
Short name T543
Test name
Test status
Simulation time 4702711930 ps
CPU time 24.67 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:47 PM PDT 24
Peak memory 214124 kb
Host smart-0f896268-bac1-4595-a7b2-3519200a8add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142861651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.142861651
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1138449580
Short name T450
Test name
Test status
Simulation time 1737794998 ps
CPU time 14.93 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:39 PM PDT 24
Peak memory 207816 kb
Host smart-5d7d5ca0-53fb-4796-8a8a-bb37222cf4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138449580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1138449580
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2046193637
Short name T73
Test name
Test status
Simulation time 129226533 ps
CPU time 4.84 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 214920 kb
Host smart-55d73df0-6b6d-4cd4-b5f6-2b7da4342ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046193637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2046193637
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.24055129
Short name T323
Test name
Test status
Simulation time 2181597388 ps
CPU time 24.17 seconds
Started Jul 27 05:40:21 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 222376 kb
Host smart-efb25dd6-148a-4d30-8d57-e06f13c4e816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24055129 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.24055129
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3221787574
Short name T202
Test name
Test status
Simulation time 98948201 ps
CPU time 4.43 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 208156 kb
Host smart-ca6914f1-45ba-449e-86c6-56d2d272232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221787574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3221787574
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2905892577
Short name T367
Test name
Test status
Simulation time 485140392 ps
CPU time 1.92 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 209576 kb
Host smart-740e6c1a-414c-4781-aaab-4f1674952c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905892577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2905892577
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3987679491
Short name T541
Test name
Test status
Simulation time 32816599 ps
CPU time 0.84 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:40:40 PM PDT 24
Peak memory 205748 kb
Host smart-59a85f00-cb43-4b6c-943b-0371ed0230cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987679491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3987679491
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2885051467
Short name T397
Test name
Test status
Simulation time 91457174 ps
CPU time 3.6 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 215144 kb
Host smart-b8355140-062e-44ee-a908-84e4fc65cabe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885051467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2885051467
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.931647749
Short name T283
Test name
Test status
Simulation time 119012066 ps
CPU time 3.68 seconds
Started Jul 27 05:40:25 PM PDT 24
Finished Jul 27 05:40:29 PM PDT 24
Peak memory 219844 kb
Host smart-33fe8b7f-da3d-4a1f-9c78-b41ae8f31d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931647749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.931647749
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2403117300
Short name T366
Test name
Test status
Simulation time 1157725733 ps
CPU time 5.41 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 220092 kb
Host smart-4105bd09-b433-4daf-b2ea-63b1df94672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403117300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2403117300
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2130052091
Short name T327
Test name
Test status
Simulation time 183347207 ps
CPU time 4.81 seconds
Started Jul 27 05:40:27 PM PDT 24
Finished Jul 27 05:40:32 PM PDT 24
Peak memory 214004 kb
Host smart-c11c4206-053d-4b68-9900-cb8d1a733e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130052091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2130052091
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.200569023
Short name T841
Test name
Test status
Simulation time 474591365 ps
CPU time 2.58 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 207676 kb
Host smart-129abf9c-9b1b-487a-9f31-62f15ba9603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200569023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.200569023
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3217358854
Short name T104
Test name
Test status
Simulation time 113749596 ps
CPU time 4.42 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 209172 kb
Host smart-e230041a-0406-4b45-85bc-cfe836dd786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217358854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3217358854
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4142534507
Short name T598
Test name
Test status
Simulation time 109149585 ps
CPU time 2.22 seconds
Started Jul 27 05:40:22 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 206588 kb
Host smart-40ea5b9c-158f-422f-9b8e-42689fa4051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142534507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4142534507
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3469170180
Short name T471
Test name
Test status
Simulation time 231568311 ps
CPU time 2.48 seconds
Started Jul 27 05:40:19 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 208080 kb
Host smart-ad261452-7aad-4091-87aa-7158669c08b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469170180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3469170180
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2891141627
Short name T455
Test name
Test status
Simulation time 633555119 ps
CPU time 5.19 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:28 PM PDT 24
Peak memory 208700 kb
Host smart-4f683379-206c-453e-90a4-dea6a78a6c4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891141627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2891141627
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1103610450
Short name T566
Test name
Test status
Simulation time 2468197720 ps
CPU time 7.61 seconds
Started Jul 27 05:40:27 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 208476 kb
Host smart-b06d4d5b-d95e-47b5-8bb8-4f079de86132
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103610450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1103610450
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3029182179
Short name T630
Test name
Test status
Simulation time 144291760 ps
CPU time 2.26 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:27 PM PDT 24
Peak memory 207616 kb
Host smart-03bf2b68-5726-4b95-8f76-ec8bf7080ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029182179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3029182179
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.4151535378
Short name T190
Test name
Test status
Simulation time 101126324 ps
CPU time 2.42 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:25 PM PDT 24
Peak memory 208240 kb
Host smart-6f30d319-4231-4d98-a7f0-2e84f0f9a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151535378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4151535378
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1855844396
Short name T886
Test name
Test status
Simulation time 549645158 ps
CPU time 19.19 seconds
Started Jul 27 05:40:23 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 222432 kb
Host smart-4afde09c-66c9-4c06-afa0-43789c20c749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855844396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1855844396
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1547851639
Short name T714
Test name
Test status
Simulation time 486080688 ps
CPU time 5.25 seconds
Started Jul 27 05:40:24 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 209056 kb
Host smart-48ef6e28-9d98-48cc-a1ad-6125f5fa3e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547851639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1547851639
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2911226117
Short name T887
Test name
Test status
Simulation time 25125387 ps
CPU time 1.62 seconds
Started Jul 27 05:40:29 PM PDT 24
Finished Jul 27 05:40:31 PM PDT 24
Peak memory 209540 kb
Host smart-949dc65f-4070-4877-8334-52bd24a225ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911226117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2911226117
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1763874945
Short name T556
Test name
Test status
Simulation time 47850861 ps
CPU time 0.8 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 205916 kb
Host smart-c437dabe-51c5-4186-ab5e-a65684b01f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763874945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1763874945
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.370269568
Short name T285
Test name
Test status
Simulation time 1178405363 ps
CPU time 60.44 seconds
Started Jul 27 05:40:39 PM PDT 24
Finished Jul 27 05:41:40 PM PDT 24
Peak memory 214728 kb
Host smart-555cfb53-4838-4e1e-8956-b5c2dab54243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370269568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.370269568
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.214256607
Short name T63
Test name
Test status
Simulation time 368461470 ps
CPU time 3.71 seconds
Started Jul 27 05:40:30 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 218340 kb
Host smart-2122a427-76ff-4034-928b-72964a6a3b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214256607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.214256607
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1180736577
Short name T74
Test name
Test status
Simulation time 262576635 ps
CPU time 2.34 seconds
Started Jul 27 05:40:37 PM PDT 24
Finished Jul 27 05:40:40 PM PDT 24
Peak memory 208912 kb
Host smart-67a76b99-81a7-48f6-aeec-52339d61896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180736577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1180736577
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.871303189
Short name T55
Test name
Test status
Simulation time 673460104 ps
CPU time 4.34 seconds
Started Jul 27 05:40:33 PM PDT 24
Finished Jul 27 05:40:38 PM PDT 24
Peak memory 214336 kb
Host smart-5ffc0a36-80df-47ec-ac50-0112f681ad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871303189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.871303189
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3904685435
Short name T491
Test name
Test status
Simulation time 39902957 ps
CPU time 3.01 seconds
Started Jul 27 05:40:49 PM PDT 24
Finished Jul 27 05:40:52 PM PDT 24
Peak memory 218296 kb
Host smart-4b449b6a-7dcf-4ec0-9c1d-50147dd2ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904685435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3904685435
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4041066156
Short name T725
Test name
Test status
Simulation time 33754197 ps
CPU time 2.49 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 208076 kb
Host smart-d593bc2c-1066-4fdd-b07a-d872a43d8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041066156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4041066156
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2135501744
Short name T831
Test name
Test status
Simulation time 227679454 ps
CPU time 3.44 seconds
Started Jul 27 05:40:42 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 208228 kb
Host smart-f9ec5d5d-9cc1-48b4-aa06-03c28aeadc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135501744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2135501744
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3801462718
Short name T846
Test name
Test status
Simulation time 144765770 ps
CPU time 2.83 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 208780 kb
Host smart-0cbd682b-1429-445f-945f-998209c57f3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801462718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3801462718
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1278416999
Short name T562
Test name
Test status
Simulation time 60012787 ps
CPU time 3.02 seconds
Started Jul 27 05:40:30 PM PDT 24
Finished Jul 27 05:40:33 PM PDT 24
Peak memory 208392 kb
Host smart-1878cc51-5f99-43e5-94c4-1c8a150d0e0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278416999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1278416999
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4196002681
Short name T906
Test name
Test status
Simulation time 622162839 ps
CPU time 4.33 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 208228 kb
Host smart-cd64cd0e-65ab-43d9-b35e-4ef9e83db60e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196002681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4196002681
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4105658392
Short name T704
Test name
Test status
Simulation time 566310450 ps
CPU time 4.25 seconds
Started Jul 27 05:40:33 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 214088 kb
Host smart-f4f29ad9-d23b-46cf-a15a-f8c0a4470e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105658392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4105658392
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3310474534
Short name T413
Test name
Test status
Simulation time 87011241 ps
CPU time 2.77 seconds
Started Jul 27 05:40:33 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 208244 kb
Host smart-b22c159d-8ba9-4d2d-96ac-87a5426b5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310474534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3310474534
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1176008637
Short name T772
Test name
Test status
Simulation time 1237796851 ps
CPU time 24.37 seconds
Started Jul 27 05:40:35 PM PDT 24
Finished Jul 27 05:40:59 PM PDT 24
Peak memory 214268 kb
Host smart-59d1fe44-6a0c-4398-ada2-a68deac9a9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176008637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1176008637
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3244925890
Short name T252
Test name
Test status
Simulation time 328347705 ps
CPU time 4.34 seconds
Started Jul 27 05:40:33 PM PDT 24
Finished Jul 27 05:40:38 PM PDT 24
Peak memory 214088 kb
Host smart-c35f9299-6d86-4eb7-bd4c-d03889fca83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244925890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3244925890
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3386524418
Short name T377
Test name
Test status
Simulation time 84636189 ps
CPU time 2.18 seconds
Started Jul 27 05:40:46 PM PDT 24
Finished Jul 27 05:40:48 PM PDT 24
Peak memory 209512 kb
Host smart-6762c122-0523-4375-9fb8-8b6a85509175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386524418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3386524418
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.292215944
Short name T434
Test name
Test status
Simulation time 44168645 ps
CPU time 0.74 seconds
Started Jul 27 05:40:31 PM PDT 24
Finished Jul 27 05:40:32 PM PDT 24
Peak memory 205820 kb
Host smart-6f087091-5c5b-4b9a-9e3c-070d894975cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292215944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.292215944
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1669318892
Short name T682
Test name
Test status
Simulation time 221012303 ps
CPU time 3.65 seconds
Started Jul 27 05:40:41 PM PDT 24
Finished Jul 27 05:40:45 PM PDT 24
Peak memory 209060 kb
Host smart-7381459b-d46d-43a9-b72a-a8c69afdffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669318892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1669318892
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.873694123
Short name T26
Test name
Test status
Simulation time 121309536 ps
CPU time 3.33 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 214120 kb
Host smart-3d913f0c-6333-4a08-aa50-238d9c50eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873694123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.873694123
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4012998460
Short name T276
Test name
Test status
Simulation time 108374282 ps
CPU time 2.48 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 214100 kb
Host smart-92285dc7-e061-48da-bdac-9796797f0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012998460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4012998460
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4179136329
Short name T689
Test name
Test status
Simulation time 162932108 ps
CPU time 3.82 seconds
Started Jul 27 05:40:38 PM PDT 24
Finished Jul 27 05:40:42 PM PDT 24
Peak memory 214148 kb
Host smart-61cade1b-4f33-4954-8f73-63029873ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179136329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4179136329
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2874897375
Short name T816
Test name
Test status
Simulation time 153351586 ps
CPU time 2.68 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:35 PM PDT 24
Peak memory 207256 kb
Host smart-8d11a9a0-4135-4d61-96f9-a50a97fcd210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874897375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2874897375
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.701070087
Short name T672
Test name
Test status
Simulation time 762199439 ps
CPU time 5.96 seconds
Started Jul 27 05:40:34 PM PDT 24
Finished Jul 27 05:40:40 PM PDT 24
Peak memory 208168 kb
Host smart-87f51d11-45dc-4d5a-bb02-3dfb08ef8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701070087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.701070087
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2427296411
Short name T552
Test name
Test status
Simulation time 148330392 ps
CPU time 4.15 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 208168 kb
Host smart-0e8d1579-e1b1-421a-bc83-eb0d95b06f37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427296411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2427296411
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.948535718
Short name T729
Test name
Test status
Simulation time 16008231816 ps
CPU time 54.52 seconds
Started Jul 27 05:40:36 PM PDT 24
Finished Jul 27 05:41:31 PM PDT 24
Peak memory 209048 kb
Host smart-1c9ca38f-272c-42de-a2bc-654aff280481
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948535718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.948535718
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3721970595
Short name T459
Test name
Test status
Simulation time 173021384 ps
CPU time 3.37 seconds
Started Jul 27 05:40:34 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 206788 kb
Host smart-26e3d2a6-b6b5-4fb3-9cc7-623fbacafe29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721970595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3721970595
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1339724744
Short name T902
Test name
Test status
Simulation time 280469795 ps
CPU time 8.9 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:40:41 PM PDT 24
Peak memory 209136 kb
Host smart-ebc0aa26-1dac-484d-a20f-d51b69eb3476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339724744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1339724744
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1729069992
Short name T195
Test name
Test status
Simulation time 143645309 ps
CPU time 2.34 seconds
Started Jul 27 05:40:35 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 208204 kb
Host smart-b8f00a67-11b6-45a0-85da-2445bd212dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729069992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1729069992
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1262796786
Short name T220
Test name
Test status
Simulation time 512344711 ps
CPU time 20.01 seconds
Started Jul 27 05:40:34 PM PDT 24
Finished Jul 27 05:40:54 PM PDT 24
Peak memory 216748 kb
Host smart-12cdf572-2e6f-47f0-9388-535e6aaedfbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262796786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1262796786
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.648711757
Short name T803
Test name
Test status
Simulation time 12942540351 ps
CPU time 32.07 seconds
Started Jul 27 05:40:32 PM PDT 24
Finished Jul 27 05:41:04 PM PDT 24
Peak memory 220948 kb
Host smart-47bbfab6-aa7d-476c-95e7-de852f0f8284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648711757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.648711757
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2222481118
Short name T188
Test name
Test status
Simulation time 211761825 ps
CPU time 2.41 seconds
Started Jul 27 05:40:31 PM PDT 24
Finished Jul 27 05:40:33 PM PDT 24
Peak memory 209664 kb
Host smart-1508c019-5591-4898-8ec1-22015bb3ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222481118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2222481118
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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