Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	39	1			T9	1		T42	2		T43	1
auto[OpGenId]	7	1			T54	1		T103	1		T75	1
auto[OpGenSwOut]	29	1			T6	1		T53	1		T47	1
auto[OpGenHwOut]	21	1			T7	1		T8	1		T45	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1597	1			T47	4		T103	4		T8	1
auto[StInit]	94	1			T1	1		T3	1		T53	1
auto[StCreatorRootKey]	59	1			T6	1		T38	1		T39	1
auto[StOwnerIntKey]	46	1			T15	1		T29	1		T59	1
auto[StOwnerKey]	34	1			T19	1		T63	1		T113	1
auto[StDisabled]	466	1			T28	1		T47	10		T103	7
auto[StInvalid]	48	1			T34	1		T35	1		T90	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3334

1

T1

2

T2

1

T3

2

auto[1]

96

1

T6

1

T53

1

T54

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1593	1			T47	4		T103	4		T8	1
auto[StReset]	auto[1]	4	1			T51	1		T52	1		T181	1
auto[StInit]	auto[0]	49	1			T1	1		T3	1		T47	1
auto[StInit]	auto[1]	45	1			T53	1		T54	1		T47	1
auto[StCreatorRootKey]	auto[0]	41	1			T38	1		T39	1		T205	1
auto[StCreatorRootKey]	auto[1]	18	1			T6	1		T45	1		T55	1
auto[StOwnerIntKey]	auto[0]	34	1			T15	1		T29	1		T59	1
auto[StOwnerIntKey]	auto[1]	12	1			T42	2		T55	1		T111	1
auto[StOwnerKey]	auto[0]	28	1			T19	1		T63	1		T113	1
auto[StOwnerKey]	auto[1]	6	1			T67	1		T206	1		T207	1
auto[StDisabled]	auto[0]	455	1			T28	1		T47	10		T103	7
auto[StDisabled]	auto[1]	11	1			T55	1		T131	1		T67	1
auto[StInvalid]	auto[0]	48	1			T34	1		T35	1		T90	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T51	1		T52	1		-	-
auto[StReset]	auto[OpGenSwOut]	2	1			T181	1		T208	1		-	-
auto[StInit]	auto[OpAdvance]	18	1			T9	1		T43	1		T44	1
auto[StInit]	auto[OpGenId]	3	1			T54	1		T103	1		T209	1
auto[StInit]	auto[OpGenSwOut]	13	1			T53	1		T47	1		T8	2
auto[StInit]	auto[OpGenHwOut]	11	1			T7	1		T8	1		T177	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T55	1		T56	1		T140	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T108	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T6	1		T145	1		T210	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T45	1		T68	1		T211	1
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T42	2		T212	1		T213	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T52	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T55	1		T111	1		T214	1
auto[StOwnerKey]	auto[OpAdvance]	2	1			T67	1		T207	1		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T206	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T215	1		T216	1		T217	1
auto[StDisabled]	auto[OpAdvance]	2	1			T218	1		T219	1		-	-
auto[StDisabled]	auto[OpGenId]	2	1			T75	1		T220	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	4	1			T55	1		T221	1		T222	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T131	1		T67	1		T223	1