Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4700

1

T1

3

T2

12

T4

5

auto[1]

566

1

T16

1

T18

3

T41

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4700

1

T1

3

T2

12

T4

5

auto[1]

566

1

T16

1

T18

3

T41

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T1

3

T2

12

T4

5

auto[1]

594

1

T16

1

T32

3

T41

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T1

3

T2

12

T4

5

auto[1]

594

1

T16

1

T32

3

T41

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	428	1			T84	4		T120	2		T47	2
auto[OpGenId]	1063	1			T4	1		T5	2		T16	1
auto[OpGenSwOut]	1111	1			T1	3		T4	2		T5	1
auto[OpGenHwOut]	2583	1			T2	12		T4	2		T5	1
auto[OpDisable]	81	1			T46	1		T47	1		T48	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	428	1			T84	4		T120	2		T47	2
auto[OpGenId]	1063	1			T4	1		T5	2		T16	1
auto[OpGenSwOut]	1111	1			T1	3		T4	2		T5	1
auto[OpGenHwOut]	2583	1			T2	12		T4	2		T5	1
auto[OpDisable]	81	1			T46	1		T47	1		T48	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4720

1

T1

3

T2

10

T4

5

auto[1]

546

1

T2

2

T16

1

T84

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4720

1

T1

3

T2

10

T4

5

auto[1]

546

1

T2

2

T16

1

T84

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4981

1

T1

3

T2

12

T4

5

auto[1]

285

1

T84

4

T120

1

T121

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1877	1			T1	2		T2	4		T4	3
auto[1]	664	1			T2	1		T4	1		T16	1
auto[2]	664	1			T32	1		T83	1		T84	2
auto[3]	687	1			T1	1		T2	3		T4	1
auto[4]	337	1			T32	1		T41	1		T83	2
auto[5]	340	1			T17	1		T18	2		T32	1
auto[6]	338	1			T2	2		T18	1		T32	1
auto[7]	359	1			T2	2		T5	1		T32	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1374	1			T2	4		T5	1		T17	1
clear_one[1]	664	1			T2	1		T4	1		T16	1
clear_one[2]	664	1			T32	1		T83	1		T84	2
clear_one[3]	687	1			T1	1		T2	3		T4	1
clear_none	1877	1			T1	2		T2	4		T4	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	993	1			T1	3		T2	4		T4	1
auto[StInit]	634	1			T2	1		T5	3		T17	1
auto[StCreatorRootKey]	529	1			T2	1		T18	1		T32	1
auto[StOwnerIntKey]	524	1			T2	1		T4	1		T16	1
auto[StOwnerKey]	463	1			T2	1		T17	1		T18	1
auto[StDisabled]	1839	1			T2	4		T4	3		T16	1
auto[StInvalid]	284	1			T34	1		T35	4		T90	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	993	1			T1	3		T2	4		T4	1
auto[StInit]	634	1			T2	1		T5	3		T17	1
auto[StCreatorRootKey]	529	1			T2	1		T18	1		T32	1
auto[StOwnerIntKey]	524	1			T2	1		T4	1		T16	1
auto[StOwnerKey]	463	1			T2	1		T17	1		T18	1
auto[StDisabled]	1839	1			T2	4		T4	3		T16	1
auto[StInvalid]	284	1			T34	1		T35	4		T90	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T153	1		T107	1		T230	1
auto[0]	auto[StReset]	auto[OpGenId]	146	1			T5	1		T41	1		T28	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	151	1			T1	2		T84	1		T195	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	276	1			T2	2		T4	1		T6	1
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T85	1		T231	1		T103	2
auto[0]	auto[StInit]	auto[OpGenId]	96	1			T199	1		T8	3		T205	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	81	1			T47	1		T192	1		T62	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	189	1			T17	1		T18	1		T83	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T47	1		T232	2		T128	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	43	1			T26	1		T57	1		T8	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T41	1		T47	1		T19	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	77	1			T2	1		T102	1		T233	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	25	1			T232	1		T141	1		T234	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	37	1			T16	1		T153	1		T8	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	37	1			T200	1		T198	1		T128	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T32	1		T47	1		T235	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T67	1		T236	1		T68	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	13	1			T47	1		T61	1		T237	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T47	1		T196	1		T238	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T202	1		T176	1		T139	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	24	1			T82	1		T231	1		T8	1
auto[0]	auto[StDisabled]	auto[OpGenId]	67	1			T4	1		T120	1		T8	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	75	1			T4	1		T41	1		T120	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	174	1			T2	1		T18	1		T32	1
auto[0]	auto[StDisabled]	auto[OpDisable]	21	1			T58	1		T8	1		T176	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T87	1		T239	1		T240	1
auto[0]	auto[StInvalid]	auto[OpGenId]	20	1			T87	1		T241	1		T242	3
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T243	1		T86	1		T244	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	29	1			T35	1		T245	1		T246	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T128	1		T131	1		T247	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	12	1			T120	1		T87	1		T136	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T24	1		T248	1		T8	1
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T249	1		T250	1		T251	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T84	1		T68	1		T182	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T48	1		T60	1		T51	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	20	1			T2	1		T136	1		T252	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T60	1		T25	1		T131	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T51	1		T68	1		T253	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T138	1		T60	1		T128	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T18	1		T101	1		T254	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T68	2		T255	1		T256	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T257	1		T258	1		T259	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T138	1		T260	1		T129	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T4	1		T261	1		T62	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T262	1		T143	1		T263	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	9	1			T264	1		T225	1		T265	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T60	1		T264	3		T25	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T199	1		T101	1		T235	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	22	1			T84	1		T176	1		T113	1
auto[1]	auto[StDisabled]	auto[OpGenId]	40	1			T84	1		T47	3		T153	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	72	1			T84	1		T47	3		T153	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T16	1		T32	1		T84	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T48	1		T60	1		T266	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T89	1		T239	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T35	1		T50	1		T241	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T88	1		T268	1		T243	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T90	1		T246	2		T269	1
auto[2]	auto[StReset]	auto[OpGenId]	27	1			T90	1		T24	1		T8	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	15	1			T34	1		T193	1		T8	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	51	1			T137	1		T270	1		T245	1
auto[2]	auto[StInit]	auto[OpAdvance]	11	1			T84	1		T120	1		T271	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T47	1		T60	1		T262	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	8	1			T55	1		T56	1		T36	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T272	1		T273	1		T274	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T84	1		T68	1		T275	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T276	1		T277	1		T278	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T66	1		T67	1		T206	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T103	1		T270	1		T252	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T19	1		T279	1		T280	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T281	1		T272	1		T56	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T98	1		T60	1		T128	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T83	1		T101	1		T47	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T113	1		T282	1		T71	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T8	1		T222	1		T259	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T198	1		T60	1		T141	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T32	1		T102	1		T204	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	28	1			T47	1		T121	1		T231	1
auto[2]	auto[StDisabled]	auto[OpGenId]	34	1			T47	1		T85	1		T194	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T121	2		T103	1		T8	4
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T101	1		T47	2		T235	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T8	1		T115	1		T51	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T90	1		T49	1		T283	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T88	1		T86	1		T269	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T35	1		T90	2		T86	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T267	1		T284	1		T285	2
auto[3]	auto[StReset]	auto[OpGenId]	25	1			T90	1		T51	2		T56	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	9	1			T1	1		T30	1		T25	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T2	1		T32	2		T233	1
auto[3]	auto[StInit]	auto[OpAdvance]	1	1			T286	1		-	-		-	-
auto[3]	auto[StInit]	auto[OpGenId]	6	1			T5	1		T47	1		T128	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	6	1			T5	1		T72	1		T91	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	27	1			T32	1		T248	1		T287	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T84	1		T130	1		T140	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	20	1			T36	1		T69	1		T67	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T196	1		T98	1		T56	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T47	1		T235	1		T288	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T121	1		T8	1		T289	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T8	1		T113	1		T55	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T8	2		T135	1		T290	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T84	1		T203	1		T233	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T153	1		T8	1		T60	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T103	1		T66	1		T291	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T195	1		T85	1		T292	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T200	1		T233	1		T248	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	16	1			T51	1		T293	1		T294	1
auto[3]	auto[StDisabled]	auto[OpGenId]	74	1			T82	1		T153	1		T193	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T4	1		T196	1		T58	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T2	2		T18	2		T102	1
auto[3]	auto[StDisabled]	auto[OpDisable]	17	1			T47	1		T62	1		T67	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	11	1			T268	1		T89	2		T239	1
auto[3]	auto[StInvalid]	auto[OpGenId]	8	1			T241	1		T284	1		T295	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T245	1		T88	1		T89	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T34	1		T50	1		T245	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T87	1		T296	1		T223	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T103	1		T67	2		T249	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	35	1			T233	1		T248	1		T8	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T142	1		T91	1		T68	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T137	1		T68	1		T76	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T142	1		T131	1		T68	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T101	1		T297	1		T298	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T142	1		T299	1		T223	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T103	1		T222	1		T300	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T301	1		T302	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T83	1		T28	1		T203	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T256	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T28	1		T304	1		T66	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T57	1		T305	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T204	1		T202	1		T24	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T77	1		T307	1		T308	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T193	1		T272	1		T130	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T309	1		T310	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T47	1		T203	1		T261	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T103	1		T238	1		T142	1
auto[4]	auto[StDisabled]	auto[OpGenId]	19	1			T192	1		T237	1		T103	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T47	1		T103	1		T62	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T32	1		T41	1		T83	1
auto[4]	auto[StDisabled]	auto[OpDisable]	11	1			T46	1		T72	1		T60	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T312	1		T313	1		T314	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T87	1		T315	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T317	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T87	1		T141	1		T68	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T88	1		T272	1		T249	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T32	1		T101	1		T248	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T30	1		T108	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T68	1		T318	1		T77	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T193	1		T140	1		T319	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T320	1		T321	1		T69	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T197	1		T144	1		T322	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T48	1		T69	1		T217	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T131	1		T322	2		T323	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T261	1		T8	1		T69	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T144	1		T277	1		T324	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T29	1		T302	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T144	1		T325	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T18	1		T326	1		T139	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T76	1		T277	1		T327	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T60	1		T130	1		T279	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T17	1		T68	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T270	1		T329	1		T330	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T98	1		T60	1		T68	1
auto[5]	auto[StDisabled]	auto[OpGenId]	21	1			T47	1		T237	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T47	1		T232	2		T113	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T18	1		T83	2		T204	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T51	1		T56	1		T302	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T89	1		T331	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	9	1			T89	1		T332	1		T110	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T333	1		T334	1		T335	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T35	1		T50	1		T239	2
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T268	1		T69	2		T336	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T34	1		T245	1		T131	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T2	1		T337	1		T338	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T94	1		T77	2		T93	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T29	1		T69	1		T76	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T24	1		T288	1		T225	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T339	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T216	1		T256	1		T340	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T75	1		T206	1		T341	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T32	1		T204	1		T248	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T25	1		T69	1		T342	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T8	1		T60	1		T131	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T128	1		T343	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T2	1		T69	1		T345	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T24	1		T325	1		T322	2
auto[6]	auto[StOwnerKey]	auto[OpGenId]	2	1			T346	1		T347	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T68	1		T76	1		T348	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T18	1		T83	1		T349	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	16	1			T120	1		T68	1		T350	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T193	1		T351	1		T51	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T103	1		T51	1		T247	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T47	1		T352	1		T8	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T61	1		T309	1		T215	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T50	1		T246	1		T353	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T244	1		T354	1		T110	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T240	1		T355	1		T356	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T49	1		T244	1		T357	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T358	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T245	1		T113	1		T359	2
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T195	1		T8	1		T68	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	23	1			T101	1		T233	1		T338	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T227	1		T360	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T68	1		T361	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	1	1			T196	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T5	1		T338	1		T362	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T201	1		T363	1		T364	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T128	1		T130	1		T76	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T51	1		T75	1		T365	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T326	1		T85	1		T321	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T108	1		T230	1		T348	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T194	1		T60	1		T55	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T60	1		T66	1		T76	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T102	1		T47	1		T103	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T366	1		T69	1		T265	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	15	1			T194	1		T103	1		T176	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T47	1		T77	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T2	1		T367	1		T368	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T8	1		T176	1		T238	1
auto[7]	auto[StDisabled]	auto[OpGenId]	33	1			T120	1		T121	1		T305	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T103	1		T8	1		T304	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T2	1		T32	1		T101	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T369	1		T370	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T268	1		T372	1		T373	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T87	1		T86	1		T284	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T49	1		T88	1		T243	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T246	1		T356	1		T374	2

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1374

1

T2

4

T5

1

T17

1

clear_one[1]

auto[0]

auto[0]

auto[0]

378

1

T2

1

T4

1

T18

1

clear_one[1]

auto[0]

auto[0]

auto[1]

117

1

T199

2

T102

2

T47

3

clear_one[1]

auto[0]

auto[1]

auto[0]

123

1

T32

1

T84

1

T288

1

clear_one[1]

auto[0]

auto[1]

auto[1]

46

1

T16

1

T84

3

T47

2

clear_one[2]

auto[0]

auto[0]

auto[0]

402

1

T32

1

T83

1

T84

2

clear_one[2]

auto[0]

auto[0]

auto[1]

105

1

T102

1

T47

2

T19

1

clear_one[2]

auto[1]

auto[0]

auto[0]

116

1

T101

2

T326

2

T352

2

clear_one[2]

auto[1]

auto[0]

auto[1]

41

1

T47

2

T196

1

T85

1

clear_one[3]

auto[0]

auto[0]

auto[0]

386

1

T1

1

T2

3

T4

1

clear_one[3]

auto[0]

auto[1]

auto[0]

132

1

T84

1

T203

3

T58

1

clear_one[3]

auto[1]

auto[0]

auto[0]

126

1

T18

2

T47

2

T82

1

clear_one[3]

auto[1]

auto[1]

auto[0]

43

1

T153

3

T196

1

T193

1

clear_none

auto[0]

auto[0]

auto[0]

1329

1

T1

2

T2

2

T4

3

clear_none

auto[0]

auto[0]

auto[1]

132

1

T2

2

T102

2

T47

1

clear_none

auto[0]

auto[1]

auto[0]

148

1

T32

2

T83

1

T203

1

clear_none

auto[0]

auto[1]

auto[1]

28

1

T58

1

T231

1

T51

1

clear_none

auto[1]

auto[0]

auto[0]

130

1

T16

1

T18

1

T101

2

clear_none

auto[1]

auto[0]

auto[1]

36

1

T47

1

T196

1

T61

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T41

1

T47

2

T192

1

clear_none

auto[1]

auto[1]

auto[1]

41

1

T47

1

T196

1

T8

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1286	1			T2	4		T5	1		T17	1
clear_all	auto[1]	88	1			T232	2		T238	2		T142	4
clear_one[1]	auto[0]	629	1			T2	1		T4	1		T16	1
clear_one[1]	auto[1]	35	1			T84	2		T153	2		T232	6
clear_one[2]	auto[0]	613	1			T32	1		T83	1		T84	1
clear_one[2]	auto[1]	51	1			T84	1		T121	2		T141	1
clear_one[3]	auto[0]	654	1			T1	1		T2	3		T4	1
clear_one[3]	auto[1]	33	1			T84	1		T153	2		T322	2
clear_none	auto[0]	1799	1			T1	2		T2	4		T4	3
clear_none	auto[1]	78	1			T120	1		T153	1		T232	2