Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11128

1

T1

10

T2

16

T4

7

auto[Attestation]

7586

1

T2

2

T3

1

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2636	1			T1	3		T4	2		T5	5
auto[Aes]	3390	1			T1	3		T4	4		T5	6
auto[Kmac]	3349	1			T4	3		T5	2		T15	4
auto[Otbn]	3448	1			T1	2		T2	18		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7681	1			T1	1		T2	8		T3	1
auto[OpGenId]	5891	1			T1	2		T3	1		T4	2
auto[OpGenSwOut]	5897	1			T1	3		T4	6		T5	10
auto[OpGenHwOut]	6926	1			T1	5		T2	18		T4	4
auto[OpDisable]	149	1			T46	1		T47	4		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10648

1

T1

1

T2

8

T3

1

auto[OpDoneFail]

15896

1

T1

10

T2

18

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6478	1			T1	11		T2	11		T3	1
auto[StInit]	3795	1			T2	2		T3	1		T4	2
auto[StCreatorRootKey]	3200	1			T2	2		T4	2		T15	4
auto[StOwnerIntKey]	2784	1			T2	2		T4	2		T15	2
auto[StOwnerKey]	2425	1			T2	2		T4	2		T16	6
auto[StDisabled]	7862	1			T2	7		T4	7		T16	8

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	298	1			T1	1		T5	1		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	117	1			T5	1		T28	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	75	1			T16	1		T41	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T41	1		T80	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	80	1			T16	1		T17	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T17	1		T47	2		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	306	1			T1	2		T4	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T5	2		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T4	1		T47	2		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T15	1		T47	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	69	1			T16	1		T47	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	224	1			T47	6		T48	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	331	1			T15	2		T6	1		T84	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	95	1			T47	1		T87	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T47	1		T194	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T26	1		T103	1		T8	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	66	1			T4	1		T47	4		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	227	1			T16	1		T41	2		T47	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	338	1			T15	1		T28	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	94	1			T47	1		T196	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T46	1		T47	2		T82	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T197	1		T198	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T16	1		T47	1		T8	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	193	1			T17	1		T84	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T34	1		T8	4		T62	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	92	1			T5	1		T17	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T28	1		T47	2		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T26	1		T47	3		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T84	1		T47	1		T153	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	224	1			T4	1		T41	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	92	1			T34	2		T8	4		T176	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T4	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	95	1			T47	5		T80	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T26	1		T47	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T28	1		T85	1		T8	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	239	1			T26	1		T47	2		T82	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T34	1		T103	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	90	1			T5	1		T41	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	66	1			T28	1		T199	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T84	1		T29	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	55	1			T47	1		T121	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	219	1			T4	1		T47	3		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T34	2		T103	2		T8	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	95	1			T5	2		T15	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T15	1		T121	1		T192	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T16	1		T58	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T16	1		T195	2		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	210	1			T120	1		T47	1		T200	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	239	1			T1	2		T15	2		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	91	1			T5	1		T82	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T47	2		T200	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T197	1		T198	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T47	1		T80	1		T8	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	161	1			T84	1		T199	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	439	1			T1	1		T4	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	124	1			T5	1		T18	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T16	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	92	1			T47	2		T80	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T18	1		T195	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	261	1			T18	2		T199	2		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	495	1			T4	1		T6	2		T32	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	125	1			T5	1		T17	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T15	1		T17	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T83	1		T84	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T32	1		T120	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	295	1			T16	1		T32	1		T83	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	544	1			T1	2		T2	10		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T2	1		T5	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T2	1		T47	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T17	1		T26	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T2	1		T199	1		T195	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	270	1			T2	3		T17	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T103	1		T176	2		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	96	1			T5	1		T17	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T16	1		T47	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T4	1		T16	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T47	1		T103	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	174	1			T17	2		T41	2		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T34	1		T103	2		T8	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T5	1		T101	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	138	1			T101	1		T47	4		T121	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T18	1		T199	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T101	1		T47	2		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T18	2		T41	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T8	2		T176	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	130	1			T83	1		T84	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T15	1		T28	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T32	1		T47	2		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	76	1			T83	1		T121	1		T153	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	248	1			T16	1		T32	3		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T90	1		T8	4		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T47	1		T34	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T102	1		T19	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T2	1		T15	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	94	1			T16	1		T195	2		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	288	1			T2	1		T17	1		T41	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T16	2		T41	2		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	640	1			T1	1		T5	2		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	225	1			T4	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	668	1			T1	2		T4	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T4	1		T26	1		T47	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	664	1			T15	2		T6	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	224	1			T16	1		T46	1		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	638	1			T15	1		T17	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	202	1			T84	1		T28	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	406	1			T4	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	187	1			T28	1		T47	6		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	461	1			T4	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T84	1		T28	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	377	1			T4	1		T5	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	218	1			T15	1		T16	2		T195	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	389	1			T5	2		T15	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T47	2		T200	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	509	1			T1	2		T5	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	263	1			T16	1		T17	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	834	1			T1	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T15	1		T17	1		T32	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	933	1			T4	1		T5	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T2	2		T17	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	956	1			T1	2		T2	14		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	165	1			T4	1		T16	2		T47	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	343	1			T5	1		T17	3		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	288	1			T18	1		T199	1		T101	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	464	1			T5	1		T18	2		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T15	1		T32	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	450	1			T16	1		T32	3		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	481	1			T2	1		T17	1		T41	1