Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32539

1

T1

12

T2

31

T3

3

auto[1]

272

1

T84

6

T121

2

T153

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32548	1			T1	12		T2	31		T3	3
auto[134217728:268435455]	13	1			T238	1		T264	1		T144	1
auto[268435456:402653183]	8	1			T264	1		T322	1		T400	1
auto[402653184:536870911]	8	1			T322	1		T107	1		T385	1
auto[536870912:671088639]	12	1			T84	1		T153	2		T143	1
auto[671088640:805306367]	11	1			T264	1		T144	1		T322	1
auto[805306368:939524095]	5	1			T143	1		T322	1		T230	1
auto[939524096:1073741823]	10	1			T232	2		T264	2		T322	1
auto[1073741824:1207959551]	10	1			T121	1		T144	1		T234	1
auto[1207959552:1342177279]	9	1			T232	1		T386	1		T401	1
auto[1342177280:1476395007]	7	1			T322	1		T107	2		T401	1
auto[1476395008:1610612735]	7	1			T141	1		T234	2		T401	1
auto[1610612736:1744830463]	11	1			T84	1		T153	1		T264	2
auto[1744830464:1879048191]	14	1			T153	1		T264	1		T234	1
auto[1879048192:2013265919]	1	1			T364	1		-	-		-	-
auto[2013265920:2147483647]	11	1			T84	1		T322	1		T230	1
auto[2147483648:2281701375]	7	1			T142	1		T386	1		T400	1
auto[2281701376:2415919103]	11	1			T84	1		T264	1		T402	1
auto[2415919104:2550136831]	8	1			T144	1		T322	2		T384	1
auto[2550136832:2684354559]	5	1			T230	1		T387	1		T360	1
auto[2684354560:2818572287]	8	1			T84	1		T264	1		T384	1
auto[2818572288:2952790015]	12	1			T232	1		T141	1		T346	2
auto[2952790016:3087007743]	6	1			T230	2		T403	1		T404	1
auto[3087007744:3221225471]	11	1			T264	1		T322	1		T299	1
auto[3221225472:3355443199]	6	1			T232	2		T142	1		T143	1
auto[3355443200:3489660927]	6	1			T144	1		T322	1		T384	1
auto[3489660928:3623878655]	8	1			T400	1		T289	1		T230	1
auto[3623878656:3758096383]	9	1			T142	1		T264	1		T322	1
auto[3758096384:3892314111]	5	1			T232	1		T264	1		T386	1
auto[3892314112:4026531839]	11	1			T264	1		T144	1		T322	1
auto[4026531840:4160749567]	8	1			T84	1		T121	1		T264	1
auto[4160749568:4294967295]	5	1			T238	1		T364	1		T405	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32539	1			T1	12		T2	31		T3	3
auto[0:134217727]	auto[1]	9	1			T238	1		T144	1		T322	1
auto[134217728:268435455]	auto[1]	13	1			T238	1		T264	1		T144	1
auto[268435456:402653183]	auto[1]	8	1			T264	1		T322	1		T400	1
auto[402653184:536870911]	auto[1]	8	1			T322	1		T107	1		T385	1
auto[536870912:671088639]	auto[1]	12	1			T84	1		T153	2		T143	1
auto[671088640:805306367]	auto[1]	11	1			T264	1		T144	1		T322	1
auto[805306368:939524095]	auto[1]	5	1			T143	1		T322	1		T230	1
auto[939524096:1073741823]	auto[1]	10	1			T232	2		T264	2		T322	1
auto[1073741824:1207959551]	auto[1]	10	1			T121	1		T144	1		T234	1
auto[1207959552:1342177279]	auto[1]	9	1			T232	1		T386	1		T401	1
auto[1342177280:1476395007]	auto[1]	7	1			T322	1		T107	2		T401	1
auto[1476395008:1610612735]	auto[1]	7	1			T141	1		T234	2		T401	1
auto[1610612736:1744830463]	auto[1]	11	1			T84	1		T153	1		T264	2
auto[1744830464:1879048191]	auto[1]	14	1			T153	1		T264	1		T234	1
auto[1879048192:2013265919]	auto[1]	1	1			T364	1		-	-		-	-
auto[2013265920:2147483647]	auto[1]	11	1			T84	1		T322	1		T230	1
auto[2147483648:2281701375]	auto[1]	7	1			T142	1		T386	1		T400	1
auto[2281701376:2415919103]	auto[1]	11	1			T84	1		T264	1		T402	1
auto[2415919104:2550136831]	auto[1]	8	1			T144	1		T322	2		T384	1
auto[2550136832:2684354559]	auto[1]	5	1			T230	1		T387	1		T360	1
auto[2684354560:2818572287]	auto[1]	8	1			T84	1		T264	1		T384	1
auto[2818572288:2952790015]	auto[1]	12	1			T232	1		T141	1		T346	2
auto[2952790016:3087007743]	auto[1]	6	1			T230	2		T403	1		T404	1
auto[3087007744:3221225471]	auto[1]	11	1			T264	1		T322	1		T299	1
auto[3221225472:3355443199]	auto[1]	6	1			T232	2		T142	1		T143	1
auto[3355443200:3489660927]	auto[1]	6	1			T144	1		T322	1		T384	1
auto[3489660928:3623878655]	auto[1]	8	1			T400	1		T289	1		T230	1
auto[3623878656:3758096383]	auto[1]	9	1			T142	1		T264	1		T322	1
auto[3758096384:3892314111]	auto[1]	5	1			T232	1		T264	1		T386	1
auto[3892314112:4026531839]	auto[1]	11	1			T264	1		T144	1		T322	1
auto[4026531840:4160749567]	auto[1]	8	1			T84	1		T121	1		T264	1
auto[4160749568:4294967295]	auto[1]	5	1			T238	1		T364	1		T405	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1605

1

T1

1

T5

5

T84

1

auto[1]

1721

1

T1

2

T5

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T26	1		T47	1		T19	1
auto[134217728:268435455]	104	1			T5	1		T16	1		T195	1
auto[268435456:402653183]	105	1			T47	4		T121	1		T90	1
auto[402653184:536870911]	105	1			T1	1		T6	1		T47	1
auto[536870912:671088639]	101	1			T84	1		T48	1		T35	1
auto[671088640:805306367]	123	1			T47	2		T34	1		T57	1
auto[805306368:939524095]	104	1			T47	3		T103	1		T8	4
auto[939524096:1073741823]	108	1			T84	2		T28	1		T47	1
auto[1073741824:1207959551]	100	1			T5	1		T41	1		T120	2
auto[1207959552:1342177279]	93	1			T195	1		T47	1		T200	1
auto[1342177280:1476395007]	102	1			T1	1		T41	1		T35	1
auto[1476395008:1610612735]	115	1			T1	1		T5	1		T54	1
auto[1610612736:1744830463]	99	1			T17	1		T28	1		T120	1
auto[1744830464:1879048191]	97	1			T84	1		T195	1		T46	1
auto[1879048192:2013265919]	103	1			T84	1		T47	1		T103	1
auto[2013265920:2147483647]	104	1			T54	1		T47	3		T85	1
auto[2147483648:2281701375]	105	1			T16	1		T47	2		T85	1
auto[2281701376:2415919103]	109	1			T41	1		T26	1		T195	1
auto[2415919104:2550136831]	101	1			T16	1		T84	1		T28	1
auto[2550136832:2684354559]	113	1			T17	1		T120	1		T47	1
auto[2684354560:2818572287]	111	1			T5	1		T26	2		T47	3
auto[2818572288:2952790015]	96	1			T47	1		T34	1		T8	2
auto[2952790016:3087007743]	123	1			T5	1		T41	1		T28	1
auto[3087007744:3221225471]	89	1			T28	1		T85	1		T49	1
auto[3221225472:3355443199]	100	1			T19	1		T24	1		T50	1
auto[3355443200:3489660927]	115	1			T195	1		T46	1		T47	3
auto[3489660928:3623878655]	93	1			T29	1		T47	3		T82	1
auto[3623878656:3758096383]	115	1			T47	3		T48	1		T57	1
auto[3758096384:3892314111]	113	1			T5	1		T16	1		T17	1
auto[3892314112:4026531839]	95	1			T84	1		T53	2		T193	1
auto[4026531840:4160749567]	101	1			T47	4		T58	1		T24	1
auto[4160749568:4294967295]	89	1			T47	1		T7	2		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T19	1		T7	1		T61	1
auto[0:134217727]	auto[1]	48	1			T26	1		T47	1		T27	1
auto[134217728:268435455]	auto[0]	51	1			T195	1		T19	1		T7	1
auto[134217728:268435455]	auto[1]	53	1			T5	1		T16	1		T47	2
auto[268435456:402653183]	auto[0]	57	1			T47	3		T90	1		T103	1
auto[268435456:402653183]	auto[1]	48	1			T47	1		T121	1		T24	1
auto[402653184:536870911]	auto[0]	46	1			T47	1		T176	1		T98	1
auto[402653184:536870911]	auto[1]	59	1			T1	1		T6	1		T192	1
auto[536870912:671088639]	auto[0]	50	1			T35	1		T197	1		T245	1
auto[536870912:671088639]	auto[1]	51	1			T84	1		T48	1		T9	1
auto[671088640:805306367]	auto[0]	54	1			T34	1		T57	1		T58	1
auto[671088640:805306367]	auto[1]	69	1			T47	2		T192	1		T103	1
auto[805306368:939524095]	auto[0]	46	1			T47	1		T89	1		T43	1
auto[805306368:939524095]	auto[1]	58	1			T47	2		T103	1		T8	4
auto[939524096:1073741823]	auto[0]	48	1			T33	1		T61	1		T103	2
auto[939524096:1073741823]	auto[1]	60	1			T84	2		T28	1		T47	1
auto[1073741824:1207959551]	auto[0]	47	1			T5	1		T120	1		T34	1
auto[1073741824:1207959551]	auto[1]	53	1			T41	1		T120	1		T87	1
auto[1207959552:1342177279]	auto[0]	52	1			T195	1		T47	1		T90	2
auto[1207959552:1342177279]	auto[1]	41	1			T200	1		T9	1		T87	1
auto[1342177280:1476395007]	auto[0]	49	1			T49	2		T50	1		T8	1
auto[1342177280:1476395007]	auto[1]	53	1			T1	1		T41	1		T35	1
auto[1476395008:1610612735]	auto[0]	51	1			T1	1		T5	1		T47	1
auto[1476395008:1610612735]	auto[1]	64	1			T54	1		T120	2		T47	1
auto[1610612736:1744830463]	auto[0]	54	1			T46	1		T34	1		T35	1
auto[1610612736:1744830463]	auto[1]	45	1			T17	1		T28	1		T120	1
auto[1744830464:1879048191]	auto[0]	50	1			T195	1		T47	2		T196	1
auto[1744830464:1879048191]	auto[1]	47	1			T84	1		T46	1		T47	1
auto[1879048192:2013265919]	auto[0]	53	1			T47	1		T103	1		T50	1
auto[1879048192:2013265919]	auto[1]	50	1			T84	1		T304	1		T176	1
auto[2013265920:2147483647]	auto[0]	45	1			T47	1		T85	1		T231	1
auto[2013265920:2147483647]	auto[1]	59	1			T54	1		T47	2		T103	1
auto[2147483648:2281701375]	auto[0]	48	1			T47	2		T61	1		T8	1
auto[2147483648:2281701375]	auto[1]	57	1			T16	1		T85	1		T8	1
auto[2281701376:2415919103]	auto[0]	52	1			T195	1		T57	1		T42	1
auto[2281701376:2415919103]	auto[1]	57	1			T41	1		T26	1		T47	1
auto[2415919104:2550136831]	auto[0]	52	1			T53	1		T47	1		T80	1
auto[2415919104:2550136831]	auto[1]	49	1			T16	1		T84	1		T28	1
auto[2550136832:2684354559]	auto[0]	62	1			T120	1		T47	1		T80	1
auto[2550136832:2684354559]	auto[1]	51	1			T17	1		T121	1		T153	1
auto[2684354560:2818572287]	auto[0]	50	1			T5	1		T26	1		T47	2
auto[2684354560:2818572287]	auto[1]	61	1			T26	1		T47	1		T34	1
auto[2818572288:2952790015]	auto[0]	45	1			T34	1		T8	1		T245	1
auto[2818572288:2952790015]	auto[1]	51	1			T47	1		T8	1		T42	1
auto[2952790016:3087007743]	auto[0]	54	1			T5	1		T47	1		T80	1
auto[2952790016:3087007743]	auto[1]	69	1			T41	1		T28	1		T29	1
auto[3087007744:3221225471]	auto[0]	48	1			T49	1		T50	1		T8	2
auto[3087007744:3221225471]	auto[1]	41	1			T28	1		T85	1		T201	1
auto[3221225472:3355443199]	auto[0]	49	1			T19	1		T24	1		T8	1
auto[3221225472:3355443199]	auto[1]	51	1			T50	1		T8	1		T241	1
auto[3355443200:3489660927]	auto[0]	54	1			T195	1		T46	1		T47	1
auto[3355443200:3489660927]	auto[1]	61	1			T47	2		T27	1		T103	1
auto[3489660928:3623878655]	auto[0]	44	1			T47	2		T82	1		T60	1
auto[3489660928:3623878655]	auto[1]	49	1			T29	1		T47	1		T34	1
auto[3623878656:3758096383]	auto[0]	49	1			T47	2		T48	1		T200	1
auto[3623878656:3758096383]	auto[1]	66	1			T47	1		T57	1		T196	1
auto[3758096384:3892314111]	auto[0]	55	1			T5	1		T195	1		T47	2
auto[3758096384:3892314111]	auto[1]	58	1			T16	1		T17	1		T304	1
auto[3892314112:4026531839]	auto[0]	53	1			T84	1		T53	1		T193	1
auto[3892314112:4026531839]	auto[1]	42	1			T53	1		T8	1		T73	1
auto[4026531840:4160749567]	auto[0]	48	1			T47	2		T24	1		T103	2
auto[4026531840:4160749567]	auto[1]	53	1			T47	2		T58	1		T176	1
auto[4160749568:4294967295]	auto[0]	42	1			T7	2		T406	1		T8	2
auto[4160749568:4294967295]	auto[1]	47	1			T47	1		T58	1		T103	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T1

1

T5

5

T41

1

auto[1]

1750

1

T1

2

T5

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T47	1		T57	2		T153	1
auto[134217728:268435455]	104	1			T1	1		T16	1		T84	1
auto[268435456:402653183]	96	1			T84	1		T35	1		T58	1
auto[402653184:536870911]	100	1			T41	2		T34	1		T153	1
auto[536870912:671088639]	102	1			T120	1		T47	1		T7	1
auto[671088640:805306367]	89	1			T47	3		T9	1		T103	1
auto[805306368:939524095]	113	1			T195	1		T120	1		T47	3
auto[939524096:1073741823]	115	1			T28	1		T47	1		T200	2
auto[1073741824:1207959551]	109	1			T84	1		T54	1		T46	1
auto[1207959552:1342177279]	89	1			T5	1		T6	1		T195	1
auto[1342177280:1476395007]	101	1			T47	2		T80	1		T34	2
auto[1476395008:1610612735]	99	1			T17	1		T195	1		T47	4
auto[1610612736:1744830463]	131	1			T5	1		T195	1		T46	1
auto[1744830464:1879048191]	94	1			T19	1		T7	1		T103	1
auto[1879048192:2013265919]	90	1			T16	1		T47	2		T7	1
auto[2013265920:2147483647]	102	1			T5	1		T47	3		T7	2
auto[2147483648:2281701375]	86	1			T47	3		T35	1		T121	1
auto[2281701376:2415919103]	95	1			T1	1		T16	1		T120	1
auto[2415919104:2550136831]	116	1			T84	1		T26	1		T29	1
auto[2550136832:2684354559]	105	1			T28	1		T26	1		T47	2
auto[2684354560:2818572287]	104	1			T28	1		T120	1		T47	2
auto[2818572288:2952790015]	107	1			T120	1		T47	1		T80	1
auto[2952790016:3087007743]	111	1			T5	1		T41	1		T29	1
auto[3087007744:3221225471]	125	1			T1	1		T84	2		T28	1
auto[3221225472:3355443199]	84	1			T47	2		T57	1		T8	3
auto[3355443200:3489660927]	112	1			T82	1		T35	1		T90	1
auto[3489660928:3623878655]	106	1			T84	1		T28	1		T26	1
auto[3623878656:3758096383]	93	1			T47	1		T34	1		T406	1
auto[3758096384:3892314111]	113	1			T53	1		T80	1		T24	1
auto[3892314112:4026531839]	105	1			T5	1		T41	1		T195	1
auto[4026531840:4160749567]	125	1			T5	1		T16	1		T17	1
auto[4160749568:4294967295]	100	1			T17	1		T53	1		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T47	1		T57	1		T196	1
auto[0:134217727]	auto[1]	58	1			T57	1		T153	1		T196	1
auto[134217728:268435455]	auto[0]	54	1			T120	1		T47	2		T24	1
auto[134217728:268435455]	auto[1]	50	1			T1	1		T16	1		T84	1
auto[268435456:402653183]	auto[0]	47	1			T84	1		T35	1		T198	1
auto[268435456:402653183]	auto[1]	49	1			T58	1		T8	1		T241	1
auto[402653184:536870911]	auto[0]	41	1			T41	1		T34	1		T205	1
auto[402653184:536870911]	auto[1]	59	1			T41	1		T153	1		T200	1
auto[536870912:671088639]	auto[0]	49	1			T82	1		T34	1		T57	1
auto[536870912:671088639]	auto[1]	53	1			T120	1		T47	1		T7	1
auto[671088640:805306367]	auto[0]	41	1			T47	1		T8	1		T45	1
auto[671088640:805306367]	auto[1]	48	1			T47	2		T9	1		T103	1
auto[805306368:939524095]	auto[0]	50	1			T195	1		T47	2		T7	1
auto[805306368:939524095]	auto[1]	63	1			T120	1		T47	1		T34	1
auto[939524096:1073741823]	auto[0]	50	1			T47	1		T200	1		T193	1
auto[939524096:1073741823]	auto[1]	65	1			T28	1		T200	1		T27	1
auto[1073741824:1207959551]	auto[0]	45	1			T46	1		T87	1		T8	2
auto[1073741824:1207959551]	auto[1]	64	1			T84	1		T54	1		T47	1
auto[1207959552:1342177279]	auto[0]	46	1			T5	1		T195	1		T48	1
auto[1207959552:1342177279]	auto[1]	43	1			T6	1		T54	1		T85	1
auto[1342177280:1476395007]	auto[0]	48	1			T47	1		T34	2		T196	1
auto[1342177280:1476395007]	auto[1]	53	1			T47	1		T80	1		T198	1
auto[1476395008:1610612735]	auto[0]	48	1			T195	1		T47	2		T19	1
auto[1476395008:1610612735]	auto[1]	51	1			T17	1		T47	2		T153	1
auto[1610612736:1744830463]	auto[0]	63	1			T5	1		T195	1		T46	1
auto[1610612736:1744830463]	auto[1]	68	1			T47	1		T19	1		T82	1
auto[1744830464:1879048191]	auto[0]	48	1			T19	1		T7	1		T245	1
auto[1744830464:1879048191]	auto[1]	46	1			T103	1		T8	1		T42	1
auto[1879048192:2013265919]	auto[0]	38	1			T87	1		T50	1		T62	1
auto[1879048192:2013265919]	auto[1]	52	1			T16	1		T47	2		T7	1
auto[2013265920:2147483647]	auto[0]	46	1			T47	2		T7	2		T200	1
auto[2013265920:2147483647]	auto[1]	56	1			T5	1		T47	1		T8	1
auto[2147483648:2281701375]	auto[0]	45	1			T47	2		T35	1		T200	1
auto[2147483648:2281701375]	auto[1]	41	1			T47	1		T121	1		T176	1
auto[2281701376:2415919103]	auto[0]	45	1			T47	2		T61	1		T231	2
auto[2281701376:2415919103]	auto[1]	50	1			T1	1		T16	1		T120	1
auto[2415919104:2550136831]	auto[0]	53	1			T26	1		T47	2		T34	2
auto[2415919104:2550136831]	auto[1]	63	1			T84	1		T29	1		T195	1
auto[2550136832:2684354559]	auto[0]	40	1			T200	1		T8	1		T245	1
auto[2550136832:2684354559]	auto[1]	65	1			T28	1		T26	1		T47	2
auto[2684354560:2818572287]	auto[0]	51	1			T47	2		T8	1		T45	1
auto[2684354560:2818572287]	auto[1]	53	1			T28	1		T120	1		T35	1
auto[2818572288:2952790015]	auto[0]	49	1			T80	1		T90	1		T197	1
auto[2818572288:2952790015]	auto[1]	58	1			T120	1		T47	1		T8	1
auto[2952790016:3087007743]	auto[0]	50	1			T5	1		T47	2		T85	1
auto[2952790016:3087007743]	auto[1]	61	1			T41	1		T29	1		T53	1
auto[3087007744:3221225471]	auto[0]	68	1			T1	1		T26	1		T47	2
auto[3087007744:3221225471]	auto[1]	57	1			T84	2		T28	1		T198	1
auto[3221225472:3355443199]	auto[0]	37	1			T8	1		T137	1		T86	1
auto[3221225472:3355443199]	auto[1]	47	1			T47	2		T57	1		T8	2
auto[3355443200:3489660927]	auto[0]	48	1			T35	1		T90	1		T45	1
auto[3355443200:3489660927]	auto[1]	64	1			T82	1		T9	1		T304	1
auto[3489660928:3623878655]	auto[0]	51	1			T47	1		T61	1		T49	1
auto[3489660928:3623878655]	auto[1]	55	1			T84	1		T28	1		T26	1
auto[3623878656:3758096383]	auto[0]	48	1			T47	1		T34	1		T8	2
auto[3623878656:3758096383]	auto[1]	45	1			T406	1		T268	1		T60	2
auto[3758096384:3892314111]	auto[0]	53	1			T53	1		T80	1		T24	1
auto[3758096384:3892314111]	auto[1]	60	1			T103	1		T8	2		T138	1
auto[3892314112:4026531839]	auto[0]	58	1			T5	1		T195	1		T121	1
auto[3892314112:4026531839]	auto[1]	47	1			T41	1		T33	1		T48	1
auto[4026531840:4160749567]	auto[0]	70	1			T5	1		T193	1		T103	1
auto[4026531840:4160749567]	auto[1]	55	1			T16	1		T17	1		T46	1
auto[4160749568:4294967295]	auto[0]	49	1			T57	1		T90	1		T193	1
auto[4160749568:4294967295]	auto[1]	51	1			T17	1		T53	1		T8	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1580

1

T1

1

T5

5

T41

1

auto[1]

1746

1

T1

2

T5

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T1	1		T195	1		T54	1
auto[134217728:268435455]	96	1			T84	1		T53	1		T8	2
auto[268435456:402653183]	93	1			T84	1		T47	3		T85	1
auto[402653184:536870911]	108	1			T1	1		T17	1		T84	1
auto[536870912:671088639]	90	1			T84	1		T28	1		T120	1
auto[671088640:805306367]	111	1			T29	1		T47	2		T48	1
auto[805306368:939524095]	98	1			T47	3		T90	1		T49	1
auto[939524096:1073741823]	96	1			T5	2		T47	3		T57	1
auto[1073741824:1207959551]	116	1			T5	1		T120	1		T80	1
auto[1207959552:1342177279]	110	1			T121	1		T58	1		T90	1
auto[1342177280:1476395007]	88	1			T53	1		T120	1		T47	4
auto[1476395008:1610612735]	107	1			T195	1		T47	3		T7	1
auto[1610612736:1744830463]	102	1			T47	4		T57	1		T193	1
auto[1744830464:1879048191]	94	1			T17	1		T26	1		T120	1
auto[1879048192:2013265919]	94	1			T1	1		T84	1		T28	1
auto[2013265920:2147483647]	112	1			T47	2		T121	1		T200	1
auto[2147483648:2281701375]	109	1			T41	1		T47	1		T33	1
auto[2281701376:2415919103]	122	1			T16	1		T28	2		T29	1
auto[2415919104:2550136831]	119	1			T5	1		T195	1		T46	1
auto[2550136832:2684354559]	108	1			T16	1		T26	1		T47	5
auto[2684354560:2818572287]	97	1			T41	1		T120	1		T46	1
auto[2818572288:2952790015]	107	1			T41	1		T195	1		T7	1
auto[2952790016:3087007743]	96	1			T47	1		T19	1		T34	1
auto[3087007744:3221225471]	101	1			T84	1		T28	1		T35	1
auto[3221225472:3355443199]	101	1			T26	1		T47	1		T200	1
auto[3355443200:3489660927]	116	1			T5	1		T41	1		T53	1
auto[3489660928:3623878655]	119	1			T5	1		T47	1		T34	1
auto[3623878656:3758096383]	107	1			T6	1		T195	1		T47	1
auto[3758096384:3892314111]	118	1			T16	1		T17	1		T26	1
auto[3892314112:4026531839]	113	1			T84	1		T33	1		T34	1
auto[4026531840:4160749567]	81	1			T16	1		T46	1		T50	1
auto[4160749568:4294967295]	103	1			T195	1		T54	1		T47	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T195	1		T47	2		T80	1
auto[0:134217727]	auto[1]	47	1			T1	1		T54	1		T34	1
auto[134217728:268435455]	auto[0]	44	1			T84	1		T304	1		T268	1
auto[134217728:268435455]	auto[1]	52	1			T53	1		T8	2		T98	1
auto[268435456:402653183]	auto[0]	43	1			T84	1		T47	2		T8	1
auto[268435456:402653183]	auto[1]	50	1			T47	1		T85	1		T8	1
auto[402653184:536870911]	auto[0]	53	1			T1	1		T200	1		T50	1
auto[402653184:536870911]	auto[1]	55	1			T17	1		T84	1		T120	1
auto[536870912:671088639]	auto[0]	35	1			T47	1		T19	1		T9	1
auto[536870912:671088639]	auto[1]	55	1			T84	1		T28	1		T120	1
auto[671088640:805306367]	auto[0]	53	1			T48	1		T35	1		T193	1
auto[671088640:805306367]	auto[1]	58	1			T29	1		T47	2		T57	1
auto[805306368:939524095]	auto[0]	49	1			T47	1		T90	1		T49	1
auto[805306368:939524095]	auto[1]	49	1			T47	2		T103	1		T243	1
auto[939524096:1073741823]	auto[0]	51	1			T5	2		T47	2		T24	1
auto[939524096:1073741823]	auto[1]	45	1			T47	1		T57	1		T231	1
auto[1073741824:1207959551]	auto[0]	45	1			T80	1		T8	1		T60	2
auto[1073741824:1207959551]	auto[1]	71	1			T5	1		T120	1		T200	1
auto[1207959552:1342177279]	auto[0]	59	1			T90	1		T103	1		T50	1
auto[1207959552:1342177279]	auto[1]	51	1			T121	1		T58	1		T8	2
auto[1342177280:1476395007]	auto[0]	42	1			T53	1		T47	2		T200	1
auto[1342177280:1476395007]	auto[1]	46	1			T120	1		T47	2		T58	1
auto[1476395008:1610612735]	auto[0]	61	1			T195	1		T47	2		T7	1
auto[1476395008:1610612735]	auto[1]	46	1			T47	1		T85	1		T8	3
auto[1610612736:1744830463]	auto[0]	41	1			T47	1		T57	1		T24	2
auto[1610612736:1744830463]	auto[1]	61	1			T47	3		T193	1		T8	2
auto[1744830464:1879048191]	auto[0]	43	1			T120	1		T47	1		T197	1
auto[1744830464:1879048191]	auto[1]	51	1			T17	1		T26	1		T82	1
auto[1879048192:2013265919]	auto[0]	45	1			T47	3		T34	1		T87	1
auto[1879048192:2013265919]	auto[1]	49	1			T1	1		T84	1		T28	1
auto[2013265920:2147483647]	auto[0]	52	1			T47	1		T121	1		T200	1
auto[2013265920:2147483647]	auto[1]	60	1			T47	1		T24	2		T198	1
auto[2147483648:2281701375]	auto[0]	52	1			T7	1		T57	1		T8	4
auto[2147483648:2281701375]	auto[1]	57	1			T41	1		T47	1		T33	1
auto[2281701376:2415919103]	auto[0]	50	1			T7	1		T49	1		T103	1
auto[2281701376:2415919103]	auto[1]	72	1			T16	1		T28	2		T29	1
auto[2415919104:2550136831]	auto[0]	62	1			T5	1		T195	1		T46	1
auto[2415919104:2550136831]	auto[1]	57	1			T47	1		T82	1		T103	2
auto[2550136832:2684354559]	auto[0]	41	1			T47	1		T34	1		T61	1
auto[2550136832:2684354559]	auto[1]	67	1			T16	1		T26	1		T47	4
auto[2684354560:2818572287]	auto[0]	45	1			T46	1		T47	1		T90	1
auto[2684354560:2818572287]	auto[1]	52	1			T41	1		T120	1		T80	1
auto[2818572288:2952790015]	auto[0]	57	1			T41	1		T195	1		T7	1
auto[2818572288:2952790015]	auto[1]	50	1			T34	1		T9	1		T406	1
auto[2952790016:3087007743]	auto[0]	48	1			T47	1		T34	1		T200	1
auto[2952790016:3087007743]	auto[1]	48	1			T19	1		T406	1		T103	1
auto[3087007744:3221225471]	auto[0]	46	1			T35	1		T90	1		T88	1
auto[3087007744:3221225471]	auto[1]	55	1			T84	1		T28	1		T304	1
auto[3221225472:3355443199]	auto[0]	51	1			T47	1		T90	1		T193	1
auto[3221225472:3355443199]	auto[1]	50	1			T26	1		T200	1		T205	1
auto[3355443200:3489660927]	auto[0]	48	1			T5	1		T53	1		T47	1
auto[3355443200:3489660927]	auto[1]	68	1			T41	1		T47	2		T103	1
auto[3489660928:3623878655]	auto[0]	61	1			T5	1		T34	1		T24	1
auto[3489660928:3623878655]	auto[1]	58	1			T47	1		T27	1		T138	1
auto[3623878656:3758096383]	auto[0]	60	1			T195	1		T34	1		T49	1
auto[3623878656:3758096383]	auto[1]	47	1			T6	1		T47	1		T19	1
auto[3758096384:3892314111]	auto[0]	53	1			T26	1		T7	1		T20	1
auto[3758096384:3892314111]	auto[1]	65	1			T16	1		T17	1		T47	1
auto[3892314112:4026531839]	auto[0]	60	1			T33	1		T34	1		T35	1
auto[3892314112:4026531839]	auto[1]	53	1			T84	1		T57	1		T87	1
auto[4026531840:4160749567]	auto[0]	39	1			T50	1		T137	1		T245	1
auto[4026531840:4160749567]	auto[1]	42	1			T16	1		T46	1		T8	1
auto[4160749568:4294967295]	auto[0]	44	1			T50	2		T176	1		T245	2
auto[4160749568:4294967295]	auto[1]	59	1			T195	1		T54	1		T47	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T5

6

T16

1

T41

2

auto[1]

1711

1

T1

3

T6

1

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T1	1		T6	1		T47	2
auto[134217728:268435455]	105	1			T5	1		T84	1		T33	1
auto[268435456:402653183]	114	1			T120	1		T47	1		T19	1
auto[402653184:536870911]	121	1			T16	1		T47	2		T34	1
auto[536870912:671088639]	107	1			T5	1		T16	1		T17	2
auto[671088640:805306367]	93	1			T54	1		T46	1		T47	2
auto[805306368:939524095]	107	1			T80	1		T7	1		T82	1
auto[939524096:1073741823]	102	1			T26	1		T48	1		T34	3
auto[1073741824:1207959551]	107	1			T195	1		T46	1		T47	1
auto[1207959552:1342177279]	114	1			T5	1		T29	1		T47	1
auto[1342177280:1476395007]	116	1			T5	1		T16	1		T46	1
auto[1476395008:1610612735]	93	1			T41	2		T120	1		T80	1
auto[1610612736:1744830463]	116	1			T84	1		T26	1		T47	2
auto[1744830464:1879048191]	97	1			T1	1		T53	1		T7	1
auto[1879048192:2013265919]	103	1			T5	1		T17	1		T53	1
auto[2013265920:2147483647]	105	1			T47	2		T231	1		T406	1
auto[2147483648:2281701375]	106	1			T120	1		T47	5		T35	3
auto[2281701376:2415919103]	96	1			T47	1		T200	1		T90	1
auto[2415919104:2550136831]	104	1			T41	1		T84	1		T47	1
auto[2550136832:2684354559]	104	1			T41	1		T47	1		T48	1
auto[2684354560:2818572287]	95	1			T26	2		T120	1		T121	1
auto[2818572288:2952790015]	107	1			T84	1		T28	1		T47	4
auto[2952790016:3087007743]	107	1			T28	1		T47	2		T192	1
auto[3087007744:3221225471]	100	1			T16	1		T47	2		T48	1
auto[3221225472:3355443199]	108	1			T53	1		T47	1		T33	1
auto[3355443200:3489660927]	108	1			T28	2		T195	1		T47	3
auto[3489660928:3623878655]	105	1			T5	1		T84	1		T120	1
auto[3623878656:3758096383]	94	1			T84	1		T195	1		T47	1
auto[3758096384:3892314111]	99	1			T29	1		T195	1		T120	1
auto[3892314112:4026531839]	99	1			T84	1		T195	1		T47	2
auto[4026531840:4160749567]	108	1			T29	1		T47	1		T19	1
auto[4160749568:4294967295]	98	1			T1	1		T28	1		T47	2