Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4500

1

T1

2

T5

8

T16

4

auto[1]

2150

1

T1

4

T5

4

T6

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	192	1			T53	2		T47	4		T19	2
auto[134217728:268435455]	202	1			T5	2		T47	2		T57	2
auto[268435456:402653183]	214	1			T84	2		T26	2		T120	2
auto[402653184:536870911]	178	1			T28	2		T47	4		T193	2
auto[536870912:671088639]	212	1			T84	2		T47	4		T33	2
auto[671088640:805306367]	208	1			T17	2		T53	2		T47	4
auto[805306368:939524095]	176	1			T5	2		T16	2		T47	2
auto[939524096:1073741823]	194	1			T195	4		T47	2		T57	2
auto[1073741824:1207959551]	180	1			T41	2		T34	2		T200	2
auto[1207959552:1342177279]	228	1			T28	2		T120	2		T47	6
auto[1342177280:1476395007]	228	1			T47	6		T82	2		T34	4
auto[1476395008:1610612735]	192	1			T47	2		T85	4		T103	2
auto[1610612736:1744830463]	198	1			T5	2		T54	2		T47	6
auto[1744830464:1879048191]	194	1			T1	2		T17	2		T47	4
auto[1879048192:2013265919]	214	1			T47	4		T121	2		T24	2
auto[2013265920:2147483647]	190	1			T1	2		T29	2		T19	2
auto[2147483648:2281701375]	218	1			T84	2		T47	4		T121	2
auto[2281701376:2415919103]	248	1			T5	2		T16	2		T41	2
auto[2415919104:2550136831]	196	1			T80	2		T196	2		T49	2
auto[2550136832:2684354559]	224	1			T16	2		T17	2		T54	2
auto[2684354560:2818572287]	198	1			T47	2		T200	2		T8	2
auto[2818572288:2952790015]	232	1			T16	2		T195	2		T47	10
auto[2952790016:3087007743]	236	1			T47	8		T48	2		T193	2
auto[3087007744:3221225471]	210	1			T195	2		T120	2		T47	4
auto[3221225472:3355443199]	226	1			T6	2		T26	2		T120	2
auto[3355443200:3489660927]	182	1			T29	2		T47	4		T80	2
auto[3489660928:3623878655]	202	1			T26	2		T80	2		T7	2
auto[3623878656:3758096383]	198	1			T1	2		T84	2		T46	2
auto[3758096384:3892314111]	184	1			T5	4		T41	2		T84	2
auto[3892314112:4026531839]	242	1			T84	2		T195	2		T47	2
auto[4026531840:4160749567]	228	1			T26	2		T120	2		T47	4
auto[4160749568:4294967295]	226	1			T41	2		T28	4		T53	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	128	1			T53	2		T47	4		T121	2
auto[0:134217727]	auto[1]	64	1			T19	2		T34	2		T35	2
auto[134217728:268435455]	auto[0]	134	1			T5	2		T47	2		T57	2
auto[134217728:268435455]	auto[1]	68	1			T231	2		T8	2		T268	2
auto[268435456:402653183]	auto[0]	158	1			T84	2		T120	2		T46	2
auto[268435456:402653183]	auto[1]	56	1			T26	2		T8	4		T176	2
auto[402653184:536870911]	auto[0]	114	1			T47	4		T193	2		T8	2
auto[402653184:536870911]	auto[1]	64	1			T28	2		T87	2		T49	2
auto[536870912:671088639]	auto[0]	148	1			T47	2		T33	2		T80	2
auto[536870912:671088639]	auto[1]	64	1			T84	2		T47	2		T34	2
auto[671088640:805306367]	auto[0]	150	1			T17	2		T53	2		T47	4
auto[671088640:805306367]	auto[1]	58	1			T48	2		T196	2		T8	2
auto[805306368:939524095]	auto[0]	136	1			T5	2		T16	2		T47	2
auto[805306368:939524095]	auto[1]	40	1			T66	2		T36	2		T97	2
auto[939524096:1073741823]	auto[0]	128	1			T47	2		T57	2		T200	2
auto[939524096:1073741823]	auto[1]	66	1			T195	4		T133	2		T175	2
auto[1073741824:1207959551]	auto[0]	126	1			T41	2		T34	2		T200	2
auto[1073741824:1207959551]	auto[1]	54	1			T61	2		T128	2		T51	2
auto[1207959552:1342177279]	auto[0]	138	1			T28	2		T47	4		T58	2
auto[1207959552:1342177279]	auto[1]	90	1			T120	2		T47	2		T197	2
auto[1342177280:1476395007]	auto[0]	150	1			T47	2		T82	2		T34	4
auto[1342177280:1476395007]	auto[1]	78	1			T47	4		T57	2		T8	2
auto[1476395008:1610612735]	auto[0]	124	1			T47	2		T85	4		T304	2
auto[1476395008:1610612735]	auto[1]	68	1			T103	2		T8	2		T45	2
auto[1610612736:1744830463]	auto[0]	128	1			T5	2		T47	6		T192	2
auto[1610612736:1744830463]	auto[1]	70	1			T54	2		T8	2		T42	2
auto[1744830464:1879048191]	auto[0]	128	1			T47	4		T82	2		T35	2
auto[1744830464:1879048191]	auto[1]	66	1			T1	2		T17	2		T34	2
auto[1879048192:2013265919]	auto[0]	154	1			T47	4		T24	2		T192	2
auto[1879048192:2013265919]	auto[1]	60	1			T121	2		T61	2		T42	4
auto[2013265920:2147483647]	auto[0]	142	1			T1	2		T19	2		T90	2
auto[2013265920:2147483647]	auto[1]	48	1			T29	2		T8	2		T60	2
auto[2147483648:2281701375]	auto[0]	156	1			T84	2		T47	4		T200	2
auto[2147483648:2281701375]	auto[1]	62	1			T121	2		T27	2		T8	2
auto[2281701376:2415919103]	auto[0]	156	1			T41	2		T84	2		T28	2
auto[2281701376:2415919103]	auto[1]	92	1			T5	2		T16	2		T47	2
auto[2415919104:2550136831]	auto[0]	136	1			T80	2		T196	2		T103	2
auto[2415919104:2550136831]	auto[1]	60	1			T49	2		T8	2		T62	2
auto[2550136832:2684354559]	auto[0]	154	1			T16	2		T17	2		T47	2
auto[2550136832:2684354559]	auto[1]	70	1			T54	2		T47	2		T103	2
auto[2684354560:2818572287]	auto[0]	128	1			T47	2		T8	2		T245	2
auto[2684354560:2818572287]	auto[1]	70	1			T200	2		T281	2		T128	2
auto[2818572288:2952790015]	auto[0]	160	1			T47	8		T33	2		T87	2
auto[2818572288:2952790015]	auto[1]	72	1			T16	2		T195	2		T47	2
auto[2952790016:3087007743]	auto[0]	162	1			T47	2		T48	2		T193	2
auto[2952790016:3087007743]	auto[1]	74	1			T47	6		T8	2		T51	2
auto[3087007744:3221225471]	auto[0]	124	1			T195	2		T47	2		T34	2
auto[3087007744:3221225471]	auto[1]	86	1			T120	2		T47	2		T8	2
auto[3221225472:3355443199]	auto[0]	148	1			T120	2		T46	2		T47	2
auto[3221225472:3355443199]	auto[1]	78	1			T6	2		T26	2		T90	2
auto[3355443200:3489660927]	auto[0]	128	1			T29	2		T47	2		T80	2
auto[3355443200:3489660927]	auto[1]	54	1			T47	2		T60	2		T130	2
auto[3489660928:3623878655]	auto[0]	142	1			T80	2		T7	2		T34	2
auto[3489660928:3623878655]	auto[1]	60	1			T26	2		T8	2		T60	2
auto[3623878656:3758096383]	auto[0]	122	1			T84	2		T46	2		T200	2
auto[3623878656:3758096383]	auto[1]	76	1			T1	2		T35	2		T113	2
auto[3758096384:3892314111]	auto[0]	128	1			T5	2		T47	4		T50	2
auto[3758096384:3892314111]	auto[1]	56	1			T5	2		T41	2		T84	2
auto[3892314112:4026531839]	auto[0]	178	1			T84	2		T195	2		T47	2
auto[3892314112:4026531839]	auto[1]	64	1			T133	2		T88	2		T60	2
auto[4026531840:4160749567]	auto[0]	132	1			T47	4		T7	2		T58	2
auto[4026531840:4160749567]	auto[1]	96	1			T26	2		T120	2		T19	2
auto[4160749568:4294967295]	auto[0]	160	1			T41	2		T28	2		T53	2
auto[4160749568:4294967295]	auto[1]	66	1			T28	2		T85	2		T20	2