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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2936 1 T1 2 T5 6 T6 1
auto[1] 253 1 T84 1 T120 2 T121 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 95 1 T47 2 T121 1 T200 1
auto[134217728:268435455] 123 1 T6 1 T46 1 T47 2
auto[268435456:402653183] 99 1 T28 1 T195 1 T53 1
auto[402653184:536870911] 94 1 T84 1 T47 2 T34 1
auto[536870912:671088639] 101 1 T1 1 T28 1 T153 1
auto[671088640:805306367] 97 1 T35 1 T192 1 T87 1
auto[805306368:939524095] 102 1 T5 1 T29 1 T193 1
auto[939524096:1073741823] 93 1 T5 1 T120 2 T80 1
auto[1073741824:1207959551] 111 1 T5 1 T17 1 T47 4
auto[1207959552:1342177279] 107 1 T28 1 T120 2 T47 2
auto[1342177280:1476395007] 120 1 T26 1 T47 2 T121 2
auto[1476395008:1610612735] 91 1 T41 2 T47 1 T19 1
auto[1610612736:1744830463] 89 1 T47 1 T200 1 T192 1
auto[1744830464:1879048191] 93 1 T84 1 T120 1 T47 1
auto[1879048192:2013265919] 106 1 T16 1 T84 1 T54 1
auto[2013265920:2147483647] 98 1 T5 1 T120 1 T47 2
auto[2147483648:2281701375] 106 1 T29 1 T47 2 T80 1
auto[2281701376:2415919103] 82 1 T84 1 T28 1 T26 1
auto[2415919104:2550136831] 98 1 T17 1 T195 1 T46 1
auto[2550136832:2684354559] 101 1 T1 1 T120 1 T47 3
auto[2684354560:2818572287] 89 1 T195 1 T34 1 T121 1
auto[2818572288:2952790015] 83 1 T84 1 T19 1 T34 1
auto[2952790016:3087007743] 103 1 T16 1 T195 1 T80 1
auto[3087007744:3221225471] 111 1 T7 1 T82 1 T34 1
auto[3221225472:3355443199] 108 1 T16 1 T28 1 T195 1
auto[3355443200:3489660927] 107 1 T41 1 T47 1 T82 1
auto[3489660928:3623878655] 92 1 T17 1 T47 2 T85 1
auto[3623878656:3758096383] 92 1 T5 1 T16 1 T26 1
auto[3758096384:3892314111] 90 1 T84 1 T26 1 T47 1
auto[3892314112:4026531839] 111 1 T84 1 T195 1 T34 2
auto[4026531840:4160749567] 102 1 T5 1 T41 1 T84 1
auto[4160749568:4294967295] 95 1 T34 1 T49 1 T8 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 87 1 T47 2 T121 1 T200 1
auto[0:134217727] auto[1] 8 1 T386 1 T289 1 T401 1
auto[134217728:268435455] auto[0] 114 1 T6 1 T46 1 T47 2
auto[134217728:268435455] auto[1] 9 1 T264 1 T143 1 T322 1
auto[268435456:402653183] auto[0] 92 1 T28 1 T195 1 T53 1
auto[268435456:402653183] auto[1] 7 1 T121 1 T107 1 T403 1
auto[402653184:536870911] auto[0] 89 1 T84 1 T47 2 T34 1
auto[402653184:536870911] auto[1] 5 1 T400 1 T385 1 T409 1
auto[536870912:671088639] auto[0] 92 1 T1 1 T28 1 T200 1
auto[536870912:671088639] auto[1] 9 1 T153 1 T142 2 T107 1
auto[671088640:805306367] auto[0] 89 1 T35 1 T192 1 T87 1
auto[671088640:805306367] auto[1] 8 1 T322 1 T346 2 T265 1
auto[805306368:939524095] auto[0] 97 1 T5 1 T29 1 T193 1
auto[805306368:939524095] auto[1] 5 1 T144 1 T299 1 T400 1
auto[939524096:1073741823] auto[0] 85 1 T5 1 T120 2 T80 1
auto[939524096:1073741823] auto[1] 8 1 T264 1 T384 1 T401 1
auto[1073741824:1207959551] auto[0] 103 1 T5 1 T17 1 T47 4
auto[1073741824:1207959551] auto[1] 8 1 T264 1 T144 1 T386 1
auto[1207959552:1342177279] auto[0] 100 1 T28 1 T120 2 T47 2
auto[1207959552:1342177279] auto[1] 7 1 T121 1 T234 1 T401 1
auto[1342177280:1476395007] auto[0] 109 1 T26 1 T47 2 T8 1
auto[1342177280:1476395007] auto[1] 11 1 T121 2 T153 1 T299 1
auto[1476395008:1610612735] auto[0] 85 1 T41 2 T47 1 T19 1
auto[1476395008:1610612735] auto[1] 6 1 T264 1 T384 1 T401 1
auto[1610612736:1744830463] auto[0] 80 1 T47 1 T200 1 T192 1
auto[1610612736:1744830463] auto[1] 9 1 T232 1 T384 1 T385 1
auto[1744830464:1879048191] auto[0] 86 1 T84 1 T120 1 T47 1
auto[1744830464:1879048191] auto[1] 7 1 T232 1 T238 2 T230 1
auto[1879048192:2013265919] auto[0] 93 1 T16 1 T84 1 T54 1
auto[1879048192:2013265919] auto[1] 13 1 T141 1 T264 1 T322 1
auto[2013265920:2147483647] auto[0] 92 1 T5 1 T47 2 T35 1
auto[2013265920:2147483647] auto[1] 6 1 T120 1 T232 1 T238 1
auto[2147483648:2281701375] auto[0] 95 1 T29 1 T47 2 T80 1
auto[2147483648:2281701375] auto[1] 11 1 T142 1 T322 1 T386 1
auto[2281701376:2415919103] auto[0] 75 1 T84 1 T28 1 T26 1
auto[2281701376:2415919103] auto[1] 7 1 T264 1 T401 1 T388 1
auto[2415919104:2550136831] auto[0] 94 1 T17 1 T195 1 T46 1
auto[2415919104:2550136831] auto[1] 4 1 T384 1 T401 1 T230 1
auto[2550136832:2684354559] auto[0] 96 1 T1 1 T47 3 T33 1
auto[2550136832:2684354559] auto[1] 5 1 T120 1 T264 2 T385 1
auto[2684354560:2818572287] auto[0] 82 1 T195 1 T34 1 T85 1
auto[2684354560:2818572287] auto[1] 7 1 T121 1 T144 1 T234 1
auto[2818572288:2952790015] auto[0] 76 1 T84 1 T19 1 T34 1
auto[2818572288:2952790015] auto[1] 7 1 T322 1 T386 1 T401 1
auto[2952790016:3087007743] auto[0] 93 1 T16 1 T195 1 T80 1
auto[2952790016:3087007743] auto[1] 10 1 T238 1 T141 1 T144 1
auto[3087007744:3221225471] auto[0] 102 1 T7 1 T82 1 T34 1
auto[3087007744:3221225471] auto[1] 9 1 T234 1 T322 1 T299 1
auto[3221225472:3355443199] auto[0] 97 1 T16 1 T28 1 T195 1
auto[3221225472:3355443199] auto[1] 11 1 T232 1 T264 1 T144 1
auto[3355443200:3489660927] auto[0] 101 1 T41 1 T47 1 T82 1
auto[3355443200:3489660927] auto[1] 6 1 T141 1 T299 1 T400 1
auto[3489660928:3623878655] auto[0] 84 1 T17 1 T47 2 T85 1
auto[3489660928:3623878655] auto[1] 8 1 T322 1 T299 1 T385 1
auto[3623878656:3758096383] auto[0] 81 1 T5 1 T16 1 T26 1
auto[3623878656:3758096383] auto[1] 11 1 T153 1 T402 1 T299 1
auto[3758096384:3892314111] auto[0] 84 1 T84 1 T26 1 T47 1
auto[3758096384:3892314111] auto[1] 6 1 T238 1 T141 1 T322 1
auto[3892314112:4026531839] auto[0] 101 1 T195 1 T34 2 T121 1
auto[3892314112:4026531839] auto[1] 10 1 T84 1 T141 1 T234 1
auto[4026531840:4160749567] auto[0] 96 1 T5 1 T41 1 T84 1
auto[4026531840:4160749567] auto[1] 6 1 T289 1 T385 1 T364 2
auto[4160749568:4294967295] auto[0] 86 1 T34 1 T49 1 T8 2
auto[4160749568:4294967295] auto[1] 9 1 T142 1 T264 1 T230 1

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